M.E.

Degree Examination June 2010

VL9221 CAD for VLSI Circuit
Part A (10*2=20)
1. When is a problem said to be NP-complete?
2. Distinguish between behavioral and structural design domains.
3. What is meant by layout compaction?
4. Compare standard cell placement and building block placement problems.
5. What are the objectives of floor planning?
6. Distinguish between local and global routing.
7. State the importance of Binary decision diagram.
8. What is the role of logic synthesis in VLSI design?
9. Give the differences between assignment and allocation.
10. Define high level synthesis.
Part B (5*16=80)
11. (a) Explain the Prims algorithm for spanning trees with necessary Pseudo code. (8)
(b) Write down the Pseudo code and discuss briefly the principle of Tabu search. (8)
(or)
12. (a) Explain the concepts of linear programming with suitable expressions. (10)
(b) Describe simulated annealing with a Pseudo code. (6)
13. (a) Explain the Bellman Ford algorithm for constraint graph compaction. (8)
(b) Discuss the applications of Genetic algorithm in VLSI placement. (8)
(or)
14. (a) Describe the Kernighan-Lin partitioning algorithm with Pseudo code and necessary diagrams. (10)
(b) Draw the bipartite and tripartite graph models of RS latch and explain briefly. Explain them. (6)
15. Write short notes on :
(a) Shape functions and floor plan sizing. (8)
(b) Area routing. (8)
(or)
16. (a) Discuss the construction of rectilinear Steiner trees. (8)
(b) Give a brief account on channel routing (8)
17. (a) Explain event driven simulation and its applications. (8)
(b) Explain briefly switch level simulation. (8)
(or)
18. (a) Explain the principle and implementation of ROBDD. (8)
(b) Give a brief note on two level logic syntheses. (8)
19. Explain any two scheduling algorithms in detail. (16)
(or)
20. (a) Write a brief note on high level transformations. (8)
(b) Discuss the different sub problems of assignment problem. (8)
M.E. Degree Examination Apr/ May 2011
VL9221 CAD for VLSI Circuit
Part A (10*2=20)
1. Compare and contrast tractable and intractable problems.
2. What are the entities to be optimized while designing VLSI circuits?
3. What is the common type of minimum distance rule?
4. How do you enhance the partitioning efficiency?
5. What is a shape function?
6. List out any four local routing problem.
7. What are the different delay models?

8. What is the principle behind the reduced ordered binary decision diagram?
9. What are the goals of high level synthesis?
10. Draw the data flow graph (DFG) for iterative data flow with example.
Part B (5*16=80)
11. With an aid of Y chart explain the different design domains and compare the different design
methodologies.
(or)
12. Explain, how can the principle of backtracking be used in travelling salesman problem with example.
13. Write the Pseudo code of Kernighan Lin Partitioning algorithm and explain it with suitable example.
(or)
14. List out the factors to be considered for partitioning and explain how can simulate annealing be applied
to placement problem.
15. (a) Describe the shape functions, floor plan sizing, and optimization problems in floor planning.
(b) What is the goal of channel routing and describe the classical model?
(or)
16. What are the different approaches to solve global routing problem? Write an efficient algorithm to find
a path between a pair of points in a rectangular grid.
17. Write about the issues related to event driven simulation and their merits and demerits.
(or)
18. Explain the specific simulation tools for different abstraction level.
19. Explain various scheduling algorithms in high level synthesis and compare them.
(or)
20. Write explanatory note on
(a) High level transformation
(b) Hardware models, internal representation in high level synthesis
M.E. Degree Examination June 2012
VL9221 CAD for VLSI Circuit
Part A (10*2=20)
1. List out the general purpose integrated circuits.
2. Define integer linear programming.
3. What is the job of symbolic layout editor?
4. What does the partitioning problem deal with?
5. Formulate the sizing algorithm for slicing floor plans.
6. List the parameters characterizing for local routing problem.
7. Compare static partitioning and dynamic partitioning.
8. Write the problem definition for two level logic synthesis.
9. Write the demerits of ASAP scheduling.
10. Define super vertices.
Part B (5*16=80)
11. (a) Explain the design domain to describe the VLSI design process.
(b) What are the ways of checking the correctness of an IC without actually fabricating it?
(or)
12. (a) Explain the suitable data structure to represent graph.
(b) Write the Prims algorithm for minimum spanning trees.
13. (a) With diagram explain the minimum distance design rules.
(b) List the types of placement problems and explain.
(or)
14. Write the algorithms for constraint graph compaction.
15. Describe the concepts of floor planning.

(or)
16. Write the algorithm used for channel routing.
17. Explain the various issues related to gate level simulation.
(or)
18. Explain the principle, construction and manipulation of ROBDD.
19. With suitable diagrams, explain the types of data flow.
(or)
20. Explain the optimization issues and formulation of assignment problems.