FET Amplifiers
CHAPTER OBJECTIVES
Become acquainted with the smallsignal ac model for a JFET and MOSFET.
Be able to perform a smallsignal ac analysis of a variety of JFET and MOSFET
configurations.
Begin to appreciate the design sequence applied to FET configurations.
Understand the effects of a source resistor and load resistor on the input impedance,
output impedance and overall gain.
Be able to analyze cascaded configurations with FETs and/or BJT amplifiers.
8.1
INTRODUCTION
Fieldeffect transistor amplifiers provide an excellent voltage gain with the added feature
of a high input impedance. They are also lowpowerconsumption configurations with
good frequency range and minimal size and weight. JFETs, depletion MOSFETs, and
MESFETs can be used to design amplifiers having similar voltage gains. The depletion
MOSFET (MESFET) circuit, however, has a much higher input impedance than a similar
JFET configuration.
Whereas a BJT device controls a large output (collector) current by means of a relatively
small input (base) current, the FET device controls an output (drain) current by means of
a small input (gatevoltage) voltage. In general, therefore, the BJT is a currentcontrolled
device and the FET is a voltagecontrolled device. In both cases, however, note that the
output current is the controlled variable. Because of the high input characteristic of FETs,
the ac equivalent model is somewhat simpler than that employed for BJTs. Whereas the BJT
has an amplification factor, b (beta), the FET has a transconductance factor, gm.
The FET can be used as a linear amplifier or as a digital device in logic circuits. In
fact, the enhancement MOSFET is quite popular in digital circuitry, especially in CMOS
circuits that require very low power consumption. FET devices are also widely used in
highfrequency applications and in buffering (interfacing) applications. Table 8.1 in Section 8.13 provides a summary of FET smallsignal amplifier circuits and related formulas.
Although the commonsource configuration is the most popular one, providing an inverted, amplified signal, one also finds commondrain (sourcefollower) circuits providing
unity gain with no inversion and commongate circuits providing gain with no inversion. As
with BJT amplifiers, the important circuit features described in this chapter include voltage
gain, input impedance, and output impedance. Due to the very high input impedance, the
input current is generally assumed to be 0 mA and the current gain is an undefined quantity.
481
Whereas the voltage gain of an FET amplifier is generally less than that obtained using a
BJT amplifier, the FET amplifier provides a much higher input impedance than that of a
BJT configuration. Output impedance values are comparable for both BJT and FET circuits.
FET ac amplifier networks can also be analyzed using computer software. Using PSpice
or Multisim, one can perform a dc analysis to obtain the circuit bias conditions and an ac
analysis to determine the smallsignal voltage gain. Using PSpice transistor models, one can
analyze the circuit using specific transistor models. On the other hand, one can develop a
program using a language such as C that can perform both the dc and ac analyses and
provide the results in a very special format.
8.2
The ac analysis of a JFET configuration requires that a smallsignal ac model for the JFET
be developed. A major component of the ac model will reflect the fact that an ac voltage
applied to the input gatetosource terminals will control the level of current from drain to
source.
The gatetosource voltage controls the draintosource (channel) current of a JFET.
Recall from Chapter 7 that a dc gatetosource voltage controls the level of dc drain
current through a relationship known as Shockleys equation: ID = IDSS (1  VGS >VP)2.
The change in drain current that will result from a change in gatetosource voltage can be
determined using the transconductance factor gm in the following manner:
ID = gm VGS
(8.1)
The prefix trans in the terminology applied to gm reveals that it establishes a relationship between an output and an input quantity. The root word conductance was chosen
because gm is determined by a currenttovoltage ratio similar to the ratio that defines the
conductance of a resistor, G = 1>R = I>V.
Solving for gm in Eq. (8.1), we have
gm =
ID
VGS
(8.2)
Graphical Determination of gm
If we now examine the transfer characteristics of Fig. 8.1, we find that gm is actually the
slope of the characteristics at the point of operation. That is,
gm = m =
y
ID
=
x
VGS
(8.3)
ID
IDSS
gm
ID
(= Slope at Qpoint)
VGS
Qpoint
ID
VGS
VP
VGS
FIG. 8.1
Definition of gm using transfer characteristic.
Following the curvature of the transfer characteristics, it is reasonably clear that the
slope and, therefore, gm increase as we progress from VP to IDSS. In other words, as VGS
approaches 0 V, the magnitude of gm increases.
Equation (8.2) reveals that gm can be determined at any Qpoint on the transfer characteristics by simply choosing a finite increment in VGS (or in ID) about the Qpoint and then
finding the corresponding change in ID (or VGS, respectively). The resulting changes in each
quantity are then substituted in Eq. (8.2) to determine gm.
EXAMPLE 8.1 Determine the magnitude of gm for a JFET with IDSS = 8 mA and
VP = 4 Vat the following dc bias points:
a. VGS = 0.5 V.
b. VGS = 1.5 V.
c. VGS = 2.5 V.
Solution: The transfer characteristics are generated as Fig. 8.2 using the procedure
defined in Chapter 7. Each operating point is then identified and a tangent line is drawn at
each point to best reflect the slope of the transfer curve in this region. An appropriate
increment is then chosen for VGS to reflect a variation to either side of each Qpoint. Equation (8.2) is then applied to determine gm.
ID
2.1 mA
a. gm =
= 3.5 mS
VGS
0.6 V
ID
1.8 mA
b. gm =
2.57 mS
VGS
0.7 V
ID
1.5 mA
c. gm =
=
= 1.5 mS
VGS
1.0 V
Note the decrease in gm as VGS approaches VP.
I (mA)
D
8
7
gm at 0.5 V
ID = 8 mA 1
VGS
4 V
0.6 V
1.8 mA
3
2
gm at 2.5 V
2.1 mA
gm at 1.5 V
4
VP
0.7 V
1.5 mA
2
1
0
VGS (V)
1.0 V
FIG. 8.2
Calculating gm at various bias points.
Mathematical Definition of gm
The graphical procedure just described is limited by the accuracy of the transfer plot and
the care with which the changes in each quantity can be determined. Naturally, the larger
the graph, the better is the accuracy, but this can then become a cumbersome problem. An
alternative approach to determining gm employs the approach used to find the ac resistance
of a diode in Chapter 1, where it was stated that:
The derivative of a function at a point is equal to the slope of the tangent line drawn at
that point.
If we therefore take the derivative of ID with respect to VGS (differential calculus) using
Shockleys equation, we can derive an equation for gm as follows:
VGS 2
dID
d
gm =
`
=
c IDSS a 1 b d
dVGS Q@pt.
dVGS
VP
VGS 2
VGS d
VGS
d
= IDSS
a1 b = 2IDSS c 1 d
a1 b
dVGS
VP
VP dVGS
VP
VGS
VGS
d
1 dVGS
1
= 2IDSS c 1 dc
(1) d = 2IDSS c 1 d c0 d
VP dVGS
VP dVGS
VP
VP
and
2IDSS
gm =
0 VP 0
VGS
d
VP
c1 
(8.4)
2IDSS
0 VP 0
gm0 =
and
c1 
0
d
VP
2IDSS
(8.5)
0 VP 0
where the added subscript 0 reminds us that it is the value of gm when VGS = 0 V. Equation (8.4) then becomes
gm = gm0 c 1 
EXAMPLE 8.2
VGS
d
VP
(8.6)
At VGS
2IDSS
2(8 mA)
= 4 mS
(maximum possible value of gm)
4V
= 0.5 V,
VGS
0.5 V
gm = gm0 c 1 d = 4 mS c 1 d = 3.5 mS
(vs. 3.5 mS
VP
4 V
graphically)
= 1.5 V,
VGS
1.5 V
gm = gm0 c 1 d = 4 mS c 1 d = 2.5 mS (vs. 2.57 mS
VP
4 V
graphically)
0 VP 0
At VGS = 2.5 V,
gm = gm0 c 1 
VGS
2.5 V
d = 4 mS c 1 d = 1.5 mS
VP
4 V
(vs. 1.5 mS
graphically)
The results of Example 8.2 are certainly sufficiently close to validate Eq. (8.4) through
(8.6) for future use when gm is required.
(8.7)
For the JFET of Fig. 6.20, gfs ranges from 1000 mS to 5000 mS, or 1 mS to 5 mS.
In general, therefore
the maximum value of gm occurs where VGS 0 V and the minimum value at
VGS VP. The more negative the value of VGS the less the value of gm.
Figure 8.3 also shows that when VGS is onehalf the pinchoff value, gm is onehalf the
maximum value.
gm (S)
gm 0
gm0
2
VP
VP
2
VGS (V)
FIG. 8.3
Plot of gm versus VGS.
EXAMPLE 8.3 Plot gm versus VGS for the JFET of Examples 8.1 and 8.2.
Solution:
gm (S)
4 mS
2 mS
4 V
2 V
VGS (V)
FIG. 8.4
Plot of gm versus VGS for a JFET with IDSS
8 mA and VP 4 V.
Effect of ID on gm
A mathematical relationship between gm and the dc bias current ID can be derived by noting that Shockleys equation can be written in the following form:
1 
VGS
ID
=
VP
A IDSS
(8.8)
VGS
ID
b = gm0
VP
A IDSS
(8.9)
Using Eq. (8.9) to determine gm for a few specific values of ID, we obtain the following
results:
a. If ID = IDSS,
IDSS
gm = gm0
= gm0
A IDSS
b. If ID = IDSS >2,
IDSS >2
gm = gm0
= 0.707gm0
A IDSS
c. If ID = IDSS >4,
gm = gm0
EXAMPLE 8.4
IDSS >4
gm0
=
= 0.5gm0
A IDSS
2
gm (S)
4 mS
2.83 mS
2 mS
2
IDSS
4
4
IDSS
8
IDSS
10
ID (mA)
FIG. 8.5
Plot of gm versus ID for a JFET with IDSS 8 mA and VGS 4 V.
(8.10)
For a JFET a practical value of 109 (1000 M) is typical, whereas a value of 1012
to 1015 is typical for MOSFETs and MESFETs.
1
1
=
gos
yos
(8.11)
The output impedance is defined on the characteristics of Fig. 8.6 as the slope of the
horizontal characteristic curve at the point of operation. The more horizontal the curve, the
greater is the output impedance. If it is perfectly horizontal, the ideal situation is on hand
with the output impedance being infinite (an open circuit)an often applied approximation.
In equation form,
rd =
VDS
`
ID VGS = constant
(8.12)
Note the requirement when applying Eq. (8.12) that the voltage VGS remain constant
when rd is determined. This is accomplished by drawing a straight line approximating the
VGS line at the point of operation. A VDS or ID is then chosen and the other quantity
measured off for use in the equation.
ID (mA)
VGS = 0 V
rd =
VDS
ID
VGS = constant at 1 V
VGS
Qpoint
1 V
ID
VDS
2 V
VDS (V)
FIG. 8.6
Definition of rd using JFET drain characteristics.
EXAMPLE 8.5 Determine the output impedance for the JFET of Fig. 8.7 for VGS = 0 V
and VGS = 2 V at VDS = 8 V.
ID (mA)
VGS = 0 V
8
7
ID = 0.2 mA
VDS = 5 V
VGS = 1 V
5
4
VGS = 2 V
ID = 0.1 mA
3
VDS = 8 V
VGS = 3 V
VGS = 4 V
1
0
10 11 12 13 14
VDS (V)
FIG. 8.7
Drain characteristics used to calculate rd in Example 8.5.
Solution: For VGS = 0 V, a tangent line is drawn and VDS is chosen as 5 V, resulting in
a ID of 0.2 mA. Substituting into Eq. (8.12), we find
VDS
5V
rd =
`
=
= 25 k
ID VGS = 0 V
0.2 mA
For VGS = 2 V, a tangent line is drawn and VDS is chosen as 8 V, resulting in a ID of
0.1 mA. Substituting into Eq. (8.12), we find
VDS
8V
rd =
`
=
= 80 k
ID VGS = 2 V
0.1 mA
which shows that rd does change from one operating region to another, with lower values
typically occurring at lower levels of VGS (closer to 0 V).
+
gmVgs
Vgs
rd
FIG. 8.8
JFET ac equivalent circuit.
The input impedance is represented by the open circuit at the input terminals and the output impedance by the resistor rd from drain to source. Note that the gatetosource voltage is
now represented by Vgs (lowercase subscripts) to distinguish it from dc levels. In addition,
note that the source is common to both input and output circuits, whereas the gate and drain
terminals are only in touch through the controlled current source gmVgs.
In situations where rd is ignored (assumed sufficiently large in relation to other elements
of the network to be approximated by an open circuit), the equivalent circuit is simply a
current source whose magnitude is controlled by the signal Vgs and parameter gmclearly
a voltagecontrolled current source.
EXAMPLE 8.6
Given gfs = 3.8 mS and gos = 20 mS, sketch the FET ac equivalent model.
Solution:
gm = gfs = 3.8 mS
and
rd =
1
1
=
= 50 k
gos
20 mS
+
rd
50 k
Vgs
FIG. 8.9
JFET ac equivalent model for Example 8.6.
8.3
FIXEDBIAS CONFIGURATION
Now that the JFET equivalent circuit has been defined, a number of fundamental JFET
smallsignal configurations are investigated. The approach parallels the ac analysis of BJT
amplifiers with a determination of the important parameters of Zi, Zo, and Av for each
configuration.
The fixedbias configuration of Fig. 8.10 includes the coupling capacitors C1 and C2,
which isolate the dc biasing arrangement from the applied signal and load; they act as shortcircuit equivalents for the ac analysis.
+VDD
RD
D
C1
Vo
Vi
RG
Zi
C2
Zo
VGG
FIG. 8.10
JFET fixedbias configuration.
Once the levels of gm and rd are determined from the dc biasing arrangement, specification sheet, or characteristics, the ac equivalent model can be substituted between the appropriate terminals as shown in Fig. 8.11. Note that both capacitors have the shortcircuit
equivalent because the reactance XC = 1>(2pfC) is sufficiently small compared to other
impedance levels of the network, and the dc batteries VGG and VDD are set to 0 V by a
shortcircuit equivalent.
The network of Fig. 8.11 is then carefully redrawn as shown in Fig. 8.12. Note the defined polarity of Vgs, which defines the direction of gmVgs. If Vgs is negative, the direction
of the current source reverses. The applied signal is represented by Vi and the output signal
across RD rd by Vo.
FIXEDBIAS 489
CONFIGURATION
XC 0
XC 0
Vi
RG
gmVgs
Zi
Battery VGG
replaced by
short
Vo
RD
rd
Zo
Battery VDD
replaced by
short
FIG. 8.11
Substituting the JFET ac equivalent circuit unit into the network of
Fig. 8.10.
D
+
Vi
+
Zi
RG
+
gmVgs
Vgs
rd
RD
Zo
Vo
FIG. 8.12
Redrawn network of Fig. 8.11.
(8.13)
because of the infinite input impedance at the input terminals of the JFET.
Zo Setting Vi = 0 V as required by the definition of Zo will establish Vgs as 0 V also. The
result is gmVgs = 0 mA, and the current source can be replaced by an opencircuit equivalent as shown in Fig. 8.13. The output impedance is
Zo = RD rd
(8.14)
D
gmVgs = 0 mA
rd
RD
Zo
S
FIG. 8.13
Determining Zo.
If the resistance rd is sufficiently large (at least 10:1) compared to RD, the approximation
rd RD RD can often be applied and
Zo RD
rd 10RD
(8.15)
FIXEDBIAS 491
CONFIGURATION
so that
Av =
Vo
= gm (rd RD)
Vi
(8.16)
If rd 10RD,
Av =
Vo
= gmRD
Vi
(8.17)
rd 10RD
Phase Relationship The negative sign in the resulting equation for Av clearly reveals a
phase shift of 180 between input and output voltages.
EXAMPLE 8.7 The fixedbias configuration of Example 7.1 had an operating point defined
by VGSQ = 2 V and IDQ = 5.625 mA, with IDSS = 10 mA and VP = 8 V. The network
is redrawn as Fig. 8.14 with an applied signal Vi. The value of yos is provided as 40 mS.
a.
b.
c.
d.
e.
f.
Determine gm.
Find rd.
Determine Zi.
Calculate Zo.
Determine the voltage gain Av.
Determine Av ignoring the effects of rd.
20 V
RD
2 k
D
C1
IDSS = 10 mA
VP = 8 V
+
RG
Vi
Zi
C2
1 M
S
Zo
2V
Vo
FIG. 8.14
JFET configuration for Example 8.7.
Solution:
2IDSS
2(10 mA)
= 2.5 mS
8V
VGSQ
(2 V)
gm = gm0 a 1 b = 2.5 mS a 1 b = 1.88 mS
VP
(8 V)
1
1
b. rd =
=
= 25 k
yos
40 mS
c. Zi = RG = 1 M
d. Zo = RD rd = 2 k 25 k = 1.85 k
e. Av = gm(RD rd) = (1.88 mS)(1.85 k)
= 3.48
f. Av = gmRD = (1.88 mS)(2 k) = 3.76
As demonstrated in part (f), a ratio of 25 k:2 k = 12.5:1 between rd and RD results
in a difference of 8% in the solution.
a. gm0 =
0 VP 0
8.4
SELFBIAS CONFIGURATION
Bypassed RS
The fixedbias configuration has the distinct disadvantage of requiring two dc voltage
sources. The selfbias configuration of Fig. 8.15 requires only one dc supply to establish
the desired operating point.
VDD
RD
C2
D
C1
Vo
Vi
S
Zo
RG
Zi
CS
RS
FIG. 8.15
Selfbias JFET configuration.
The capacitor CS across the source resistance assumes its opencircuit equivalence for
dc, allowing RS to define the operating point. Under ac conditions, the capacitor assumes
the shortcircuit state and short circuits the effects of RS. If left in the ac, gain will be
reduced, as will be shown in the paragraphs to follow.
The JFET equivalent circuit is established in Fig. 8.16 and carefully redrawn in Fig. 8.17.
Since the resulting configuration is the same as appearing in Fig. 8.12, the resulting
equations for Zi, Zo, and Av will be the same.
XC 0
XC 0
Vi
gmVgs
rd
Zo
RD
RG
Zi
Vo
RS bypassed
by X C
VDD
FIG. 8.16
Network of Fig. 8.15 following the substitution of
the JFET ac equivalent circuit.
D
+
Vi
+
Zi
RG
+
gmVgs
Vgs
rd
FIG. 8.17
Redrawn network of Fig. 8.16.
RD
Zo
Vo
Zi
Zi = RG
(8.18)
Zo
Zo = rd RD
(8.19)
If rd 10RD,
Zo RD
(8.20)
rd 10RD
Av
Av = gm(rd RD)
(8.21)
If rd 10RD,
Av = gmRD
(8.22)
rd 10RD
Phase Relationship The negative sign in the solutions for Av again indicates a phase shift
of 180 between Vi and Vo.
Unbypassed RS
If CS is removed from Fig 8.15, the resistor RS will be part of the ac equivalent circuit as
shown in Fig. 8.18. In this case, there is no obvious way to reduce the network to lower its
level of complexity. In determining the levels of Zi, Zo, and Av, one must be very careful
with notation and defined polarities and direction. Initially, the resistance rd will be left out
of the analysis to form a basis for comparison.
D
Io
gmVgs
Zi
Vi
ID
Vgs
RG
Zo
Vo
RD
RS
Io
FIG. 8.18
Selfbias JFET configuration including the effects of RS with
rd .
Zi Due to the opencircuit condition between the gate and the output network, the input
remains the following:
Zi = RG
(8.23)
SELFBIAS 493
CONFIGURATION
so that
or
and
Since
then
Vo
= RD
Io
Zo =
and
(8.24)
rd =
If rd is included in the network, the equivalent will appear as shown in Fig. 8.19.
G
+
Vi
Io
ID
RD
Zo
Vgs
RG
rd
gmVgs
Zi
Vo
RS
Io + ID
Io
FIG. 8.19
Including the effects of rd in the selfbias JFET configuration.
Vo
IDRD
`
= Io Vi = 0 V
Io
we should try to find an expression for Io in terms of ID.
Applying Kirchhoffs current law, we have
Io = gmVgs + Ird  ID
but
Vrd = Vo + Vgs
Vo + Vgs
and
Io = gmVgs +
 ID
rd
Zo =
Since
or
Now,
so that
Io = a gm +
IDRD
1
b Vgs  ID using Vo = IDRD
rd
rd
RS
RS
RD
d = ID c 1 + gmRS +
+
d
rd
rd
rd
RS
RD
+
d
rd
rd
RS
1 + gmRS +
rd
ID c 1 + gmRS +
or
and
Io =
Zo =
Vo
=
Io
IDRD
RS
RD
+
b
rd
rd
RS
1 + gmRS +
rd
ID a 1 + gmRS +
RS
d
rd
R
Zo =
RS
RD D
c 1 + gmRS +
+
d
rd
rd
SELFBIAS 495
CONFIGURATION
c 1 + gmRS +
and finally,
(8.25a)
For rd 10RD,
a 1 + gmRS +
and
1 + gmRS +
RS
RD
b W
rd
rd
RS
RS
RD
+
1 + gmRS +
rd
rd
rd
resulting in
Zo RD
rd 10RD
(8.25b)
Av For the network of Fig. 8.19, application of Kirchhoffs voltage law to the input circuit results in
Vi  Vgs  VRS = 0
Vgs = Vi  IDRS
The voltage across rd using Kirchhoffs voltage law is
Vrd = Vo  VRS
Vo  VRS
Vrd
I =
=
rd
rd
and
ID c 1 + gmRS +
RD + RS
d = gmVi
rd
gmVi
ID =
or
(IDRD)  (IDRS)
rd
1 + gmRS +
RD + RS
rd
and
Av =
Vo
= Vi
gmRDVi
RD + RS
1 + gmRS +
rd
gmRD
RD + RS
1 + gmRS +
rd
(8.26)
Vo
gmRD
Vi
1 + gmRS
(8.27)
rd 10(RD + RS)
Phase Relationship The negative sign in Eq. (8.26) again reveals that a 180 phase shift
will exist between Vi and Vo.
Determine gm.
Find rd.
Find Zi.
Calculate Zo with and without the effects of rd. Compare the results.
Calculate Av with and without the effects of rd. Compare the results.
20 V
RD
3.3 k
C2
Vo
D
C1
IDSS = 8 mA
VP = 6 V
Vi
S
Zi
Zo
RG
1 M
RS
1 k
FIG. 8.20
Network for Example 8.8.
Solution:
2IDSS
2(8 mA)
= 2.67 mS
6V
VGSQ
(2.6 V)
gm = gm0 a 1 b = 2.67 mS a 1 b = 1.51 mS
VP
(6 V)
1
1
b. rd =
=
= 50 k
yos
20 mS
c. Zi = RG = 1 M
d. With rd,
rd = 50 k 7 10RD = 33 k
Therefore,
Zo = RD = 3.3 k
If rd = ,
Zo = RD = 3.3 k
e. With rd,
gmRD
(1.51 mS)(3.3 k)
Av =
=
RD + RS
3.3 k + 1 k
1 + gmRS +
1 + (1.51 mS)(1 k) +
rd
50 k
= 1.92
With rd (opencircuit equivalence),
gmRD
(1.51 mS)(3.3 k)
Av =
= 1.98
=
1 + gmRS
1 + (1.51 mS)(1 k)
As above, the effect of rd is minimal because the condition rd 10(RD + RS) is satisfied.
Note also that the typical gain of a JFET amplifier is less than that generally encountered
for BJTs of similar configurations. Keep in mind, however, that Zi is magnitudes greater than
the typical Zi of a BJT, which will have a very positive effect on the overall gain of a system.
a. gm0 =
0 VP 0
8.5
VOLTAGEDIVIDER CONFIGURATION
VOLTAGEDIVIDER 497
CONFIGURATION
The popular voltagedivider configuration for BJTs can also be applied to JFETs as demonstrated in Fig. 8.21.
+VDD
RD
C2
R1
Vo
C1
G
Zo
+
Vi
R2
Zi
RS
CS
FIG. 8.21
JFET voltagedivider configuration.
Substituting the ac equivalent model for the JFET results in the configuration of Fig. 8.22.
Replacing the dc supply VDD by a shortcircuit equivalent has grounded one end of R1 and
RD. Since each network has a common ground, R1 can be brought down in parallel with
R2 as shown in Fig. 8.23. RD can also be brought down to ground, but in the output circuit
across rd. The resulting ac equivalent network now has the basic format of some of the
networks already analyzed.
Zi R1 and R2 are in parallel with the opencircuit equivalence of the JFET, resulting in
Zi = R1 R2
(8.28)
(8.29)
For rd 10RD,
Zo RD
RD
R1
G
Vi
Zi
Vo
+
R2
(8.30)
rd 10RD
gmVgs
Vgs
RD
FIG. 8.22
Network of Fig. 8.21 under ac conditions.
Vi
Vo
+
Zi
Zo
Zo
R1
R2
gmVgs
Vgs
FIG. 8.23
Redrawn network of Fig. 8.22.
rd
RD
Av
Vgs = Vi
Vo = gmVgs(rd RD)
and
gmVgs(rd RD)
Vo
=
Vi
Vgs
Av =
so that
Vo
= gm(rd RD)
Vi
Av =
and
If rd 10RD,
Vo
gmRD
Vi
Av =
(8.31)
(8.32)
rd 10RD
Note that the equations for Zo and Av are the same as obtained for the fixedbias and selfbias (with bypassed RS) configurations. The only difference is the equation for Zi, which is
now sensitive to the parallel combination of R1 and R2.
8.6
COMMONGATE CONFIGURATION
C1
C1
C2
+
Vi
RD
RS
Z'i
VDD
FIG. 8.24
JFET commongate configuration.
Zo
Vi
+
C2
+
+
Zi
rd
Zi
+
gmVgs
RS
Vo
Z'i
Vgs
Z'o
RD
Zo
+G
Vo
FIG. 8.25
Network of Fig. 8.24 following substitution of JFET ac
equivalent model.
Zi The resistor RS is directly across the terminals defining Zi. Let us therefore find the
impedance Zi of Fig. 8.24, which will simply be in parallel with RS when Zi is defined.
The network of interest is redrawn as Fig. 8.26. The voltage V = Vgs. Applying
Kirchhoffs voltage law around the output perimeter of the network results in
V  Vrd  VRD = 0
and
Vrd = V  VRD = V  IRD
Applying Kirchhoffs current law at node a results in
I + gmVgs = Ird
(V  IRD)
and
I = Ird  gmVgs =
 gmVgs
rd
or
I =
IRD
V
 gm [V]
rd
rd
COMMONGATE 499
CONFIGURATION
I'
I'
a
Ird
Z'i
rd
gmVgs
V'
Vgs
+
V rd
I'
RD
VRD
FIG. 8.26
Determining Zi for the network of Fig. 8.24.
so that
and
or
and
which results in
RD
1
d = Vc + gm d
rd
rd
Ic 1 +
V
=
I
Zi =
Zi =
c1 +
RD
d
rd
1
c gm + d
rd
(8.33)
rd + RD
V
=
I
1 + gmrd
Zi = RS Zi
Zi = RS c
rd + RD
d
1 + gmrd
(8.34)
If rd 10RD, Eq. (8.33) permits the following approximation since RD>rd V 1 and
1>rd V gm:
RD
c1 +
d
rd
1
Zi =
g
1
m
c gm + d
rd
and
Zi RS 1>gm
rd 10RD
(8.35)
Zo Substituting Vi = 0 V in Fig. 8.25 will shortout the effects of RS and set Vgs to 0 V.
The result is gmVgs = 0, and rd will be in parallel with RD. Therefore,
Zo = RD rd
(8.36)
For rd 10RD,
Zo RD
rd 10RD
Vi = Vgs
Vo = IDRD
Vrd = Vo  Vi
(8.37)
Ird =
and
Vo  Vi
rd
and
ID =
so that
Vi  Vo
+ gmVi
rd
Vo = ID RD = c
=
Vo RD
Vi RD
+ gm
rd
rd
Vo c 1 +
and
with
Vi  Vo
+ gmVi d RD
rd
RD
RD
d = Vi c
+ gmRD d
rd
rd
Vo
Av =
=
Vi
c gmRD +
RD
d
rd
(8.38)
RD
c1 +
d
rd
For rd 10RD, the factor RD>rd of Eq. (8.38) can be dropped as a good approximation, and
Av gmRD
(8.39)
rd 10RD
Phase Relationship The fact that Av is a positive number will result in an inphase relationship between Vo and Vi for the commongate configuration.
EXAMPLE 8.9 Although the network of Fig. 8.27 may not initially appear to be of the
commongate variety, a close examination will reveal that it has all the characteristics of
Fig. 8.24. If VGSQ = 2.2 V and IDQ = 2.03 mA:
a.
b.
c.
d.
e.
Determine gm.
Find rd.
Calculate Zi with and without rd. Compare results.
Find Zo with and without rd. Compare results.
Determine Vo with and without rd. Compare results.
+12 V
RD
3.6 k
10 F
Vo
IDSS = 10 mA
VP = 4 V
gos = 50 S
+
Vi = 40 mV
10 F
RS
1.1 k
FIG. 8.27
Network for Example 8.9.
SOURCEFOLLOWER 501
(COMMONDRAIN)
CONFIGURATION
Solution:
2IDSS
2(10 mA)
= 5 mS
4V
0 VP 0
VGSQ
(2.2 V)
b = 5 mS a 1 gm = gm0 a 1 b = 2.25 mS
VP
(4 V)
1
1
b. rd =
= 20 k
=
gos
50 mS
a. gm0 =
c. With rd,
rd + RD
20 k + 3.6 k
d = 1.1 k c
d
1 + gmrd
1 + (2.25 mS)(20 k)
= 1.1 k 0.51 k = 0.35 k
Zi = RS c
Without rd,
Zi = RS 1>gm = 1.1 k 1>2.25 ms = 1.1 k 0.44 k
= 0.31 k
Even though the condition rd 10RD is not satisfied with rd = 20 k and
10RD = 36 k, both equations result in essentially the same level of impedance. In
this case, 1>gm was the predominant factor.
d. With rd,
Zo = RD rd = 3.6 k 20 k = 3.05 k
Without rd,
Zo = RD = 3.6 k
Again the condition rd 10RD is not satisfied, but both results are reasonably close.
RD is certainly the predominant factor in this example.
e. With rd,
RD
3.6 k
c gmRD +
d
c (2.25 mS)(3.6 k) +
d
rd
20 k
=
Av =
RD
3.6 k
c1 +
d
c1 +
d
rd
20 k
8.1 + 0.18
=
= 7.02
1 + 0.18
Vo
and
Av =
1 Vo = AvVi = (7.02)(40 mV) = 280.8 mV
Vi
Without rd,
Av = gmRD = (2.25 mS)(3.6 k) = 8.1
with
Vo = AvVi = (8.1)(40 mV) = 324 mV
In this case, the difference is a little more noticeable, but not dramatically so.
Example 8.9 demonstrates that even though the condition rd 10RD was not satisfied,
the results for the parameters given were not significantly different using the exact and approximate equations. In fact, in most cases, the approximate equations can be used to find
a reasonable idea of particular levels with a reduced amount of effort.
8.7
SOURCEFOLLOWER (COMMONDRAIN)
CONFIGURATION
The JFET equivalent of the BJT emitterfollower configuration is the sourcefollower configuration of Fig. 8.28. Note that the output is taken off the source terminal and, when the
dc supply is replaced by its shortcircuit equivalent, the drain is grounded (hence, the terminology commondrain).
Substituting the JFET equivalent circuit results in the configuration of Fig. 8.29. The
controlled source and the internal output impedance of the JFET are tied to ground at
one end and RS on the other, with Vo across RS. Since gmVgs, rd, and RS are connected to
VDD
D
C1
Vi
S
Zi
C2
Vo
RG
RS
Zo
FIG. 8.28
JFET sourcefollower configuration.
Vi
+
gmVgs
Vgs
Zi
rd
RG
RS
Vo
Zo
FIG. 8.29
Network of Fig. 8.28 following the substitution of the JFET ac
equivalent model.
the same terminal and ground, they can all be placed in parallel as shown in Fig. 8.30.
The current source reversed direction, but Vgs is still defined between the gate and source
terminals.
Io
Vi
Vgs
Zi
RG
Zo
gmVgs
rd
RS
Vo
FIG. 8.30
Network of Fig. 8.29 redrawn.
(8.40)
Zo Setting Vi = 0 V results in the gate terminal being connected directly to the ground as
shown in Fig. 8.31.
The fact that Vgs and Vo are across the same parallel network results in Vo = Vgs.
SOURCEFOLLOWER 503
(COMMONDRAIN)
CONFIGURATION
Io
+
gmVgs
Vgs
Zo
rd
RS
Vo
FIG. 8.31
Determining Zo for the network of Fig. 8.30.
Zo = rd RS 1>gm
(8.41)
For rd 10 RS,
Zo RS 1>gm
rd 10RS
(8.42)
gm(rd RS)
Vo
=
Vi
1 + gm(rd RS)
(8.43)
Vo
gmRS
Vi
1 + gmRS
(8.44)
rd 10RS
Since the denominator of Eq. (8.43) is larger than the numerator by a factor of one, the
gain can never be equal to or greater than one (as encountered for the emitterfollower BJT
network).
Phase Relationship Since Av of Eq. (8.43) is a positive quantity, Vo and Vi are in phase
for the JFET sourcefollower configuration.
Determine gm.
Find rd.
Determine Zi.
Calculate Zo with and without rd. Compare results.
Determine Av with and without rd. Compare results.
+9 V
IDSS = 16 mA
VP = 4 V
gos = 25 S
0.05 F
Vi
Zi
RG
1 M
RS
0.05 F
2.2 k
Zo
Vo
FIG. 8.32
Network to be analyzed in Example 8.10.
Solution:
b.
c.
d.
e.
2IDSS
2(16 mA)
= 8 mS
4V
0 VP 0
VGSQ
(2.86 V)
gm = gm0 a 1 b = 8 mS a 1 b = 2.28 mS
VP
(4 V)
1
1
rd =
=
= 40 k
gos
25 mS
Zi = RG = 1 M
With rd,
Zo = rd RS 1>gm = 40 k 2.2 k 1>2.28 mS
= 40 k 2.2 k 438.6
= 362.52
which shows that Zo is often relatively small and determined primarily by 1>gm.
Without rd,
Zo = RS 1>gm = 2.2 k 438.6 = 365.69
which shows that rd typically has little effect on Zo.
With rd,
gm(rd RS)
(2.28 mS)(40 k 2.2 k)
Av =
=
1 + gm(rd RS)
1 + (2.28 mS)(40 k 2.2 k)
(2.28 mS)(2.09 k)
4.77
=
=
= 0.83
1 + (2.28 mS)(2.09 k)
1 + 4.77
which is less than 1, as predicted above.
a. gm0 =
Without rd,
gm RS
(2.28 mS)(2.2 k)
Av =
=
1 + gm RS
1 + (2.28 mS)(2.2 k)
5.02
=
= 0.83
1 + 5.02
which shows that rd usually has little effect on the gain of the configuration.
8.8
DEPLETIONTYPE MOSFETs
Vgs
G
S
gmVgs
rd
FIG. 8.33
DMOSFET ac equivalent model.
EXAMPLE 8.11 The network of Fig. 8.34 was analyzed as Example 7.7, resulting in
VGSQ = 0.35 V and IDQ = 7.6 mA.
a.
b.
c.
d.
e.
f.
RD
R1
C1
C2
110 M
D
Vo
IDSS = 6 mA
VP = 3 V
gos = 10 S
Vi
1.8 k
Zi
R2
10 M RS
150
FIG. 8.34
Network for Example 8.11.
Zo
CS
DEPLETIONTYPE 505
MOSFETs
Solution:
2IDSS
2(6 mA)
= 4 mS
3V
0 VP 0
VGSQ
(+0.35 V)
b = 4 mS a 1 gm = gm0 a 1 b = 4 mS(1 + 0.117) = 4.47 mS
VP
(3 V)
1
1
b. rd =
= 100 k
=
yos
10 mS
a. gm0 =
c. See Fig. 8.35. Note the similarities with the network of Fig. 8.23. Equations (8.28)
through (8.32) are therefore applicable.
+
Vi
Zi
R1
110 M R2
10 M
+
4.47 10 3 Vgs
Vgs
rd
100 k
RD
1.8 k
Zo
Vo
FIG. 8.35
AC equivalent circuit for Fig. 8.34.
8.9
ENHANCEMENTTYPE MOSFETs
D
pMOS
+
Vgs
gmVgs
rd
nMOS
G
S
1
1
gm = gfs = yfs rd = g = y
os
os
FIG. 8.36
Enhancement MOSFET ac smallsignal model.
gm = 2k(VGSQ  VGS(Th))
and
(8.45)
Recall that the constant k can be determined from a given typical operating point on a
specification sheet. In every other respect, the ac analysis is the same as that employed for
JFETs or DMOSFETs. Be aware, however, that the characteristics of an EMOSFET are
such that the biasing arrangements are somewhat limited.
8.10
The EMOSFET drainfeedback configuration appears in Fig. 8.37. Recall from dc calculations that RG could be replaced by a shortcircuit equivalent since IG = 0 A and therefore
VRG = 0 V. However, for ac situations it provides an important high impedance between Vo
and Vi. Otherwise, the input and output terminals would be connected directly and Vo = Vi.
VDD
RD
RF
C2
RF
Vo
Ii
Ii
D
Zo
C1
Vi
+
Vi
G
S
Zi
FIG. 8.37
EMOSFET drainfeedback configuration.
Zi
Vgs
Vo
+
gmVgs
rd
RD
Zo
FIG. 8.38
AC equivalent of the network of Fig. 8.37.
Substituting the ac equivalent model for the device results in the network of Fig. 8.38.
Note that RF is not within the shaded area defining the equivalent model of the device, but
does provide a direct connection between input and output circuits.
Zi
Applying Kirchhoffs current law to the output circuit (at node D in Fig. 8.38) results in
Vo
Ii = gmVgs +
rd RD
and
Vgs = Vi
Vo
so that
Ii = gmVi +
rd RD
Vo
or
Ii  gmVi =
rd RD
Therefore,
Vo = (rd RD)(Ii  gmVi)
Vi  (rd RD)(Ii  gmVi)
Vi  Vo
with
Ii =
=
RF
RF
and
so that
Zi =
and finally,
RF + rd RD
Vi
=
Ii
1 + gm(rd RD)
(8.46)
RF
1 + gm(rd RD)
For rd 10RD,
Zi
RF
1 + gmRD
(8.47)
RF W rd RD, rd 10RD
Vi = Vgs = 0 V
RF
(8.48)
D
gmVgs = 0 mA
rd
RD
Zo
FIG. 8.39
Determining Zo for the network of Fig. 8.37.
RF W rd RD, rd 10RD
(8.49)
gm W
and
1
RF
Av = gm(RF rd RD)
so that
(8.50)
(8.51)
RF W rd RD, rd 10RD
Phase Relationship The negative sign for Av reveals that Vo and Vi are out of phase
by 180.
EXAMPLE 8.12 The EMOSFET of Fig. 8.40 was analyzed in Example 7.10, with the
result that k = 0.24 * 103 A>V2, VGSQ = 6.4 V, and IDQ = 2.75 mA.
a.
b.
c.
d.
e.
Determine gm.
Find rd.
Calculate Zi with and without rd. Compare results.
Find Zo with and without rd. Compare results.
Find Av with and without rd. Compare results.
12 V
RD
2 k
Vo
1 F
RF
Vi
1 F
10 M
Zo
ID ( on) = 6 mA
VGS ( on) = 8 V
VGS ( Th) = 3 V
gos = 20 S
Zi
FIG. 8.40
Drainfeedback amplifier from Example 8.11.
Solution:
a. gm = 2k(VGSQ  VGS(Th)) = 2(0.24 * 103 A>V2)(6.4 V  3 V)
= 1.63 mS
1
1
= 50 k
b. rd =
=
gos
20 mS
c. With rd,
RF + rd RD
10 M + 50 k 2 k
Zi =
=
1 + gm(rd RD)
1 + (1.63 mS)(50 k 2 k)
10 M + 1.92 k
=
= 2.42 M
1 + 3.13
Without rd,
RF
10 M
Zi
=
= 2.53 M
1 + gmRD
1 + (1.63 mS)(2 k)
which shows that since the condition rd 10RD = 50 k 40 k is satisfied, the
results for Zo with or without rd will be quite close.
d. With rd,
Zo = RF rd RD = 10 M 50 k 2 k = 49.75 k 2 k
= 1.92 k
Without rd,
Zo RD = 2 k
again providing very close results.
e. With rd,
Av = gm(RF rd RD)
= (1.63 mS)(10 M 50 k 2 k)
= (1.63 mS)(1.92 k)
= 3.21
Without rd,
Av = gmRD = (1.63 mS)(2 k)
= 3.26
which is very close to the above result.
8.11
RD
R1
C1
Vo
D
Zo
Vi
Vi
S
Zi
Vo
+
Zi
R2
RS
CS
R1
Zo
Vgs
R2
gmVgs
rd
RD
FIG. 8.41
EMOSFET voltagedivider configuration.
FIG. 8.42
AC equivalent network for the configuration of Fig. 8.41.
Zi
Zi = R1 R2
(8.52)
Zo = rd RD
(8.53)
Zo
For rd 10RD,
Zo Rd
rd 10RD
(8.54)
Av
Av =
Vo
= gm(rd RD)
Vi
(8.55)
and if rd 10RD,
Av =
8.12
Vo
gm RD
Vi
(8.56)
Design problems at this stage are limited to obtaining a desired dc bias condition or ac
voltage gain. In most cases, the various equations developed are used in reverse to define
the parameters necessary to obtain the desired gain, input impedance, or output impedance. To avoid unnecessary complexity during the initial stages of the design, the approximate equations are often employed because some variation will occur when calculated
resistors are replaced by standard values. Once the initial design is completed, the results
can be tested and refinements made using the complete equations.
Throughout the design procedure be aware that although superposition permits a separate analysis and design of the network from a dc and an ac viewpoint, a parameter chosen
in the dc environment will often play an important role in the ac response. In particular,
recall that the resistance RG could be replaced by a shortcircuit equivalent in the feedback
configuration because IG 0 A for dc conditions, but for the ac analysis, it presents an
important highimpedance path between Vo and Vi. In addition, recall that gm is larger for
operating points closer to the ID axis (VGS = 0 V), requiring that RS be relatively small.
In the unbypassed RS network, a small RS will also contribute to a higher gain, but for the
sourcefollower, the gain is reduced from its maximum value of 1. In total, simply keep
in mind that network parameters can affect the dc and ac levels in different ways. Often a
balance must be made between a particular operating point and its effect on the ac response.
In most situations, the available dc supply voltage is known, the FET to be employed has
been determined, and the capacitors to be employed at the chosen frequency are defined.
It is then necessary to determine the resistive elements necessary to establish the desired
gain or impedance level. The next three examples determine the required parameters for a
specific gain.
EXAMPLE 8.13 Design the fixedbias network of Fig. 8.43 to have an ac gain of 10. That
is, determine the value of RD.
VDD (+30 V)
RD
D
C1
Vi
0.1 F
Vo
IDSS = 10 mA
VP = 4 V
gos = 20 S
G
RG
10 M
FIG. 8.43
Circuit for desired voltage gain in Example 8.13.
1
1
=
= 50 k
gos
20 * 106 S
Substituting, we find
RD rd = RD 50 k = 2 k
RD(50 k)
and
= 2 k
RD + 50 k
or
50RD = 2(RD + 50 k) = 2RD + 100 k
with
48RD = 100 k
100 k
and
RD =
2.08 k
48
The closest standard value is 2 k (Appendix D), which would be employed for this
design.
The resulting level of VDSQ is then determined as follows:
VDSQ = VDD  IDQ RD = 30 V  (10 mA)(2 k) = 10 V
The levels of Zi and Zo are set by the levels of RG and RD, respectively. That is,
Zi = RG = 10 M
Zo = RD rd = 2 k 50 k = 1.92 k RD = 2 k
EXAMPLE 8.14 Choose the values of RD and RS for the network of Fig. 8.44 that will
result in a gain of 8 using a relatively high level of gm for this device defined at VGSQ = 14VP.
VDD
+20 V
RD
C2
Vo
C1
Vi
0V
0.1 F
RL
10 M
0.1 F
RG
10 M
RS
CS
40 F
IDSS = 10 mA
VP = 4 V
gos = 20 S
gm 0 = 5 mS
FIG. 8.44
Network for desired voltage gain in Example 8.14.
so that
8
= 2.13 k
3.75 mS
rd =
and
with the result that
RD = 2.2 k
which is a standard value.
The level of RS is determined by the dc operating conditions as follows:
VGSQ = IDRS
1 V = (5.625 mA)RS
1V
and
RS =
= 177.8
5.625 mA
The closest standard value is 180 . In this example, RS does not appear in the ac design
because of the shorting effect of CS.
In the next example, RS is unbypassed and the design becomes a bit more complicated.
EXAMPLE 8.15 Determine RD and RS for the network of Fig. 8.44 to establish a gain of 8
if the bypass capacitor CS is removed.
Solution: VGSQ and IDQ are still 1 V and 5.625 mA, respectively, and since the equation
VGS = ID RS has not changed, RS continues to equal the standard value of 180 obtained
in Example 8.14.
The gain of an unbypassed selfbias configuration is
gmRD
1 + gmRS
For the moment it is assumed that rd 10(RD + RS). Using the full equation for Av at
this stage of the design would simply complicate the process unnecessarily.
Substituting (for the specified magnitude of 8 for the gain), we obtain
(3.75 mS)RD
(3.75 mS)RD
080 = `
` =
1 + (3.75 mS)(180 )
1 + 0.675
and
8(1 + 0.675) = (3.75 mS)RD
13.4
so that
RD =
= 3.573 k
3.75 mS
with the closest standard value at 3.6 k.
We can now test the condition
rd 10(RD + RS)
We have
50 k 10(3.6 k + 0.18 k) = 10(3.78 k)
and
50 k 37.8 k
which is satisfiedthe solution stands!
Av = 
8.13
SUMMARY TABLE
To provide a quick comparison between configurations and offer a listing that can be helpful for a variety of reasons, Table 8.1 was developed. The exact and approximate equations
for each important parameter are provided with a typical range of values for each. Although
TABLE 8.1
Zi, Zo, and Av for various FET configurations
Configuration
Zi
Zo
Av =
Vo
Vi
Fixedbias
[JFET or DMOSFET]
+VDD
Fixedbias
[JFET or DMOSFET]
RD
Medium (2 k)
C2
Vo
C1
Vi
RG
Zo
RG
Zi
Medium ( 10)
RD r d
RD
(rd 10 RD)
 gm(rd RD)
 gmRD
(rd 10 RD)
V
GG
+
Selfbias
bypassed RS
[JFET or DMOSFET]
+VDD
Selfbias
bypassed RS
[JFET or DMOSFET]
RD
Medium (2 k)
C2
Vo
C1
Vi
RG
Zo
Zi
RG
RS
RD r d
RD
(rd 10 RD)
+VDD
RD
C2
Vo
RG
RD
RG
Zo
Zi
RS
dR
rd D
RS
RD
c 1 + gmRS +
+
d
rd
rd
 gm(rd RD)
 gmRD
(rd 10 RD)
Low ( 2)
c 1 + gmRS +
C1
Vi
CS
Selfbias
unbypassed RS
[JFET or DMOSFET]
Selfbias
unbypassed RS
[JFET or DMOSFET]
Medium ( 10)
rd 10 RD or rd =
gmRD
RD + RS
1 + gmRS +
rd

RS
gmRD
1 + gmRS
3 rd 10 (RD + RS)4
Voltagedivider bias
[JFET or DMOSFET]
+VDD
Voltagedivider bias
[JFET or DMOSFET]
Medium (2 k)
RD
R1
Vo
C1
Vi
Zo
Zi
514
R2
RS
CS
Medium ( 10)
C2
R1 R2
RD r d
RD
(rd 10 RD)
 gm(rd RD)
 gmRD
(rd 10 RD)
TABLE 8.1
(Continued)
Configuration
Zo
Zi
Av =
Commongate
[JFET or DMOSFET]
Medium (+ 10)
+VDD
Commongate
[JFET or DMOSFET]
Low (1 k)
Medium (2 k)
RD
Q1
C1
r d + RD
RS c
d
1 + gmrd
C2
Vi
Vo
RS
Zi
RS
Zo
CS
RG
=
1 +
1
gm
gmRD +
RD r d
RD
RD
rd
RD
rd
(Rd 10 RD)
(rd 10 RD)
Sourcefollower
[JFET or DMOSFET]
gmRD
(rd 10 RD)
Low ( 6 1)
Sourcefollower
[JFET or DMOSFET]
Low (100 k)
+VDD
High (10 M)
C1
Vi
C2
Zi
Vo
Vi
RG
Vo
RG
rd RS 1>gm
RS 1>gm
(rd 10 RS)
RS
Zo
gm(rd RS)
1 + gm(rd RS)
gmRS
1 + gmRS
(rd 10 RS)
Drainfeedback bias
EMOSFET
Medium (1 M)
+VDD
DrainFeedback bias
EMOSFET
RD
RF
Medium (2 k)
RF + r d RD
C2
1 + gm(rd RD)
Vo
C1
Vi
Zo
Zi
RF
1 + gmRD
Medium ( 10)
RF r d RD
 gm(RF rd RD)
RD
 gmRD
(RF, rd 10RD)
(RF, rd 10RD)
(rd 10 RD)
Voltagedivider bias
EMOSFET
Voltagedivider bias
EMOSFET
+VDD
RD
R1
C1
Vi
G
Zo
R2
Medium (10)
Medium (1 M)
Vo
S
Zi
Medium (2 k)
C2
R1 R2
RD r d
RD
(rd 10 RD)
 gm(rd RD)
 gmRD
(rd 10 RD)
RS
515
all the possible configurations are not present, the majority of the most frequently encountered are included. In fact, any configuration not listed will probably be some variation of
those appearing in the table, so at the very least, the listing will provide some insight as to
what expected levels should be and which path will probably generate the desired equations. The format chosen was designed to permit a duplication of the entire table on the
front and back of one 812 by 11 inch page.
8.14
This section will parallel Sections 5.16 and 5.17 of the BJT smallsignal ac analysis chapter dealing with the effect of the source resistance and load resistance on the ac gain of an
amplifier. There are again two approaches to the analysis. One can simply substitute the ac
model for the FET of interest and perform a detailed analysis similar to the unloaded situation, or apply the twoport equations introduced in Section 5.17.
All of the twoport equations developed for the BJT transistor apply to FET networks
also because the quantities of interest are defined at the input and output terminals and
not the components of the system.
A few of the most important equations are repeated below to provide an easy reference
for the analysis of this chapter and to refresh your memory about the conclusions:
AvL =
RL
A
RL + Ro vNL
Ai = AvL
Avs =
Vo
Vi
=
Vs
Vs
Zi
RL
Vo
Ri
RL
= a
ba
bA
Vi
Ri + Rsig RL + Ro vNL
(8.57)
(8.58)
(8.59)
Some of the important conclusions about the gain of BJT transistor configurations are
also applicable to FET networks. They include the following facts:
The greatest gain of an amplifier is the noload gain.
The loaded gain is always less than the noload gain.
A source impedance will always reduce the overall gain below the noload or
loaded level.
In general, therefore,
AvNL 7 AvL 7 AvS
(8.60)
Recall from Chapter 5 that some BJT configurations are such that the output impedance
is sensitive to the source impedance or the input impedance is sensitive to the applied load.
For FET networks, however:
Due to the high impedance between the gate terminal and the channel, one can generally assume that the input impedance is unaffected by the load resistor and the output
impedance is unaffected by the source resistance.
One must always be aware, however, that there are special situations where the above
may not be totally true. Take, for instance, the feedback configuration that results in a direct
connection between input and output networks. Although the feedback resistor is usually
many times that of the source resistance, permitting the approximation that the source
resistance is essentially 0 , it does present a situation where the source resistance could
possibly affect the output resistance or the load resistance could affect the input impedance.
In general, however, due to the high isolation provided between the gate and the drain or
source terminals, the general equations for the loaded gain are less complex than those
encountered for BJT transistors. Recall that the base current provided a direct link between
input and output circuits of any BJT transistor configuration.
To demonstrate each approach, let us examine the selfbias configuration of Fig. 8.45
with a bypassed source resistance. Substituting the ac equivalent model for the JFET results
in the configuration of Fig. 8.46.
VDD
RD
D
C1
Zi
Zo
RL V
o
RG
Vi
RS
CS
Vs
Rsig
C2
FIG. 8.45
JFET amplifier with Rsig and RL.
Note that the load resistance appears in parallel with the drain resistance and the source
resistance Rsig appears in series with the gate resistance R. For the overall voltage gain the
result is a modified form of Eq. (8.21):
AvL =
Vo
= gm(rd RD RL)
Vi
Rsig
+
Vs
(8.61)
+
Zo
Zi
Vi
RG
gmVgs
Vgs
rd
RD
RL
Vo
FIG. 8.46
Network of Fig. 8.45 following the substitution of the ac equivalent circuit for the JFET.
The output impedance is the same as obtained for the unloaded situation without a source
resistance:
Zo = rd RD
(8.62)
Zi = RG
(8.63)
RGVS
RG + Rsig
and
AvS =
Vo
Vi Vo
# = c RG d [gm(rd RD RL)]
=
Vs
Vs Vi
RG + Rsig
(8.64)
(8.65)
If we now turn to the twoport approach for the same network, the equation for the overall
gain becomes
RL
RL
AvL =
AvNL =
[gm(rd RD)]
RL + Ro
RL + Ro
but
Ro = RD rd,
(rd RD)(RL)
RL
so that
AvL =
[gm(rd RD] = gm
(rd + RD) + RL
RL + RD rd
and
AvL = gm(rd RD RL)
matching the previous result.
The above derivation was included to demonstrate that the same result will be obtained
using either approach. If numerical values for Ri, Ro, and AvNLwere available, it would
simply be a matter of substituting the values into Eq. (8.57).
Continuing in the same manner for the most common configurations results in the equations of Table 8.2.
8.15
CASCADE CONFIGURATION
The cascade configuration introduced in Chapter 5 for BJTs can also be used with JFETs
or MOSFETs, as shown for JFETs in Fig. 8.47. Recall that the output of one stage appears
as the input for the following stage. The input impedance for the second stage is the load
impedance for the first stage.
The total gain is the product of the gain of each stage including the loading effects of
the following stage.
Too often, the noload gain is employed and the overall gain is an unrealistic result. For
each stage the loading effect of the following stage must be included in the gain calculations. Using the results of the previous sections of this chapter results in the following
equation for the overall gain of the configuration of Fig. 8.47:
Av = Av1Av2 = (gm1RD1)(gm2RD2) = gm1gm2 RD1RD2
518
FIG. 8.47
Cascaded FET amplifier.
(8.66)
TABLE 8.2
Configuration
AvL Vo Vi
Zi
Zo
 gm(RD RL)
RG
RD
 gm(RD RL rd)
RG
RD r d
 gm(RD RL)
RG
RD
1 + gmRS
+
Vss
Including rd:
1 + gmRS
+
Vs
Including rd:
 gm(RD RL)
RD + RS
1 + gmRS +
rd
RG
 gm(RD RL)
R 1 R2
RD
 gm(RD RL rd)
R 1 R2
RD r d ;
gm(RS RL)
RG
RS 1>gm
RD
1 + gmRS
+
Vs
Including rd:
1 + gm(RS RL)
+
Vs
Including rd:
=
gmrd(RS RL)
RG
+
Vs
Including rd:
gm(RD RL)
RS
1 + gmRS
Zi =
1 +
RS
gmrdRS
RS
gmrdRS
1 +
r d + RD
RD
RD r d
r d + RD RL
519
(8.67)
(8.68)
The main function of cascading stages is the larger overall gain achieved. Since dc bias and
ac calculations for a cascade amplifier follow those derived for the individual stages, an
example will demonstrate the various calculations to determine dc bias and ac operation.
EXAMPLE 8.16 Calculate the dc bias, voltage gain, input impedance, output impedance,
and resulting output voltage for the cascade amplifier shown in Fig. 8.48.
+20 V
2.4 k
2.4 k
Vo
D
0.05 F
Vi
10 mV
IDSS = 10 mA
VP = 4 V
G
0.05 F
IDSS = 10 mA
VP = 4 V
S
3.3 M
680
0.05 F
S
3.3 M
100 F
100 F
680
FIG. 8.48
Cascade amplifier circuit for Example 8.16.
Solution: Both amplifier stages have the same dc bias. Using dc bias techniques from
Chapter 7 results in
VGSQ = 1.9 V,
IDQ = 2.8 mA
gm0 =
2IDSS
0 VP 0
2(10 mA)
= 5 mS
0 4 V 0
VGSQ
VP
b = (5 mS)a 1 
1.9 V
b = 2.6 mS
4 V
TROUBLESHOOTING 521
A combination of FET and BJT stages can also be used to provide high voltage gain and
high input impedance, as demonstrated by the next example.
EXAMPLE 8.17 For the cascade amplifier of Fig. 8.49, use the dc bias calculated in
Examples 5.15 and 8.16 to calculate input impedance, output impedance, voltage gain, and
resulting output voltage.
+20 V
D
Vi
1 mV
C
0.5 F
IDSS = 10 mA
VP = 4 V
0.05 F
Vo
= 200
S
3.3 M
680
2.2 k
0.5 F
15 k
2.4 k
100 F
4.7 k
100 F
1 k
FIG. 8.49
Cascaded JFETBJT amplifier for Example 8.17.
8.16
TROUBLESHOOTING
variety of configurations. For any smallsignal amplifier one might consider the following steps:
1. Look at the circuit board to see if any obvious problems can be seen: an area charred by
excess heating of a component; a component that feels or seems too hot to touch; what
appears to be a poor solder joint; any connection that appears to have come loose.
2. Use a dc meter: make some measurements as marked in a repair manual containing
the circuit schematic diagram and a listing of test dc voltages.
3. Apply a test ac signal: measure the ac voltages starting at the input and work along
toward the output.
4. If the problem is identified at a particular stage, the ac signal at various points should
be checked using an oscilloscope to see the waveform, its polarity, amplitude, and
frequency, as well as any unusual waveform glitches that may be present. In particular, observe that the signal is present for the full signal cycle.
The basic components of a threechannel JFET audio mixer are shown in Fig. 8.50. The
three input signals can come from different sources such as a microphone, a musical instrument, background sound generators, and so on. All signals can be applied to the same gate
terminal because the input impedance of the JFET is so high that it can be approximated by
C1
v1
10 F
R1
1 M
R4
20 V
100 k
R7
3.3 k
C2
C5
v2
vo
D
10 F
R2
1 M
10 F
IDSS = 10 mA
VP = 6 V
R5
100 k
+
S
C3
v3
10 F
vG
R3
1 M
Volume control
R6
100 k
Signalisolation
resistors
R8
1 k
C4
20 F
Preamplifier
gm ~
= 1.5 mS
Av = 4.95
FIG. 8.50
Basic components of a threechannel JFET audio mixer.
an open circuit. In general, the input impedance is 1000 M (109 ) or better for
JFETs and 100 million M (1014 ) or better for MOSFETs. If BJTs were employed
instead of JFETs, the lower input impedance would require a transistor amplifier for each
channel or at least an emitterfollower as the first stage to provide a higher input impedance.
The 10mF capacitors are there to prevent any dc biasing levels on the input signal from
appearing at the gate of the JFET, and the 1M potentiometers are the volume controls for
each channel. The need for the 100k resistors for each channel is less obvious. Their purpose is to ensure that one channel does not load down the other channels and severely reduce
or distort the signal at the gate. For instance, in Fig. 8.51a, one channel has a highimpedance
(10k) microphone, whereas another channel has a lowimpedance (0.5k) guitar amplifier. Channel 3 is left open, and the 100k isolation resistors have been removed for the
moment. Replacing the capacitors by their shortcircuit equivalent for the frequency range of
interest and ignoring the effects of the parallel 1M potentiometers (set at their maximum
value) result in the equivalent circuit of Fig. 8.51b at the gate of the JFET amplifier. Using
the superposition theorem, we determine the voltage at the gate of the JFET by
10 k(vguitar)
0.5 k(vmic)
vG =
+
10.5 k
10.5 k
= 0.047vmic + 0.95vguitar vguitar
PRACTICAL 523
APPLICATIONS
C1
Highimpedance
microphone
10 F
Rm
10 k
1 M
vmic
vG
C2
vG
vG
Lowimpedance
guitar
Rm
10 F
Rg
0.5 k
10 k
Rg
1 M
vmic
Rm
100 k
10 k
Rg
0.5 k
100.5 k
vguitar
100 k
R5
110 k
vguitar
0.5 k
R4
vmic
vguitar
(a)
(b)
(c)
FIG. 8.51
(a) Application of a high and a lowimpedance source to the mixer of Fig. 8.50; (b) reduced equivalent without
the 100k isolation resistors; (c) reduced equivalent with the 100k resistors.
clearly showing that the guitar has swamped the signal of the microphone. The only response of the amplifier of Fig. 8.51 will be to the guitar. Now, with the 100k resistors in
place, the situation of Fig. 8.51c results. Using the superposition theorem again, we obtain
the following equation for the voltage at the gate:
110 k(vguitar)
101 k(vmic)
+
vG =
211 k
211 k
0.48vmic + 0.52vguitar
showing an even balance in the signals at the gate of the JFET. In general, therefore, the
100k resistors compensate for any difference in signal impedance to ensure that
one does not load down the other and develop a mixed level of signals at the amplifier.
Technically, they are often called signal isolation resistors.
An interesting consequence of a situation such as described in Fig. 8.51b is depicted in
Fig. 8.52, where a guitar of low impedance has a signal level of about 150 mV, whereas the
microphone, having a larger internal impedance, has a signal strength of only 50 mV. As
pointed out above, the major part of the signal at the feed point (vG) is that of the guitar.
The resulting direction of current and power flow is unquestionably from the guitar to the
microphone. Furthermore, since the basic construction of a microphone and a speaker
is quite similar, the microphone may be forced to act like a speaker and broadcast the
guitar signal. New acoustic bands often face this problem as they learn the rudiments of
vG
Rm
+
vmic
Rg
is
+
vguitar >> vmic
pmic = vmic is
FIG. 8.52
Demonstrating that for parallel
signals, the channel with the least
internal impedance and most power
controls the situation.
good amplifier basics. In general, for parallel signals, the channel with the least internal
impedance controls the situation.
In Fig. 8.50, the gain of the selfbiased JFET is determined by gmRD, which for this
situation is
gm RD = (1.5 mS)(3.3 k) = 4.95
For some it may come as quite a surprise that a microphone can actually behave like a
speaker. However, the classical example of the use of one voice cone to act as a microphone
and a speaker is in the typical intercom system such as appearing in Fig. 8.53a. The 8 , 0.2 W
speaker of Fig. 8.53b can be used as a microphone or a speaker, depending on the position of
the activation switch. It is important to note, however, as in the microphoneguitar example
above, that most speakers are designed to handle reasonable power levels, but most microphones are designed to simply accept the voiceactivated input, and they cannot handle the
power levels normally associated with speakers. Just compare the size of each in any audio
system. In general, a situation such as described above, where the guitar signal is heard
over the microphone, will ultimately damage the microphone. For an intercom system the
speaker is designed to handle both types of excitation without difficulty.
8, 0.2W
speaker
Proteomics
transformer
0.022F
capacitors
4diode
bridge network
Capacitors
Resistor
banks
120 V power
cord
Slide rheostat
volume control
386D JRC
lowvoltage audio
power amplifier
NXP
HEF4069UB
Hex inverter
Lock
Call
Talk
Volume
control
Channel
selector
LED
power
(a)
LED in use
5670 JRC
LED controller
Switches
(b)
FIG. 8.53
Twostation, two channel intercom: (a) external appearance; (b) internal construction.
(Photos by Dan Trudden/Pearson).
Silent Switching
Any electronic system that incorporates mechanical switching such as shown in Fig.
8.54 is prone to developing noise on the line that will reduce the signaltonoise ratio.
When the switch of Fig. 8.54 is opened and closed, one often gets an annoying pfft, pfft
sound as part of the output signal. In addition, the longer wires normally associated with
RF
Noise
R1
v1
Noise
R2
v2
Mechanical switching
FIG. 8.54
Noise development due to mechanical switching.
vo
PRACTICAL 525
APPLICATIONS
mechanical switches will require that the switch be as close to the amplifier as possible to
reduce the noise pickup on the line.
One effective method to essentially eliminate this source of noise is to use electronic
switching such as shown in Fig. 8.55a for a twochannel mixing network. Recall from
Chapter 7 that the drain to source of a JFET for low values of VDS can be looked on as a
R1
RF
RDS
47 k
47 k
v1
vo
741
Q1
1 M
vo =
ON = 0 V
OFF = 10 V
47 nF
47 k
RF
v
R1 i
Q1, Q2 = 2N3819
v2
Q2
1 M
ON = 0 V
OFF = 10 V
47 nF
(a)
RDS1
v1
47 k
100
47 k
47 k
47.1 k
RDS2
v2
RF
vTh = 1 v1 + 1 v2
2
2
RTh
vTh
~ 23.5 k
=
47.1 k
100
v1
vo =
v2
RF
v
RTh i
47 k
1 v + 1v
( 23.5
k ) ( 2 1 2 2 )
= 2 ( 1 v1 + 1 v2 )
2
2
=
Thvenin
vTh = 1 v1 + 1 v2
2
2
~ 23.5 k
RTh = 47.1 k =
2
vo = v1 v2
or vo = (v1 + v2)
(b)
RF
47 k
R1 = 47.1 k
47 k
v1
RDS1
100
vo
v2
47 k
RF
47 k
~ v
= v
vo = v
=
i
47.1 k i
R1 i
(c)
FIG. 8.55
Silent switching audio network: (a) JFET configuration; (b) with both signals present; (c) with one signal on.
vo
PhaseShift Networks
Using the voltagecontrolled draintosource resistance characteristic of a JFET, we can
control the phase angle of a signal using the configurations of Fig. 8.57. The network of
Fig. 8.57a is a phaseadvance network, which adds an angle to the applied signal,
whereas the network of Fig. 8.57b is a phaseretard configuration, which creates a negative phase shift.
PRACTICAL 527
APPLICATIONS
FIG. 8.56
Specification sheet for a lowcost analog
JFET current switch.
(Copyright of Semiconductor Components Industries, LLC. Used by permission.)
RDS
+
vi
D
G
Control
RDS
VGS
vo
+
vi
VGS
C
vo
Control
(b)
(a)
FIG. 8.57
Phaseshift networks: (a) advance; (b) retard.
For example, let us consider the effect of RDS on an input signal having a frequency such
as 10 kHz if we apply it to the network of Fig. 8.57a. For discussion, let us assume that
the draintosource resistance is 2 k due to an applied gatetosource voltage of 3 V.
Drawing the equivalent network results in the general configuration of Fig. 8.58. Solving
for the output voltage results in
RDS0 Vi0
RDSVi0
Vo =
=
XC
RDS  j XC
2
2RDS
+ X C2  tan1
RDS
RDSVi
R
X
XC
C
DS
=
tan1
= a
b Vi tan1
2
2
RDS
RDS
2RDS
+ XC2
2RDS
+ X C2
so that
Vo = k1Vi u1
where
k1 =
RDS
2
2R DS +
X C2
and u1 = tan1
XC
RDS
(8.69)
and
k1 =
with
u1 = tan1
X 2C
2 k
= 0.782
XC
1.592 k
= tan1 0.796 = 38.52
= tan1
RDS
2 k
Vo = 0.782Vi 38.52
so that
and an output signal that is 78.2% of its applied signal but with a phase shift of 38.52.
vi
Vi
+
180
90
vo
360
RDS
Vi
0.78Vi
0.01 F
2 k Vo
180
180
360
38.52
FIG. 8.58
RC phaseadvance network.
In general, therefore, the network of Fig. 8.57a can introduce a positive phase shift extending from a few degrees (with XC relatively small compared to RDS) to almost 90 (with
XC relatively large compared to RDS). Keep in mind, however, that for fixed values of RDS,
as the frequency increases, XC will decrease and the phase shift will approach 0. For decreasing frequencies and a fixed RDS, the phase shift will approach 90. It is also important
to realize that for a fixed RDS, an increasing level of XC results in diminishing magnitude for
Vo. For such a network, a balance between gain and desired phase shift will have to be made.
For the network of Fig. 8.57b, the resulting equation is
Vo = k2Viu2
(8.70)
where
k2 =
XC
2
2RDS
XC2
and
u2 = tan1
RDS
XC
PRACTICAL 529
APPLICATIONS
MotionDetection System
The basic components of a passive infrared (PIR) motiondetection system are shown in
Fig. 8.59. The heart of the system is the pyroelectric detector, which generates a voltage
that varies with the amount of incident heat. It filters out all but the infrared radiation
from a particular area and focuses the energy onto a temperaturesensing element. Recall
from Chapter 7, Section 7.13, that the infrared band is a nonvisible band just below the
visible light spectrum. Passive detectors do not emit a signal of any kind but simply
respond to the energy flow of the environment.
VDD
RD
Lowfrequency
amplifier
Comparator
network
RG
vS
RS
Infrared
heat
Parabolic
optical
filter
Pyroelectric
element
FIG. 8.59
Passive infrared (PIR) motiondetection system.
An external and an internal view of a commercially available unit are provided in Fig.
8.60a and b, respectively. Four interchangeable lens are provided for different coverage
areas. For our purposes the pet option was selected with the coverage indicated in Fig.
8.60c. The unit is mounted at a height of 76 and operates at a dc voltage of 8.5 V to 15.4 V,
drawing a current of 17 mA at 12 V dc. The range of coverage is 35 perpendicular to the
sensor and 20 to each side. In the lowest sensitivity setting the combined weight of the
animals cannot exceed 80 lbs.
To focus the incident ambient heat on the pyroelectric detector, the unit of Fig. 8.60
uses a parabolic deflector. As a person walks past a sensor, he or she will cut the various
fields appearing in Fig. 8.60c, and the detector will sense the rapid changes in heat level.
The result is a changing dc level akin to a lowfrequency ac signal of relatively high
internal impedance appearing at the gate of the JFET. One might then ask why turning
a heating system on or turning on a lamp doesnt generate an alarm signal since heat will be
generated. The answer is that both will generate a voltage at the detector that grows steadily
with increasing heat level from the heating system or the burning bulb. Remember that for
the lamp, the detector is heat sensitive and not light sensitive. The resulting voltage is not
oscillating between levels, but simply climbing in level and will not set off the alarma
varying ac voltage will not be generated by the pyroelectric detector!
Note in Fig. 8.59 that a JFET sourcefollower configuration was employed to ensure
a very high input impedance to capture most of the pyroelectric signal. It is then passed
through a lowfrequency amplifier, followed by a peakdetecting network and a comparator
to determine whether the alarm should be set off. The dc voltage comparator is a network
that captures the peak value of the generated ac voltage and compares it to a known dc
voltage level. The output processor determines whether the difference between the two
levels is sufficient to tell the driver to energize the alarm.
Controller/
driver
network
Alarm
system,
counter,
light
control,
etc.
Wideangle
lens
IC providing
bus protection
100 F
capacitor
IR
Detector
47 F
capacitors
LED
display
Control settings
DIP switch
A4
microprocessor
Voltage
regulator
MOSFET optical
solidstate relay
LED
For external
wiring
0.01 F
capacitors
(b)
(a)
DETECTION PATTERNS
Top View
Wide Angle Pet Immune Lens
20'
7'
13'
20'
27'
35'
1
2
13'
12
7'
18
19
7'
20
13
5
Side View
Pet Immune Lens
14
6
15
7'
0
LookDown* Lower
1820
13'
20'
Intermediate
1217
27'
35'
Long
111
16
8
13'
7'6''
17
(c)
9
10
11
20'
FIG. 8.60
Commercially available PIR motiondetection unit: (a) external appearance; (b) internal construction; (c) pet option coverage.
[Photos (a) and (b) by Dan Trudden/Pearson.]
8.18 SUMMARY
Important Conclusions and Concepts
7. The voltage gain for the fixedbias and selfbias JFET configurations (with a bypassed
source capacitance) is the same.
8. The ac analysis of JFETs and depletiontype MOSFETs is the same.
9. The ac equivalent network for an enhancementtype MOSFET is the same as that
employed for JFETs and depletiontype MOSFETs. The only difference is the equation for gm.
10. The magnitude of the gain of FET networks is typically between 2 and 20. The selfbias configuration (without a bypass source capacitance) and the sourcefollower
are lowgain configurations.
11. There is no phase shift between input and output for the sourcefollower and commongate configurations. Most others have a 180 phase shift.
12. The output impedance for most FET configurations is determined primarily by RD.
For the sourcefollower configuration it is determined by RS and gm.
13. The input impedance for most FET configurations is quite high. However, it is quite
low for the commongate configuration.
14. When troubleshooting any electronic or mechanical system, always check the
most obvious causes first.
Equations
gm = yfs =
gm0 =
ID
VGS
2IDSS
0 VP 0
gm = gm0 c 1 
VGS
d
VP
ID
A IDSS
VDS
1
rd =
=
`
yos
ID VGS = constant
gm = gm0
For JFET and depletiontype MOSFET configurations, see Tables 8.1 and 8.2.
IDSS
0 VP 0
10 mA
= 0.625 mA>V2
42V2
and is inserted in the Edit Model dialog box obtained by the sequence EDITPROPERTIES.
Vto is also changed to 4 V. The remaining elements of the network are set as described
for the transistor in Chapter 5.
An analysis of the network results in the printout of Fig. 8.62. The CIRCUIT
DESCRIPTION includes all the elements of the network along with their assigned nodes.
In particular, note that Vi is set at 10 mV at a frequency of 10 kHz and a phase angle of 0
****
CIRCUIT DESCRIPTION
************************************************************************************************
*Analysis directives:
.AC LIN 1 10kHz 10kHz
.OP
.PROBE V(alias(*)) I(alias(*)) W(alias(*)) D(alias(*)) NOISE(alias(*))
.INC "..\SCHEMATIC1.net"
**** INCLUDING SCHEMATIC1.net ****
* source ORCAD 81
V_Vi
N00344 0 AC 10mV
+SIN 0 10mV 10kHz 0 0 0
C_C1
N00344 N00351 0.02uF TC=0,0
C_C2
N00315 N00326 2uF TC=0,0
R_RG
N00358 N00351 10Meg TC=0,0
R_RD
N00315 N00303 2k TC=0,0
R_RL
0 N00326 10Meg TC=0,0
V_VDD
N00303 0 20Vdc
V_VGG
0 N00358 1.5Vdc
J_J1
N00315 N00351 0 J2N3819
.PRINT
AC
+ VM([N00344])
.PRINT
AC
+ VM([N00351])
.PRINT
AC
+ VM([N00315])
.PRINT
AC
+ VM([N00326])
.END
****
Junction FET MODEL PARAMETERS
************************************************************************************************
J2N3819
NJF
VTO
4
BETA
625.000000E06
LAMBDA
2.250000E03
IS
33.570000E15
ISR 322.400000E15
ALPHA
311.700000E06
VK 243.6
RD
1
RS
1
CGD
1.600000E12
CGS
2.414000E12
M
.3622
VTOTC
2.500000E03
BETATCE
.5
KF
9.882000E18
****
SMALL SIGNAL BIAS SOLUTION
TEMPERATURE =
27.000 DEG C
************************************************************************************************
NODE
VOLTAGE
NODE
VOLTAGE
NODE
VOLTAGE
(N00303)
20.0000
(N00315) 12.0020
(N00326)
0.0000
(N00344)
0.0000
(N00351) 1.5000
(N00358) 1.5000
VOLTAGE SOURCE CURRENTS
NAME
CURRENT
V_Vi
0.000E+00
V_VDD
3.999E03
V_VGG
1.366E12
FIG. 8.61
Fixedbias JFET configuration with an ac source.
****
OPERATING POINT INFORMATION
TEMPERATURE = 27.000 DEG C
************************************************************************************************
**** JFETS
NAME
J_J1
MODEL
J2N3819
ID
4.00E03
VGS
1.50E+00
VDS
1.20E+01
GM
3.20E03
GDS
8.76E06
CGS
1.73E12
CGD
6.07E13
****
AC ANALYSIS
TEMPERATURE =
27.000 DEG C
************************************************************************************************
FREQ
VM(N00344)
1.000E+04 1.000E02
FREQ
VM(N00351)
1.000E+04 9.997E03
FREQ
VM(N00315)
1.000E+04 6.275E02
FREQ
VM(N00326)
1.000E+04 6.275E02
FIG. 8.62
Output file for the network of Fig. 8.61.
degrees. In the following list of Junction FET MODEL PARAMETERS note that VTO
is 4 V and BETA is 625E6 A>V2 0.625 mA>V2, as entered earlier. The SMALL
SIGNAL BIAS SOLUTION reveals that the voltage at both ends of RG is 1.5 V, resulting in VGS 1.5 V. The voltage levels of this section can be related to the original
network by simply noting the assigned node list in the CIRCUIT DESCRIPTION. The
voltage from drain to source (ground) is 12 V, leaving a drop of 8 V across RD. The AC
ANALYSIS listing reveals that the voltage at the source (N01707) is 10 mV as set, but the
voltage at the other end of the capacitor is 3 mV less due to the impedance of the capacitor
at 10 kHzcertainly a drop to be ignored. The choice of 0.02 mF for this frequency was
obviously a good one. The voltages before and after the capacitor on the output side are
exactly the same (to three places), revealing that the larger the capacitor, the closer are the
characteristics to those of a short circuit. The output of 6.275E2 62.75 mV reflects a
gain of 6.275.
FIG. 8.63
JFET voltagedivider configuration with an ac source.
To run the analysis, select the New Simulation Profile key to obtain the New Simulation dialog box. After entering Name of OrCAD 82, select Create, and the Simulation
Settings dialog box will appear. Under Analysis type, select AC/Sweep/Noise, and then
under AC Sweep choose Linear. The Start Frequency is 5 kHz, the End Frequency is
5 kHz and the Total Points is 1. An OK, and the simulation can be initiated by selecting
the Run PSpice key. A schematic will appear, which can be exited to result in the display
of Fig. 8.63 with all the voltage levels displayed as controlled by the V option. The resulting dc levels reveal that VGS is 1.823 V 3.635 V 1.812 V, comparing very well with
the 1.8 V calculated in Example 7.4. VD is 10.18 V, compared to the calculated level of
10.24 V, and VDS is 10.18 V 3.635 V 6.545 V, compared to 6.64 V.
For the ac solution, we can select ViewOutput File and find under OPERATING POINT
INFORMATION that gm is 2.22 mS, comparing very well with the handcalculated value of
2.2 mS, and under AC ANALYSIS that the output ac voltage is 125.8 mV, resulting in a gain of
125.8 mV24 mV 5.24. The handcalculated level is gmRD = (2.2 mS)(2.4 k) = 5.28.
The ac waveform for the output voltage can be obtained by returning to the Simulation Settings dialog box and under Analysis type choosing Time Domain (Transient). Then, since
the period of a 5kHz signal is 200 ms, select a Run to time of 1 ms, so that five cycles of the
waveform will appear. Leave the Start saving data after option at 0 s, and under Transient
options enter a Maximum step size of 2 ms, so that we have at least 100 plot points for each
cycle of the waveform. An OK, and the SCHEMATIC screen will appear. Select TraceAdd TraceV(J1:d) and the waveform at the bottom of Fig 8.64 appears. If you then choose
FIG. 8.64
The ac drain and gate voltage for the voltagedivider JFET
configuration of Fig. 8.63.
FIG. 8.65
Design Center network for analyzing cascaded JFET amplifiers.
****
CIRCUIT DESCRIPTION
**************************************************************************************
*Libraries:
* Profile Libraries :
* Local Libraries :
.LIB "../../../orcad 83pspicefiles/orcad 83.lib"
* From [PSPICE NETLIST] section of C:\OrCAD\OrCAD_16.3_Demo\tools\PSpice\PSpice.ini file:
.lib "nomd.lib"
*Analysis directives:
.AC LIN 1 10kHz 10kHz
.OP
.PROBE V(alias(*)) I(alias(*)) W(alias(*)) D(alias(*)) NOISE(alias(*))
.INC "..\SCHEMATIC1.net"
**** INCLUDING SCHEMATIC1.net ****
* source ORCAD 83
J_J1
N00328 N00336 N00332 J2N3819
J_J2
N00340 N00416 N00344 J2N3819
V_VDD
N00308 0 20Vdc
R_RD1
N00328 N00308 2.4k TC=0,0
R_RS1
0 N00332 680 TC=0,0
R_RG1
0 N00336 3.3Meg TC=0,0
R_RD2
N00340 N00308 2.4k TC=0,0
R_RS2
0 N00344 680 TC=0,0
R_RG2
0 N00416 3.3Meg TC=0,0
R_RL
0 N00361 10k TC=0,0
C_C1
N01393 N00336 0.05uF TC=0,0
C_C2
N00328 N00416 0.05uF TC=0,0
C_C3
N00340 N00361 0.05uF TC=0,0
C_CS1
0 N00332 100uF TC=0,0
C_CS2
0 N00344 100uF TC=0,0
.PRINT
AC
+ VM([N00361])
.PRINT
AC
+ VM([N00328])
V_Vi
N01393 0 DC 0Vdc AC 10mV
**** RESUMING "OrCAD 83.cir" ****
.END
****
Junction FET MODEL PARAMETERS
**************************************************************************************
J2N3819
NJF
VTO
4
BETA 625.000000E06
FIG. 8.66
Display of resulting JFET model definition.
****
SMALL SIGNAL BIAS SOLUTION
TEMPERATURE =
27.000 DEG C
**************************************************************************************
NODE
VOLTAGE
NODE
VOLTAGE
NODE
VOLTAGE NODE
VOLTAGE
(N00308) 20.0000
(N00328) 13.3270
(N00332) 1.8908
N00336) 50.28E06
(N00340) 13.3270
(N00344)
1.8908
(N00361) 0.0000
(N00416) 50.28E06
(N01393)
0.0000
VOLTAGE SOURCE CURRENTS
NAME
CURRENT
V_VDD
5.561E03
V_Vi
0.000E+00
****
OPERATING POINT INFORMATION
TEMPERATURE =
27.000 DEG C
**************************************************************************************
**** JFETS
NAME
J_J1
J_J2
MODEL
J2N3819
J2N3819
ID
2.78E03
2.78E03
VGS
1.89E+00 1.89E+00
VDS
1.14E+01 1.14E+01
GM
2.64E03
2.64E03
GDS
0.00E+00 0.00E+00
CGS
0.00E+00 0.00E+00
CGD
0.00E+00 0.00E+00
****
AC ANALYSIS
TEMPERATURE =
27.000 DEG C
**************************************************************************************
FREQ
VM(N00361)
1.000E+04 3.226E01
****
AC ANALYSIS
TEMPERATURE =
27.000 DEG C
**************************************************************************************
FREQ
VM(N00328)
1.000E+04 6.323E02
FIG. 8.67
PSpice output for the network of Fig. 8.65.
for the second stage is 322.6 mV>63.23 mV 5.1. The gains and output voltage are very
close to the results obtained in Example 8.1.
In Fig. 8.67 the V option is selected to obtain the dc levels of the network. In particular,
note how close the gate voltages are to 0 V, ensuring that the gatetosource bias voltage is
essentially the same as that across the source resistor. In fact, due to the isolation offered
by the C2 capacitor, the bias levels of each configuration are exactly the same.
Multisim
The ac gain for the JFET selfbias network of Fig. 8.68 will now be determined using Multisim. The entire procedure for setting up the network and obtaining the desired readings
was described for BJT ac networks in Chapter 5. This particular network will appear again
535
FIG. 8.68
Analysis of a JFET selfbias network using Multisim.
in Chapter 9 as Fig. 9.70 when we turn our attention to the frequency response of a loaded
JFET amplifier. A detailed analysis is provided in Chapter 9, including determining the dc
levels, the value of gm, and the loaded gain. The drain current of Example 9.12 is 2 mA,
resulting in a drain voltage of 10.6 V and a source voltage of 2 V, which compare very well
with the 10.594 V and 2.0 V respectively, of Fig. 8.68. When a load such as RL is added to
the network, it will appear in parallel with RD of the network, changing the gain equation
to gmRD RL. For Example 9.12, gm is 2 mS, resulting in a gain Vo > Vi of (2 mS)
(2.2 k 4.7 k) = 2.997. The meters of Fig. 8.68 provide the effective values of the
voltages at those points. Since we used a power source, the reading of the meter XMM1 is
very close to that of the applied source. The difference is due solely to the ac drop of voltage across Rsig and CG. The magnitude of the ac gain (Vo > Vi) of the configuration is
2.042 mV>0.699 mV 2.921, which is very close to the handcalculated solution.
PROBLEMS
Note: Asterisks indicate more difficult questions.
8.2
gos = 25 mS
PROBLEMS 537
ID (mA)
10
9
8
7
6
5
4
3
2
1
5
VGS (V)
FIG. 8.69
JFET transfer characteristic for Problem 11.
11. Using the transfer characteristic of Fig. 8.69:
a. What is the value of gm0?
b. Determine gm at VGS =  0.5 V graphically.
c. What is the value of gm at VGSQ =  0.5 V using Eq. (8.6)? Compare with the solution to
part (b).
d. Graphically determine gm at VGS =  1 V.
e. What is the value of gm at VGSQ =  1 V using Eq. (8.6)? Compare with the solution to
part (d).
12. Using the drain characteristic of Fig. 8.70:
a. What is the value of rd for VGS = 0 V?
b. What is the value of gm0 at VDS = 10 V?
ID (mA)
10
VGS = 0 V
9
8
7
6
1 V
5
4
3
2 V
3 V
1
0
4 V
10 11 12 13 14 15 16 17 18 19 20
VDS (V)
FIG. 8.70
JFET drain characteristic for Problem 12.
13. For a 2N4220 nchannel JFET [gfs(minimum) = 750 mS, gos(maximum) = 10 mS]:
a. What is the value of gm?
b. What is the value of rd?
14. a. Plot gm versus VGS for an nchannel JFET with IDSS = 12 mA and VP =  6 V.
b. Plot gm versus ID for the same nchannel JFET as part (a).
15. Sketch the ac equivalent model for a JFET if gfs = 5.6 mS and gos = 15 mS.
16. Sketch the ac equivalent model for a JFET if IDSS = 10 mA, VP =  4 V, VGSQ =  2 V, and
gos = 25 mS.
+18 V
RD
1.8 k
Vo
Vo
IDSS = 10 mA
VP = 4 V
Zo
Vi
4.7 k
10 V
Zo
1 M
Zi
RG
Vi
1.5 V
Zi
FIG. 8.71
Fixedbias amplifier for Problems 17 and 18.
8.4
2.5 V
2 M
FIG. 8.72
Problem 19.
SelfBias Configuration
20. Determine Zi, Zo, and Av for the network of Fig. 8.73 if gfs = 3000 mS and gos = 50 ms.
21. Determine Zi, Zo, and Av for the network of Fig. 8.73 if the 20@mF capacitor is removed and the
parameters of the network are the same as in Problem 20. Compare results with those of
Problem 20.
22. Repeat Problem 20 if gos is 10 mS. Compare the results to those of Problem 20.
23. a. Find the value of RS to obtain a voltage gain of 2 for the network of Fig. 8.74 using rd .
b. Repeat part (a) with rd 30 k. What was the impact of the change in rd on the gain and
the analysis?
+12 V
16 V
RD
3.3 k
2.7 k
Vo
Vo
C2
Vi
Zo
C1
Zi
IDSS = 9 mA
VP = 8 V
Vi
1 M
10 M
1.1 k
CS
20 F
FIG. 8.73
Problems 20, 21, 22, and 59.
RS
FIG. 8.74
Problem 23.
24. Determine Zi, Zo, and Av for the network of Fig. 8.75 if IDSS = 6 mA, VP =  6 V, and
gos = 40 mS.
+20 V
PROBLEMS 539
20 V
2 k
2 k
82 M
Vo
Vo
C2
IDSS = 12 mA
VP = 3 V
rd = 50 k
Vi
Vi
Zo
C1
Zi
1 M
Zi
11 M
Zo
CS
FIG. 8.76
Problems 25 to 28 and 61.
FIG. 8.75
Selfbias configuration for Problems 24 and 60.
8.5
RS
610
VoltageDivider Configuration
25. Determine Zi, Zo, and Vo for the network of Fig. 8.76 if Vi = 20 mV.
26. Repeat Problem 25 with the capacitor CS removed and compare results.
27. Repeat Problem 25 if rd = 20 k and compare results.
28. Repeat Problem 26 if rd = 20 k and compare results.
8.6
29. Determine Zi, Zo, and Vo for the network of Fig. 8.77 if Vi = 4 mV.
30. Repeat Problem 29 if rd = 20 k and compare results.
31. Determine Zi, Zo, and Av for the network of Fig. 8.78 if rd = 30 k.
+22 V
+15 V
91 M
3.3 k
2.2 k
Vi
Vi
Vo
Vo
Zi
IDSS = 8 mA
VP = 2.8 V
rd = 40 k
1.5 k
Zo
Zi
Zo
1 k
11 M
FIG. 8.77
Problems 29, 30, and 62.
8.7
IDSS = 7.5 mA
VP = 4 V
FIG. 8.78
Problem 31.
32. Determine Zi, Zo, and Av for the network of Fig. 8.79.
33. Repeat Problem 32 if rd = 20 k and compare results.
34. Determine Zi, Zo, and Av for the network of Fig. 8.80.
20 V
+20 V
3.3 k
IDSS = 9 mA
VP = 4.5 V
rd = 40 k
Vi
Zi
Vo
10 M
2.2 k
FIG. 8.79
Problems 32 and 33.
Zo
IDSS = 6 mA
VP = 6 V
rd = 50 k
Vi
Zi
Vo
10 M
3.3 k
FIG. 8.80
Problem 34.
Zo
Vo
Vo
IDSS = 8 mA
VP = 3 V
IDSS = 12 mA
VP = 3.5 V
Vi
Zi
Vi = 2 mV
10 M
10 M
Zo
100
FIG. 8.82
Problems 36, 37, and 63.
FIG. 8.81
Problem 35.
Vo
Vi
IDSS = 12 mA
VP = 3 V
rd = 45 k
91 M
gfs = 35 S
gos = 6000 S
Vi
Vo
15 M
Zi
10 M
3.3 k
1.1 k
FIG. 8.83
Problem 38.
Zo
FIG. 8.84
Problem 39.
Vi
Zi
FIG. 8.85
Problems 41, 42, and 64.
PROBLEMS 541
44. Determine Vo for the network of Fig. 8.86 if Vi = 4 mV, VGS(Th) = 4 V, and ID(on) = 4 mA,
with VGS(on) = 7 V and gos = 20 mS.
+20 V
10 k
22 M
Vo
VGS(Th) = 3.5 V
k = 0.3 103
gos = 30 S
Vi
FIG. 8.86
Problems 43 and 44.
8.11
45. Determine the output voltage for the network of Fig. 8.87 if Vi = 0.8 mV and rd = 40 k.
30V
3.3 k
40 M
+
VGS(Th) = 3 V
k = 0.4 10 3
Vo
Vi
10 M
1.2 k
FIG. 8.87
Problem 45.
RD
Vo
IDSS = 8 mA
VP = 2.5 V
yos = 20 S
Vi
10 M
Vo
IDSS = 12 mA
VP = 3 V
rd = 40 k
Vi
10 M
RS
FIG. 8.88
Problem 46.
FIG. 8.89
Problem 47.
2.7 k
10 F
Vo
Rsig
Vi
0.6 k
IDSS = 10 mA
VP = 6 V
10 F
Zo
Vs
1 M
Zi
4.7 k
20 F
0.51 k
RL
FIG. 8.90
Problem 48.
Rsig
8.2 F
IDSS = 6 mA
VP = 6 V
Vi
0.5 k
Vo
+
Vs
2 M
8.2 F
3.3 k
Zi
Zo
2.2 k
FIG. 8.91
Problem 49.
50. For the commongate configuration of Fig. 8.92:
a. Determine AvNL, Zi, and Zo.
b. Sketch the twoport model of Fig. 5.75 with the parameters determined in part (a) in place.
c. Determine AvL and Avs.
d. Change RL to 2.2 k and calculate AvL and Avs. What was the effect of changing RL on the
voltage gains?
PROBLEMS 543
18 V
3.3 k
5.6 F
Vo
IDSS = 5 mA
VP = 4 V
Rsig
5.6 F
Zo
Vi
4.7 k
0.5 k
Vs
Zi
1.2 k
FIG. 8.92
Problem 50.
e. Change Rsig to 0.1 k (with RL at 4.7 k) and calculate AvL and Avs. What was the effect of
changing Rsig on the voltage gains?
f. Change RL to 2.2 k and Rsig to 0.1 k and calculate Zi and Zo. What was the effect on both
parameters?
g. What general conclusions can you draw from the above calculations?
8.15
Cascade Configuration
51. For the JFET cascade amplifier in Fig. 8.93, calculate the dc bias conditions for the two identical stages, using JFETs with IDSS = 8 mA and VP =  4.5 V.
52. For the JFET cascade amplifier of Fig. 8.93, using identical JFETs with IDSS = 8 mA and
VP =  4.5 V, calculate the voltage gain of each stage, the overall gain of the amplifier, and
the output voltage Vo.
53. If both JFETs in the cascade amplifier of Fig. 8.93 are changed to those having specifications
IDSS = 12 mA and VP =  3 V, calculate the resulting dc bias of each stage.
54. If both JFETs in the cascade amplifier of Fig. 8.93 are changed to those having the specifications IDSS = 12 mA, VP =  3 V, and gos = 25 mS, calculate the resulting voltage gain for
each stage, the overall voltage gain, and the output voltage, Vo.
Vo
Vi
20 mV
FIG. 8.93
Problems 51 to 55, 65, and 66.
55. For the cascade amplifier of Fig. 8.93, using JFETs with specifications IDSS = 12 mA,
VP =  3 V, and gos = 25 mS, calculate the circuit input impedance (Zi) and output impedance (Zo).
56. For the cascade amplifier of Fig. 8.94, calculate the dc bias voltages currents of each stage.
57. For the amplifier circuit of Fig. 8.94, calculate the voltage gain of each stage and the overall
amplifier voltage gain.
58. Calculate the input impedance (Zi) and output impedance (Zo) for the amplifier circuit of
Fig. 8.94.
FIG. 8.94
Problems 56 to 58.
8.19
Computer Analysis
59. Using PSpice Windows, determine the voltage gain for the network of Fig. 8.73.
60. Using Multisim, determine the voltage gain for the network of Fig. 8.75.
61. Using PSpice Windows, determine the voltage gain for the network of Fig. 8.76.
62. Using Multisim, determine the voltage gain for the network of Fig. 8.77.
63. Using PSpice Windows, determine the voltage gain for the network of Fig. 8.82.
64. Using PSpice Windows, determine the voltage gain for the network of Fig. 8.85.
*65. Use the Design Center to draw a schematic circuit of the cascade JFET amplifier as in Fig.
8.93. Set the JFET parameters for IDSS 12 mA and VP = 3 V, and have the analysis determine the dc bias.
*66. Use the Design Center to draw a schematic circuit for a cascade JFET amplifier as shown
in Fig. 8.93. Set the analysis to calculate the ac output voltage Vo for IDSS 12 mA and
VP 3 V.
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