Beruflich Dokumente
Kultur Dokumente
Dual Synchronous,
400mA/800mA, 2.25MHz
Step-Down DC/DC Regulator
FEATURES
DESCRIPTION
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APPLICATIONS
PDAs/Palmtop PCs
Digital Cameras
Cellular Phones
Portable Media Players
PC Cards
Wireless and DSL Modems
TYPICAL APPLICATION
LTC3548 Efciency Curve
VIN = 2.8V
TO 5.5V
100
RUN2
VIN
MODE/SYNC
RUN1
100k
POR
RESET
4.7H
VOUT1 = 1.8V
AT 800mA
33pF
280k
GND
10
80
POWER LOSS
75
70
VFB1
VFB2
887k
4.7F
2.2H
SW1
SW2
68pF
100
EFFICIENCY
85
604k
301k
60
3548 TA01
65
10F
90
LTC3548
VOUT2 = 2.5V
AT 400mA
1000
95
EFFICIENCY (%)
10F
10
100
LOAD CURRENT (mA)
0.1
1000
3548 TA02
3548fa
LTC3548
ABSOLUTE MAXIMUM RATINGS
(Note 1)
PIN CONFIGURATION
TOP VIEW
10 VFB2
VFB1
RUN1
VIN
SW1
7 SW2
GND
6 MODE/
SYNC
TOP VIEW
9 RUN2
11
VFB1
RUN1
VIN
SW1
GND
8 POR
1
2
3
4
5
11
10
9
8
7
6
VFB2
RUN2
POR
SW2
MODE/
SYNC
DD PACKAGE
10-LEAD (3mm 3mm) PLASTIC DFN
MSE PACKAGE
10-LEAD PLASTIC MSOP
ORDER INFORMATION
LEAD FREE FINISH
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC3548EDD#PBF
LTC3548EDD#TRPBF
LBNJ
40C to 85C
LTC3548IDD#PBF
LTC3548IDD#TRPBF
LBNJ
40C to 85C
LTC3548EMSE#PBF
LTC3548EMSE#TRPBF
LTBNH
40C to 85C
LTC3548IMSE#PBF
LTC3548IMSE#TRPBF
LTBNH
40C to 85C
Consult LTC Marketing for parts specied with wider operating temperature ranges. *The temperature grade is identied by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based nish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specications, go to: http://www.linear.com/tapeandreel/
ELECTRICAL CHARACTERISTICS
The denotes the specications which apply over the full operating
temperature range, otherwise specications are at TA = 25C. VIN = 3.6V, unless otherwise specied. (Note 2)
SYMBOL
PARAMETER
CONDITIONS
VIN
l
l
IFB
VFB
0C TA 85C
40C TA 85C
VLINE REG
MIN
TYP
2.5
0.588
0.585
MAX
UNITS
5.5
30
nA
0.6
0.6
0.612
0.612
V
V
0.3
0.5
%V
3548fa
LTC3548
ELECTRICAL CHARACTERISTICS
The denotes the specications which apply over the full operating
temperature range, otherwise specications are at TA = 25C. VIN = 3.6V, unless otherwise specied. (Note 2)
SYMBOL
PARAMETER
CONDITIONS
MIN
VLOAD REG
(Note 3)
0.5
IS
700
40
0.1
950
60
1
A
A
A
VFB = 0.6V
2.25
2.7
MHz
fOSC
Oscillator Frequency
fSYNC
Synchronization Frequency
ILIM
RDS(ON)
ISW(LKG)
POR
TYP
1.8
MAX
2.25
0.95
0.6
UNITS
MHz
1.2
0.7
1.6
0.9
A
A
(Note 6)
(Note 6)
0.35
0.30
0.45
0.45
0.01
8.5
100
200
262,144
VRUN
RUN Threshold
IRUN
IL
500mA/DIV
ILOAD
500mA/DIV
IL
200mA/DIV
3548 G01
1.5
VOUT
200mV/DIV
VOUT
10mV/DIV
IL
200mA/DIV
1
0.01
Load Step
SW
5V/DIV
VOUT
20mV/DIV
Cycles
SW
5V/DIV
0.3
Note 3: The LTC3548 is tested in a proprietary test mode that connects VFB
to the output of the error amplier.
Note 4: Dynamic supply current is higher due to the internal gate charge
being delivered at the switching frequency.
Note 5: TJ is calculated from the ambient TA and power dissipation PD
according to the following formula: TJ = TA + (PD JA).
Note 6: The DFN switch on-resistance is guaranteed by correlation to
wafer level measurements.
2s/DIV
VIN = 3.6V
VOUT = 1.8V
ILOAD = 180mA
CHANNEL 1; CIRCUIT OF FIGURE 3
1s/DIV
VIN = 3.6V
VOUT = 1.8V
ILOAD = 30mA
CHANNEL 1; CIRCUIT OF FIGURE 3
3548 G02
VIN = 3.6V
20s/DIV
VOUT = 1.8V
ILOAD = 80mA TO 800mA
CHANNEL 1; CIRCUIT OF FIGURE 3
3548 G03
3548fa
LTC3548
TYPICAL PERFORMANCE CHARACTERISTICS
Oscillator Frequency vs
Temperature
2.5
VIN = 3.6V
95
FREQUENCY (MHz)
EFFICIENCY (%)
10mA
85
1mA
80
800mA
75
70
60
2
2.3
2.2
2.1
65
2.4
100mA
90
2
0
2
4
6
10
50
25
75
0
TEMPERATURE (C)
100
125
VIN = 3.6V
TA = 25C
0.610
VIN = 2.7V
500
450
VIN = 4.2V
450
350
300
0.590
250
0.585
50 25
200
50
25
75
0
TEMPERATURE (C)
100
MAIN
SWITCH
RDS(ON) (m)
RDS(ON) (m)
0.595
400
125
SYNCHRONOUS
SWITCH
350
300
250
200
4
VIN (V)
3548 G07
100
50 25
Load Regulation
Line Regulation
0.5
95
1.5
0.4
0.5
0
0.5
1.0
70
VIN = 3.6V, VOUT = 1.8V
NO LOAD ON OTHER CHANNEL
CHANNEL 1; CIRCUIT OF FIGURE 3
65
60
1
10
100
LOAD CURRENT (mA)
1000
3548 G11
1.5
2.0
1
10
100
LOAD CURRENT (mA)
VOUT = 1.8V
IOUT = 200mA
TA = 25C
0.3
EFFICIENCY (%)
1.0
80
2.0
85
MAIN SWITCH
SYNCHRONOUS SWITCH
3548 G08
100
90
VIN = 3.6V
400
150
1
6
3548 G06
500
0.600
3548 G05
0.605
3548 G04
8
2.0
50 25
0.615
1000
3548 G12
0.2
0.1
0
0.1
0.2
0.3
0.4
0.5
2
4
VIN (V)
6
3548 G15
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LTC3548
TYPICAL PERFORMANCE CHARACTERISTICS
Efciency vs Load Current
100
2.7V
100
3.6V
100
95
90
4.2V
EFFICIENCY (%)
80
70
60
VOUT = 2.5V, CHANNEL 1
50 Burst Mode OPERATION
NO LOAD ON OTHER CHANNEL
CIRCUIT OF FIGURE 3
40
1
10
100
LOAD CURRENT (mA)
95
3.6V
90
2.7V
EFFICIENCY (%)
90
EFFICIENCY (%)
85
4.2V
80
75
70
1000
3548 G10
80
65
60
3548 G14
4.2V
75
70
1000
3.6V
2.7V
85
10
100
LOAD CURRENT (mA)
1000
3548 G13
PIN FUNCTIONS
VFB1 (Pin 1): Output Feedback. Receives the feedback voltage from the external resistive divider across the output.
Nominal voltage for this pin is 0.6V.
RUN1 (Pin 2): Regulator 1 Enable. Forcing this pin to VIN
enables regulator 1, while forcing it to GND causes regulator
1 to shut down. This pin must be driven; do not oat.
VIN (Pin 3): Main Power Supply. Must be closely decoupled
to GND.
SW1 (Pin 4): Regulator 1 Switch Node Connection to the
Inductor. This pin swings from VIN to GND.
GND (Pin 5): Main Ground. Connect to the () terminal
of COUT, and () terminal of CIN.
MODE/SYNC (Pin 6): Combination Mode Selection and
Oscillator Synchronization. This pin controls the operation of the device. When tied to VIN or GND, Burst Mode
operation or pulse skipping mode is selected, respectively.
Do not oat this pin. The oscillation frequency can be
3548fa
LTC3548
BLOCK DIAGRAM
REGULATOR 1
MODE/SYNC
BURST
CLAMP
VIN
SLOPE
COMP
0.6V
EA
VFB1
ITH
BURST
SLEEP
ICOMP
0.35V
EN
Q
RS
LATCH
R
0.55V
UVDET
Q
SWITCHING
LOGIC
AND
BLANKING
CIRCUIT
UV
ANTI
SHOOTTHRU
4 SW1
+
OVDET
0.65V
OV
IRCMP
SHUTDOWN
11 GND
VIN
PGOOD1
RUN1
8 POR
2
0.6V REF
RUN2
3 VIN
POR
COUNTER
OSC
OSC
5 GND
PGOOD2
10
7 SW2
3548 BD
OPERATION
The LTC3548 uses a constant frequency, current mode
architecture. The operating frequency is set at 2.25MHz
and can be synchronized to an external oscillator. Both
channels share the same clock and run in-phase. To suit a
variety of applications, the selectable Mode pin allows the
user to choose between low noise and high efciency.
The output voltage is set by an external divider returned
to the VFB pins. An error ampler compares the divided
output voltage with a reference voltage of 0.6V and adjusts
the peak inductor current accordingly. An undervoltage
comparator will pull the POR output low if the output
voltage is not above 8.5% of the reference voltage. The
POR output will go high after 262,144 clock cycles (about
117ms) of achieving regulation.
LTC3548
OPERATION
decrease causes the error amplier to increase the ITH
voltage until the average inductor current matches the
new load current.
The main control loop is shut down by pulling the RUN
pin to ground.
Low Current Operation
By selecting MODE/SYNC (pin 6), two modes are available
to control the operation of the LTC3548 at low currents. Both
modes automatically switch from continuous operation to
the selected mode when the load current is low.
To optimize efciency, the Burst Mode operation can be
selected. When the load is relatively light, the LTC3548
automatically switches into Burst Mode operation, in which
the PMOS switch operates intermittently based on load
demand with a xed peak inductor current. By running
cycles periodically, the switching losses which are dominated by the gate charge losses of the power MOSFETs
are minimized. The main control loop is interrupted when
the output voltage reaches the desired regulated value. A
voltage comparator trips when ITH is below 0.35V, shutting
off the switch and reducing the power. The output capacitor and the inductor supply the power to the load until ITH
exceeds 0.65V, turning on the switch and the main control
loop which starts another cycle.
For lower ripple noise at low currents, the pulse skipping
APPLICATIONS INFORMATION
A general LTC3548 application circuit is shown in
Figure 2. External component selection is driven by the
load requirement, and begins with the selection of the
inductor L. Once the inductor is chosen, CIN and COUT
can be selected.
Inductor Selection
Although the inductor does not inuence the operating frequency, the inductor value has a direct effect on
ripple current. The inductor ripple current IL decreases
with higher inductance and increases with higher VIN or
VOUT:
V
V
IL = OUT 1 OUT
fO L
VIN
3548fa
LTC3548
APPLICATIONS INFORMATION
The inductor value will also have an effect on Burst Mode
operation. The transition from low current operation
begins when the peak inductor current falls below a level
set by the burst clamp. Lower inductor values result in
higher ripple current which causes this to occur at lower
load currents. This causes a dip in efciency in the upper
range of low current operation. In Burst Mode operation,
lower inductance values will cause the burst frequency
to increase.
VALUE
(H)
DCR
(MAX)
MAX DC
CURRENT (A)
SIZE
W L H (mm3)
Sumida
CDRH3D16
2.2
3.3
4.7
0.075
0.110
0.162
1.20
1.10
0.90
Sumida
CDRH2D11
1.5
2.2
0.068
0.170
0.900
0.780
Sumida
CMD4D11
2.2
3.3
0.116
0.174
0.950
0.770
Murata
LQH32CN
1.0
2.2
0.060
0.097
1.00
0.079
Toko
D312F
2.2
3.3
0.060
0.260
1.08
0.92
Panasonic
ELT5KT
3.3
4.7
0.17
0.20
1.00
0.95
LTC3548
APPLICATIONS INFORMATION
of any aluminum electrolytic at a somewhat higher price.
Special polymer capacitors, such as Sanyo POSCAP,
Panasonic Special Polymer (SP), and Kemet A700, offer very low ESR, but have a lower capacitance density
than other types. Tantalum capacitors have the highest
capacitance density, but they have a larger ESR and it
is critical that the capacitors are surge tested for use in
switching power supplies. An excellent choice is the AVX
TPS series of surface mount tantalums, available in case
heights ranging from 2mm to 4mm. Aluminum electrolytic
capacitors have a signicantly larger ESR, and are often
used in extremely cost-sensitive applications provided that
consideration is given to ripple current ratings and long
term reliability. Ceramic capacitors have the lowest ESR
and cost, but also have the lowest capacitance density,
a high voltage and temperature coefcient, and exhibit
audible piezoelectric effects. In addition, the high Q of
ceramic capacitors along with trace inductance can lead
to signicant ringing.
VIN = 2.5V
TO 5.5V
CIN
RUN2
BM*
PS*
VIN
MODE/SYNC
R5
RUN1
POWER-ON
RESET
POR
LTC3548
L1
L2
VOUT2
SW1
SW2
C5
C4
COUT2
VFB1
VFB2
R4
VOUT1
GND
R3
R2
R1
COUT1
3548 F02
LTC3548
APPLICATIONS INFORMATION
R2
VOUT = 0.6V 1+
R1
Keeping the current small (<5A) in these resistors maximizes efciency, but making them too small may allow
stray capacitance to cause noise problems and reduce the
phase margin of the error amp loop.
To improve the frequency response, a feed-forward capacitor CF may also be used. Great care should be taken to
route the VFB line away from noise sources, such as the
inductor or the SW line.
Power-On Reset
The POR pin is an open-drain output which pulls low when
either regulator is out of regulation. When both output voltages are above 8.5% of regulation, a timer is started which
releases POR after 218 clock cycles (about 117ms). This
delay can be signicantly longer in Burst Mode operation
with low load currents, since the clock cycles only occur
during a burst and there could be milliseconds of time
between bursts. This can be bypassed by tying the POR
output to the MODE/SYNC input, to force pulse skipping
mode during a reset. In addition, if the output voltage faults
during Burst Mode sleep, POR could have a slight delay for
an undervoltage output condition. This can be avoided by
using pulse skipping mode instead. When either channel
is shut down, the POR output is pulled low, since one or
both of the channels are not in regulation.
Mode Selection and Frequency Synchronization
The MODE/SYNC pin is a multipurpose pin which provides
mode selection and frequency synchronization. Connecting this pin to VIN enables Burst Mode operation, which
provides the best low current efciency at the cost of a
higher output voltage ripple. Connecting this pin to ground
selects pulse skipping mode, which provides the lowest
output ripple, at the cost of low current efciency.
The LTC3548 can also be synchronized to an external
2.25MHz clock signal by the MODE/SYNC pin. During
synchronization, the mode is set to pulse skipping and
the top switch turn-on is synchronized to the rising edge
of the external clock.
3548fa
10
LTC3548
APPLICATIONS INFORMATION
produce the most improvement. Percent efciency can
be expressed as:
% Efciency = 100% (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percentage of input power.
Although all dissipative elements in the circuit produce
losses, 4 main sources usually account for most of the
losses in LTC3548 circuits: 1)VIN quiescent current,
2) switching losses, 3) I2R losses, 4) other losses.
1) The VIN current is the DC supply current given in the
Electrical Characteristics which excludes MOSFET driver
and control currents. VIN current results in a small (<0.1%)
loss that increases with VIN, even at no load.
2) The switching current is the sum of the MOSFET driver
and control currents. The MOSFET driver current results
from switching the gate capacitance of the power MOSFETs.
Each time a MOSFET gate is switched from low to high
to low again, a packet of charge dQ moves from VIN to
ground. The resulting dQ/dt is a current out of VIN that is
typically much larger than the DC bias current. In continuous mode, IGATECHG = fO(QT + QB), where QT and QB are
the gate charges of the internal top and bottom MOSFET
switches. The gate charge losses are proportional to VIN
and thus their effects will be more pronounced at higher
supply voltages.
3) I2R losses are calculated from the DC resistances of
the internal switches, RSW, and external inductor, RL. In
continuous mode, the average output current ows through
inductor L, but is chopped between the internal top and
bottom switches. Thus, the series resistance looking into
the SW pin is a function of both top and bottom MOSFET
RDS(ON) and the duty cycle (D) as follows:
RSW = (RDS(ON)TOP)(D) + (RDS(ON)BOT)(1 D)
The RDS(ON) for both the top and bottom MOSFETs can
be obtained from the Typical Performance Characteristics
curves. Thus, to obtain I2R losses:
I2R losses = IOUT2(RSW + RL)
4) Other hidden losses such as copper trace and internal
battery resistances can account for additional efciency
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11
LTC3548
APPLICATIONS INFORMATION
The MS package junction-to-ambient thermal resistance,
JA, is 45C/W. Therefore, the junction temperature of
the regulator operating in a 70C ambient temperature is
approximately:
TJ = (0.272 + 0.068) 45 + 70 = 85.3C
which is below the absolute maximum junction temperature of 125C.
Design Example
As a design example, consider using the LTC3548 in an
portable application with a Li-Ion battery. The battery provides a VIN = 2.8V to 4.2V. The load requires a maximum
of 800mA in active mode and 2mA in standby mode. The
output voltage is VOUT = 2.5V. Since the load still needs
power in standby, Burst Mode operation is selected for
good low load efciency.
First, calculate the inductor value for about 30% ripple
current at maximum VIN:
2.5V
2.5V
1
L=
=1.9H
2.25MHz 240mA 4.2V
Choosing a vendors closest inductor value of 2.2H,
results in a maximum ripple current of:
2.5V
2.5V
1
IL =
= 204mA
2.25MHz 2.2 4.2V
For cost reasons, a ceramic capacitor will be used. COUT
selection is then based on load step droop instead of ESR
requirements. For a 5% output droop:
800mA
COUT 2.5
= 7.1F
2.25MHz (5% 2.5V)
A good standard value is 10F. Since the output impedance
of a Li-Ion battery is very low, CIN is typically 10F.
The output voltage can now be programmed by choosing
the values of R1 and R2. To maintain high efciency, the
current in these resistors should be kept small. Choosing
2A with the 0.6V feedback voltage makes R1~300k. A close
standard 1% resistor is 280k, and R2 is then 887k.
The PGOOD pin is a common drain output and requires a pull-up resistor. A 100k resistor is used for
adequate speed.
Figure 3 shows the complete schematic for this design
example.
Board Layout Considerations
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC3548. These items are also illustrated graphically
in the layout diagram of Figure 4. Check the following in
your layout:
1. Does the capacitor CIN connect to the power VIN (Pin
3) and GND (exposed pad) as close as possible? This
capacitor provides the AC current to the internal power
MOSFETs and their drivers.
2. Are the COUT and L1 closely connected? The () plate of
COUT returns current to GND and the () plate of CIN.
3. The resistor divider, R1 and R2, must be connected
between the (+) plate of COUT and a ground sense line
terminated near GND (exposed pad). The feedback signals
VFB should be routed away from noisy components and
traces, such as the SW line (Pins 4 and 7), and its trace
should be minimized.
4. Keep sensitive components away from the SW pins. The
input capacitor CIN and the resistors R1 to R4 should be
routed away from the SW traces and the inductors.
5. A ground plane is preferred, but if not available, keep
the signal and power grounds segregated with small signal
components returning to the GND pin at one point and
should not share the high current path of CIN or COUT.
6. Flood all unused areas on all layers with copper. Flooding with copper will reduce the temperature rise of power
components. These copper areas should be connected to
VIN or GND.
3548fa
12
LTC3548
APPLICATIONS INFORMATION
VIN = 2.5V*
TO 5.5V
VIN
C1
10F
RUN2 VIN
MODE/SYNC
VOUT2 = 2.5V*
AT 400mA
L2
4.7H
R5
100k
RUN1
RUN2
RUN1
POR
LTC3548
VOUT1 = 1.8V
AT 800mA
SW1
C5, 68pF
VIN
MODE/SYNC
L1
2.2H
LTC3548
SW2
CIN
POWER-ON
RESET
POR
C4, 33pF
L1
L2
VOUT2
SW1
SW2
C5
C3
4.7F
R4
887k
VFB1
VFB2
R3
280k
R2
R1 604k
301k
GND
C2
10F
VFB1
VFB2
R4
COUT2
VOUT1
C4
GND
R3
R2
R1
COUT1
3548 F03
3548 F04
TYPICAL APPLICATIO S
Low Ripple Buck Regulators Using Ceramic Capacitors
VIN = 2.5V
TO 5.5V
C1
10F
RUN2
VIN
RUN1
R5
100k
POWER-ON
RESET
POR
C3
10F
LTC3548
L2
10H
L1
4.7H
SW1
SW2
C5, 68pF
R4
887k
C4, 33pF
MODE/SYNC
VOUT1 = 1.2V
AT 800mA
VFB1
VFB2
R3
442k
GND
R2
R1 604k
604k
C2
10F
3548 TA03
1.8V
90
EFFICIENCY (%)
VOUT2 = 1.8V
AT 400mA
85
1.2V
80
75
70
65
60
55
50
10
VIN = 3.3V
PULSE SKIP MODE
NO LOAD ON OTHER CHANNEL
100
LOAD CURRENT (mA)
1000
3548 TA03b
3548fa
13
LTC3548
TYPICAL APPLICATIO S
1mm Prole Core and I/O Supplies
VIN = 3.6V
TO 5.5V
C1*
10F
RUN2
VIN
MODE/SYNC
VOUT2 = 3.3V
AT 400mA
C3
4.7F
R5
100k
RUN1
POWER-ON
RESET
POR
LTC3548
L2
4.7H
SW2
L1
2.2H
SW1
C5, 68pF
R4
887k
C4, 33pF
VFB1
VFB2
R3
196k
VOUT1 = 1.8V
AT 800mA
R2
R1 604k
301k
GND
C2
10F
3548 TA07
3.3V
EFFICIENCY (%)
90
85
1.8V
80
75
70
VIN = 5V
65 Burst Mode OPERATION
NO LOAD ON OTHER CHANNEL
60
10
100
1
LOAD CURRENT (mA)
1000
3548 TA08
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14
LTC3548
PACKAGE DESCRIPTION
DD Package
10-Lead Plastic DFN (3mm 3mm)
(Reference LTC DWG # 05-08-1699)
R = 0.115
TYP
0.38 0.10
10
0.675 0.05
3.50 0.05
1.65 0.05
2.15 0.05 (2 SIDES)
3.00 0.10
(4 SIDES)
1.65 0.10
(2 SIDES)
PIN 1
PACKAGE
TOP MARK
OUTLINE (SEE NOTE 6)
0.25 0.05
0.50 BSC
0.75 0.05
0.200 REF
0.25 0.05
0.50
BSC
2.38 0.05
(2 SIDES)
2.38 0.10
(2 SIDES)
0.00 0.05
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2).
CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
MSE Package
10-Lead Plastic MSOP, Exposed Die Pad
(Reference LTC DWG # 05-08-1664 Rev B)
2.794 0.102
(.110 .004)
BOTTOM VIEW OF
EXPOSED PAD OPTION
3.00 0.102
(.118 .004)
(NOTE 3)
0.889 0.127
(.035 .005)
10 9 8 7 6
5.23
(.206)
MIN
0.254
(.010)
DETAIL A
0 6 TYP
0.497 0.076
(.0196 .003)
REF
2.06 0.102
(.081 .004)
1.83 0.102
(.072 .004)
3.00 0.102
(.118 .004)
(NOTE 4)
4.90 0.152
(.193 .006)
GAUGE PLANE
0.50
0.305 0.038
(.0197)
(.0120 .0015)
BSC
TYP
RECOMMENDED SOLDER PAD LAYOUT
0.53 0.152
(.021 .006)
DETAIL A
SEATING
PLANE
0.17 0.27
(.007 .011)
TYP
10
0.86
(.034)
REF
1.10
(.043)
MAX
0.18
(.007)
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
1 2 3 4 5
0.50
(.0197)
BSC
0.1016 0.0508
(.004 .002)
MSOP (MSE) 0307 REV B
3548fa
15
LTC3548
TYPICAL APPLICATION
2mm Height Lithium-Ion Single Inductor Buck-Boost Regulator and a Buck Regulator
VIN = 2.8V
TO 4.2V
C1
10F
RUN2
VIN
MODE/SYNC
L2
15H
D1
VOUT2 = 3.3V
AT 100mA
C6
22F
SW1
C5, 22pF
R4
887k
C3
4.7F
POWER-ON
RESET
L1
2.2H
POR
LTC3548
SW2
M1
R5
100k
RUN1
C4, 33pF
VFB1
VFB2
R3
196k
VOUT1 = 1.8V
AT 800mA
R2
R1 604k
301k
GND
C2
10F
3548 TA04
90
95
80
2.8V
70
60
EFFICIENCY (%)
EFFICIENCY (%)
90
4.2V
3.6V
2.8V
50
85
4.2V
3.6V
80
75
70
40 VOUT = 3.3V
Burst Mode OPERATION
NO LOAD ON OTHER CHANNEL
30
1
10
100
LOAD CURRENT (mA)
VOUT = 1.8V
Burst Mode OPERATION
NO LOAD ON OTHER CHANNEL
65
60
1000
10
100
LOAD CURRENT (mA)
1000
3548 TA06
3548 TA05
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC1878
LT1940
LTC3252
LTC3405/LTC3405A
LTC3406/LTC3406B
LT3407/LT3407-2
LTC3411
LTC3412
LTC3414
LTC3440
3548fa
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