IPASJ International Journal of Electronics & Communication (IIJEC)

Web Site: http://www.ipasj.org/IIJEC/IIJEC.htm

Email: editoriijec@ipasj.org
ISSN 2321-5984

A Publisher for Research Motivation........

Volume 3, Issue 5, May 2015

A Review Paper on Power Minimization

Techniques in FPGAs
1

Mohit Bajpai , Dinesh Chand Gupta2

Student-M.Tech, Poornima College of Engineering

Assistant Professor, Department of ECE, Poornima College of Engineering

ABSTRACT
This review paper presents a survey to show the work done on how power of FPGA is minimized by applying different
techniques. Among these the self adaptive voltage controlling is most efficient technique which able to reduce power without
affecting system performance. This review paper includes the study of 14 research papers on low power FPGA.

Keywords: Voltage control, Low power, FPGA

1. INTRODUCTION
Field-Programmable Gate Arrays (FPGAs) are widely used to implement special-purpose processors. FPGAs are costeffective and flexible for low volume applications because the users can freely change the function of the programmable
logic blocks and the connection of the programmable switch blocks. Despite the advantages, FPGAs have a large power
overhead compared to the custom VLSI [1]. Reducing the supply voltage is an effective technique for reducing power in
VLSI circuits. However, it also has negative effects on the circuit performance. A well-known technique to reap the
benefits of voltage scaling without the performance penalty is the use of multiply supply voltages. Multi-voltage
techniques can be mainly classified as follows:
Static Voltage Scaling (SVS): different blocks are given different, fixed supply voltages.
Dynamic Voltage and Frequency Scaling (DVFS): blocks are dynamically switched between two or more voltage levels
follow changing workloads [3].
The area of FPGAs design is evolving at a rapid pace as they are ideal for adaptive systems because these are
reconfigurable and can be programmed to implement any digital logic. As concerned to utility the FPGAs are always
found in the field of researchers in context with area and speed but increasing demand in market for portable devices
the FPGAs are concerned to the low power design mechanisms.
The timing of critical blocks operates on the normal supply voltage and the non-critical blocks operate on a low supply
voltage. While this technique has been successfully applied in low-power custom ICs [2], it is difficult to be applied in
FPGAs for power reduction. Thus, a large proportion of blocks can be supplied with the lower voltage. This approach
saves the power consumption significantly.
There are several methods evaluated in the last few years which conclude the power of the FPGAs to low level to
increase its efficiency at user level. Among these techniques self adaptive voltage control scheme is found very useful to
implement as it is capable to reduce the power at design level more precisely without system performance degradation.
This paper presents a review on 14 research papers which provides different techniques for reducing power and self
adaptive voltage control in FPGA.

2. LITERATURE REVIEW
The review of literature is relevant to the objective of the study, i.e., power optimization and low power FPGA design.
As historically, FPGAs have been slower, less energy efficient and generally achieved less functionality than their fixed
ASIC counterparts. An older study had shown that designs implemented on FPGAs need on average 40 times as much
area, draw 12 times as much dynamic power, and run at one third the speed of corresponding ASIC implementations.
More recently, FPGAs such as the Xilinx Virtex-7 or the Altera, Stratix 5 have come to rival corresponding ASIC
solutions by providing significantly reduced power, increased speed, lower materials cost, minimal implementation
real-estate, and increased possibilities for re-configuration 'on-the-fly'. Because the most common and wide spread
threat associated with FPGA is power consumption, so the review of literature is relevant to the objective of the study,
i.e., power optimization and low power FPGA design. The process which is adopted for review is given below:

Volume 3, Issue 5, May 2015

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IPASJ International Journal of Electronics & Communication (IIJEC)

Web Site: http://www.ipasj.org/IIJEC/IIJEC.htm
Email: editoriijec@ipasj.org
ISSN 2321-5984

A Publisher for Research Motivation........

Volume 3, Issue 5, May 2015

2.1 REVIEW PROCESS ADOPTED

Literature survey includes the study of various sources of literature in the area of research. It includes finding the
related material from magazines, books, research articles, scientific research papers published in various conferences,
journals & transactions. At the same time these contents cannot be considered as base to arrive at the conclusion of
framing research objectives as it is not supported through proper review by various researchers working in the area. For
this we adopt certain path for such literature.
The process diagram is shown in Figure-1, which includes in all five stages defined as under:
1.
Stage 0: Get the Feel
2.
Stage 1: Get Big Picture
3.
Stage 2: Get the Details
4.
Stage 3: Evaluate the Details
5.
Stage 3 +: Synthesize the Details

Stage 0
Get a feel

Stage 1
Get the big picture

Stage 2
Get the details

Stage 3
Evaluate the details

Stage 4
Synthesize the details
Figure 1 Flow Chart of Review Process
2.2 LIST OF PAPERS IN CHRONOLOGICAL ORDER
The list of papers reviewed on FPGA for low power in chronological order and findings from their studies also
presented in Table-1.
Table 1: List of papers with their key findings

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IPASJ International Journal of Electronics & Communication (IIJEC)

A Publisher for Research Motivation........

Volume 3, Issue 5, May 2015

Web Site: http://www.ipasj.org/IIJEC/IIJEC.htm

Email: editoriijec@ipasj.org
ISSN 2321-5984

3. RESULT AND DISCUSSION

Increasing demand of portable devices attract researchers to design less power hungry FPGAs which draw the results to
different techniques such as hybridization of CMOS with CNT based NEMS, design with a CNFET model, Proposed a
MUX tree based round robin scheduler, dual VDD supply method and the most important and efficient method i.e. self
adaptive voltage controlling.
Self adaptive voltage control method is utilized by many researchers and got different results with remarks. In the
proposed implementation, each LB is powered by a programmable power supply and dynamically switches to VDDH
(High Voltage) or VDDL (low voltage) according to the VDD-control signal from the next LB [11]. The self-adaptive
voltage control scheme seems more suitable for dynamically reconfigurable processors. Since their data paths change
dynamically and frequently, deciding the supply voltage for each LB using offline analysis is more difficult than FPGAs
[3]-[11].

4. CONCLUSION
The aim of this paper has been to present the contributions of FPGAs to the control of voltage and power. This paper
reviews a low-power FPGA based on self adaptive voltage control. A self-adaptive voltage controller is designed and
embedded in each LB which switches the supply according to the requirement of LB, to high level and low level to
saves power without deteriorating the system performance.

Volume 3, Issue 5, May 2015

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IPASJ International Journal of Electronics & Communication (IIJEC)

A Publisher for Research Motivation........

Volume 3, Issue 5, May 2015

Web Site: http://www.ipasj.org/IIJEC/IIJEC.htm

Email: editoriijec@ipasj.org
ISSN 2321-5984

AKNOWLEDGEMENT
The authors are thankful to Mr. Manish Singhal, Associate Professor, Electronics & Communication Engineering
Department, Poornima College of Engineering, Jaipur, Dr. Ajay Kumar Bansal, Director, Poornima Institute of
Engineering & Technology, Jaipur and Dr. Mukul Bajpai, Dr. Reddys Labs Private Limited, Hydrabad for their
valuable suggestions and support.

REFERENCES
[1]. Zhengfan Xia, Mansanori Hariyama and Michitaka Kameyama, A Low Power FPGA Based on Self Adaptive
Multi-Voltage Control, ISOCC, 2013.
[2]. M. Takahashi et.al., A 60-mW MPEG4 Video Codec Using Clustered Voltage Scaling with Variable SupplyVoltage Scheme, In IEEE Journal of Solid-State Circuits, Vol. 33, No. 11, Nov. 1998.
[3]. Shota Ishihara, Zhengfan Xia, Mansanori Hariyama and Michitaka Kameyama, Evaluation of a Self-Adaptive
Voltage Control Scheme for Low-Power FPGAs, Journal of Semiconductor Technology and Science, Vol. 10, No.
3, September, 2010.
[4]. Varghese George, Hui Zhang and Jan Rabaey, The Design of a Low Energy FPGA, ISLPED99, San Diago, CA,
USA.
[5]. Francis G. Wolff Michael J., Knieser Dan J., Weyer Chris A. Papachristou, High-Level Low Power FPGA
Design Methodology, Electrical Engineering and Computer Science Department, Case Western Reverse
University, Cleveland, 2000,IEEE.
[6]. Li Shang, Alireza S Kaviani, Kusuma Bathala, Dynamic Power Consumption in VIRTEX -II FPGA Family,
FPGA, 24-26, Monterery, California, USA, Feburary-2002.
[7]. Jason H. Anderson and Farid N. Najm, Active Leakage Power Optimization for FPGAs, IEEE Transaction on
Computer Aided Design of Integtrated Circuits and Systems, Vol. 25, No. 3, March 2006.
[8]. Yu Zhou, Shijo Thekkel and Swarup Bhunia, Low Power FPGA Design using Hybrid CMOS-NEMS Approach
ISLPED07, Portland, USA, August 27-29, 2007.
[9]. Julien Lamoureux and Wayne Luk, An Overview of Low-power Techniques for Field-Programmable Gate
Arrays, IEEE, 2008.
[10]. Zhengfan Xia, Shota Ishihara, Mansanori Hariyama and Michitaka Kameyama An Asynchronous FPGA Based
on Dual/single Rail Hybrid Architecture, International Conference on Reconfigurable Systems and Algorithm,
ERSA12.
[11]. Shota Ishihara, Zhengfan Xia, Mansanori Hariyama and Michitaka Kameyama, Architecture of a Low Power
FPGA based on a Self Adaptive Voltage Control, IEEE, 2009.
[12]. Kwang-Soo Han, Dong-Ik Jeon and Ki-Seok Chung, Ultra Low Power and High Speed FPGA Design with
CNFET, International Symposium on Communication and Information Technologies (ISCIT).
[13]. S.A. Raja Ram, Mr. D. Jerish Solomon, Reducing Power in Reconfigurable Processors using Dual VDD,
International Journal for Research and Development in Engineering (IJRDE), ISSN: 2279-0500, Issue: pp- 211216, 2014.
[14]. P.A.Kamble, Prof. M.B. Mali, Low Power Techniques for High Speed FPGA, International Journal of Scientific
and Research Publications, Volume 5, Issue 3, March 2015.
[15]. B. Sankar, Dr. C.N. Marimuthu, Power Optimization using Body Biasing Method for Dual Voltage FPGA,
International Research Journal of Engineering and Technology (IRJET), Volume: 02, Issue: 01, April 2015.

AUTHORS
Mohit Bajpai has received his B.Tech Degree in 2010 Electronics & Communication Engineering in from Poornima
College of Engineering, Jaipur & now pursuing M.Tech in VLSI DESIGN from Poornima College of Engineering,
Jaipur. His current area of research include power minimization in Field programmable gate arrays using different
techniques.
Mr. Dinesh Chand Gupta passed B.Tech in 2008 and M.Tech in 2012 from NIT, Jalandhar with specialization in
VLSI Design. He has 3 years teaching experience and publishes four papers in international journals. His research area
is Low Power circuit design.

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