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CHIEF PATRON

Sri P. Shyama Raju

Maximum number of participants is limited to 30. You can


also send a scanned copy of application to get the priority.
You shall be intimated about your participation status through
th
e-mail by 10 July 2014.

Chancellor, REVA University, Bangalore.

Faculty Development Programme

WHO CAN REGISTER?

PATRON
Prof . V. G. Talawar
Vice-Chancellor, REVA University, Bangalore.

Faculty of Engineering College, Researchers, Practicing Engineers,


PG Students.

ADVISORY COMMITTEE

REGISTRATION FEES

on

"ASIC Front End Design Using


Cadence Tool
21 - 25 July 2014

Dr. N. Ranapratap Reddy


Dean, Engineering Studies, REVA University, Bangalore.

For Teachers & Students

: Rs. 3500/-

Dr. T. V. Ramamoorthy

Industry Persons

: Rs. 5000/-

Senior Prof. REVA University, Bangalore.

ADDRESS FOR CORRESPONDENCE

Dr. K. S. Gurumurthy
Senior Prof. REVA University, Bangalore.

PROGRAMME CONVENER
Dr. Sunil Kumar S. Manvi
Dean R&D, Prof. & Head, Dept. of ECE, REVA ITM

CO-ORDINATORS

Dr. Bharathi S. H / Prof Prashanth Joshi


Coordinator,
FDP on "ASIC Front End Design Using Cadence Tool".
School of Electronics and Communication Engineering
REVA University, Rukmini Knowledge Park
Kattigenahalli, Yelahanka
Bangalore - 560 064

MAP TO REVA ITM CAMPUS

Dr. Bharathi S. H.
Mobile: 09900821465
e mail: bharathish@revainstituion.org

Mr. Prashant V. Joshi


Mobile: 08147857039
e mail: prashanth_joshi@revainstitution.org

HOW TO APPLY
Application in the attached form or in a similar format along with
the DD/at par multi-city cheque for the registration amount,
Application Form, sponsorship certificate and a self addressed
envelope with enough postage should reach the course coordinator by
th
30 June 2014.

Jointly organized by

Department of Electronics &


Communication Engineering
&
UTL Technologies
REVA University
Rukmini Knowledge Park, Kattigenahalli,
Yelahanka, Bangalore - 560 064
Phone: +91-80-39354444, +91-80-65687563/64/65
Fax: 080-28478539
www.reva.edu.in
Rukmini Educational
Charitable Trust

A Unit of DivyaSree

ABOUT REVA UNIVERISTY

COURSE INTRODUCTION

Reva Group of Educational Institutions was established in the


year 2004 under the aegis of Rukmini Educational Charitable Trust led
by Shri P. Shyama Raju as founder chairman. REVA Institute of
Technology & Management is approved by AICTE, New Delhi and
accredited by NBA. REVA University has been established under
REVA University Act 2012 of the Government of Karnataka with a
mandate to impart higher education of global standards. REVA
University focuses on promoting universal and equitable access to
higher education in various disciplines and inculcate in students
knowledge and confidence embedded with professional traits to
become highly competent in the dynamic global market. Located on the
way to Bangalore International Airport, the University has a sprawling
green campus spread over 35 Acres of land equipped with state-of-the
art of infrastructure and conducive environment for higher learning.
For further details please logon to our website: www.reva.edu.in

This 40 hour course is designed in a way such that, by the end of the
course the audience will be able to perform the whole ASIC front-end
design(RTL-Netlist) by buying equal theoretical and practical exposure
BY USING Cadence Tool. The course imitates the ASIC front-end flow
followed by semiconductor industries which includes RTL design,
Timing analysis and design for testability. The course will start from the
basics of the digital design, digital system design using Verilog HDL,
Logic synthesis, Timing analysis, DFT analysis and ends with the case
study, so the audience are given chance to learn the theoretical
concepts and practicing the same with the help of EDA tools.

ABOUT SCHOOL OF ELECTRONICS &


COMMUNICATION ENGINEERING
The School of Electronics and Communication Engineering REVA
University offers B-Tech, M-Tech and PhD. programmes in Electronics
and communication for the academic year 2014-15. These degree
programmes are designed to meet the present day demand for specific
requirements of Engineering and Technology field. The programme
provides an opportunity for students to know about applications of
electronics in several fields of practical interest. The department is well
equipped with state of art laboratories, faculty with rich academic and
R&D exposure. Major thrust areas in which research activities being
pursued in the department are Wireless Communications / Networks,
Digital Signal Processing, Image Processing, VLSI Design and Digital
Design, Microwave Engineering and Antennas and Optical Fiber
Communications. The students have to take compulsorily the major
and mini projects integrated with company experience. This will boost
their confidence level.

ABOUT UTL TECHNOLOGIES


UTL Technologies Ltd., a UTL Group company, one of India's highly
appreciated and widely recognized prominent high-end training
organization in providing Industry relevant training solutions to
Students, Working Professionals and Corporate houses.
UTL Technologies is known as a trailblazer in emerging technologies
training, its comprehensive and innovative training methodology on a
vibrant spectrum of latest technologies makes it a leader. UTL offers
courses in niche areas like Embedded Systems Design, VLSI Design,
Mobile Communication and Networking.

Application Form Faculty Development Programme


on
ASIC Front End Design Using Cadence Tool"

21 - 25 July 2014
School of Electronics and Communication Engineering,
REVA University Bangalore
(Use block capital letters only)

Day 4:
Static Timing Analysis: ASIC design flow, Timing models, Concept of
static timing analysis-Setup and hold analysis with and without skew
false paths and multi-cycle paths, Timing closure.
Lab:
1. RTL synthesis
2. Static timing analysis with SDC

Name:__________________________________________
A) Date of Birth : B) Sex : M/F _______________________
Designation:____________________________________
Institute:________________________________________
Address for Communication :
_______________________________________________
_______________________________________________
_______________________________________________
Phone:_________________________________________
Email ID:________________________________________
Highest Qualification:____________________________
Specification:____________________________________
Years of Experience:
Teaching:_______________________________________
Industry:________________________________________
Area of work/Interest:____________________________
Whether accommodation needed : Yes/No:____________
DD No./Cheque No.:_____________Dated:____________
The information furnished above is true to the best of my
knowledge. I agree to abide by the rules and regulations
governing the course. If selected, I shall attend the course for
the entire duration.

Day 5:
Design for testability, Importance of testing, Fault models, Test pattern
generation, Full scan design methodology, Scanviolations and its fix
Stitching scan flops creating scan chains ATE Vs. BIST

PLACE :
DATE :

SIGNATURE OF THE APPLICANT

FORWARDED BY:

SIGNATURE OF HOD/PRINCIPAL
OF THE INSTITUTION

COURSE CONTENTS
Day 1:
Digital Design Concepts, Introduction to Verilog HDL Modules and
ports
Lab1: Hierarchy Modeling, Introduction to Test benches
Lab 2: Synthesis and Simulation
Day 2:
Verilog Operators and Expressions, Continuous Assign
Statements
Lab 3: Data flow Modeling, Verilog Procedural Statements
Lab 4: Behavioral Modeling-1, Control Statements
Lab 5: Behavioral Modeling-2
Day 3:
Tasks and Functions, System Tasks
Lab 6: Tasks and Functions Lab, Finite State Machines
Lab 7: Finite State Machines, Different types of test benches
Lab 8: Different types of test benches

Case study:
Timing, DFT analysis of 1K gate design