Beruflich Dokumente
Kultur Dokumente
PATRON
Prof . V. G. Talawar
Vice-Chancellor, REVA University, Bangalore.
ADVISORY COMMITTEE
REGISTRATION FEES
on
: Rs. 3500/-
Dr. T. V. Ramamoorthy
Industry Persons
: Rs. 5000/-
Dr. K. S. Gurumurthy
Senior Prof. REVA University, Bangalore.
PROGRAMME CONVENER
Dr. Sunil Kumar S. Manvi
Dean R&D, Prof. & Head, Dept. of ECE, REVA ITM
CO-ORDINATORS
Dr. Bharathi S. H.
Mobile: 09900821465
e mail: bharathish@revainstituion.org
HOW TO APPLY
Application in the attached form or in a similar format along with
the DD/at par multi-city cheque for the registration amount,
Application Form, sponsorship certificate and a self addressed
envelope with enough postage should reach the course coordinator by
th
30 June 2014.
Jointly organized by
A Unit of DivyaSree
COURSE INTRODUCTION
This 40 hour course is designed in a way such that, by the end of the
course the audience will be able to perform the whole ASIC front-end
design(RTL-Netlist) by buying equal theoretical and practical exposure
BY USING Cadence Tool. The course imitates the ASIC front-end flow
followed by semiconductor industries which includes RTL design,
Timing analysis and design for testability. The course will start from the
basics of the digital design, digital system design using Verilog HDL,
Logic synthesis, Timing analysis, DFT analysis and ends with the case
study, so the audience are given chance to learn the theoretical
concepts and practicing the same with the help of EDA tools.
21 - 25 July 2014
School of Electronics and Communication Engineering,
REVA University Bangalore
(Use block capital letters only)
Day 4:
Static Timing Analysis: ASIC design flow, Timing models, Concept of
static timing analysis-Setup and hold analysis with and without skew
false paths and multi-cycle paths, Timing closure.
Lab:
1. RTL synthesis
2. Static timing analysis with SDC
Name:__________________________________________
A) Date of Birth : B) Sex : M/F _______________________
Designation:____________________________________
Institute:________________________________________
Address for Communication :
_______________________________________________
_______________________________________________
_______________________________________________
Phone:_________________________________________
Email ID:________________________________________
Highest Qualification:____________________________
Specification:____________________________________
Years of Experience:
Teaching:_______________________________________
Industry:________________________________________
Area of work/Interest:____________________________
Whether accommodation needed : Yes/No:____________
DD No./Cheque No.:_____________Dated:____________
The information furnished above is true to the best of my
knowledge. I agree to abide by the rules and regulations
governing the course. If selected, I shall attend the course for
the entire duration.
Day 5:
Design for testability, Importance of testing, Fault models, Test pattern
generation, Full scan design methodology, Scanviolations and its fix
Stitching scan flops creating scan chains ATE Vs. BIST
PLACE :
DATE :
FORWARDED BY:
SIGNATURE OF HOD/PRINCIPAL
OF THE INSTITUTION
COURSE CONTENTS
Day 1:
Digital Design Concepts, Introduction to Verilog HDL Modules and
ports
Lab1: Hierarchy Modeling, Introduction to Test benches
Lab 2: Synthesis and Simulation
Day 2:
Verilog Operators and Expressions, Continuous Assign
Statements
Lab 3: Data flow Modeling, Verilog Procedural Statements
Lab 4: Behavioral Modeling-1, Control Statements
Lab 5: Behavioral Modeling-2
Day 3:
Tasks and Functions, System Tasks
Lab 6: Tasks and Functions Lab, Finite State Machines
Lab 7: Finite State Machines, Different types of test benches
Lab 8: Different types of test benches
Case study:
Timing, DFT analysis of 1K gate design