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CONTINUOUS-TIME
ANALOG CIRCUIT OPERATION
OUTLINE
I.
II.
Introduction
Basic techniques for continuous-time lowvoltage operation
III. Continuous-time low-voltage amplifier schemes
IV. Low-voltage op-amp architectures with rail-torail input and output swings
V. Low-voltage circuits based on floating gates
VI. Conclusions
I. INTRODUCTION: Definition
Low-Voltage circuit
Operation with single supply VDD less
than the sum of the threshold voltages of a
PMOS and an NMOS transistor
VDD<VTHn+|VTHp|
VDD<1V for current CMOS technology
with VTH=0.45V
I. INTRODUCTION
Example : Two stage OP-AMP with class AB
output stage
+
VDS
VGS
_
+
VSG
MoutP
Vbat
MoutN
VGS
Vdd>Vth+2VDSsat+Vinswing
Vdd>2Vth+VDSsat+Vbat
Vb
+
A
Vin
Vout
Vin
Vb
Vout
(a)
Vb
B
I1
(b)
(c)
I1+I2
(d)
Vth=Vth-Vb
Vb=Vth then Vth= 0 Then Vtotal= 4VDSsat (<1V)
Multiple Input Floating Gate Transistor: (a) Layout (b) symbol (c)
equivalent circuit model.
ai=Ci/(C1+C2+..+Cn)
C1
Vth' = Vth VBIAS
C1 + C 2
"Modeling Multiple-Input Floating Gate Transistors for Analog Signal Processing," J. Ramrez-Angulo, G. GonzalezAltamirano and S.C. Choi, IEEE International Symposium on Circuits and Systems, Hong Kong, June 9-12, 1997
c) Layout
d) Equivalent circuit
Drawbacks
Rlarge forms high pass circuit with signal coupling capacitors
swing at junction implementing Rlarge must be limited to avoid forward
biasing the junction
PN junction nonlinear can introduce distortion for gate swings
Rz HIGH!
Ibias
Vz
Ry
VERY
HIGH!
Iin
Vy
LOW!
Rx
z
y
Iin
Vbias
x
+
Vin
Low voltage mirror with very low input impedance and low input
voltage requirements
Low Voltage High Performance CMOS Current Mirrors," J. Ramrez-Angulo,
R.G. Carvajal and A. Torralba, IEEE 43drd Midwest Symposium on Circuits and
Systems. Lansing, MI, August 8-11, 2000.
VSGQ
V1
M2
VCM
M1
ID1
ID2
VSGQ
MCM
M1
VCM
VSGQ+Vd/2
M2
V2
ID2
V2
Ib
Vd
common mode
sensor
(a)
( c )
( b)
Approach:
Keep both input terminals of op-amp closte to one of the supply rails by Inserting a floating DC
source with value Vbat=VDD/2 in series with negative op-amp input.
"A simple technique for low-voltage op-amp operation in continuous-time," J. Ramrez-Angulo, A Torralba, R.G.
Carvajal and J.Tombs, IEE Electronics Letters, vol. 35, No. 4, February 18th, 1999, pp. 263-264
R2
Vin
R1
VDD/2
_
+
RF
Vin
R1
Vout
I
VDD/2
R1
_
Vout
(b)
Vbat
+ _
_+
Vout
R1
(a)
+
Vin
_
R2
RF
(c)
Low voltage amplifier based on DC floating sources (a) Standard inverting configuration (b) wideband
constant bandwidth configuration based on current sensing c) Fully differential version of circuit of Fig. a
Ib
+
_ Vs
OA
Vo
OA
OA
Vo
Vo
Vs
_+
(a)
(b)
Ib
Ib=Vs/R
(c)
Dynamic FVCVS technique. a) Op-amp in voltage follower configuration. b) Grounding the op-amp input and
inserting a FVCVS in the feedback path c) implementation of FVCVS with resistor and current sources
Ib
Vref
Vref
+
_ DA
V's
R
Ib
_OA
Vcn
(a)
R
Ib
Vout
Ib
(b)
Vref
OA
A'
(A-1)*I bQ
R
A*I b
B
Vout
A*I b
(A-1)*I bQ
B'
Icnt
Vbias
M17
M5
Rb
Vi-
Vi+
RCM4
RCM3
Va
R1
Vb
M3
M4
VcntCMN
Vb
VcntCMN
M18
VcntCMP
MBCMFN
Vo+
M9
M10
M15
Ro
Vo-
Icnt
RCM
RCM
M11
M12
(b)
_+
Vout
RF
M6
(c)
M16
Ro
+_
Icnt
M20
Vbias
Vbat
Rbp
(a)
VrefCM
+
Vin
_
M8
Vo+
Rbat
Va
Icnt
M19
M2
M1
Vo-
M7
MBINPST
R1
Icnt
VcntCMP
M14
VcntCMN
Simple technique using Local CMFB to enhance Slew Rate and bandwidth of one-Stage cmos op-amps, Jaime
Ramirez-Angulo and Michael Holmes. Electronics Letters, vol. 38, No 23, pp. 1409-1411, November 7th 2002,
Icnt
VbatP
MBINPst
M17
M5
M1P
Va
M1
Vi-
Vsh
MFVF
MBFVF
Rbat
Vb
Rbat
Vbias
Vi-
M1
M2
Va
Icnt
M3
VbatN
M4
VbatN
Cc
Vb
M6
M3
M7
M3P
Rc
M4
M6
VcntCM
Icnt
M18
Vo+
Vi+
Vo+
Cc Rc
M7
M8
M8
VoVa
MBinpst
M5
Vb
M2P
Vi+
Ibat
M2
Ibat
Vo-
VbiasP
Icnt
M19
M4P
(a)
(a)
Vbias
VbiasN
MBCMFN
MB
VbatP
M13
M9P
Vo-
M10P
M9
Ro
M10
VbatN
Ro
Va
M11
Vb
M12
Ibat
Ibat
Vo+
Ro
M10
M9
Ro
VrefCM
VoRbat
RCM
VrefCM
M20B
RCM
RCM
IQ
VbatP
(b)
M15
IQ
Vo+
RCM
M19B
MBCMFN
M16
VbatN
M11
VcntCM
M12
M14
(c)
(b)
**************************************************************
750
V(VO)
V(VO)
500
TRANSIENT
RESPONSES (mV)
250
V(VI)
0
-250
V(VI)
V(VO)
400
V(VI)
0
-400
-500
-800
0
-750
0
0.4
0.8
1.2
TIME (us)
1.6
0.4
1.2
1.6
2.0
TIME (us)
V(VI)
V(VO)
TopSPICEw32 5.82b
(a)
0.8
2.0
01-APR-2003 05:27:37
(b)
(a) Transient response of new class AB/AB op-amp (b) Transient response of
conventional class A/A op-amp with same static bias current
A New Power Efficient Fully Differential Low Voltage Two State Op-Amp Architecture , J.
Ramrez-Angulo S. Thoutam G.O. Ducoudray and R.G. Carvajal, VLSI'03: June 23-26, 2003, Las
Vegas, Nevada, USA. pp. 87-02
"Low-voltage CMOS Op-amp with rail-to-rail signal swing for continuous-time signal processing using multiple-input
floating-gate transistors," J. Ramirez-Angulo, R. G. Carvajal, J. Tombs, and A. Torralba, IEEE Transactions on Circuits
and Systems, special issue on applications of floating gate transistors, vol. 48, No. 1, January 2001, pp. 110-116
V I+
V I-
SW 4
8C
SW 3
4C
SW 2
2C
SW 1
QFGMOS1
_
+
SW 1
SW 2
2C
SW 3
4C
SW 4
8C
_
+
VO+
V O-
C
QFGMOS2
1.5
QFGMOS1 (2N-1)C
VDDd2
2C
C
_
+
VDDd0
C
-VDDd0
2C
-VDDd1
VO-
0
-0.5
(2N-1)C
-VDDd2
2N-1C
VO+
-1
4C
-VDDdN-1
0.5
Volta ge (V)
VDDd1
QFGMOS2
-1.5
3
4
Time (ms )
QFGMOS1 (2N-1)C
VDDd2
2C
VDDd1
C
_
+
VDDd0
C
-VDDd0
2C
-VDDd1
4C
(2N-1)C
-VDDd2
2N-1C
-VDDdN-1
QFGMOS2
VO+
VO-
IB
M2
VINVI2VI1-
M4
M3
CN
C2
C1
CN
M1A
M2A
MQ2
MQ1
C2
C1
M5
VIN+
M1B
VI2+
VI1+
VOSW B
CAZ
R1
R1 M
6
CMFB
CC RC
M7
RC CC
M8
M2B
R1
M9 R1
VO+
SW A
CAZ
DC input offset voltage can be amplified by large DC open opamp open loop gain
Closed loop applications require operational amplifier with an
autozeroing circuit
RL
RL
Rlarge
Rlarge
Vin1a
Vin2a
M1
M2
Ib
Rlarge
Rlarge
Rlarge
Vin1b
Vin1b
Vin2a
Vin2b C
MFVF
Vin1a
M3
M4
Vin2b
Vin2a
Vin1a
Vin2a
Vin1a
Vin2b
C
C
M5
Vcm
C
C
A new Family of Low-Voltage Analog Circuits Based on Quasi Floating Gate Transistors, J. Ramirez-Angulo, C.
Urquidi, R.G. Carvajal, A. Lopez-Martin, IEEE Transactions on Circuits and Systems, II May 2003.
C1
Vin
Vclksh
MRlarge1
MRlarge2
Vclkn
Vclk
MRlarge2
C2
MpassN
Vclkn
MpassP
V clknsh
MpassP
MpassN
Vclk
Vclkn
Vclkn
Vout
Chold
VG
Vin
(a)
Mswitch
Vout
Chold
(c)
MRlargeP
Vclk
Vclk
Vclknsh
MRlargeP1
Vout
Vin
V1
Chold
(b)
MRlargeP2
C1
V2
C2
V2sh
V1sh
M2
M1
R
Q
(d)
Low voltage quasi-floating gate circuits using supply voltage boosting: examples of quasifloating gate supply boosting (a) Rail-to-rail sample and hold using complementary CMOS
switch (b) almost rail-to-rail to-rail sample and hold with NMOS switch, (c) rail-to-rail sample
and hold with bootstrapped switch (d) NAND gate with resistive load.
A New Analogue Switch for Very Low Voltage Applications, F. Muoz1 J. B. Palomo and M.
Kachare, IEE Electronics Letters, MAY 1 2003; v.39, no.9, p.701-702
V. CONCLUSIONS
a) Three basic techniques to reduce supply requirements of
continuous-time analog systems were discussed
b) A new family of low-voltage high performance linear analog
circuits that operate in continuous-time with single supply
voltages close to a transistor thresholds voltage presented
c) Most circuits presented are class AB and have also very low
static power dissipation
d) The circuits presented here will allow implementation of
mixed-mode systems with a single supply voltage Vdd<0.7V
in new CMOS technologies (<0.2um) with transistor
thresholds voltages close to 0.4v