IOSR Journal of VLSI and Signal Processing (IOSR-JVSP)

Volume 5, Issue 3, Ver. II (May - Jun. 2015), PP 13-19

e-ISSN: 2319 4200, p-ISSN No. : 2319 4197
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Fault Tolerant System for SRAM-Based FPGA with Scrubbers

Nikhila Admane1, Dinesh Rotake2
1,2

(Department of Electronics and Telecommunication, GHRIETW, India)

Abstract: SRAM-based FPGAs area unit extremely engaging for space applications because of their
reconfigurability, remittent development time and price, enlarged style and testing flexibility. SRAM-based
FPGAs are tremendously sensitive to Single Event Upsets (SEUs) introduced by radiation particles. So, as to
effectively establish safety- or mission-critical applications, designer has to validate the correctness of the
obtained styles for each everlasting and transient fault, throughout the planning stage of the circuits. The
proposed architecture is a group of computation strips containing computation cells and equivalent auxiliary
cells. We tend to worked with Associate in nursing approach to beat failures caused by unidirectional SEUs
occurring in forefront module, so to permit error mitigation and avoid failure because of error accumulation we
used the scrubbing technique. The proposed design is implemented on Altera cyclone II FPGA device and
verified with the help of Modelsim software.
Keywords- Fault injection, fault-tolerant (FT), FPGA, scrubbing, single event upset (SEU), Triple-modular
redundancy (TMR).

I.

Introduction

FPGAs are unit widespread for style solutions as a result of they improve logic density and
performance for several applications. SRAM-based FPGAs, specially, area unit extremely versatile as a result of
they are reprogrammable, permitting onsite style changes. However, these devices area unit powerfully prone to
house radiation effects that area unit ready to cause unwanted single event upsets (SEUs) within the
configuration memory. The radiation surroundings contain many charged particles, generated by sun activity,
that act with semiconductor atoms, exciting and ionized the atomic electrons. One particle will hit either the
combinatory or the serial logic within the semiconductor. Once a charged particle strikes a memory cells
vulnerable nodes, it generates a transient current pulse which will incorrectly activate the contradictory
transistors gate. The impact will invert the keep worth that is; manufacture somewhat flip within the memory
cell. This impact is termed a single-event upset (SEU) or soft error.
In an ASIC, the impact of a particle striking either the combinatory or the serial logic is transient; the
sole variation is however long the fault lasts [1]. In Associate in Nursing SRAMbased FPGA customizable
memory cells that area unit SRAM cells implement each the user is combinatory and serial logic. Once
Associate in Nursing upset happens within the combinatory logic synthesized within the FPGA, it corresponds
to somewhat flip in one in all the LUTs cells or within the cells that management the routing. An upset in an
LUT memory cell modifies the enforced combinatory logic. This impact is equivalent to a stuck-at fault at one
or zero within the combinational logic outlined by that LUT.
The possibility of faults taking place in the field increases with the progress of the CMOS technologies.
In order to reliably operate in a radiation environment, most systems that use FPGAs apply SEU mitigation
through some form of design redundancy. Scrubbing is an efficient fault alleviation technique for configuration
memory in SRAM-based FPGAs .These are susceptible to ionizing radiation effects, which make both a long
term cumulative degradation Total Ionization Dose( TID), as well as immediate harm Single Event Effects
(SEE). SEE can in turn be divided into soft errors, which influence information integrity, and hard errors,
which harm silicon structures.
The rest of this paper is prepared as follows. Section II gives the detailed description of the proposed
architecture for fault tolerant FPGA. Section III comprises the simulation-based fault injection technique with
the three main approaches. Block diagram of Fault-tolerant system has been presented in Section IV. Section V
contains the configuration memory scrubbing techniques. Section VI gives the simulation results of memory for
various fault injection and detection .Section VII draws some Conclusions by considering future enhancements.
1.1 Previous work
Adaptive computing systems (ACSs) accept reconfigurable hardware to adapt the system operation to
changes within the external surroundings, and to increase mission capability by implementing new functions on
an equivalent hardware platform [2].During this paper, they need offered fault-tolerant (FT) techniques for
FPGA programmable logic blocks (PLBs), developed as a part of the Roving STARs project. In most foot
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Fault Tolerant System for SRAM-Based FPGA with Scrubbers

strategies, faults area unit detected inside the operating a part of the system, and that they should be situated and
bypassed as quick as attainable in order that traditional system operation will resume as shortly as attainable.
Within the roving self-testing areas (STARs) approach, we tend to divide the FPGA into two distinct parts: the
celebs, wherever integral self-test (BIST) and designation happen, and also the operating region wherever the
system operate operates.
The high-level SEU mitigation technique used most frequently to guard styles synthesized within the
Virtex design is predicated principally on TMR combined with cleansing, that places never-ending load on the
bitstream. TMR has been shown to considerably improve style reliability; it carries a high overhead value. At a
minimum [3], full TMR of a style needs three times the hardware to realize three identical copies of a specified
circuit. Further, further logic is needed to implement the bulk logic voters. The extra hardware resources needed
to triplicate the first circuit lead to different secondary issues like inflated power and slower temporal
arrangement.
A fault-injection that has been introduced by L. Sterpone and M. Violante [4], supported the inside
configuration access port (ICAP) that recent FPGA devices from Xilinx offer. This methodology does not would
like definite hardware and each one in all the operations needed for injecting faults area unit performed on-chip.
It is able to emulate solely all the probable effects evoked by SEUs among the FPGAs configuration memory
throughout a run time application. As inadequacy, it is unable to insert bit-flips among the configuration
machine registers used alone throughout the configuration methodology. An extra defect is it desires a bunch
computer for a configuration and additionally the generation of a fault location list.
The main downside in antecedently planned architectures is that the massive area-overhead to faultcoverage magnitude relation. TMR is not capable to handle quite one fault occurring at the same time .If we
wish to implement antecedently planned fault-tolerant schemes within the existing island-style routing design,
further space is needed to implement the router logic

II.

The Proposed Architecture

Fig.1 A fault-tolerant FPGA architecture with self-repairing capabilities.

(a) Proposed architecture (b) Computation Tile (c) Computation Cell.
The proposed design is consists of variety of computation tiles (CTs), as shown in Fig.1(a) We have
planned such Associate in Nursing design, which might be enforced in existing FPGA devices with existing
island-style routing methods [5]. It is able to tolerate each unifacial bit-flip and stuck-at faults. Every
computation tile, shown in Fig. 1(b), is split into kind of computation cells. All computation tiles to boot contain
a separate portion for spare cells as shown in Fig. 1(b). This portion holds the redundant copy of the initial
perform of all computation cells gift inside identical computation tile. The region of spare cells is partly
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Fault Tolerant System for SRAM-Based FPGA with Scrubbers

reconfigurable. This region is reconfigured dynamically once every the initial and spare functions. The
coincident errors occurring inside the computation tile area unit handled by a fault-tolerant core (shown in Fig.
1(a)).The fault-tolerant core is needed to observe and handle coincident errors via dynamic partial
reconfiguration.

III.

Simulation-Based Fault Injection

Numerous hard works have been done to build up techniques for injecting faults into a system model.
A fault injection system provides the ability of injecting a fault at any preferred position into the VHDL model
of a circuit. The injection procedure permits faults to be inserted at changeable levels of VHDL ladder and for
this reason help out in evaluating the presentation of a testable structure. The foremost concern of implementing
designs targeted for space within SRAM-based FPGAs is how to alleviate and defend against an increased
possibility of faults. Simulation-based error insertion techniques are lithe and have superior controllability and
observability [6]. We will use the Simulation-based fault insertion method to inject the faults in system image,
because it provides most quantity of observability and controllability. There is Full management of each fault
models and injection mechanisms within the simulation -based fault injection technique.
There are three main approaches:
1. VHDL code modification
2. Modified simulation tools
3. Simulation command language and interface
A saboteur may be a special VHDL part additional to the initial model [7]. The mission of this part is to
change the worth, or temporal order characteristics, of one or additional signals once a fault is injected,
remaining inactive throughout the conventional operation of the system. Saboteurs can be used to replica most
faults and to simulate environmental condition such as noise or ESD. Saboteurs are injected, in sequence or in
parallel, moreover interactively at the graphic editor level or manually/automatically straight into the VHDL
source code. Serial introduction consists of flouting the signal pathway between a driver and its equivalent
recipient and inserting a saboteur in between.

IV.

BLOCK DIAGRAM

The block diagram of fault tolerant system is shown in fig.3. It is essentially carries with it fault
injection electronic equipment, SRAM-Based system, Fault detection electronic equipment and fault correction
& scrubber electronic equipment [8]. In this, we have a tendency to use the keys on the DE2 board to inject the
faults within the SRAM-Based system victimization fault injection electronic equipment.

Fig.2 Block diagram of fault tolerant system.

SRAM-based FPGAs have fastened range of resources (wires, switches and look-up tables) whose
perform is outlined by a bitstream, which provides Associate in Nursing SRAM-based FPGA the aptitude to
implement any quite digital circuit on identical chip. Designers might program SRAM-based FPGAs thousands
of times, therefore making a additional open logic style flow, facilitating increased hardware testing, and
permitting reconfigurability of the look. The last block is that the fault correction and scrubber electronic
equipment. Many scrubbing techniques mentioned in this paper. The dependability of the configuration
bitstream is crucial to SRAM-based FPGA operation. If the bitstream keep in non-volatile memory is
accidentally altered by Associate in Nursing SEU before loading onto the FPGA, then the user style delineate by
the bitstream may operate incorrectly or fail entirely. If the FPGA configuration programmed by the bitstream is
altered whereas the user style is working on the FPGA, it may cause errors within the style operation or failure
of the look. The only scrubbing methodology consists on reconfiguring cyclically the FPGA, while not acting
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Fault Tolerant System for SRAM-Based FPGA with Scrubbers

any error detection whatever. This can be referred as preventive or blind scrubbing [9], and such a scrubber is
claimed to control in open-loop.

Fig.3 Fault injection flows in combinational parts.

V.

Configuration Memory Scrubbing

5.1 Scrubbing
A scrubbing technique may be a single algorithmic rule that may be utilized in a system to mitigate
configuration memory upsets. There are two types of techniques, detection techniques and correction
techniques. A scrubbing approach consists of one or more correction techniques and variety of detection
techniques. Blind scrubbing may be a scrubbing strategy with no detection method, whereas a scrubbing
strategy with at least one discovery technique is called readback scrubbing, as a result of the present state of
configuration memory is scan back from the device to sight an upset [10]. External scrubbing, particularly with
radiation-hardened elements, is reliable however is expensive in terms of power, size, and value as a result of it
needs a minimum of one further processor. Internal scouring is superior with relevancy these constraints,
however needs further care in implementation as a result of the scrubber itself is liable to SEUs and SEFIs.
5.2 Correction Techniques
The two correction techniques widely used for scrubbing square measure golden copy correction and
error syndrome correction. In past duplicate correction, a trustworthy golden copy of the first configuration is
maintained off-chip in computer storage, like a radiation-hardened promenade, and wont to reconfigure the
FPGA as required. Blind scrubbing ways that use solely golden copy correction square measure wide utilized in
FPGA-based area platforms owing to their effectiveness and ease. To avoid the memory-access penalty of
golden copy correction, in addition because the expense of further off-chip memory, the error syndrome
correction technique is used. During this case, the correction technique decodes a slip-up syndrome to work out
the first configuration.

VI.

Simulation Result

Fig .4 Output of memory before fault injection.

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Fault Tolerant System for SRAM-Based FPGA with Scrubbers

Fig .5 Output of memory after stuck-at-0 fault injection.

Fig .6 Output of memory after stuck-at-1 fault injection.

Fig .7 Output of memory after Transient fault injection.

Fig .8 Output of memory after Delay fault injection.

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Fault Tolerant System for SRAM-Based FPGA with Scrubbers

Fig.9 fault_detected = 1; Stuck-at-0 fault is detected.

Fig.10 fault_detected = 1; Stuck-at-1 fault is detected.

Fig.11 fault_detected = 1; Transient fault is detected.

Fig.12 fault_detected = 1; Delay fault is detected.

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Fault Tolerant System for SRAM-Based FPGA with Scrubbers

VII.

Conclusion

This paper presents a fault tolerant system for SRAM-based FPGA in conjunction with scrubbers that
are used to mitigate errors caused by unidirectional SEUs occurring either all together or one at a time. In the
proposed architecture, for injecting fault simulation based fault injection technique is used as it provides
maximum amount of controllability and observability. Using partial reconfiguration capabilities existing in
some FPGAs, the proposed approach could lead to perceptible time savings compared with other fault injection
techniques. Simulation results of memory are performed on Modelsim software indicates that the fault injection
and detection is performed correctly as per the expectation. The fault tolerant system is able to tolerate both
permanent and transient faults. In future Error- detection schemes and SEUs occurring in the nets can be
studied.

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