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Tim Cheng,
02_fault_model, v1.0
02_fault_model, v1.0
02_fault_model, v1.0
Material defects
Time-dependent failures
Dielectric breakdown
Electromigration
Packaging failures
Contact degradation
Seal leaks
02_fault_model, v1.0
02_fault_model, v1.0
FAULTY RESPONSE
TRUE RESPONSE
0
0
0 (1)
0 (1)
STUCK - AT - 1
02_fault_model, v1.0
02_fault_model, v1.0
Required
fault coverage
02_fault_model, v1.0
Definitions
Given
T1 is set of all tests for fault F1
T2 is set of all tests for fault F2
F2 dominates F1
T2
T1
T1=T2
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02_fault_model, v1.0
Fault Equivalence
Two equivalent faults are detected by exactly
the same tests
s-a-0
s-a-1
s-a-1
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s-a-1
s-a-1
s-a-0
s-a-1
s-a-1
s-a-0
s-a-0
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02_fault_model, v1.0
0
0
0
0
0
0
0
(a)
0
0
0
0
(b)
K.T. Tim Cheng,
02_fault_model, v1.0
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Functional Equivalence
s - a. 0
x
s. a. 0
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02_fault_model, v1.0
F2: s - a - 1
T2
T1
s -a-1
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Checkpoint Faults
Checkpoints
Primary inputs
Gate-inputs fed by fanout lines
Checkpoint faults
Sufficient to model stuck-at faults at checkpoints
Model only input faults in fanout-free circuit
K.T. Tim Cheng,
02_fault_model, v1.0
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02_fault_model, v1.0
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Fault Detection
For combinational circuits: A test vector t
detects a fault f iff Zf(t) Z(t)
s. a. 0
X
Example :
C
B
Z (A, B, C) = AC + BC
Zf (A, B, C) = BC
>t = (1, 0, 0) is a test for A s.a.0. fault
K.T. Tim Cheng,
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02_fault_model, v1.0
X4
Z = (X2 + X3) X1 + X1 X4
Fault: X4 s-a-0
Zf = (X2 + X3) X1
Z(x) Zf(x) = X1 X4 = 1
Any of the four tests: 0 0 0 1, 0 0 1 1, 0 1 0 1, 0 1 1 1 detects f
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Sensitization
X2
X3
0
0
X1
G1
0
G3
0
G5
G2
X4
V/Vf :
0/1
x
s. a. 1
0/1
G4
0/1
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Error Propagation
Propagating fault effect to a primary output
Example: the fault effect propagates along
the path G2, G4, G5
A line is sensitized to the fault by the test
t if its value in the test t changes in the
presence of the fault f
Example: G2, G4 and G5 are sensitized.
A path composed of sensitized line is called
a sensitized path.
Example: path G2-G4-G5 is a sensitized path
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10
l x
m
n
l
m
n
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Redundancy
s. a. 0
l x
m
n
l
m
n
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Conflict!
0
1 1
0
s.a.0
A
B
0
C
Z is glitch-free
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12
An Example
y1
X
y2
y1
y2
y1
X
y2
Xa
y1
y2
X
y1
Y1
y1
Y2
y2
b
y2
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02_fault_model, v1.0
State table:
In itia l
S ta te
Y1
Y2
A, 0
D, 0
C, 1
C, 1
B, 1
A, 0
A, 1
B, 1
O u tp u t S e q u e n c e to T =
10111
F a u lt-fr e e
a s-a -1
b s-a -0
01011
01010
01101
11100
11100
11101
00011
00010
01010
11001
10010
11010
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Stuck-Open Example
Vector 1: test for A s-a-0
(Initialization vector)
pMOS
FETs
1
VDD
Stuckopen
1(Z)
Good circuit states
nMOS
FETs
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Stuck-Short Example
Test vector for A s-a-0
pMOS
FETs
1
0
VDD
IDDQ path in
faulty circuit
Stuckshort
nMOS
FETs
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Bridging Faults
Shorting of adjacent lines (layout dependent)
Usually assuming a low resistance path (hard short)
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Delay Faults
Used to test whether device meets performance
specification
Related to propagation delay in combinational circuit
(from inputs/flip-flops to outputs/flip-flops)
Two types of faults
Path-delay fault
Gate-delay fault
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Gate-delay-fault:
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PLA Faults
Stuck-at faults
Cross-point faults
Bridging faults
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f1
f2
f2
P1
f1
P2 x
P2
P1
AND-Array
PLA
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02_fault_model, v1.0
f1
f2
AB
p1
C 00 01 11 10
0 1
1 1 1 1
p2
p2 x
C
s-a-1
K.T. Tim Cheng,
p1 [ ( C, p1 ) MISSING
OR - ARRAY
DISAPPEARANCE
p1 = B.C.
p1 = B
02_fault_model, v1.0
..
. . p.1
. .p.2
AND - ARRAY
GROWTH
p1
f1 = p1 + p2
f1 = p2
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20
f1
f2
AB
P1
SHRINKAGE
DISAPPEARANCE
P2 x
C 00 01 11 10
0 1
1 1 1 1
p2
p2 : ( C, p2 ) ADDED
APPEARANCE
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Bridging faults
99% covered by stuck-at fault tests
Layout-dependence in all PLAs
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