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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSII: EXPRESS BRIEFS, VOL. 53, NO. 4, APRIL 2006
I. INTRODUCTION
Manuscript received March 22, 2005; revised June 22, 2005. This work was
supported by the Research Grant Council of Hong Kong SAR Government
under Project HKUST 6150/03E. This paper was recommended by Associate
Editor S. Banerjee.
M. Siu was with Department of Electrical and Electronic Engineering, The
Hong Kong University of Science and Technology, Hong Kong. She is currently
with Fujitsu Microelectronics Pacific Asia Ltd., World Commerce Centre, Tsim
Sha Tsui, Hong Kong (e-mail: eesman@ee.ust.hk).
P. K. T. Mok, Y.-H. Lam, and W.-H. Ki are with Department of Electrical and
Electronic Engineering, The Hong Kong University of Science and Technology,
Hong Kong (e-mail: eemok@ee.ust.hk; hylas@ee.ust.hk; eeki@ee.ust.hk).
K. N. Leung was with Department of Electrical and Electronic Engineering,
The Hong Kong University of Science and Technology, Hong Kong. He is currently with Department of Electronic Engineering, The Chinese University of
Hong Kong, Shatin, Hong Kong (e-mail: knleung@ee.cuhk.edu.hk).
Digital Object Identifier 10.1109/TCSII.2005.862024
. An error voltage
is then
where
in a
generated to PWM controller to determine duty cycle
switching period
for voltage regulation, according to [11]. A
buck regulator operated in continuous-conduction mode (CCM)
has a conversion relationship given by
(2)
where
and
are upper and lower bounds of the ramp signal
is changed,
in the PWM controller. As in Fig. 2, when
is changed by changing
with different
according to
is connected at
(2). Since a large compensation capacitor
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, the reference
B. Loop Gain
Stability of power converters is studied by loop-gain analysis.
of a voltage-mode buck converter in
The open-loop gain
CCM is given by [11], [12]
(5)
where
and
are the transfer functions of the error amis
plifier and power stage, respectively. As
used in the proposed EPP scheme, the loop gain of the proposed
structure is given by
to determine
is given by
(3)
, the relation
(4)
(6)
The stability of the voltage-gain buck regulator is independent
. Stability of the proposed buck regulator can be achieved
of
by dominant-pole compensation. A low frequency pole, which
ensures complex poles from the power stage located after the
unity-gain frequency of the loop gain, is created at the erroramplifier output.
C. Circuit Implementation
Advanced circuit implementation is needed to achieve the
EPP scheme successfully. The circuit implementation involves
designs of voltage-controlled oscillator (VCO) to provide a
, and a constant switching
ramp signal with
and
to
frequency, voltage summation circuit to sum
form , and over-current protection circuit. The circuit designs
of these three important building blocks are introduced below.
1) VCO: The VCO design is the key of the EPP scheme.
to
The ramp signal amplitude needs to change from
with a constant switching frequency. The
proposed VCO design is shown in Fig. 4. When the resistor
is designed as , as stated in (1), is
ratio
given by
(7)
This current is copied by the current mirror into two current
branches. One is to charge a capacitor
to form the ramp
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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSII: EXPRESS BRIEFS, VOL. 53, NO. 4, APRIL 2006
(8)
where is the switching frequency of the designed buck converter, and hence
(9)
to give the relationship of switching frequency of
(10)
and
From (8), the switching frequency is independent of
is fixed by the design of
and
, and the ramp amplitude
and
.
changes between
is set to about 0.2 V so that
V
In the design,
to allow the error amplifier to operate in the high-gain region.
that is independent of injected current
Moreover, to provide
, an inverted linear regulator is used, as shown in Fig. 5.
The output voltage is defined by the input of the error amplifier,
while regulation is continuously achieved by negative feedback.
Since there are two high-impedance nodes, Miller compensation
, can
is used. The design of the compensation capacitor used,
be evaluated by [13]
(11)
where
and
are transconductance of the error amplifier
and the nMOS transistor, respectively, at minimum
, and
is the worst-case parasitic capacitance at the drain of the nMOS
transistor. Since this circuit is to provide a stable DC voltage,
provides more stable
the speed is not important and large
operation.
2) Voltage Summation Circuit: The proposed current-mode
voltage summation circuit is shown in Fig. 6. The input is
from the error-amplifier output, while
at
is generated
is converted into
given by
by the circuit in Fig. 5. Thus,
, and
is copied to another current branch to
by
form
(12)
297
Fig. 9. Measured ramp signals of the buck regulator with EPP by the proposed
VCO in Fig. 4 at different input voltages.
Fig. 11 shows
(input of the PWM controller) for the conventional and the EPP controls. As predicted, is slowed down
slowly.
by the large compensation capacitor to generate new
quickly.
However, in EPP changes much faster to provide
It is noted that there is a small change on
due to the nonideal
power transistors and inductor on nonzero on-resistance and series-equivalent resistance. Since the change is small, it does not
degrade the tracking speed significantly.
V. CONCLUSION
Fast reference tracking feature is very important for systems
powered up by adaptive supply voltages. Voltage-mode PWM
power converters compensated by dominant-pole approach has
slow dynamic response, which is mainly limited by the large
off-chip compensation capacitor. In this paper, this problem is
solved by the proposed End-Point Prediction scheme and circuit
implementation. With the EPP scheme, the simplicity and the
robustness of a voltage-mode buck converter with dominantpole compensation are retained, while the dynamic response is
greatly improved by just an additional adder circuit. Moreover,
a buck converter using the proposed idea and implementation
method has been designed and fabricated. Measurement results
support the proposed idea.
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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSII: EXPRESS BRIEFS, VOL. 53, NO. 4, APRIL 2006
REFERENCES
ACKNOWLEDGMENT
The authors would like to thank S. F. Luk and F. Kwok for
their technical support.