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# Simulation of Power Electronic

## Systems Using PSpice

Presentation Outlines
In order to use Pspice for power electronic
systems, we have to:
Know background of SPICE
Understand Power Electronics Circuits/Systems
Know how to use VPULSE to generate useful
waveforms
Know how to make simple models using ABM

Scope
This presentation covers:
PSpice
System/Circuit Level Simulation
Power Electronic Circuits/Systems
Simulation

SPICE/PSpice
Did you know?
SPICE turns 38 years old this year
I Knew SPICE when she was 17 years old
I love PSpice because she can do almost
anything I need with FOC.
I like to talk about her.

Why simulation?
Simulations are essential ingredients of the
analysis and design process in power
electronics:

## Saving of development time

Saving of costs (burnt power circuits tend
to be expensive)
Better understanding of the function

continued
Testing and finding of critical states and
regions of operation (Worst Case Analysis)
Stress test (Smoke Analysis)
Optimization of system
Testing new ideas

Overview
Simulation of analog circuits normally
uses three basic tools:
SPICE simulator,
Mathematical analysis package,
and Microsoft Excel.

SPICE
Simulation Program for Integrated Circuit
Emphasis
Intended for ICs, not for power electronics.

## Uses iterative Newton-Raphson Algorithm

to solve a set of nonlinear equations.

SPICE LIMITATIONS
The Newton-Raphson algorithm is guaranteed
to converge if the equations is continuous.
The transient analysis has the additional
possibility of unable to converge because of the
discontinuity in time.

SPICE LIMITATIONS
Computer Hardware Limitation:
Voltage and currents are limited to +/-1e10.
Derivatives in PSpice are limited to 1e14.
The arithmetic used in PSpice is double
precision and has 15 digits of accuracy.

10

## Power Electronic Circuit

Power electronic circuits
are characterized by switching
on and off of power
semiconductor switches; the
generated waveform is
passed through inductors and
capacitors for filtering.

11

## Power Electronic Circuit

Due to switching action of the switch,
discontinuity (in circuit variables and in
time) can easily occur during simulation,
Avoid discontinuity

12

Discontinuity Analogy:
Unacceptable Bump

Acceptable Bump

## Whole car shakes when I hit a bump on the road

PSpice doesnt like discontinuity as we dont like
13

Avoid Discontinuity
S

VGS

VGS

## All signals must be made less discontinuous

All relationships must be continuous
14

VPULSE
Waveform generator
PULSE
SAWTOOTH
TRIANGULAR

15

VPULSE
Waveform generator
In order to use PSpice for power electronic
circuits, the first thing you have to know is to
program VPULSE to produce these waveforms:
PULSE
Sawtooth
Triangular

16

VPULSE
Waveform Generator Part
has 7 parameters to set
TD can be zero, others can not!
V1=
V2=
TD=
TR=
TF=
PW=
PER=
know

PW

V2

V1

TD
PER

## what parameters to adjust and to fix.

17

VPULSE
To Generate Pulse Waveform
Very small values for TR and TF
Duty cycle = PW/PER

V1=0
V2=12
TD=0
TR=10n
TF=10n
PW=10u
PER=20u

PW
V2

V1

TR 0

TF 0

PER
18

A Typical application
Buck Converter (Open Loop)
M2
IR F15 0
10 0uH

68 0uF

V2
V3
20 V

10

MU R1 520

V+

V-

TD = 0
TF = 1 0n
PW = 10u
PE R = 20u
V1 = 0
TR = 1 0n
V2 = 1 2V

ON and OFF.
19

V1=0
V2=12
TD=0
TR=10n
TF=10n
PW=10u
PER=20u
PW 10
Duty Cycle, D

50%
PER 20
20

## Its Pulse (II)

V1=0
V2=12
TD=0
TR=10n
TF=10n
PW=5u
PER=20u

PW
5
D

25%
PER 20
21

VPULSE
To Generate Sawtooth
Very small values for TF and PW
TRPER
V1=0
V2=12
TD=0
TR={20u-20n}
TF=10n
PW=10n
PER=20u

PW

TF

PER

22

A Typical application
Buck Converter (Closed Loop)
M2
IR F15 0
10 0uH

68 0uF

V2
+
-

+
-

Gate
Driver

20 V

Sawtooth
Gen.

V4

Comparator
+

Control
0 Signal

10

E1
MU R1 520

E
GA IN = 4

## For Closed-loop, the control signal

is compared with a sawtooth
waveform to produce the pulse
waveform.
23

PSpice Implementation
M2
IR F15 0
10 0uH

+
-

68 0uF

Gate
Driver

+
-

V2
20 V

10

E1
MU R1 520

E
GA IN = 1

Comparator
E2

V5

Control
2.5 Vdc
Signal

IN +OU T+
IN - OU TETABL E
V3

Gate Driver E
Comparator ETABLE

TD = 0
TA BLE = (0 ,0 ( 200u ,12 )
TF = 1 0n
V( %IN +, % IN-)
PW = 10n
0PE R = 20u
V1 = 1 V
TR = { 20u- 20n}
V2 = 4 V

Vpulse

Sawtooth VPULSE
Control VDC

24

Control
Sawtooth

D = 50 %

Pulse

25

## Its Waveform (II)

Control
Sawtooth

D = 33%
Pulse

Control Signal.
26

VPULSE
To Generate Triangular wave
Very small value for PW
TRTF PER/2
V1= -1
V2= +1
TD=0
TR= {10u-10n}
TF= {10u-10n}
PW=20n
PER=20u

PW

PER

27

VPULSE
Its Triangular Wave

28

Triangular Wave
Typical applications
Bipolar SPWM
TR I

SI NE
V

V1 = -1
V1
V2 = +1
TD = 0
V2
TR = { (1/(F TRI *2))- 10n}
VO FF = 0
TF = {( 1/(F TRI* 2)-1 0n)}
VA MPL = { Ma}
PW = 20n
FR EQ = {F SIN E}
PE R = {1/F TRI }
PH ASE = { -90/ Mf }

## VD C*( V(SI NE) -V(TRI))/ ABS (V(S INE )-V( TRI) )

SP WM
V

Comparator

PARAMETERS:
Ma = 0 .8
Mf = 2 1
FTRI = {FS INE *Mf }
FS INE = 5 0
VD C = 100

29

Triangular Wave
Typical applications
Bipolar SPWM
1.0V

0V

-1.0V
V(TRI)

V(SINE)

100

-100
40ms
42ms
V(SPWM)
0

44ms

46ms

48ms

50ms

52ms

54ms

56ms

58ms

60ms

Time [ms]
30

Triangular Wave
Typical applications
Unipolar SPWM
TR I

V1 = -1
V1
V2 = +1
TD = 0
TR = { (1/(F TRI *2))- 10n }
TF = {( 1/(F TRI *2)-1 0n)}
PW = 20n
PE R = {1/F TRI }

SI NE1
V

0.5 *VD C*( V(SI NE1 )-V( TRI) )/AB S(V (SIN E1) -V(TRI))

V2

VO FF = 0
VA MPL = { Ma}
FR EQ = {F SIN E}
PH ASE = { -90/ Mf }

Comparator 1

0
SI NE2
V

PARAMETERS:
Ma = 0 .8
V2 a
Mf = 2 1
FTRI = {FS INE *Mf } VO FF = 0
VA MPL = { Ma}
FS INE = 5 0
FR EQ = {F SIN E}
VD C = 100
PH ASE = { -90/ Mf +180}

0.5 *VD C*( V(SI NE2 )-V( TRI) )/AB S(V (SIN E2) -V(TRI))
B
V

Comparator 2
31

Triangular Wave
Typical applications
Unipolar SPWM
1.0V

0V

-1.0V
V(SINE1)

V(SINE2)

V(TRI)

100V

0V

-100V
40ms
42ms
V(A)-V(B)

44ms

46ms

48ms

50ms

52ms

54ms

56ms

58ms

60ms

Time [ms]
32

## Analog Behavior Model (ABM)

Makes the Circuit Simpler
Use equations to model circuits
Comparator
Single Phase Rectifier
Three Phase Rectifier
Buck Converter in CCM
Single Phase Inverter

33

ABM
Behavior Model of Comparator
V(out)

V(-)
V(+)

## IF the voltage at the terminal V(+) is

greater than the voltage at terminal
V(-) the output V(out) is HIgh,
otherwise the output is LOw.

## (1) Using IF-Then-Else function

IF(V(+)>V(-),HI, LO)

## (2) Using signum function

(V(+)-V(-))/ABS(V(+)-V(-))
34

ABM
Behavior Model of Comparator
V(out)

+
(3) Using I/O graph
V(out)

V(-)
V(+)

## (4) Using Op-amp alike

V(+)
V(out)
+
- A*(V(+)-V(-))

V(+)-V(-)
V(-)

0
35

ABM
Comparator in PSpice
IF (V(S INE )>V( TRI) ,10, -10)
TR I

V1 = -1
V1
V2 = +1
TD = 0
TR = { (1/(F TRI *2))- 10n }
TF = {( 1/(F TRI *2)-1 0n)}
PW = 20n
PE R = {1/F TRI }

SI NE
V

V2
VO FF = 0
VA MPL = { Ma}
FR EQ = {F SIN E}
PH ASE = { -90/ Mf }

SI NE E1

2
TR I

IN +OU T+
IN - OU TETABL E
V( %IN +, % IN-)

ou t2
V

## TA BLE = (- 100 u,-10 ) (1 00u, 10)

PARAMETERS:
Ma = 0 .8
Mf = 2 1
FTRI = {FS INE *Mf }
FS INE = 5 0
VD C = 10

ou t1

## NO 2 is implemented using ETABLE

Others are implemented using ABM part
NO 2 & NO 4 are suitable for Op-amp
(Error Amplifier)

ou t3
V

## LIMIT( 10k* (V(S INE )-V( TRI) ),10 ,-10)

ou t4
V

36

ABM
Behavior Model of Comparator
1.0V

0V

-1.0V
V(TRI)

V(SINE)

10V

0V

## These waveforms come from the outputs of four comparators

-10V
40ms
42ms
44ms
46ms
V(OUT3) V(OUT2) V(OUT1) V(OUT4)

48ms

50ms

52ms

54ms

56ms

58ms

60ms

Time [ms]

37

ABM
Behavior Model of Rectifier (I)
D3
Db reak

D4
Db reak

V1 a
VO FF = 0
VA MPL = 3 40
FR EQ = 50

R1 a
1k

D5
Db reak

D6
Db reak

0
in

V(out)=ABS(V(IN))
V1

E1

VO FF = 0
VA MPL = 3 40
FR EQ = 50

R1 b

IN +OU T+
IN - OU TEV ALU E

1k

ABS(V(IN))
0

0
38

ABM
Behavior Model of Rectifier (II)
+
Van
Vbn
Vcn

V(out) = 0.5*(ABS(V(an)-V(bn)
+ABS(V(bn)-V(cn))
+ABS(V(cn)-V(an)))
-

39

ABM
Behavior Model of Buck in CCM
IR F54 0

10 0uH

V2

20 Vdc

V3

Vd

MU R1 520

TD = 0
TF = 1 0n
PW = 10u
PE R = 20u
V1 = 0
TR = 1 0n
V2 = 1 2V

d is a PWM signal
with 1V amplitude.

68 0uF

Vd = d*Vin

+
d
Vin

RL

E1
IN +OU T+
IN - OU TEV ALU E

V(%IN+)*V( %IN-)

Vd

10 0uH

68 0uF

RL

0
40

ABM
Behavior Model of Inverter
a

+
Vab
-

VDC

SINE
TRI

Bipolar SPWM
E1
IN+ OUT+
IN- OUTEVALUE

+
Vab
-

## VDC*(V(%IN+)-V( %IN-))/ABS(V(%IN+)-V( %IN-))

0
41

#TIPS
There are many different ways
to model the same thing. So, be
creative!
Use a simple model wherever
possible to reduce modeling time
and make simulation run faster
and converge better!
42

43

## Our Case Study

A Buck Converter with VMC
A Simple PWM Controller IC Model
A PWM IC Controller IC Model including
Soft-start
A PWM IC Controller IC Model Including
Soft-start, Duty Cycle Max and Current
Limiter
44

+
-

+
-

## Our Case Study

A Buck Converter with VMC

SG3525
PWM Controller IC

45

SG3525
PWM Controller IC
Key Functions:
Oscillator
(Sawtooth Generator)
PWM Comparator
and SR Flip-flop
Error Amplifier
5.1 V Reference
Pulse Steering
Logic
Shutdown and
Soft-start Circuitry
46

SG3525
We do not need to have SG3525 model in
PSpices library to simulate buck converter with
VMC.
To verify the controller design, all we need are
functional models of these:
Error Amplifier
Comparator
Sawtooth generator

47

SG3525
A Simple Model
Sawtooth

+
Error Amp.

To MOSFET
Driver

Comparator

48

+
-

+
-

Buck Converter

## Consider we know all

circuit parameters.
Our interest is to
simulate the system.

Comparator

Error Amp.

## The controller is used

to regulate the output
voltage at 5 V.

Vref
VP ULSE

Sawtooth

49

## A Buck Converter with VMC

The controller is a linear controller and the
design is based on a small-signal model.
So, the controller can not cope with large
signal scenario such as start-up.
Initial values, which are equal to their steady
state values, for the inductor current and the
capacitor voltage must be set.

50

How to set a load disturbance ?
3A

1A
0A
8 ms

8.5 ms

R = 1.666 W
R=5W

R=5W

51

## Our Case Study

How to set load disturbance ?
Using IPULSE

I1 = 1
I2 = 3
TD = 8m
TR = 0.1u
TF = 0.1u
PW = 0.5m
PER = 1m

I1

## Allocate enough times for TR and TF

52

How to set load disturbance ?
Using SW_tclose and SW_topen
TOPEN = 8.5m
1

TCLOSE = 8m

2 .5

5//2.5 =1.666
53

i nput

M1
IRF150

R1av

L1
out
{L}

50m

V 0Vdc

IC = 1A

V2

GA IN = 3

R2av
{Resr}

D5
Dbreak

E1

+
-

+
-

15Vdc

C1av
{C}
IC = 5V

I1 = 1
I2 = 3
TD = 8m
TR = 0.1u
TF = 0.1u
PW = 0.5m
PE R = 1m

I1

C3av

E2av

R7av

C4av

{R2}

{C2}

{R1}

{C1}

OUT+ IN+
OUT- IN-

(0,0) (250u,5) V1 = 0
0

C2av

E1av

OUT+ IN+
OUT- INET ABLE
V(%IN+, %IN-)

R6av{C3}

V2 = 3
TD = 0
TR = {10u-20n}
TF = 10n
PW = 10n
PE R = 10u

R4av

{R3}

V2av

ET ABLE
-V(%IN+, %IN-)

V1

R2

## (0,0) (250u ,6)

0

{Rbias}

{Vref }
0

54

5.2V

Output Voltage
5.0V

4.8V
4.0A

V(OUT)

2.0A

0A
7.8ms
7.9ms
8.0ms

Inductor Current

8.1ms

8.2ms

8.3ms

8.4ms

8.5ms

8.6ms

8.7ms 8.8ms

Time [ms]

55

Input Disturbance
How to set an input disturbance ?
Let the input disturbance is:
25 V

15 V

0V
8 ms

8.5 ms

56

Input Disturbance
How to set an input disturbance ?

## Use VPWL (Piece-Wise Linear Voltage Source)

25 V

15 V

0V
8 ms

9 ms

PWL(T1,V1)(T2,V2)(T3,V3)(T4,V4)(T5,V5)

## PWL (0,15) (8m,15) (8.0001m,25) (9m,25) (9.0001m,15)

57

Input Disturbance
Responses
30V
25V

Input Voltage

20V
10V
V(INPUT)
5.1V
5.0V

Output Voltage

4.9V
4.8V
V(OUT)
2.0A

Inductor Current

1.0A
0A
7.8ms
I(L1)

8.0ms

8.2ms

8.4ms

8.6ms

8.8ms

9.0ms

9.2ms

9.4ms

9.6ms

9.8ms 10.0ms

Time [ms]

58

Start-up Scenario
Previous simulation skips start-up scenario.
To know how the controller handles start-up, set the initial
values for iL and vc to zero.
20

15

Inductor Current
10

Output Voltage
5

0
0s
I(L1)

100us
V(OUT)

200us

300us

400us

500us

600us

700us

800us

Time [s]
59

Start-up Scenario
A very large overshoot and undershoot occur in inductor current.
The duty cycle is at first at 1 for a long time and later at 0 for a long
time too, then after that it gradually increases.
Convergence problem can easily occurs at this extreme condition.

5.0V

2.5V

Gate Signal
0V
V(E1:1)
20
15
10
5
0
0s
I(L1)

100us
V(OUT)

200us

300us

400us

500us

600us

700us

800us

Time
60

Start-up
In practical circuit, another auxiliary controller is
required to handle start-up.
This circuit is known as soft-start.
Soft start
Controller

5.0V

VMC
Controller

2.5V

Gate Signal
0V
V(E1:1)
20
15
10
5
0
0s
I(L1)

100us
V(OUT)

200us

300us

400us

500us

600us

700us

800us

Time [s]

## Soft-start circuit works by gradually increasing the duty

cycle. So do the inductor current and capacitor voltage.
61

Soft-start
The previous PWM IC model is very useful and it is
simple to set-up in PSpice.
It is enough to verify the design of controller based on
small signal model.
However, to add soft-start controller and other
protection circuits, we need a more flexible PWM IC
model.

62

Oscillator

Clock

Sawtooth
SR Flip-flop

Comparator

+
+

S
R

Error Amp.

## The output of SR flip-flop is set by the Clock.

The output of SR flip-flop is reset by Comparator.
63

Oscillator

Clock

Sawtooth
Error Amp.
SR Flip-flop

Comparator
+
+

Analog
Signals

R
R
Digital
Signals

## Analog signals can be added at minus terminals of the

comparator.
Digital signals can be added at the input Resets of FF.
64

Soft-start
Sawtooth

Control
Signal

Error Amp.
Output
Soft-start

To R of SR
Flip-Flop

## Sawtooth is still compared with the control signal.

But, Control Signal can be either Error Amp. output
(EAO) or Soft-start signal (SS), whichever is lower.
65

Soft-start
Sawtooth
50 A

Soft-start (SS)
C

+
-

Error Amp.
Output (EAO) -

To R of SR
Flip-Flop

## The soft-start voltage is the capacitor voltage.

The capacitor C is charged by a constant current
source of 50 A. The result is a ramp voltage.
C determines the duration of soft-start.
66

Soft-start
How Soft-start works?
Soft-start
Voltage

V
I C
t

4V
Slope =

50
C

C = 125 nF

10 ms

## Use PWL to emulate soft-start voltage

For the graph, PWL(0,0)(10ms,4V)
67

Soft-start
Sawtooth
50 A

SS
C

EAO

Control
Signal

To R of SR
Flip-Flop

Selector

## We need a selector to select either SS or EAO,

whichever is lower, to be Control Signal.
We can use IF-Then-Else function
IF(SS < EAO, SS, EAO)
68

Soft-start
In PSpice
C3av

SELECTOR
IF-Then-Else
-V(%IN+, %IN-)

IF( V(%IN2)<V(%IN1),
V(%IN2),V(%IN1) )

(0,0) (250u,5)
E2av

ET ABLE

OUT+ IN+
OUT- IN-

R7av

C4av

{R2}

{C2}

{R1}

{C1}
R4av

SoftS

R2

## (0,0) (500u ,5)

{Rbias}

V1
V3

Vout

{R3}

V2av

ET ABLE
-V(%IN+, %IN-)

Comparator
0

C2av

OUT+ IN+
OUT- IN-

Sawtooth

V1 = 0
V2 = 3
TD = 0
TR = {10u-20n}
TF = 10n
PW = 10n
PE R = 10u

R6av{C3}

E1av

1 err_out
control

Error Amplifier

{Vref }
0

TRAN = PWL(0,0)(10m,4)

Sawtooth
Generator

69

Soft-start
Start-up Signals
Control = IF(SS < EAO, SS, EAO)
5.0V
2.5V

## Error Amplifier Output

0V
5.0V

Soft-Start Signal

2.5V
0V
2.0V
1.0V
0V
0s

Control Signal
1.0ms

2.0ms

3.0ms

4.0ms

5.0ms

6.0ms

Time [ms]

70

Soft-start
C = 125 nF (Too Small!)
7.5V

5.0V

2.5V

tstart-up = 1ms

V(OUT)

0V
4.0A

I(L1)

2.0A

0A
0s

1.0ms

2.0ms

3.0ms

4.0ms

5.0ms

6.0ms

Time [ms]
Soft-start

## signal ramps up too fast

71

Soft-start
Start-up Current and Voltage
7.5V

C = 25 nF

5.0V

2.5V

tstart-up = 3.2 ms

V(OUT)

0V
2.0A

1.0A

0A
0s

I(L1)

1.0ms

2.0ms

3.0ms

4.0ms

5.0ms

6.0ms

Time [ms]

## Still has a small overshoot and undershoot in

inductor current
has a room for improvement by increasing C.
72

Soft-start
Start-up Current and Voltage
6.0V

4.0V

V(OUT)

2.0V

0V
V(OUT)
2.0A

1.0A

I(L1)
SEL>>
0A
0s

5ms

10ms

15ms

20ms

25ms

30ms

35ms

I(L1)
Time

73

Oscillator

Clock

Sawtooth
Error Amp.
SR Flip-flop

Comparator
+
+

Analog
Signals

R
R
Digital
Signals

## To add digital signals for protection.

For examples, Maximum Duty Cycle and Current Limiter
Flip-flop can be reset either by PWM comparator, or
Maximum duty cycle, or Current Limiter.
74

DutyMax and CurrentLimit
Maximum duty cycle limiter is in digital form. It can be
applied directly to the Reset of FF.
The switch current (or inductor current) must be compared
with its limit value to produce a digital signal.
Dutymax
Vdutymax
V1 = 0
V2 = 5V
TD = {10u*0.85 }
TR = 10n
TF = 10n
PW = {(10u-10u*0.85)-20n}
PE R = 10u
0

RESET 3 (DMax)
1
2
Q

U10A
7402

U12A
7432

RESET 2 (CL)
1
2
1

U11A
7402

SET
S
V1 = 0
V2 = 5V
TD = 0
TR = 1n
TF = 1n
PW = 0.1u
PE R = 10u

VClock

U16A
7432

Ecurr_l imit
OUT+ IN+
OUT- IN-

I(L1)

8A

ET ABLE

0 +V(%IN+, %IN-)
(0,0) (250u,5)

RESET 1 (EAO)

## Set only by one i. e. the clock

Reset can be done by three, whichever
comes first.
75

DutyMax and CurrentLimit
CLOCK

5.0V
2.5V
0V
V(S)
5.0V

DUTYMAX

2.5V
0V
V(DUTYMAX)
4.0V

SAWTOOTH

2.0V
0V
0s

20us
V(SAWTOOTH)

40us

60us

80us

100us

120us

140us

160us

180us

200us

Time

DUTYMAX signal will only reset FF if the duty cycle is more than 0.85
This DUTYMAX is to make sure that the MOSFET always turns-off for
each cycle
CurrentLimit signal will only appear and reset FF if the peak switch is
greater than pre-specified value.
76

DutyMax and CurrentLimit
10

Output Voltage
5

Inductor Current
0
5.6ms
V(OUT)

5.7ms
I(L1)

5.8ms

5.9ms

6.0ms

6.1ms

6.2ms

6.3ms

6.4ms

6.5ms

6.6ms

Time

## We want to limit this current at 8A

77

DutyMax and CurrentLimit
What do we expect ?
10

8A Limiter
Output Voltage

Inductor Current
0
5.6ms
V(OUT)

5.7ms
I(L1)

5.8ms

5.9ms

6.0ms

6.1ms

6.2ms

6.3ms

6.4ms

6.5ms

6.6ms

Time

Reset by EAO

Reset by
DutyMax

Reset by
CurrentLimit

Reset by EAO

78

DutyMax and CurrentLimit
5.0V
2.5V
0V

V(CLOCK)
5.0V
2.5V
0V

5.0V

V(PWMCOMP)

V(Q)

2.5V
0V
5.0V

V(CURRENTLIM)

V(Q)

2.5V
0V
5.90ms

5.95ms
V(Q)

V(DUTYMAX)

6.00ms

6.05ms

6.10ms

6.15ms

6.20ms

Time [ms]

at 6.0 ms
79

Knowing

## There is no substitute for knowing

what we are doing

80

CONCLUSION
In order to simulate power electronic circuit:
Know how to program VPULSE for Pulse,
Sawtooth, and Triangular waveforms.
Avoid discontinuity at any cost
Use the simplest model possible
Use a simple model first, and add
complexity in stages.
No replacement for good understanding

81

Q&A

82