Data Sheet

To our customers,
Old Company Name in Catalogs and Other Documents

On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology
Corporation, and Renesas Electronics Corporation took over all the business of both
companies. Therefore, although the old company name remains in this document, it is a valid
Renesas Electronics document. We appreciate your understanding.
Renesas Electronics website: http://www.renesas.com
April 1st, 2010

Renesas Electronics Corporation
Issued by: Renesas Electronics Corporation (http://www.renesas.com)

Send any inquiries to http://www.renesas.com/inquiry.
Notice
1.
2.
3.
4.
5.
6.
7.
All information included in this document is current as of the date this document is issued. Such information, however, is
subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please
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Standard:
8.
9.
10.
11.
12.
Computers; office equipment; communications equipment; test and measurement equipment; audio and visual
equipment; home electronic appliances; machine tools; personal electronic equipment; and industrial robots.
High Quality: Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anticrime systems; safety equipment; and medical equipment not specifically designed for life support.
Specific:
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PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
R8C/36A Group
RENESAS MCU
1.
REJ03B0265-0110
Rev.1.10
Sep 28, 2009
Overview
1.1
Features
The R8C/36A Group of single-chip MCUs incorporate the R8C CPU core, employing sophisticated instructions for
a high level of efficiency. With 1 Mbyte of address space, and it is capable of executing instructions at high speed.
In addition, the CPU core boasts a multiplier for high-speed operation processing.
Power consumption is low, and the supported operating modes allow additional power control. These MCUs are
designed to maximize EMI/EMS performance.
Integration of many peripheral functions, including multifunction timer and serial interface, reduces the number of
system components.
The R8C/36A Group have data flash (1 KB 4 blocks) with the background operation (BGO) function.
1.1.1
Applications
Electronic household appliances, office equipment, audio equipment, consumer equipment, etc.
REJ03B0265-0110 Rev.1.10 Sep 28, 2009

Page 1 of 55
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/36A Group
1.1.2
1. Overview
Specifications
Tables 1.1 and 1.2 outline the Specifications for R8C/36A Group.
Table 1.1
Item
CPU
Specifications for R8C/36A Group (1)

Function
Central processing
unit
Memory
ROM, RAM,
Data flash
Power Supply Voltage detection
Voltage
circuit
Detection
I/O Ports
Programmable I/O
ports
Clock
Clock generation
circuits
Interrupts
Watchdog Timer
DTC (Data Transfer Controller)
Timer
Timer RA
Timer RB
Timer RC
Timer RD
Specification
R8C CPU core
Number of fundamental instructions: 89
Minimum instruction execution time:
50 ns (f(XIN) = 20 MHz, VCC = 2.7 to 5.5 V)
200 ns (f(XIN) = 5 MHz, VCC = 1.8 to 5.5 V)
Multiplier: 16 bits 16 bits 32 bits
Multiply-accumulate instruction: 16 bits 16 bits + 32 bits 32 bits
Operation mode: Single-chip mode (address space: 1 Mbyte)
Refer to Table 1.3 Product List for R8C/36A Group
Power-on reset
Voltage detection 3 (detection level of voltage detection 0 and voltage
detection 1 selectable)
Input-only: 1 pin
CMOS I/O ports: 59, selectable pull-up resistor
3 circuits: XIN clock oscillation circuit,
XCIN clock oscillation circuit (32 kHz),
Low-speed on-chip oscillator
Oscillation stop detection: XIN clock oscillation stop detection function
Frequency divider circuit: Dividing selectable 1, 2, 4, 8, and 16
Low power consumption modes:
Standard operating mode (high-speed clock, low-speed clock, low-speed onchip oscillator), wait mode, stop mode
Real-time clock (timer RE)
Interrupt Vectors: 69
External: 9 sources (INT 5, key input 4)
Priority levels: 7 levels
14 bits 1 (with prescaler)
Reset start selectable
Low-speed on-chip oscillator for watchdog timer selectable
1 channel
Activation sources: 39
Transfer modes: 2 (normal mode, repeat mode)
8 bits (with 8-bit prescaler)
Timer mode (period timer), pulse output mode (output level inverted every
period), event counter mode, pulse width measurement mode, pulse period
measurement mode
8 bits 1 (with 8-bit prescaler)
Timer mode (period timer), programmable waveform generation mode (PWM
output), programmable one-shot generation mode, programmable wait oneshot generation mode
16 bits 1 (with 4 capture/compare registers)
Timer mode (input capture function, output compare function), PWM mode
(output 3 pins), PWM2 mode (PWM output pin)
16 bits 2 (with 4 capture/compare registers)
(output 6 pins), reset synchronous PWM mode (output three-phase
waveforms (6 pins), sawtooth wave modulation), complementary PWM mode
(output three-phase waveforms (6 pins), triangular wave modulation), PWM3
mode (PWM output 2 pins with fixed period)
REJ03B0265-0110 Rev.1.10 Sep 28, 2009

Page 2 of 55
Under development
R8C/36A Group
Table 1.2
Item
Timer
1. Overview
Specifications for R8C/36A Group (2)

Function
Timer RE
Timer RF
Timer RG
Serial
Interface
UART0, UART1
UART2
Specification
8 bits 1
Output compare mode
16 bits 1
Input capture mode (input capture circuit), output compare mode (output
compare circuit)
16 bits 1
(output 1 pin), phase counting mode (available automatic measurement for
the counts of 2-phase encoder)
Clock synchronous serial I/O/UART 2 channel
Clock synchronous serial I/O, UART, I2C mode (I2C bus), multiprocessor
communication function
Synchronous Serial
Communication Unit (SSU)
1 (shared with I2C bus)
I2C bus
LIN Module
A/D Converter
1 (shared with SSU)
D/A Converter
Comparator A
Comparator B
Flash Memory
Operating Frequency/Supply
Voltage
Current consumption
Operating Ambient Temperature

Package
Hardware LIN: 1 (timer RA, UART0)

10-bit resolution 12 channels, includes sample and hold function, with sweep
mode
8-bit resolution 2 circuits
2 circuits (shared with voltage monitor 1 and voltage monitor 2)
External reference voltage input available
2 circuits
Programming and erasure voltage: VCC = 2.7 to 5.5 V
Programming and erasure endurance: 10,000 times (data flash)
1,000 times (program ROM)
Program security: ROM code protect, ID code check
Debug functions: On-chip debug, on-board flash rewrite function
Background operation (BGO) function (data flash)
f(XIN) = 20 MHz (VCC = 2.7 to 5.5 V)
f(XIN) = 5 MHz (VCC = 1.8 to 5.5 V)
Typ. 7.0 mA (VCC = 5.0 V, f(XIN) = 20 MHz)
Typ. 3.5 mA (VCC = 3.0 V, f(XIN) = 10 MHz)
Typ. 4.0 A (VCC = 3.0 V, wait mode (f(XCIN) = 32 kHz))
Typ. 2.0 A (VCC = 3.0 V, stop mode)
20 to 85C (N version)
64-pin LQFP
Package code: PLQP0064KB-A (previous code: 64P6Q-A)
Package code: PLQP0064GA-A (previous code: 64P6U-A)
REJ03B0265-0110 Rev.1.10 Sep 28, 2009

Page 3 of 55
Under development
R8C/36A Group
1.2
1. Overview
Product List
Table 1.3 lists Product List for R8C/36A Group. Figure 1.1 shows a Part Number, Memory Size, and Package of
R8C/36A Group.
Table 1.3
Product List for R8C/36A Group
Part No.
R5F21364ANFP (D)
R5F21365ANFP (D)
R5F21366ANFP (D)
R5F21367ANFP (D)
R5F21368ANFP (D)
R5F2136AANFP (D)
R5F2136CANFP (D)
R5F21364ANFA (D)
R5F21365ANFA (D)
R5F21366ANFA (D)
R5F21367ANFA (D)
R5F21368ANFA (D)
R5F2136AANFA (D)
R5F2136CANFA (D)
ROM Capacity
Program ROM
Data flash
16 Kbytes
1 Kbyte 4
24 Kbytes
1 Kbyte 4
32 Kbytes
1 Kbyte 4
48 Kbytes
1 Kbyte 4
64 Kbytes
1 Kbyte 4
96 Kbytes
1 Kbyte 4
128 Kbytes
1 Kbyte 4
16 Kbytes
1 Kbyte 4
24 Kbytes
1 Kbyte 4
32 Kbytes
1 Kbyte 4
48 Kbytes
1 Kbyte 4
64 Kbytes
1 Kbyte 4
96 Kbytes
1 Kbyte 4
128 Kbytes
1 Kbyte 4
Current of Sep. 2009

RAM
Capacity
Package Type
1.5 Kbytes
2 Kbytes
2.5 Kbytes
4 Kbytes
6 Kbytes
8 Kbytes
10 Kbytes
1.5 Kbytes
2 Kbytes
2.5 Kbytes
4 Kbytes
6 Kbytes
8 Kbytes
10 Kbytes
PLQP0064KB-A
PLQP0064KB-A
PLQP0064KB-A
PLQP0064KB-A
PLQP0064KB-A
PLQP0064KB-A
PLQP0064KB-A
PLQP0064GA-A
PLQP0064GA-A
PLQP0064GA-A
PLQP0064GA-A
PLQP0064GA-A
PLQP0064GA-A
PLQP0064GA-A
Remarks
N version
(D): Under development
Part No. R 5 F 21 36 6 A N FP
Package type:
FP: PLQP0064KB-A
FA: PLQP0064GA-A
Classification
N: Operating ambient temperature 20C to 85C
ROM capacity
4: 16 KB
5: 24 KB
6: 32 KB
7: 48 KB
8: 64 KB
A: 96 KB
C: 128 KB
R8C/36A Group
R8C/3x Series
Memory type
F: Flash memory
Renesas MCU
Renesas semiconductor
Figure 1.1
Part Number, Memory Size, and Package of R8C/36A Group
REJ03B0265-0110 Rev.1.10 Sep 28, 2009

Page 4 of 55
Under development
R8C/36A Group
1.3
1. Overview
Block Diagram
Figure 1.2 shows a Block Diagram.
I/O ports
Port P0
Port P1
Port P2
Port P3
Port P5
Port P4
Peripheral functions
Timers
Timer RA (8 bits 1)
Timer RB (8 bits 1)
Timer RC (16 bits 1)
Timer RD (16 bits 2)
Timer RE (8 bits 1)
Timer RF (16 bits 1)
Timer RG (16 bits 1)
UART or
clock synchronous serial I/O
(8 bits 3)
System clock generation

circuit
I2C bus or SSU

(8 bits 1)
XIN-XOUT
XCIN-XCOUT
Watchdog timer
(14 bits)
LIN module

for watchdog timer
Comparator B
Voltage detection circuit
A/D converter
(10 bits 12 channels)
Comparator A
D/A converter
(8 bits 2)
DTC
Memory
R8C CPU core

R0H
R1H
R0L
R1L
R2
R3
SB
USP
ISP
INTB
A0
A1
FB
ROM (1)
RAM (2)
PC
FLG
Multiplier
Figure 1.2
Port P6
Port P8
Block Diagram
REJ03B0265-0110 Rev.1.10 Sep 28, 2009

Page 5 of 55
Notes:
1. ROM size varies with MCU type.
2. RAM size varies with MCU type.
Under development
R8C/36A Group
1.4
1. Overview
Pin Assignment
P1_0/AN8/LVCMP1/KI0(/TRCIOD)
P1_1/AN9/LVCMP2/KI1(/TRCIOA/TRCTRG)
P1_2/AN10/LVREF/KI2(/TRCIOB)
P1_3/AN11/LVCOUT1/KI3/TRBO(/TRCIOC)
P1_4(/TXD0/TRCCLK)
P1_5(/INT1/RXD0/TRAIO)
P1_6/LVCOUT2/IVREF1(/CLK0)
P1_7/IVCMP1/INT1(/TRAIO)
P4_5/ADTRG/INT0(/RXD2/SCL2)
P6_5/INT4(/CLK1/CLK2/TRCIOB)
P6_6/INT2(/TXD2/SDA2/TRCIOC)
P6_7(/INT3/TRCIOD)
P8_0(/TRFO00)
P8_1(/TRFO01)
P8_2(/TRFO02)
P8_3(/TRFI/TRFO10)
Figure 1.3 shows Pin Assignment (Top View). Tables 1.4 and 1.5 outline the Pin Name Information by Pin
Number.
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P0_7/AN0/DA1(/TRCIOC)
49
32
P8_4(/TRFO11)
P0_6/AN1/DA0(/TRCIOD)
50
31
P8_5(/TRFO12)
P0_5/AN2(/TRCIOB)
51
30
P8_6
P0_4/AN3/TREO(/TRCIOB)
P0_3/AN4(/CLK1/TRCIOB)
52
29
53
28
P3_1(/TRBO)
P3_6(/INT1)
P0_2/AN5(/RXD1/TRCIOA/TRCTRG)
54
27
P2_0(/INT1/TRCIOB/TRDIOA0/TRDCLK)
P0_1/AN6(/TXD1/TRCIOA/TRCTRG)
P0_0/AN7(/TRCIOA/TRCTRG)
55
26
25
P2_1(/TRCIOC/TRDIOC0)
P2_2(/TRCIOD/TRDIOB0)
P6_4(/RXD1)
57
24
P2_3(/TRDIOD0)
P6_3(/TXD1)
58
23
P2_4(/TRDIOA1)
P6_2(/CLK1)
59
22
P2_5(/TRDIOB1)
P6_1
60
21
P2_6(/TRDIOC1)
P6_0(/TREO)
61
20
P2_7(/TRDIOD1)
P5_7(/TRGIOB)
62
19
P3_3/IVCMP3/INT3/SCS(/CTS2/RTS2/TRCCLK)
P5_6(/TRAO/TRGIOA)
P3_2(/INT1/INT2/TRAIO/TRGCLKB)
63
18
64
17
P3_4/IVREF3/SSI(/RXD2/SCL2/TXD2/SDA2/TRCIOC)
P3_5/SCL/SSCK(/CLK2/TRCIOD)
R8C/36A Group
56
10 11 12 13 14 15 16
P4_2/VREF
MODE
P4_3(/XCIN)
P4_4(/XCOUT)
RESET
P4_7/XOUT
VSS/AVSS
P4_6/XIN
VCC/AVCC
P3_7/SDA/SSO/TRAO(/RXD2/SCL2/TXD2/SDA2)
P5_0(/TRCCLK)
P5_1(/TRCIOA/TRCTRG)
P5_2(/TRCIOB)
P5_3(/TRCIOC)
P5_4(/TRCIOD)
P3_0(/TRAO/TRGCLKA)
PLQP0064KB-A (64P6Q-A)
PLQP0064GA-A (64P6U-A)
(Top view)
Notes:
1. Can be assigned to the pin in parentheses by a program.
2. P4_2 is an input-only pin.
3. Confirm the pin 1 position on the package by referring to the package dimensions.
Figure 1.3
Pin Assignment (Top View)
REJ03B0265-0110 Rev.1.10 Sep 28, 2009

Page 6 of 55
Under development
R8C/36A Group
Table 1.4
1. Overview
Pin Name Information by Pin Number (1)

I/O Pin Functions for Peripheral Modules
Pin
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Control Pin
Port
Interrupt
P3_0
P4_2
MODE
(XCIN)
(XCOUT)
RESET
XOUT
VSS/AVSS
XIN
VCC/AVCC
Timer
Serial
Interface
SSU
A/D Converter,
D/A Converter,
I2C Comparator A,
bus Comparator B,
Voltage
Detection Circuit
(TRAO/TRGCLKA)
VREF
P4_3
P4_4
P4_7
P4_6
P5_4
P5_3
P5_2
P5_1
P5_0
(TRCIOD)
(TRCIOC)
(TRCIOB)
(TRCIOA/TRCTRG)
(TRCCLK)
16
P3_7
TRAO
17
P3_5
(TRCIOD)
18
P3_4
(TRCIOC)
(TXD2/SDA2/
SSO SDA
RXD2/SCL2)
(CLK2)
SSCK SCL
(TXD2/SDA2/
SSI
RXD2/SCL2)
INT3
(TRCCLK)
P2_0
(INT1)
(TRDIOD1)
(TRDIOC1)
(TRDIOB1)
(TRDIOA1)
(TRDIOD0)
(TRCIOD/TRDIOB0)
(TRCIOC/TRDIOC0)
(TRCIOB/TRDIOA0/
TRDCLK)
28
P3_6
(INT1)
29
30
31
32
33
34
35
36
P3_1
P8_6
P8_5
P8_4
P8_3
P8_2
P8_1
P8_0
37
P6_7
(INT3)
(TRCIOD)
38
P6_6
INT2
(TRCIOC)
(TXD2/SDA2)
39
P6_5
INT4
(TRCIOB)
(CLK2/CLK1)
19
P3_3
20
21
22
23
24
25
26
P2_7
P2_6
P2_5
P2_4
P2_3
P2_2
P2_1
27
(CTS2/RTS2)
(TRBO)
(TRFO12)
(TRFO11)
(TRFI/TRFO10)
(TRFO02)
(TRFO01)
(TRFO00)
Note:
REJ03B0265-0110 Rev.1.10 Sep 28, 2009

Page 7 of 55
SCS
IVREF3
IVCMP3
Under development
R8C/36A Group
Table 1.5
1. Overview
Pin Name Information by Pin Number (2)

I/O Pin Functions for Peripheral Modules
Pin
Number
Control Pin
Port
Interrupt
Timer
Serial
Interface
(RXD2/SCL2)
SSU
A/D Converter,
D/A Converter,
I2C Comparator A,
bus Comparator B,
Voltage
Detection Circuit
40
P4_5
INT0
41
P1_7
INT1
42
P1_6
43
P1_5
44
P1_4
45
P1_3
KI3
46
P1_2
KI2
(TRCIOB)
47
P1_1
KI1
(TRCIOA/TRCTRG)
AN9/LVCMP2
48
P1_0
KI0
(TRCIOD)
AN8/LVCMP1
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
P0_7
P0_6
P0_5
P0_4
P0_3
P0_2
P0_1
P0_0
P6_4
P6_3
P6_2
P6_1
P6_0
P5_7
P5_6
(TRCIOC)
(TRCIOD)
(TRCIOB)
TREO(/TRCIOB)
(TRCIOB)
(TRCIOA/TRCTRG)
(TRCIOA/TRCTRG)
(TRCIOA/TRCTRG)
AN0/DA1
AN1/DA0
AN2
AN3
AN4
AN5
AN6
AN7
64
P3_2
(TRAIO)
(CLK0)
(INT1)
(TRAIO)
(RXD0)
(TRCCLK)
TRBO
(/TRCIOC)
(TXD0)
(INT1/
INT2)
(TRAIO/TRGCLKB)
Note:
REJ03B0265-0110 Rev.1.10 Sep 28, 2009

Page 8 of 55
LVCOUT2/
IVREF1
AN11/
LVCOUT1
AN10/LVREF
(CLK1)
(RXD1)
(TXD1)
(RXD1)
(TXD1)
(CLK1)
(TREO)
(TRGIOB)
(TRAO/TRGIOA)
ADTRG
IVCMP1
Under development
R8C/36A Group
1.5
1. Overview
Pin Functions
Tables 1.6 and 1.7 list Pin Functions.

Table 1.6
Pin Functions (1)
Item
Pin Name
Power supply input VCC, VSS
Analog power
supply input
Reset input
AVCC, AVSS
I/O Type
Description
I
Apply 1.8 to 5.5 V to the VCC pin.
Apply 0 V to the VSS pin.
I
Power supply for the A/D converter.
Connect a capacitor between AVCC and AVSS.
I
Input L on this pin resets the MCU.
MODE
XIN clock input
XIN clock output
RESET
MODE
XIN
XOUT
XCIN clock input

XCIN clock output
XCIN
XCOUT
I
O
INT interrupt input

Key input interrupt
INT0 to INT4
KI0 to KI3
TRAIO
TRAO
TRBO
TRCCLK
TRCTRG
TRCIOA, TRCIOB,
TRCIOC, TRCIOD
TRDIOA0, TRDIOA1,
TRDIOB0, TRDIOB1,
TRDIOC0, TRDIOC1,
TRDIOD0, TRDIOD1
TRDCLK
TREO
TRFO00, TRFO10,
TRFO01,TRFO11,
TRFO02,TRFO12
TRFI
TRGIOA, TRGIOB
TRGCLKA, TRGCLKB
CLK0, CLK1, CLK2
RXD0, RXD1, RXD2
TXD0, TXD1, TXD2
Timer RA
Timer RB
Timer RC
Timer RD
Timer RE
Timer RF
Timer RG
Serial interface
CTS2
I
I
I/O
Connect this pin to VCC via a resistor.

These pins are provided for XIN clock generation circuit I/O.
Connect a ceramic resonator or a crystal oscillator between
the XIN and XOUT pins. (1)
To use an external clock, input it to the XOUT pin and leave
the XIN pin open.
These pins are provided for XCIN clock generation circuit I/O.
Connect a crystal oscillator between the XCIN and XCOUT
pins. (1)
To use an external clock, input it to the XCIN pin and leave
the XCOUT pin open.
INT interrupt input pins.
Key input interrupt input pins.
I/O
O
O
I
I
I/O
Timer RA I/O pin.

Timer RA output pin.
Timer RB output pin.
External clock input pin.
External trigger input pin.
Timer RC I/O pins.
I/O
Timer RD I/O pins.
I
O
O
External clock input pin.

Divided clock output pin.
Timer RF output pins.
I
I/O
I
I/O
I
O
I
Timer RF input pin.

Timer RG I/O ports.
External clock input pints.
Transfer clock I/O pins.
Serial data input pins.
Serial data output pins.
Transmission control input pin.
RTS2
SCL2
Reception control output pin.
I/O
I2C mode clock I/O pin.
SDA2
I/O
I2C mode data I/O pin.
I: Input
O: Output
I/O: Input and output
Note:
1. Refer to the oscillator manufacturer for oscillation characteristics.
REJ03B0265-0110 Rev.1.10 Sep 28, 2009

Page 9 of 55
Under development
R8C/36A Group
1. Overview
Table 1.7
Pin Functions (2)
Item
Pin Name
SSU
SSI
I2C bus
Reference voltage
input
A/D converter
D/A converter
Comparator A
Comparator B
Voltage detection
circuit
I/O port
Input port
I: Input
SCS
SSCK
SSO
SCL
SDA
VREF
I/O
I/O
I/O
I/O
I
AN0 to AN11
ADTRG
DA0, DA1
LVCMP1, LVCMP2
LVREF
LVCOUT1,
LVCOUT2
IVCMP1, IVCMP3
IVREF1, IVREF3
LVCMP2
P0_0 to P0_7,
P1_0 to P1_7,
P2_0 to P2_7,
P3_0 to P3_7,
P4_3 to P4_7,
P5_0 to P5_4,
P5_6, P5_7,
P6_0 to P6_7,
P8_0 to P8_6
P4_2
O: Output
I/O Type
Description
I/O
Data I/O pin.
I/O
Chip-select signal I/O pin.
I
I
Analog input pins to A/D converter.

AD external trigger input pin.
O
I
I
O
D/A converter output pins.

Comparator A analog voltage input pins.
Comparator A reference voltage input pin.
Comparator A output pins.
I
I
I
Comparator B analog voltage input pins.

Comparator B reference voltage input pins.
Detection voltage input pin for voltage detection 2.
I/O
I/O: Input and output
REJ03B0265-0110 Rev.1.10 Sep 28, 2009

Page 10 of 55
Clock I/O pin.

Data I/O pin.
Clock I/O pin
Data I/O pin
Reference voltage input pin to A/D converter.
CMOS I/O ports. Each port has an I/O select direction

register, allowing each pin in the port to be directed for input
or output individually.
Any port set to input can be set to use a pull-up resistor or not
by a program.
Input-only ports.
Under development
R8C/36A Group
2.
2. Central Processing Unit (CPU)
Central Processing Unit (CPU)
Figure 2.1 shows the CPU Registers. The CPU contains 13 registers. R0, R1, R2, R3, A0, A1, and FB configure a
register bank. There are two sets of register bank.
b31
b15
R2
R3
b8b7
b0
R0H (high-order of R0) R0L (low-order of R0)

R1H (high-order of R1) R1L (low-order of R1)
Data registers (1)
R2
R3
A0
A1
FB
b19
b15
Address registers (1)

Frame base register (1)
b0
Interrupt table register
INTBL
INTBH
The 4 high order bits of INTB are INTBH and

the 16 low order bits of INTB are INTBL.
b19
b0
Program counter
PC
b15
b0
USP
User stack pointer
ISP
Interrupt stack pointer
SB
Static base register
b15
b0
FLG
b15
b8
IPL
b7
Flag register
b0
U I O B S Z D C
Carry flag
Debug flag
Zero flag
Sign flag
Register bank select flag
Overflow flag
Interrupt enable flag
Stack pointer select flag
Reserved bit
Processor interrupt priority level
Reserved bit
Note:
1. These registers comprise a register bank. There are two register banks.
Figure 2.1
CPU Registers
REJ03B0265-0110 Rev.1.10 Sep 28, 2009

Page 11 of 55
Under development
R8C/36A Group
2.1
Data Registers (R0, R1, R2, and R3)
R0 is a 16-bit register for transfer, arithmetic, and logic operations. The same applies to R1 to R3. R0 can be split
into high-order bits (R0H) and low-order bits (R0L) to be used separately as 8-bit data registers. R1H and R1L are
analogous to R0H and R0L. R2 can be combined with R0 and used as a 32-bit data register (R2R0). R3R1 is
analogous to R2R0.
2.2
Address Registers (A0 and A1)
A0 is a 16-bit register for address register indirect addressing and address register relative addressing. It is also
used for transfer, arithmetic, and logic operations. A1 is analogous to A0. A1 can be combined with A0 and as a 32bit address register (A1A0).
2.3
Frame Base Register (FB)
FB is a 16-bit register for FB relative addressing.
2.4
Interrupt Table Register (INTB)
INTB is a 20-bit register that indicates the starting address of an interrupt vector table.
2.5
Program Counter (PC)
PC is 20 bits wide and indicates the address of the next instruction to be executed.
2.6
User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
The stack pointers (SP), USP and ISP, are each 16 bits wide. The U flag of FLG is used to switch between
USP and ISP.
2.7
Static Base Register (SB)
SB is a 16-bit register for SB relative addressing.
2.8
Flag Register (FLG)
FLG is an 11-bit register indicating the CPU state.
2.8.1
Carry Flag (C)
The C flag retains carry, borrow, or shift-out bits that have been generated by the arithmetic and logic unit.
2.8.2
Debug Flag (D)
The D flag is for debugging only. Set it to 0.
2.8.3
Zero Flag (Z)
The Z flag is set to 1 when an arithmetic operation results in 0; otherwise to 0.
2.8.4
Sign Flag (S)
The S flag is set to 1 when an arithmetic operation results in a negative value; otherwise to 0.
2.8.5
Register Bank Select Flag (B)
Register bank 0 is selected when the B flag is 0. Register bank 1 is selected when this flag is set to 1.
2.8.6
Overflow Flag (O)
The O flag is set to 1 when an operation results in an overflow; otherwise to 0.
REJ03B0265-0110 Rev.1.10 Sep 28, 2009

Page 12 of 55
Under development
R8C/36A Group
2.8.7
Interrupt Enable Flag (I)
The I flag enables maskable interrupts.

Interrupts are disabled when the I flag is set to 0, and are enabled when the I flag is set to 1. The I flag is set to 0
when an interrupt request is acknowledged.
2.8.8
Stack Pointer Select Flag (U)
ISP is selected when the U flag is set to 0; USP is selected when the U flag is set to 1.
The U flag is set to 0 when a hardware interrupt request is acknowledged or the INT instruction of software
interrupt numbers 0 to 31 is executed.
2.8.9
Processor Interrupt Priority Level (IPL)
IPL is 3 bits wide and assigns processor interrupt priority levels from level 0 to level 7.
If a requested interrupt has higher priority than IPL, the interrupt is enabled.
2.8.10
Reserved Bit
If necessary, set to 0. When read, the content is undefined.
REJ03B0265-0110 Rev.1.10 Sep 28, 2009

Page 13 of 55
Under development
R8C/36A Group
3.
3. Memory
Memory
3.1
R8C/36A Group
Figure 3.1 is a Memory Map of R8C/36A Group. The R8C/36A Group has a 1-Mbyte address space from addresses
00000h to FFFFFh. The internal ROM (program ROM) is allocated lower addresses, beginning with address
0FFFFh. For example, a 64-Kbyte internal ROM area is allocated addresses 04000h to 13FFFh.
The fixed interrupt vector table is allocated addresses 0FFDCh to 0FFFFh. The starting address of each interrupt
routine is stored here.
The internal ROM (data flash) is allocated addresses 03000h to 03FFFh.
The internal RAM is allocated higher addresses, beginning with address 00400h. For example, a 6-Kbyte internal
RAM area is allocated addresses 00400h to 01BFFh. The internal RAM is used not only for data storage but also as
a stack area when a subroutine is called or when an interrupt request is acknowledged.
Special function registers (SFRs) are allocated addresses 00000h to 002FFh and 02C00h to 02FFFh (the SFR areas
for the DTC and other modules). Peripheral function control registers are allocated here. All unallocated spaces
within the SFRs are reserved and cannot be accessed by users.
00000h
SFR
(Refer to 4. Special Function
Registers (SFRs))
002FFh
00400h
Internal RAM
0XXXXh
02C00h
02FFFh
03000h
SFR (2)
(Refer to 4. Special Function
Registers (SFRs))
0FFDCh
Internal ROM
(data flash) (1)
03FFFh
0YYYYh
Internal ROM
(program ROM)
0FFFFh
0FFFFh
Undefined instruction
Overflow
BRK instruction
Address match
Single step
Watchdog timer, oscillation stop detection, voltage monitor
Address break
(Reserved)
Reset
Internal ROM
(program ROM)
ZZZZZh
FFFFFh
Notes:
1. The data flash indicates block A (1 Kbyte), block B (1 Kbyte), block C (1 Kbyte), and block D (1 Kbyte).
2. The SFR areas for the DTC and other modules are allocated to addresses 02C00h to 02FFFh.
3. The blank areas are reserved and cannot be accessed by users.
Part Number
Internal ROM
Internal RAM
Size
Address 0YYYYh
Address ZZZZZh
Size
R5F21364ANFP
16 Kbytes
0C000h
1.5 Kbytes
009FFh
R5F21365ANFP
24 Kbytes
0A000h
2 Kbytes
00BFFh
R5F21366ANFP
32 Kbytes
08000h
2.5 Kbytes
00DFFh
R5F21367ANFP
48 Kbytes
04000h
4 Kbytes
013FFh
R5F21368ANFP
64 Kbytes
04000h
13FFFh
6 Kbytes
01BFFh
R5F2136AANFP
96 Kbytes
04000h
1BFFFh
8 Kbytes
023FFh
R5F2136CANFP
128 Kbytes
04000h
23FFFh
10 Kbytes
02BFFh
Figure 3.1
Memory Map of R8C/36A Group
REJ03B0265-0110 Rev.1.10 Sep 28, 2009

Page 14 of 55
Address 0XXXXh
Under development
R8C/36A Group
4.
4. Special Function Registers (SFRs)
Special Function Registers (SFRs)
An SFR (special function register) is a control register for a peripheral function. Tables 4.1 to 4.12 list the special
function registers. Table 4.13 list the ID Code Areas and Option Function Select Area.
Table 4.1
Address
0000h
0001h
0002h
0003h
0004h
0005h
0006h
0007h
0008h
0009h
000Ah
000Bh
000Ch
000Dh
000Eh
000Fh
0010h
0011h
0012h
0013h
0014h
0015h
0016h
0017h
0018h
0019h
001Ah
001Bh
001Ch
001Dh
001Eh
001Fh
0020h
0021h
0022h
0023h
0024h
0025h
0026h
0027h
0028h
0029h
002Ah
002Bh
002Ch
002Dh
002Eh
002Fh
0030h
0031h
0032h
0033h
0034h
0035h
0036h
0037h
0038h
0039h
SFR Information (1) (1)

Register
Symbol
After Reset
Processor Mode Register 0

Processor Mode Register 1
System Clock Control Register 0
Module Standby Control Register
Protect Register
Reset Source Determination Register
Oscillation Stop Detection Register
Watchdog Timer Reset Register
Watchdog Timer Start Register
Watchdog Timer Control Register
PM0
PM1
CM0
CM1
MSTCR
CM3
PRCR
RSTFR
OCD
WDTR
WDTS
WDTC
00h
00h
00101000b
00100000b
00h
00h
00h
0XXXXXXXb (2)
00000100b
XXh
XXh
00111111b
Count Source Protection Mode Register
CSPR
00h
10000000b (3)
On-Chip Reference Voltage Control Register
OCVREFCR
00h
Clock Prescaler Reset Flag
CPSRF
00h
Voltage Monitor Circuit/Comparator A Control Register

Voltage Monitor Circuit Edge Select Register
CMPA
VCAC
00h
00h
Voltage Detect Register 1

Voltage Detect Register 2
VCA1
VCA2
00001000b
00h (4)
00100000b (5)
Voltage Detection 1 Level Select Register
VD1LS
00000111b
Voltage Monitor 0 Circuit Control Register
VW0C
VW1C
1100X010b (4)
1100X011b (5)
10001010b
X: Undefined
Notes:
2. The CWR bit in the RSTFR register is set to 0 after power-on and voltage monitor 0 reset. Hardware reset, software reset, or watchdog timer
reset does not affect this bit.
3. The CSPROINI bit in the OFS register is set to 0.
4. The LVDAS bit in the OFS register is set to 1.
5. The LVDAS bit in the OFS register is set to 0.
REJ03B0265-0110 Rev.1.10 Sep 28, 2009

Page 15 of 55
Under development
R8C/36A Group
Table 4.2
Address
003Ah
003Bh
003Ch
003Dh
003Eh
003Fh
0040h
0041h
0042h
0043h
0044h
0045h
0046h
0047h
0048h
0049h
004Ah
004Bh
004Ch
004Dh
004Eh
004Fh
0050h
0051h
0052h
0053h
0054h
0055h
0056h
0057h
0058h
0059h
005Ah
005Bh
005Ch
005Dh
005Eh
005Fh
0060h
0061h
0062h
0063h
0064h
0065h
0066h
0067h
0068h
0069h
006Ah
006Bh
006Ch
006Dh
006Eh
006Fh
0070h
0071h
0072h
0073h
0074h
0075h
0076h
0077h
0078h
0079h
007Ah
007Bh
007Ch
007Dh
007Eh
007Fh

Register
VW2C
After Reset
10000010b
Flash Memory Ready Interrupt Control Register
FMRDYIC
XXXXX000b
INT4 Interrupt Control Register

Timer RC Interrupt Control Register
Timer RD0 Interrupt Control Register
Timer RD1 Interrupt Control Register
Timer RE Interrupt Control Register
UART2 Transmit Interrupt Control Register
UART2 Receive Interrupt Control Register
Key Input Interrupt Control Register
A/D Conversion Interrupt Control Register
SSU Interrupt Control Register/IIC bus Interrupt Control Register (2)
Timer RF Compare 1 Interrupt Control Register
Timer RA Interrupt Control Register
INT4IC
TRCIC
TRD0IC
TRD1IC
TREIC
S2TIC
S2RIC
KUPIC
ADIC
SSUIC/IICIC
CMP1IC
S0TIC
S0RIC
S1TIC
S1RIC
INT2IC
TRAIC
XX00X000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XX00X000b
XXXXX000b
Timer RB Interrupt Control Register

Timer RF Interrupt Control Register
Timer RF Compare 0 Interrupt Control Register
UART2 Bus Collision Detection Interrupt Control Register
Timer RF Capture Interrupt Control Register
TRBIC
INT1IC
INT3IC
TRFIC
CMP0IC
INT0IC
U2BCNIC
CAPIC
XXXXX000b
XX00X000b
XX00X000b
XXXXX000b
XXXXX000b
XX00X000b
XXXXX000b
XXXXX000b
Timer RG Interrupt Control Register
TRGIC
XXXXX000b
Voltage Monitor 1/Compare A1 Interrupt Control Register

Voltage Monitor 2/Compare A2 Interrupt Control Register
VCMP1IC
VCMP2IC
XXXXX000b
XXXXX000b
X: Undefined
Notes:
2. Selectable by the IICSEL bit in the SSUIICSR register.
REJ03B0265-0110 Rev.1.10 Sep 28, 2009

Page 16 of 55
Symbol
Under development
R8C/36A Group
Table 4.3
Address
0080h
0081h
0082h
0083h
0084h
0085h
0086h
0087h
0088h
0089h
008Ah
008Bh
008Ch
008Dh
008Eh
008Fh
0090h
0091h
0092h
0093h
0094h
0095h
0096h
0097h
0098h
0099h
009Ah
009Bh
009Ch
009Dh
009Eh
009Fh
00A0h
00A1h
00A2h
00A3h
00A4h
00A5h
00A6h
00A7h
00A8h
00A9h
00AAh
00ABh
00ACh
00ADh
00AEh
00AFh
00B0h
00B1h
00B2h
00B3h
00B4h
00B5h
00B6h
00B7h
00B8h
00B9h
00BAh
00BBh
00BCh
00BDh
00BEh
00BFh

DTC Activation Control Register
Register
Symbol
DTCTL
00h
DTC Activation Enable Register 0

DTCEN0
DTCEN1
DTCEN2
DTCEN3
DTCEN4
DTCEN5
DTCEN6
00h
00h
00h
00h
00h
00h
00h
Timer RF Register
TRF
00h
00h
Timer RF Control Register 0

Timer RF Control Register 1
Capture and Compare 0 Register
TRFCR0
TRFCR1
TRFM0
Compare 1 Register
TRFM1
UART0 Transmit/Receive Mode Register

UART0 Bit Rate Register
UART0 Transmit Buffer Register
U0MR
U0BRG
U0TB
UART0 Transmit/Receive Control Register 0

UART0 Receive Buffer Register
U0C0
U0C1
U0RB

U2MR
U2BRG
U2TB

U2C0
U2C1
U2RB
UART2 Digital Filter Function Select Register
URXDF
00h
00h
00h
00h
FFh
FFh
00h
XXh
XXh
XXh
00001000b
00000010b
XXh
XXh
00h
XXh
XXh
XXh
00001000b
00000010b
XXh
XXh
00h
UART2 Special Mode Register 5

UART2 Special Mode Register
U2SMR5
U2SMR4
U2SMR3
U2SMR2
U2SMR
00h
00h
000X0X0Xb
X0000000b
X0000000b
X: Undefined
Note:
REJ03B0265-0110 Rev.1.10 Sep 28, 2009

Page 17 of 55
After Reset
Under development
R8C/36A Group
Table 4.4
Address
00C0h
00C1h
00C2h
00C3h
00C4h
00C5h
00C6h
00C7h
00C8h
00C9h
00CAh
00CBh
00CCh
00CDh
00CEh
00CFh
00D0h
00D1h
00D2h
00D3h
00D4h
00D5h
00D6h
00D7h
00D8h
00D9h
00DAh
00DBh
00DCh
00DDh
00DEh
00DFh
00E0h
00E1h
00E2h
00E3h
00E4h
00E5h
00E6h
00E7h
00E8h
00E9h
00EAh
00EBh
00ECh
00EDh
00EEh
00EFh
00F0h
00F1h
00F2h
00F3h
00F4h
00F5h
00F6h
00F7h
00F8h
00F9h
00FAh
00FBh
00FCh
00FDh
00FEh
00FFh

Register
Symbol
After Reset
XXh
000000XXb
XXh
000000XXb
XXh
000000XXb
XXh
000000XXb
XXh
000000XXb
XXh
000000XXb
XXh
000000XXb
XXh
000000XXb
A/D Register 0
AD0
A/D Register 1
AD1
A/D Register 2
AD2
A/D Register 3
AD3
A/D Register 4
AD4
A/D Register 5
AD5
A/D Register 6
AD6
A/D Register 7
AD7
A/D Mode Register

A/D Input Select Register
A/D Control Register 0
A/D Control Register 1
D/A0 Register
D/A1 Register
ADMOD
ADINSEL
ADCON0
ADCON1
DA0
DA1
00h
11000000b
00h
00h
00h
00h
D/A Control Register
DACON
00h
Port P0 Register
Port P1 Register
Port P0 Direction Register
Port P2 Register
Port P3 Register
Port P4 Register
Port P5 Register
Port P6 Register
P0
P1
PD0
PD1
P2
P3
PD2
PD3
P4
P5
PD4
PD5
P6
XXh
XXh
00h
00h
XXh
XXh
00h
00h
XXh
XXh
00h
00h
XXh
PD6
00h
Port P8 Register
P8
XXh
PD8
00h
X: Undefined
Note:
REJ03B0265-0110 Rev.1.10 Sep 28, 2009

Page 18 of 55
Under development
R8C/36A Group
Table 4.5
Address
0100h
0101h
0102h
0103h
0104h
0105h
0106h
0107h
0108h
0109h
010Ah
010Bh
010Ch
010Dh
010Eh
010Fh
0110h
0111h
0112h
0113h
0114h
0115h
0116h
0117h
0118h
0119h
011Ah
011Bh
011Ch
011Dh
011Eh
011Fh
0120h
0121h
0122h
0123h
0124h
0125h
0126h
0127h
0128h
0129h
012Ah
012Bh
012Ch
012Dh
012Eh
012Fh
0130h
0131h
0132h
0133h
0134h
0135h
0136h
0137h
0138h
0139h
013Ah
013Bh
013Ch
013Dh
013Eh
013Fh

Timer RA Control Register
Timer RA I/O Control Register
Timer RA Mode Register
Timer RA Prescaler Register
Timer RA Register
LIN Control Register 2
LIN Control Register
LIN Status Register
Timer RB Control Register
Timer RB One-Shot Control Register
Timer RB I/O Control Register
Timer RB Mode Register
Timer RB Prescaler Register
Timer RB Secondary Register
Timer RB Primary Register
Register
Symbol
TRACR
TRAIOC
TRAMR
TRAPRE
TRA
LINCR2
LINCR
LINST
TRBCR
TRBOCR
TRBIOC
TRBMR
TRBPRE
TRBSC
TRBPR
00h
00h
00h
FFh
FFh
00h
00h
00h
00h
00h
00h
00h
FFh
FFh
FFh
Timer RE Second Data Register / Counter Data Register

Timer RE Minute Data Register / Compare Data Register
Timer RE Hour Data Register
Timer RE Day of Week Data Register
Timer RE Control Register 1
Timer RE Control Register 2
Timer RE Count Source Select Register
TRESEC
TREMIN
TREHR
TREWK
TRECR1
TRECR2
TRECSR
00h
00h
00h
00h
00h
00h
00001000b
Timer RC Mode Register

Timer RC Control Register 1
Timer RC Interrupt Enable Register
Timer RC Status Register
Timer RC I/O Control Register 0
Timer RC I/O Control Register 1
Timer RC Counter
TRCMR
TRCCR1
TRCIER
TRCSR
TRCIOR0
TRCIOR1
TRC
Timer RC General Register A
TRCGRA
Timer RC General Register B
TRCGRB
Timer RC General Register C
TRCGRC
Timer RC General Register D
TRCGRD
Timer RC Control Register 2

Timer RC Digital Filter Function Select Register
Timer RC Output Master Enable Register
Timer RC Trigger Control Register
TRCCR2
TRCDF
TRCOER
TRCADCR
01001000b
00h
01110000b
01110000b
10001000b
10001000b
00h
00h
FFh
FFh
FFh
FFh
FFh
FFh
FFh
FFh
00011000b
00h
01111111b
00h
Timer RD Control Expansion Register

Timer RD Trigger Control Register
Timer RD Start Register
Timer RD Mode Register
Timer RD PWM Mode Register
Timer RD Function Control Register
Timer RD Output Master Enable Register 1
Timer RD Output Master Enable Register 2
Timer RD Output Control Register
Timer RD Digital Filter Function Select Register 0
Timer RD Digital Filter Function Select Register 1
TRDECR
TRDADCR
TRDSTR
TRDMR
TRDPMR
TRDFCR
TRDOER1
TRDOER2
TRDOCR
TRDDF0
TRDDF1
00h
00h
11111100b
00001110b
10001000b
10000000b
FFh
01111111b
00h
00h
00h
Note:
REJ03B0265-0110 Rev.1.10 Sep 28, 2009

Page 19 of 55
After Reset
Under development
R8C/36A Group
Table 4.6
Address
0140h
0141h
0142h
0143h
0144h
0145h
0146h
0147h
0148h
0149h
014Ah
014Bh
014Ch
014Dh
014Eh
014Fh
0150h
0151h
0152h
0153h
0154h
0155h
0156h
0157h
0158h
0159h
015Ah
015Bh
015Ch
015Dh
015Eh
015Fh
0160h
0161h
0162h
0163h
0164h
0165h
0166h
0167h
0168h
0169h
016Ah
016Bh
016Ch
016Dh
016Eh
016Fh
0170h
0171h
0172h
0173h
0174h
0175h
0176h
0177h
0178h
0179h
017Ah
017Bh
017Ch
017Dh
017Eh
017Fh

Register
Timer RD Control Register 0
Timer RD I/O Control Register A0
Timer RD I/O Control Register C0
Timer RD Status Register 0
Timer RD Interrupt Enable Register 0
Timer RD PWM Mode Output Level Control Register 0
Timer RD Counter 0
Symbol
TRDCR0
TRDIORA0
TRDIORC0
TRDSR0
TRDIER0
TRDPOCR0
TRD0
Timer RD General Register A0
TRDGRA0
Timer RD General Register B0
TRDGRB0
Timer RD General Register C0
TRDGRC0
Timer RD General Register D0
TRDGRD0
Timer RD Control Register 1

Timer RD I/O Control Register A1
Timer RD I/O Control Register C1
Timer RD Status Register 1
Timer RD Interrupt Enable Register 1
Timer RD PWM Mode Output Level Control Register 1
Timer RD Counter 1
TRDCR1
TRDIORA1
TRDIORC1
TRDSR1
TRDIER1
TRDPOCR1
TRD1
Timer RD General Register A1
TRDGRA1
Timer RD General Register B1
TRDGRB1
Timer RD General Register C1
TRDGRC1
Timer RD General Register D1
TRDGRD1

U1MR
U1BRG
U1TB

U1C0
U1C1
U1RB
Timer RG Mode Register

Timer RG Count Control Register
Timer RG Control Register
Timer RG Interrupt Enable Register
Timer RG Status Register
Timer RG I/O Control Register
Timer RG Counter
TRGMR
TRGCNTC
TRGCR
TRGIER
TRGSR
TRGIOR
TRG
Timer RG General Register A
TRGGRA
Timer RG General Register B
TRGGRB
Timer RG General Register C
TRGGRC
Timer RG General Register D
TRGGRD
X: Undefined
Note:
REJ03B0265-0110 Rev.1.10 Sep 28, 2009

Page 20 of 55
After Reset
00h
10001000b
10001000b
11100000b
11100000b
11111000b
00h
00h
FFh
FFh
FFh
FFh
FFh
FFh
FFh
FFh
00h
10001000b
10001000b
11000000b
11100000b
11111000b
00h
00h
FFh
FFh
FFh
FFh
FFh
FFh
FFh
FFh
00h
XXh
XXh
XXh
00001000b
00000010b
XXh
XXh
01000000b
00h
10000000b
11110000b
11100000b
00h
00h
00h
FFh
FFh
FFh
FFh
FFh
FFh
FFh
FFh
Under development
R8C/36A Group
Table 4.7
Address
0180h
0181h
0182h
0183h
0184h
0185h
0186h
0187h
0188h
0189h
018Ah
018Bh
018Ch
018Dh
018Eh
018Fh
0190h
0191h
0192h
0193h
0194h
0195h
0196h
0197h
0198h
0199h
019Ah
019Bh
019Ch
019Dh
019Eh
019Fh
01A0h
01A1h
01A2h
01A3h
01A4h
01A5h
01A6h
01A7h
01A8h
01A9h
01AAh
01ABh
01ACh
01ADh
01AEh
01AFh
01B0h
01B1h
01B2h
01B3h
01B4h
01B5h
01B6h
01B7h
01B8h
01B9h
01BAh
01BBh
01BCh
01BDh
01BEh
01BFh

Timer RA Pin Select Register
Timer RB/RC Pin Select Register
Timer RC Pin Select Register 0
Timer RC Pin Select Register 1
Timer RD Pin Select Register 0
Timer RD Pin Select Register 1
Timer Pin Select Register
Timer RF Output Control Register
UART0 Pin Select Register
UART1 Pin Select Register
UART2 Pin Select Register 0
UART2 Pin Select Register 1
SSU/IIC Pin Select Register
Register
Symbol
TRASR
TRBRCSR
TRCPSR0
TRCPSR1
TRDPSR0
TRDPSR1
TIMSR
TRFOUT
U0SR
U1SR
U2SR0
U2SR1
SSUIICSR
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
INT Interrupt Input Pin Select Register

I/O Function Pin Select Register
INTSR
PINSR
00h
00h
SS Bit Counter Register

SS Transmit Data Register L / IIC bus Transmit Data Register (2)
SS Transmit Data Register H (2)
SS Receive Data Register L / IIC bus Receive Data Register (2)
SS Receive Data Register H (2)
SS Control Register H / IIC bus Control Register 1 (2)
SS Control Register L / IIC bus Control Register 2 (2)
SS Mode Register / IIC bus Mode Register (2)
SS Enable Register / IIC bus Interrupt Enable Register (2)
SS Status Register / IIC bus Status Register (2)
SS Mode Register 2 / Slave Address Register (2)
SSBR
SSTDR / ICDRT
SSTDRH
SSRDR / ICDRR
SSRDRH
SSCRH / ICCR1
SSCRL / ICCR2
SSMR / ICMR
SSER / ICIER
SSSR / ICSR
SSMR2 / SAR
11111000b
FFh
FFh
FFh
FFh
00h
01111101b
00010000b / 00011000b
00h
00h / 0000X000b
00h
Flash Memory Status Register
FST
10000X00b
Flash Memory Control Register 0

FMR0
FMR1
FMR2
00h
00h
00h
X: Undefined
Notes:
2. Selectable by the IICSEL bit in the SSUIICSR register.
REJ03B0265-0110 Rev.1.10 Sep 28, 2009

Page 21 of 55
After Reset
Under development
R8C/36A Group
Table 4.8
Address
01C0h
01C1h
01C2h
01C3h
01C4h
01C5h
01C6h
01C7h
01C8h
01C9h
01CAh
01CBh
01CCh
01CDh
01CEh
01CFh
01D0h
01D1h
01D2h
01D3h
01D4h
01D5h
01D6h
01D7h
01D8h
01D9h
01DAh
01DBh
01DCh
01DDh
01DEh
01DFh
01E0h
01E1h
01E2h
01E3h
01E4h
01E5h
01E6h
01E7h
01E8h
01E9h
01EAh
01EBh
01ECh
01EDh
01EEh
01EFh
01F0h
01F1h
01F2h
01F3h
01F4h
01F5h
01F6h
01F7h
01F8h
01F9h
01FAh
01FBh
01FCh
01FDh
01FEh
01FFh

Address Match Interrupt Register 0
Register
Symbol
RMAD0
Address Match Interrupt Enable Register 0

Address Match Interrupt Register 1
AIER0
RMAD1
Address Match Interrupt Enable Register 1
AIER1
After Reset
XXh
XXh
0000XXXXb
00h
XXh
XXh
0000XXXXb
00h
Pull-Up Control Register 0

PUR0
PUR1
PUR2
00h
00h
00h
Port P1 Drive Capacity Control Register

Port P2 Drive Capacity Control Register
Drive Capacity Control Register 0
Input Threshold Control Register 0
Comparator B Control Register 0
P1DRR
P2DRR
DRR0
DRR1
DRR2
VLT0
VLT1
VLT2
INTCMP
00h
00h
00h
00h
00h
00h
00h
00h
00h
External Input Enable Register 0

External Input Enable Register 1
INT Input Filter Select Register 0
INT Input Filter Select Register 1
Key Input Enable Register 0
INTEN
INTEN1
INTF
INTF1
KIEN
00h
00h
00h
00h
00h
X: Undefined
Note:
REJ03B0265-0110 Rev.1.10 Sep 28, 2009

Page 22 of 55
Under development
R8C/36A Group
Table 4.9
Address
2C00h
2C01h
2C02h
2C03h
2C04h
2C05h
2C06h
2C07h
2C08h
2C09h
2C0Ah
:
:
2C3Ah
2C3Bh
2C3Ch
2C3Dh
2C3Eh
2C3Fh
2C40h
2C41h
2C42h
2C43h
2C44h
2C45h
2C46h
2C47h
2C48h
2C49h
2C4Ah
2C4Bh
2C4Ch
2C4Dh
2C4Eh
2C4Fh
2C50h
2C51h
2C52h
2C53h
2C54h
2C55h
2C56h
2C57h
2C58h
2C59h
2C5Ah
2C5Bh
2C5Ch
2C5Dh
2C5Eh
2C5Fh
2C60h
2C61h
2C62h
2C63h
2C64h
2C65h
2C66h
2C67h
2C68h
2C69h
2C6Ah
2C6Bh
2C6Ch
2C6Dh
2C6Eh
2C6Fh

Register
Symbol
DTC Transfer Vector Area

DTC Control Data 0
DTCD0
DTC Control Data 1
DTCD1
DTC Control Data 2
DTCD2
DTC Control Data 3
DTCD3
DTC Control Data 4
DTCD4
DTC Control Data 5
DTCD5
X: Undefined
Note:
REJ03B0265-0110 Rev.1.10 Sep 28, 2009

Page 23 of 55
After Reset
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
Under development
R8C/36A Group
Table 4.10
Address
2C70h
2C71h
2C72h
2C73h
2C74h
2C75h
2C76h
2C77h
2C78h
2C79h
2C7Ah
2C7Bh
2C7Ch
2C7Dh
2C7Eh
2C7Fh
2C80h
2C81h
2C82h
2C83h
2C84h
2C85h
2C86h
2C87h
2C88h
2C89h
2C8Ah
2C8Bh
2C8Ch
2C8Dh
2C8Eh
2C8Fh
2C90h
2C91h
2C92h
2C93h
2C94h
2C95h
2C96h
2C97h
2C98h
2C99h
2C9Ah
2C9Bh
2C9Ch
2C9Dh
2C9Eh
2C9Fh
2CA0h
2CA1h
2CA2h
2CA3h
2CA4h
2CA5h
2CA6h
2CA7h
2CA8h
2CA9h
2CAAh
2CABh
2CACh
2CADh
2CAEh
2CAFh
DTC Control Data 6
Register
Symbol
DTCD6
DTC Control Data 7
DTCD7
DTC Control Data 8
DTCD8
DTC Control Data 9
DTCD9
DTC Control Data 10
DTCD10
DTC Control Data 11
DTCD11
DTC Control Data 12
DTCD12
DTC Control Data 13
DTCD13
X: Undefined
Note:
REJ03B0265-0110 Rev.1.10 Sep 28, 2009

Page 24 of 55
After Reset
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
Under development
R8C/36A Group
Table 4.11
Address
2CB0h
2CB1h
2CB2h
2CB3h
2CB4h
2CB5h
2CB6h
2CB7h
2CB8h
2CB9h
2CBAh
2CBBh
2CBCh
2CBDh
2CBEh
2CBFh
2CC0h
2CC1h
2CC2h
2CC3h
2CC4h
2CC5h
2CC6h
2CC7h
2CC8h
2CC9h
2CCAh
2CCBh
2CCCh
2CCDh
2CCEh
2CCFh
2CD0h
2CD1h
2CD2h
2CD3h
2CD4h
2CD5h
2CD6h
2CD7h
2CD8h
2CD9h
2CDAh
2CDBh
2CDCh
2CDDh
2CDEh
2CDFh
2CE0h
2CE1h
2CE2h
2CE3h
2CE4h
2CE5h
2CE6h
2CE7h
2CE8h
2CE9h
2CEAh
2CEBh
2CECh
2CEDh
2CEEh
2CEFh
DTC Control Data 14
Register
Symbol
DTCD14
DTC Control Data 15
DTCD15
DTC Control Data 16
DTCD16
DTC Control Data 17
DTCD17
DTC Control Data 18
DTCD18
DTC Control Data 19
DTCD19
DTC Control Data 20
DTCD20
DTC Control Data 21
DTCD21
X: Undefined
Note:
REJ03B0265-0110 Rev.1.10 Sep 28, 2009

Page 25 of 55
After Reset
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
Under development
R8C/36A Group
Table 4.12
Address
2CF0h
2CF1h
2CF2h
2CF3h
2CF4h
2CF5h
2CF6h
2CF7h
2CF8h
2CF9h
2CFAh
2CFBh
2CFCh
2CFDh
2CFEh
2CFFh
2D00h
:
2FFFh
DTC Control Data 22
Register
Symbol
DTCD22
DTC Control Data 23
DTCD23
After Reset
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
X: Undefined
Note:
Table 4.13
ID Code Areas and Option Function Select Area
Address
:
FFDBh
:
FFDFh
:
FFE3h
:
FFEBh
:
FFEFh
:
FFF3h
:
FFF7h
:
FFFBh
:
FFFFh
Area Name
Option Function Select Register 2
Symbol
OFS2
After Reset
(Note 1)
ID1
(Note 2)
ID2
(Note 2)
ID3
(Note 2)
ID4
(Note 2)
ID5
(Note 2)
ID6
(Note 2)
ID7
(Note 2)
Option Function Select Register
OFS
(Note 1)
Notes:
1. The option function select area is allocated in the flash memory, not in the SFRs. Set appropriate values as ROM data by a program.
Do not write additions to the option function select area. If the block including the option function select area is erased, the option function select
area is set to FFh.
When blank products are shipped, the option function select area is set to FFh. It is set to the written value after written by the user.
When factory-programming products are shipped, the value of the option function select area is the value programmed by the user.
2. The ID code areas are allocated in the flash memory, not in the SFRs. Set appropriate values as ROM data by a program.
Do not write additions to the ID code areas. If the block including the ID code areas is erased, the ID code areas are set to FFh.
When blank products are shipped, the ID code areas are set to FFh. They are set to the written value after written by the user.
When factory-programming products are shipped, the value of the ID code areas is the value programmed by the user.
REJ03B0265-0110 Rev.1.10 Sep 28, 2009

Page 26 of 55
Under development
R8C/36A Group
5.
5. Electrical Characteristics
Electrical Characteristics
Table 5.1
Absolute Maximum Ratings
Symbol
Parameter
Condition
VCC/AVCC Supply voltage
Rated Value
Unit
0.3 to 6.5
V
V
VI
Input voltage
0.3 to VCC + 0.3
VO
Output voltage
0.3 to VCC + 0.3
Pd
Power dissipation
500
mW
Topr
Operating ambient temperature
Tstg
Storage temperature
REJ03B0265-0110 Rev.1.10 Sep 28, 2009

Page 27 of 55
40C Topr 85C
20 to 85 (N version)
65 to 150
Under development
R8C/36A Group
Table 5.2
Recommended Operating Conditions (1)
Symbol
Parameter
Conditions
Standard
Min.
Typ.
Max.
Unit
VCC/AVCC Supply voltage
1.8
5.5
VSS/AVSS
Supply voltage
VIH
Input H voltage Other than CMOS input
0.8 VCC
VCC
0.5 VCC
VCC
2.7 V VCC < 4.0 V 0.55 VCC
VCC
1.8 V VCC < 2.7 V 0.65 VCC
VCC
4.0 V VCC 5.5 V 0.65 VCC
VCC
2.7 V VCC < 4.0 V
0.7 VCC
VCC
1.8 V VCC < 2.7 V
0.8 VCC
VCC
Input level selection: 4.0 V VCC 5.5 V 0.85 VCC

0.7 VCC
2.7 V VCC < 4.0 V 0.85 VCC
VCC
VCC
1.8 V VCC < 2.7 V 0.85 VCC
VCC
0.2 VCC
4.0 V VCC 5.5 V
0.2 VCC
2.7 V VCC < 4.0 V
0.2 VCC
1.8 V VCC < 2.7 V
0.2 VCC
4.0 V VCC 5.5 V
0.4 VCC
2.7 V VCC < 4.0 V
0.3 VCC
1.8 V VCC < 2.7 V
0.2 VCC
Input level selection: 4.0 V VCC 5.5 V

0.7 VCC
2.7 V VCC < 4.0 V
0.55 VCC
0.45 VCC
1.8 V VCC < 2.7 V
0.35 VCC
CMOS Input level Input level selection:

input
switching 0.35 VCC
function
(I/O port)
Input level selection:
0.5 VCC
VIL
4.0 V VCC 5.5 V
Input L voltage Other than CMOS input

CMOS Input level Input level selection:
input
switching 0.35 VCC
function
(I/O port)
Input level selection:
0.5 VCC
IOH(sum)
Peak sum output H

current
Sum of all pins IOH(peak)
160
mA
IOH(sum)
Average sum output H

current
Sum of all pins IOH(avg)
80
mA
IOH(peak)
Peak output H current
Drive capacity Low
10
mA
Drive capacity High
40
mA
mA
IOH(avg)
Average output H
current
Drive capacity Low

Drive capacity High
20
mA
IOL(sum)
Peak sum output L

current
Sum of all pins IOL(peak)
160
mA
IOL(sum)
Average sum output L

current
Sum of all pins IOL(avg)
80
mA
IOL(peak)
Peak output L current
Drive capacity Low
10
mA
Drive capacity High
40
mA
Drive capacity Low
mA
IOL(avg)
Average output L
current
f(XIN)
XIN clock input oscillation frequency
2.7 V VCC 5.5 V

1.8 V VCC < 2.7 V
f(XCIN)
XCIN clock input oscillation frequency
1.8 V VCC 5.5 V
System clock frequency
2.7 V VCC 5.5 V
1.8 V VCC < 2.7 V
MHz
f(BCLK)
CPU clock frequency
2.7 V VCC 5.5 V
20
MHz
1.8 V VCC < 2.7 V
MHz
Drive capacity High
Notes:
1. VCC = 1.8 to 5.5 V and Topr = 20 to 85C (N version), unless otherwise specified.
2. The average output current indicates the average value of current measured during 100 ms.
REJ03B0265-0110 Rev.1.10 Sep 28, 2009

Page 28 of 55
20
mA
20
MHz
MHz
32.768
50
kHz
20
MHz
Under development
R8C/36A Group
P0
P1
P2
P3
P4
P5
P6
P8
Figure 5.1
30 pF
Ports P0 to P6, P8 Timing Measurement Circuit
REJ03B0265-0110 Rev.1.10 Sep 28, 2009

Page 29 of 55
Under development
R8C/36A Group
Table 5.3
A/D Converter Characteristics
Symbol
Parameter
Resolution
Absolute accuracy
Vref = AVCC
10-bit mode
8-bit mode
AD
Standard
Conditions
A/D conversion clock
Min.
Typ.
Max.
Unit
10
Bit
Vref = AVCC = 5.0 V
AN0 to AN7 input,

AN8 to AN11 input
LSB
Vref = AVCC = 3.3 V
AN0 to AN7 input,

AN8 to AN11 input
LSB
Vref = AVCC = 3.0 V
AN0 to AN7 input,

AN8 to AN11 input
LSB
Vref = AVCC = 2.2 V
AN0 to AN7 input,

AN8 to AN11 input
LSB
Vref = AVCC = 5.0 V
AN0 to AN7 input,

AN8 to AN11 input
LSB
Vref = AVCC = 3.3 V
AN0 to AN7 input,

AN8 to AN11 input
LSB
Vref = AVCC = 3.0 V
AN0 to AN7 input,

AN8 to AN11 input
LSB
Vref = AVCC = 2.2 V
AN0 to AN7 input,

AN8 to AN11 input
LSB
4.0 V Vref = AVCC 5.5 V (2)
20
MHz
3.2 V Vref = AVCC 5.5 V (2)
16
MHz
2.7 V Vref = AVCC 5.5 V (2)
10
MHz
2.2 V Vref = AVCC 5.5 V
MHz
(2)
Tolerance level impedance
DNL
Differential non-linearity error
LSB
tCONV
Conversion time
10-bit mode
Vref = AVCC = 5.0 V, AD = 20 MHz
2.15
8-bit mode
Vref = AVCC = 5.0 V, AD = 20 MHz
2.15
0.75
tSAMP
Sampling time
AD = 20 MHz
VCC = 5.0 V, XIN = f1 = AD = 20 MHz
IVref
Vref current
Vref
Reference voltage
VIA
Analog input voltage (3)
45
2.2
AVCC
Vref
Notes:
1. VCC/AVCC = Vref = 2.2 to 5.5 V, VSS = 0 V, and Topr = 20 to 85C (N version), unless otherwise specified.
2. When the CPU and flash memory stop, the A/D conversion result will be undefined.
3. When the analog input voltage is over the reference voltage, the A/D conversion result will be 3FFh in 10-bit mode and FFh in
8-bit mode.
REJ03B0265-0110 Rev.1.10 Sep 28, 2009

Page 30 of 55
Under development
R8C/36A Group
Table 5.4
D/A Converter Characteristics
Symbol
Parameter
Standard
Condition
Min.
Typ.
Max.
Unit
Resolution
Bit
Absolute accuracy
2.5
LSB
tsu
Setup time
RO
Output resistor
IVref
Reference power input current
1.5
mA
(Note 2)
Notes:
1. VCC/AVCC = Vref = 2.7 to 5.5 V and Topr = 20 to 85C (N version), unless otherwise specified.
2. This applies when one D/A converter is used and the value of the DAi register (i = 0 or 1) for the unused D/A converter is 00h.
The resistor ladder of the A/D converter is not included.
Table 5.5
Comparator A Electrical Characteristics
Symbol
Parameter
Condition
Standard
Min.
Typ.
Max.
Unit
LVREF
External reference voltage input range
1.4
VCC
LVCMP1,
LVCMP2
External comparison voltage input range
0.3
VCC + 0.3
Offset
Comparator output delay time (2)
Comparator operating current
50
200
mV
At falling, VI = Vref 100 mV
At falling, VI = Vref 1 V or below
1.5
At rising, VI = Vref + 100 mV
At rising, VI = Vref + 1 V or above
0.5
VCC = 5.0 V
0.5
Notes:
2. When the digital filter is disabled.
Table 5.6
Comparator B Electrical Characteristics
Symbol
Parameter
Condition
Standard
Min.
Typ.
Max.
Unit
VCC 1.4
0.3
VCC + 0.3
100
mV
Vref
IVREF1, IVREF3 input reference voltage
VI
IVCMP1, IVCMP3 input voltage
Offset
td
Comparator output delay time (2)
VI = Vref 100 mV
0.1
ICMP
Comparator operating current
VCC = 5.0 V
17.5
Notes:
2. When the digital filter is disabled.
REJ03B0265-0110 Rev.1.10 Sep 28, 2009

Page 31 of 55
Under development
R8C/36A Group
Table 5.7
Flash Memory (Program ROM) Electrical Characteristics
Symbol
Parameter
Conditions
Standard
Min.
Typ.
Max.
Unit
1,000 (3)
times
Byte program time
80
Block erase time
0.3
td(SR-SUS) Time delay from suspend request until

suspend
5 + CPU clock
3 cycles
ms
Interval from erase start/restart until

following suspend request
33
ms
Suspend interval necessary for autoerasure to complete
33
ms
Time from suspend until erase restart
30 + CPU clock
1 cycle
Program, erase voltage
2.7
5.5
Read voltage
1.8
5.5
Program, erase temperature
60
Data hold time (7)
20
year
Program/erase endurance (2)
Ambient temperature = 55C
Notes:
1. VCC = 2.7 to 5.5 V and Topr = 0 to 60C, unless otherwise specified.
2. Definition of programming/erasure endurance
The programming and erasure endurance is defined on a per-block basis.
If the programming and erasure endurance is n (n = 1,000), each block can be erased n times. For example, if 1,024 1-byte
writes are performed to different addresses in block A, a 1 Kbyte block, and then the block is erased, the
programming/erasure endurance still stands at one. However, the same address must not be programmed more than once
per erase operation (overwriting prohibited).
3. Endurance to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed.)
4. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential
addresses in turn so that as much of the block as possible is used up before performing an erase operation. For example,
when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups
before erasing them all in one operation. It is also advisable to retain data on the erasure endurance of each block and limit
the number of erase operations to a certain number.
5. If an error occurs during block erase, attempt to execute the clear status register command, then execute the block erase
command at least three times until the erase error does not occur.
6. Customers desiring program/erase failure rate information should contact their Renesas technical support representative.
7. The data hold time includes time that the power supply is off or the clock is not supplied.
REJ03B0265-0110 Rev.1.10 Sep 28, 2009

Page 32 of 55
Under development
R8C/36A Group
Table 5.8
Flash Memory (Data flash Block A to Block D) Electrical Characteristics
Symbol
Parameter
Standard
Conditions
Min.
Typ.
Max.
Unit
10,000 (3)
times
Byte program time

(program/erase endurance 1,000 times)
160
Byte program time

(program/erase endurance > 1,000 times)
300
Block erase time

(program/erase endurance 1,000 times)
0.2
Block erase time

(program/erase endurance > 1,000 times)
0.3
td(SR-SUS) Time delay from suspend request until

suspend
5 + CPU clock
3 cycles
ms
Interval from erase start/restart until

following suspend request
33
ms
Suspend interval necessary for autoerasure to complete
33
ms
Time from suspend until erase restart
30 + CPU clock
1 cycle
Program, erase voltage
2.7
5.5
Read voltage
1.8
5.5
Program, erase temperature
20
85
Data hold time (7)
20
year
Program/erase endurance (2)
Ambient temperature = 55C
Notes:
2. Definition of programming/erasure endurance
The programming and erasure endurance is defined on a per-block basis.
If the programming and erasure endurance is n (n = 10,000), each block can be erased n times. For example, if 1,024 1-byte
writes are performed to different addresses in block A, a 1 Kbyte block, and then the block is erased, the
programming/erasure endurance still stands at one. However, the same address must not be programmed more than once
per erase operation (overwriting prohibited).
3. Endurance to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed.)
4. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential
addresses in turn so that as much of the block as possible is used up before performing an erase operation. For example,
when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups
before erasing them all in one operation. In addition, averaging the erasure endurance between blocks A to D can further
reduce the actual erasure endurance. It is also advisable to retain data on the erasure endurance of each block and limit the
number of erase operations to a certain number.
5. If an error occurs during block erase, attempt to execute the clear status register command, then execute the block erase
command at least three times until the erase error does not occur.
6. Customers desiring program/erase failure rate information should contact their Renesas technical support representative.
7. The data hold time includes time that the power supply is off or the clock is not supplied.
Suspend request
(FMR21 bit)
FST6 bit
Fixed time
Clock-dependent
time
td(SR-SUS)
FST6: Bit in FST register

FMR21: Bit in FMR2 register
Figure 5.2
Time delay until Suspend
REJ03B0265-0110 Rev.1.10 Sep 28, 2009

Page 33 of 55
Access restart
Under development
R8C/36A Group
Table 5.9
Voltage Detection 0 Circuit Electrical Characteristics
Symbol
Vdet0
Parameter
Standard
Unit
Min.
Typ.
Max.
Voltage detection level Vdet0_0 (2)
1.80
1.90
2.05
2.15
2.35
2.50
2.65
2.85
3.00
(2)
3.55
3.80
4.05
150
1.5
100
Voltage detection level Vdet0_3
Condition
Voltage detection 0 circuit response time
(4)
Voltage detection circuit self power consumption
td(E-A)
Waiting time until voltage detection circuit operation

starts (3)
At the falling of VCC from

5.0 V to (Vdet0_0 0.1) V
VCA25 = 1, VCC = 5.0 V
Notes:
1. The measurement condition is VCC = 1.8 to 5.5 V and Topr = 20 to 85C (N version).
2. Select the voltage detection level with bits VDSEL0 and VDSEL1 in the OFS register.
3. Necessary time until the voltage detection circuit operates when setting to 1 again after setting the VCA25 bit in the VCA2
register to 0.
4. Time until the voltage monitor 0 reset is generated after the voltage passes Vdet0.
Table 5.10
Symbol

Parameter
Condition
Standard
Min.
Typ.
Max.
Unit
At the falling of VCC
2.00
2.20
2.40
2.15
2.35
2.55
2.30
2.50
2.70
(2)
2.45
2.65
2.85
(2)
2.60
2.80
3.00
2.75
2.95
3.15
2.90
3.10
3.30
(2)
3.05
3.25
3.45
(2)
3.20
3.40
3.60
3.35
3.55
3.75
Voltage detection level Vdet1_A (2)
3.50
3.70
3.90
Voltage detection level Vdet1_B
(2)
3.65
3.85
4.05
Voltage detection level Vdet1_C
(2)
3.80
4.00
4.20
Voltage detection level Vdet1_D (2)
3.95
4.15
4.35
Voltage detection level Vdet1_E (2)
4.10
4.30
4.50
Voltage detection level Vdet1_F (2)
4.25
4.45
4.65
Hysteresis width at the rising of VCC in voltage

detection 1 circuit
Vdet1_0 to Vdet1_5
selected
0.07
Vdet1_6 to Vdet1_F
selected
0.10
Voltage detection 1 circuit response time (3)

5.0 V to (Vdet1_0 0.1) V
60
150
VCA26 = 1, VCC = 5.0 V
1.7
td(E-A)

starts (4)
100
Vdet1
Notes:
2. Select the voltage detection level with bits VD1S0 to VD1S3 in the VD1LS register.
3. Time until the voltage monitor 1 interrupt request is generated after the voltage passes Vdet1.
4. Necessary time until the voltage detection circuit operates when setting to 1 again after setting the VCA26 bit in the VCA2
register to 0.
REJ03B0265-0110 Rev.1.10 Sep 28, 2009

Page 34 of 55
Under development
R8C/36A Group
Table 5.11
Symbol
Vdet2
Parameter
Standard
Condition
Min.
Typ.
Unit
Max.
3.70
4.00
4.30
Voltage detection level Vdet2_EXT (2)
At the falling of LVCMP2
1.20
1.34
1.48
0.10
20
150
1.7
100
Hysteresis width at the rising of VCC in voltage

detection 2 circuit
Voltage detection 2 circuit response time (3)

5.0 V to (Vdet2_0 0.1) V
VCA27 = 1, VCC = 5.0 V
td(E-A)

starts (4)
Notes:
2. The voltage detection level varies with detection targets. Select the level with the VCA24 bit in the VCA2 register.
3. Time until the voltage monitor 2 interrupt request is generated after the voltage passes Vdet2.
4. Necessary time until the voltage detection circuit operates after setting to 1 again after setting the VCA27 bit in the VCA2
register to 0.
Table 5.12
Power-on Reset Circuit (2)
Symbol
Parameter
Condition
Standard
Min.
Typ.
Max.
50,000
External power VCC rise gradient
trth
Unit
mV/msec
Notes:
1. The measurement condition is Topr = 20 to 85C (N version), unless otherwise specified.
2. To use the power-on reset function, enable voltage monitor 0 reset by setting the LVDAS bit in the OFS register to 0.
Vdet0 (1)
Vdet0 (1)
trth
trth
External
Power VCC
0.5 V
Voltage detection 0
circuit response time
tw(por) (2)
Internal
reset signal
1
32
fOCO-S
1
32
fOCO-S
Notes:
1. Vdet0 indicates the voltage detection level of the voltage detection 0 circuit. Refer to 6. Voltage Detection
Circuit of Hardware Manual (REJ09B0480) for details.
2. tw(por) indicates the duration the external power VCC must be held below the valid voltage (0.5 V) to enable
a power-on reset. When turning on the power after it falls with voltage monitor 0 reset disabled, maintain
tw(por) for 1 ms or more.
Figure 5.3
Power-on Reset Circuit Electrical Characteristics
REJ03B0265-0110 Rev.1.10 Sep 28, 2009

Page 35 of 55
Under development
R8C/36A Group
Table 5.13
Symbol
Low-speed On-Chip Oscillator Circuit Electrical Characteristics

Parameter
Condition
Standard
Min.
Typ.
Max.
Unit
fOCO-S
Low-speed on-chip oscillator frequency
60
125
250
Oscillation stability time
VCC = 5.0 V, Topr = 25C
30
100
kHz
s
Self power consumption at oscillation
VCC = 5.0 V, Topr = 25C
Note:
Table 5.14
Symbol
td(P-R)
Power Supply Circuit Timing Characteristics

Parameter
Condition
Time for internal power supply stabilization during

power-on (2)
Notes:
1. The measurement condition is VCC = 1.8 to 5.5 V and Topr = 25C.
2. Waiting time until the internal power supply generation circuit stabilizes during power-on.
REJ03B0265-0110 Rev.1.10 Sep 28, 2009

Page 36 of 55
Standard
Min.
Typ.
Max.
2,000
Unit
s
Under development
R8C/36A Group
Table 5.15
Symbol
Timing Requirements of Synchronous Serial Communication Unit (SSU)

Parameter
Conditions
Standard
Min.
Typ.
Max.
Unit
tSUCYC
SSCK clock cycle time
tHI
SSCK clock H width
0.4
0.6
tSUCYC
tLO
SSCK clock L width
0.4
0.6
tSUCYC
tRISE
SSCK clock rising

time
tCYC (2)
tCYC (2)
Master
Slave
Master
tCYC (2)
tFALL
SSCK clock falling

time
tSU
SSO, SSI data input setup time
100
ns
tH
SSO, SSI data input hold time
tCYC (2)
tLEAD
Slave
SCS setup time
Slave
1tCYC + 50
ns
tLAG
SCS hold time
Slave
1tCYC + 50
ns
tOD
SSO, SSI data output delay time
tCYC (2)
tSA
SSI slave access time
2.7 V VCC 5.5 V
1.5tCYC + 100
ns
1.8 V VCC < 2.7 V
1.5tCYC + 200
ns
2.7 V VCC 5.5 V
1.5tCYC + 100
ns
1.8 V VCC < 2.7 V
1.5tCYC + 200
ns
tOR
SSI slave out open time
Notes:
1. VCC = 1.8 to 5.5 V, VSS = 0 V, and Topr = 20 to 85C (N version), unless otherwise specified.
2. 1tCYC = 1/f1(s)
REJ03B0265-0110 Rev.1.10 Sep 28, 2009

Page 37 of 55
Under development
R8C/36A Group
4-Wire Bus Communication Mode, Master, CPHS = 1

VIH or VOH
SCS (output)
VIL or VOL
tHI
tFALL
tRISE
SSCK (output)
(CPOS = 1)
tLO
tHI
SSCK (output)
(CPOS = 0)
tLO
tSUCYC
SSO (output)
tOD
SSI (input)
tSU
tH
4-Wire Bus Communication Mode, Master, CPHS = 0

VIH or VOH
SCS (output)
VIL or VOL
tHI
tFALL
tRISE
SSCK (output)
(CPOS = 1)
tLO
tHI
SSCK (output)
(CPOS = 0)
tLO
tSUCYC
SSO (output)
tOD
SSI (input)
tSU
tH
CPHS, CPOS: Bits in SSMR register
Figure 5.4
I/O Timing of Synchronous Serial Communication Unit (SSU) (Master)
REJ03B0265-0110 Rev.1.10 Sep 28, 2009

Page 38 of 55
Under development
R8C/36A Group
4-Wire Bus Communication Mode, Slave, CPHS = 1

VIH or VOH
SCS (input)
VIL or VOL
tLEAD
tHI
tFALL
tRISE
tLAG
SSCK (input)
(CPOS = 1)
tLO
tHI
SSCK (input)
(CPOS = 0)
tLO
tSUCYC
SSO (input)
tSU
tH
SSI (output)
tSA
tOD
tOR
4-Wire Bus Communication Mode, Slave, CPHS = 0

VIH or VOH
SCS (input)
VIL or VOL
tLEAD
tHI
tFALL
tRISE
tLAG
SSCK (input)
(CPOS = 1)
tLO
tHI
SSCK (input)
(CPOS = 0)
tLO
tSUCYC
SSO (input)
tSU
tH
SSI (output)
tSA
tOD
tOR
CPHS, CPOS: Bits in SSMR register
Figure 5.5
I/O Timing of Synchronous Serial Communication Unit (SSU) (Slave)
REJ03B0265-0110 Rev.1.10 Sep 28, 2009

Page 39 of 55
Under development
R8C/36A Group
tHI
VIH or VOH
SSCK
VIL or VOL
tSUCYC
tLO
SSO (output)
tOD
SSI (input)
tSU
Figure 5.6
tH
I/O Timing of Synchronous Serial Communication Unit (SSU) (Clock Synchronous

Communication Mode)
REJ03B0265-0110 Rev.1.10 Sep 28, 2009

Page 40 of 55
Under development
R8C/36A Group
Table 5.16
Timing Requirements of I2C bus Interface
Symbol
Parameter
Standard
Typ.
12tCYC + 600 (2)
3tCYC + 300 (2)
Condition
Min.
Max.
Unit
tSCL
SCL input cycle time
tSCLH
SCL input H width
tSCLL
SCL input L width
tsf
tSP
SCL, SDA input fall time

SCL, SDA input spike pulse rejection time
tBUF
SDA input bus-free time
5tCYC (2)
1tCYC (2)
tSTAH
Start condition input hold time
3tCYC (2)
ns
tSTAS
Retransmit start condition input setup time
3tCYC (2)
ns
tSTOP
Stop condition input setup time
3tCYC (2)
ns
tSDAS
Data input setup time
ns
tSDAH
Data input hold time
1tCYC + 40 (2)
10
ns
5tCYC + 500
(2)
ns
ns
300
ns
ns
Notes:
1. VCC = 1.8 to 5.5 V, VSS = 0 V, and Topr = 20 to 85C (N version), unless otherwise specified.
2. 1tCYC = 1/f1(s)
VIH
SDA
VIL
tBUF
tSTAH
tSCLH
tSTAS
tSP
tSTOP
SCL
P (2)
Sr (3)
S (1)
tSf
tSCLL
tSDAH
Notes:
1. Start condition
2. Stop condition
3. Retransmit start condition
Figure 5.7
I/O Timing of I2C bus Interface
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Page 41 of 55
P (2)
tSDAS
tSr
tSCL
ns
ns
Under development
R8C/36A Group
Table 5.17
Symbol
Electrical Characteristics (1) [4.2 V VCC 5.5 V]

Parameter
VOH
Output H voltage
VOL
Output L voltage
VT+-VT-
Hysteresis INT0, INT1, INT2,

INT3, INT4,
KI0, KI1, KI2, KI3,
TRAIO, TRBO,
TRCIOA, TRCIOB,
TRCIOC, TRCIOD,
TRDIOA0, TRDIOB0,
TRDIOC0, TRDIOD0,
TRDIOA1, TRDIOB1,
TRDIOC1, TRDIOD1,
TRCTRG, TRCCLK,
TRFI, TRGIOA,
TRGIOB, ADTRG,
RXD0, RXD1, RXD2,
CLK0, CLK1, CLK2,
SSI, SCL, SDA, SSO
IIH
IIL
RPULLUP
RfXIN
RfXCIN
VRAM
RESET
Input H current
Input L current
Pull-up resistance
Feedback XIN
resistance
Feedback XCIN
resistance
RAM hold voltage
Condition
Drive capacity High
Drive capacity Low
Drive capacity High
Drive capacity Low
VCC = 5.0 V
VCC = 5.0 V
VCC = 5.0 V
VCC = 5.0 V
VI = 5 V, VCC = 5.0 V
VI = 0 V, VCC = 5.0 V
VI = 0 V, VCC = 5.0 V
During stop mode
Standard
Min.
Typ.
IOH = 20 mA VCC 2.0
IOH = 5 mA VCC 2.0
IOL = 20 mA
IOL = 5 mA
0.1
1.2
Unit
V
V
V
V
V
0.1
1.2
25
50
0.3
5.0
5.0
100
A
A
k
M
1.8
Note:
1. 4.2 V VCC 5.5 V, Topr = 20 to 85C (N version), and f(XIN) = 20 MHz, unless otherwise specified.
REJ03B0265-0110 Rev.1.10 Sep 28, 2009

Page 42 of 55
Max.
VCC
VCC
2.0
2.0
Under development
R8C/36A Group
Table 5.18
Symbol
ICC
Electrical Characteristics (2) [3.3 V VCC 5.5 V]

(Topr = 20 to 85C (N version), unless otherwise specified.)
Parameter
Condition
Power supply current High-speed

(VCC = 3.3 to 5.5 V) clock mode
Single-chip mode,
output pins are open,
other pins are VSS
XIN = 20 MHz (square wave)

Low-speed on-chip oscillator on = 125 kHz
No division
No division
No division
Divide-by-8
Divide-by-8
Divide-by-8
XIN clock off
Divide-by-8, FMR27 = 1, VCA20 = 0
Low-speed
on-chip
oscillator mode
XIN clock off
Low-speed
Low-speed on-chip oscillator off
clock mode
Wait mode
Stop mode
XCIN clock oscillator on = 32 kHz

No division
FMR27 = 1, VCA20 = 0
XIN clock off
No division
Program operation on RAM
Flash memory off, FMSTP = 1, VCA20 = 0
XIN clock off
While a WAIT instruction is executed
Peripheral clock operation
VCA27 = VCA26 = VCA25 = 0, VCA20 = 1
XIN clock off
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0, VCA20 = 1
XIN clock off
XCIN clock oscillator on = 32 kHz (peripheral clock off)
VCA27 = VCA26 = VCA25 = 0, VCA20 = 1
XIN clock off, Topr = 25C
CM10 = 1
VCA27 = VCA26 = VCA25 = 0
CM10 = 1
VCA27 = VCA26 = VCA25 = 0
REJ03B0265-0110 Rev.1.10 Sep 28, 2009

Page 43 of 55
Min.
Standard
Typ. Max.
7
15
Unit
mA
5.6
12.5
mA
3.6
mA
mA
2.2
mA
1.5
mA
90
400
85
400
47
15
100
90
15
Under development
R8C/36A Group
Timing Requirements
Table 5.19
(Unless Otherwise Specified: VCC = 5 V, VSS = 0 V, Topr = 25C)
XIN Input, XCIN Input
Symbol
tc(XIN)
tWH(XIN)
tWL(XIN)
tc(XCIN)
tWH(XCIN)
tWL(XCIN)
Standard
Min.
Max.
50
24
24
14
Parameter
XIN input cycle time
XIN input H width
XIN input L width
XCIN input cycle time
XCIN input H width
XCIN input L width
tC(XIN)
Unit
ns
ns
ns
s
s
s
VCC = 5 V
tWH(XIN)
XIN input
tWL(XIN)
XIN Input and XCIN Input Timing Diagram when VCC = 5 V
Figure 5.8
Table 5.20
TRAIO Input
Symbol
Standard
Min.
Max.
100
40
40
Parameter
tc(TRAIO)
TRAIO input cycle time
tWH(TRAIO) TRAIO input H width
tWL(TRAIO) TRAIO input L width
tC(TRAIO)
Unit
ns
ns
ns
VCC = 5 V
tWH(TRAIO)
TRAIO input
tWL(TRAIO)
Figure 5.9
TRAIO Input Timing Diagram when VCC = 5 V
Table 5.21
TRFI Input
Symbol
Standard
Min.
Max.
(1)
400
Parameter
tc(TRFI)
TRFI input cycle time
tWH(TRFI)
tWL(TRFI)
Unit
ns
TRFI input H width
200
(2)
ns
TRFI input L width
200 (2)
ns
Notes:
1. When using timer RF input capture mode, adjust the cycle time to (1/timer RF count source frequency 3) or above.
2. When using timer RF input capture mode, adjust the pulse width to (1/timer RF count source frequency 1.5) or above.
tc(TRFI)
VCC = 5 V
tWH(TRFI)
TRFI input
tWL(TRFI)
Figure 5.10
TRFI Input Timing Diagram when VCC = 5 V
REJ03B0265-0110 Rev.1.10 Sep 28, 2009

Page 44 of 55
Under development
R8C/36A Group
Table 5.22
Serial Interface
Symbol
tc(CK)
tW(CKH)
tW(CKL)
td(C-Q)
th(C-Q)
tsu(D-C)
th(C-D)
Standard
Min.
Max.
200
100
100
70
0
50
90
Parameter
CLKi input cycle time
CLKi input H width
CLKi input L width
TXDi output delay time
TXDi hold time
RXDi input setup time
RXDi input hold time
Unit
ns
ns
ns
ns
ns
ns
ns
i = 0 to 2
tC(CK)
VCC = 5 V
tW(CKH)
CLKi
tW(CKL)
th(C-Q)
TXDi
td(C-Q)
tsu(D-C)
th(C-D)
RXDi
i = 0 to 2
Figure 5.11
Table 5.23
Serial Interface Timing Diagram when VCC = 5 V
External Interrupt INTi (i = 0 to 4) Input, Key Input Interrupt KIi (i = 0 to 3)
INTi input H width, KIi input H width
Standard
Min.
Max.
250 (1)
INTi input L width, KIi input L width
250 (2)
Symbol
tW(INH)
tW(INL)
Parameter
Unit
ns
ns
Notes:
1. When selecting the digital filter by the INTi input filter select bit, use an INTi input HIGH width of either (1/digital filter clock
frequency 3) or the minimum value of standard, whichever is greater.
2. When selecting the digital filter by the INTi input filter select bit, use an INTi input LOW width of either (1/digital filter clock
INTi input
(i = 0 to 4)
VCC = 5 V
tW(INL)
KIi input
(i = 0 to 3)
Figure 5.12
tW(INH)
Input Timing Diagram for External Interrupt INTi and Key Input Interrupt KIi
when VCC = 5 V
REJ03B0265-0110 Rev.1.10 Sep 28, 2009

Page 45 of 55
Under development
R8C/36A Group
Table 5.24
Electrical Characteristics (3) [2.7 V VCC < 4.2 V]
Symbol
Parameter
VOH
Output H voltage
VOL
Output L voltage
VT+-VT-
Hysteresis
IIH
IIL
RPULLUP
RfXIN
Input H current
Input L current
Pull-up resistance
Feedback
resistance
Feedback
resistance
RAM hold voltage
INT0, INT1, INT2,

INT3, INT4,
KI0, KI1, KI2, KI3,
TRAIO, TRBO,
TRCIOA, TRCIOB,
TRCIOC, TRCIOD,
TRDIOA0, TRDIOB0,
TRDIOC0, TRDIOD0,
TRDIOA1, TRDIOB1,
TRDIOC1, TRDIOD1,
TRCTRG, TRCCLK,
TRFI, TRGIOA,
TRGIOB, ADTRG,
RXD0, RXD1, RXD2,
CLK0, CLK1, CLK2,
SSI, SCL, SDA, SSO
VRAM
Drive capacity High

Drive capacity Low
Drive capacity High
Drive capacity Low
VCC = 3.0 V
Min.
IOH = 5 mA VCC 0.5
IOH = 1 mA VCC 0.5
IOL = 5 mA
IOL = 1 mA
0.1
Standard
Typ.
0.4
Max.
VCC
VCC
0.5
0.5
Unit
V
V
V
V
V
VCC = 3.0 V
0.1
0.5
VI = 3 V, VCC = 3.0 V
VI = 0 V, VCC = 3.0 V
VI = 0 V, VCC = 3.0 V
84
0.3
4.0
4.0
168
XIN
42
A
k
M
XCIN
1.8
RESET
RfXCIN
Condition
During stop mode
Note:
1. 2.7 V VCC < 4.2 V, Topr = 20 to 85C (N version), and f(XIN) = 10 MHz, unless otherwise specified.
REJ03B0265-0110 Rev.1.10 Sep 28, 2009

Page 46 of 55
Under development
R8C/36A Group
Table 5.25
Symbol
ICC

Parameter
Condition

Single-chip mode,
other pins are VSS

No division
Min.
Standard
Typ. Max.
3.5
10
Unit
mA

Divide-by-8
1.5
7.5
mA
XIN clock off

Low-speed
on-chip
oscillator mode Divide-by-8, FMR27 = 1, VCA20 = 0
90
390
Low-speed
clock mode
XIN clock off

No division
FMR27 = 1, VCA20 = 0
80
400
XIN clock off

No division
40
XIN clock off

VCA27 = VCA26 = VCA25 = 0, VCA20 = 1
15
90
XIN clock off

VCA27 = VCA26 = VCA25 = 0, VCA20 = 1
80
XIN clock off

VCA27 = VCA26 = VCA25 = 0, VCA20 = 1

CM10 = 1
VCA27 = VCA26 = VCA25 = 0

CM10 = 1
VCA27 = VCA26 = VCA25 = 0
Wait mode
Stop mode
REJ03B0265-0110 Rev.1.10 Sep 28, 2009

Page 47 of 55
Under development
R8C/36A Group
Timing requirements
Table 5.26
(Unless Otherwise Specified: VCC = 3 V, VSS = 0 V, Topr = 25C)
Symbol
tc(XIN)
tWH(XIN)
tWL(XIN)
tc(XCIN)
tWH(XCIN)
tWL(XCIN)
Standard
Min.
Max.
50
24
24
14
Parameter
XIN input H width
XIN input L width
XCIN input H width
XCIN input L width
tC(XIN)
Unit
ns
ns
ns
s
s
s
VCC = 3 V
tWH(XIN)
XIN input
tWL(XIN)
Figure 5.13
Table 5.27
XIN Input and XCIN Input Timing Diagram when VCC = 3 V
TRAIO Input
Symbol
Standard
Min.
Max.
300
120
120
Parameter
tc(TRAIO)
tC(TRAIO)
Unit
ns
ns
ns
VCC = 3 V
tWH(TRAIO)
TRAIO input
tWL(TRAIO)
Figure 5.14
Table 5.28
TRAIO Input Timing Diagram when VCC = 3 V
TRFI Input
Symbol
Standard
Min.
Max.
1,200 (1)
Parameter
tc(TRFI)
tWH(TRFI)
TRFI input H width
tWL(TRFI)
TRFI input L width
Unit
600
ns
600
(2)
ns
Notes:
tc(TRFI)
VCC = 3 V
tWH(TRFI)
TRFI input
tWL(TRFI)
Figure 5.15
TRFI Input Timing Diagram when VCC = 3 V
REJ03B0265-0110 Rev.1.10 Sep 28, 2009

Page 48 of 55
ns
(2)
Under development
R8C/36A Group
Table 5.29
Serial Interface
Symbol
tc(CK)
tW(CKH)
tW(CKL)
td(C-Q)
th(C-Q)
tsu(D-C)
th(C-D)
Standard
Min.
Max.
300
150
150
80
0
70
90
Parameter
CLKi input H width
CLKi Input L width
TXDi hold time
Unit
ns
ns
ns
ns
ns
ns
ns
i = 0 to 2
tC(CK)
VCC = 3 V
tW(CKH)
CLKi
tW(CKL)
th(C-Q)
TXDi
td(C-Q)
tsu(D-C)
th(C-D)
RXDi
i = 0 to 2
Figure 5.16
Table 5.30
Serial Interface Timing Diagram when VCC = 3 V
Standard
Min.
Max.
380 (1)
380 (2)
Symbol
tW(INH)
tW(INL)
Parameter
Unit
ns
ns
Notes:
INTi input
(i = 0 to 4)
VCC = 3 V
tW(INL)
KIi input
(i = 0 to 3)
Figure 5.17
tW(INH)
when VCC = 3 V
REJ03B0265-0110 Rev.1.10 Sep 28, 2009

Page 49 of 55
Under development
R8C/36A Group
Table 5.31
Symbol
Parameter
VOH
Output H voltage
VOL
Output L voltage
VT+-VT-
Hysteresis
IIH
IIL
RPULLUP
RfXIN
Input H current
Input L current
Pull-up resistance
Feedback
resistance
Feedback
resistance
RAM hold voltage
Condition
Drive capacity High
Drive capacity Low
Drive capacity High
Drive capacity Low
NT0, INT1, INT2,

INT3, INT4,
KI0, KI1, KI2, KI3,
TRAIO, TRBO,
TRCIOA, TRCIOB,
TRCIOC, TRCIOD,
TRDIOA0, TRDIOB0,
TRDIOC0, TRDIOD0,
TRDIOA1, TRDIOB1,
TRDIOC1, TRDIOD1,
TRCTRG, TRCCLK,
TRFI, TRGIOA,
TRGIOB, ADTRG,
RXD0, RXD1, RXD2,
CLK0, CLK1, CLK2,
SSI, SCL, SDA, SSO
Min.
IOH = 2 mA VCC 0.5
IOH = 1 mA VCC 0.5
IOL = 2 mA
IOL = 1 mA
0.05
VRAM
Max.
VCC
VCC
0.5
0.5
Unit
V
V
V
V
V
0.05
0.20
140
0.3
4.0
4.0
300
XIN
70
A
k
M
XCIN
1.8
RESET
RfXCIN
Standard
Typ.
0.20
VI = 2.2 V, VCC = 2.2 V

VI = 0 V, VCC = 2.2 V
VI = 0 V, VCC = 2.2 V
During stop mode
Note:
1. 1.8 V VCC < 2.7 V, Topr = 20 to 85C (N version), and f(XIN) = 5 MHz, unless otherwise specified.
REJ03B0265-0110 Rev.1.10 Sep 28, 2009

Page 50 of 55
Under development
R8C/36A Group
Table 5.32
Symbol
ICC

Parameter
Condition

Single-chip mode,
other pins are VSS

No division
Min.
Standard
Typ. Max.
2.2
Unit
mA

Divide-by-8
0.8
mA
XIN clock off

Low-speed
on-chip
oscillator mode Divide-by-8, FMR27 = 1, VCA20 = 0
90
300
Low-speed
clock mode
XIN clock off

No division
FMR27 = 1, VCA20 = 0
80
350
XIN clock off

No division
40
XIN clock off

VCA27 = VCA26 = VCA25 = 0, VCA20 = 1
15
90
XIN clock off

VCA27 = VCA26 = VCA25 = 0, VCA20 = 1
80
XIN clock off

VCA27 = VCA26 = VCA25 = 0, VCA20 = 1

CM10 = 1
VCA27 = VCA26 = VCA25 = 0

CM10 = 1
VCA27 = VCA26 = VCA25 = 0
15
Wait mode
Stop mode
REJ03B0265-0110 Rev.1.10 Sep 28, 2009

Page 51 of 55
Under development
R8C/36A Group
Timing requirements
Table 5.33
(Unless Otherwise Specified: VCC = 2.2 V, VSS = 0 V, Topr = 25C)
Symbol
tc(XIN)
tWH(XIN)
tWL(XIN)
tc(XCIN)
tWH(XCIN)
tWL(XCIN)
Standard
Min.
Max.
200
90
90
14
Parameter
XIN input H width
XIN input L width
XCIN input H width
XCIN input L width
tC(XIN)
Unit
ns
ns
ns
s
s
s
VCC = 2.2 V
tWH(XIN)
XIN input
tWL(XIN)
Figure 5.18
Table 5.34
XIN Input and XCIN Input Timing Diagram when VCC = 2.2 V
TRAIO Input
Symbol
Standard
Min.
Max.
500
200
200
Parameter
tc(TRAIO)
tC(TRAIO)
Unit
ns
ns
ns
VCC = 2.2 V
tWH(TRAIO)
TRAIO input
tWL(TRAIO)
Figure 5.19
Table 5.35
TRAIO Input Timing Diagram when VCC = 2.2 V
TRFI Input
Symbol
Standard
Min.
Max.
2,000 (1)
Parameter
tc(TRFI)
tWH(TRFI)
TRFI input H width
tWL(TRFI)
TRFI input L width
Unit
ns
1,000
(2)
ns
1,000
(2)
ns
Notes:
tc(TRFI)
VCC = 2.2 V
tWH(TRFI)
TRFI input
tWL(TRFI)
Figure 5.20
TRFI Input Timing Diagram when VCC = 2.2 V
REJ03B0265-0110 Rev.1.10 Sep 28, 2009

Page 52 of 55
Under development
R8C/36A Group
Table 5.36
Serial Interface
Symbol
tc(CK)
tW(CKH)
tW(CKL)
td(C-Q)
th(C-Q)
tsu(D-C)
th(C-D)
Standard
Min.
Max.
800
400
400
200
0
150
90
Parameter
CLKi input H width
CLKi input L width
TXDi hold time
Unit
ns
ns
ns
ns
ns
ns
ns
i = 0 to 2
tC(CK)
VCC = 2.2 V
tW(CKH)
CLKi
tW(CKL)
th(C-Q)
TXDi
td(C-Q)
tsu(D-C)
th(C-D)
RXDi
i = 0 to 2
Figure 5.21
Table 5.37
Serial Interface Timing Diagram when VCC = 2.2 V
Standard
Min.
Max.
1,000 (1)
1,000 (2)
Symbol
tW(INH)
tW(INL)
Parameter
Unit
ns
ns
Notes:
INTi input
(i = 0 to 4)
VCC = 2.2 V
tW(INL)
KIi input
(i = 0 to 3)
Figure 5.22
tW(INH)
when VCC = 2.2 V
REJ03B0265-0110 Rev.1.10 Sep 28, 2009

Page 53 of 55
Under development
R8C/36A Group
Package Dimensions
Package Dimensions
Diagrams showing the latest package dimensions and mounting information are available in the Packages section of
the Renesas Technology website.
JEITA Package Code
P-LQFP64-10x10-0.50
RENESAS Code
PLQP0064KB-A
Previous Code
64P6Q-A / FP-64K / FP-64KV
MASS[Typ.]
0.3g
HD
*1
48
33
49
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
32
bp
64
c1
Terminal cross section
ZE
17
Reference
Symbol
E
*2
HE
b1
16
Index mark
ZD
A
*3
A1
y
e
A2
bp
L1
Detail F
REJ03B0265-0110 Rev.1.10 Sep 28, 2009

Page 54 of 55
D
E
A2
HD
HE
A
A1
bp
b1
c
c1
e
x
y
ZD
ZE
L
L1
Dimension in Millimeters
Min Nom Max

9.9 10.0 10.1
9.9 10.0 10.1
1.4
11.8 12.0 12.2
11.8 12.0 12.2
1.7
0.05 0.1 0.15
0.15 0.20 0.25
0.18
0.09 0.145 0.20
0.125
0
8
0.5
0.08
0.08
1.25
1.25
0.35 0.5 0.65
1.0
Under development
R8C/36A Group
Package Dimensions
JEITA Package Code

P-LQFP64-14x14-0.80
RENESAS Code
PLQP0064GA-A
Previous Code
64P6U-A
MASS[Typ.]
0.7g
HD
*1
33
48
49
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
32
bp
Reference
Symbol
*2
HE
c1
b1
ZE
Terminal cross section
64
17
Index mark
A2
16
ZD
A1
D
E
A2
HD
HE
A
A1
bp
b1
c
c1
L1
y
e
Detail F
*3
bp
REJ03B0265-0110 Rev.1.10 Sep 28, 2009

Page 55 of 55
e
x
y
ZD
ZE
L
L1
Dimension in Millimeters
Min Nom Max

13.9 14.0 14.1
13.9 14.0 14.1
1.4
15.8 16.0 16.2
15.8 16.0 16.2
1.7
0.1 0.2
0
0.32 0.37 0.42
0.35
0.09 0.145 0.20
0.125
0
8
0.8
0.20
0.10
1.0
1.0
0.3 0.5 0.7
1.0
REVISION HISTORY
R8C/36A Group Datasheet

Description
Rev.
Date
0.10
Jun 29, 2009
1.00
Sep 10, 2009 All pages Preliminary Under development deleted
Page
Summary
First Edition issued
Table 1.2 revised
10
Table 1.6 Note 2 deleted
28
Table 5.1 revised
29
Table 5.2 revised, Note 3 deleted
33, 34
Table 5.7, Table 5.8 revised
35, 36
Table 5.9, Table 5.10, Table 5.11, Table 5.12 revised
43, 47, 51 Table 5.17, Table 5.24, Table 5.31 revised

46
50, 54
1.10
Table 5.22 revised, Table 5.23 INT0 INTi

Table 5.30, Table 5.37 INT0 INTi
Sep 28, 2009 All pages Preliminary Under development added

D version deleted
4
Table 1.3 (D) added
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2009. Renesas Technology Corp., All rights reserved. Printed in Japan.

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Issued by: Renesas Electronics Corporation (http://www.renesas.com)

REJ03B0265-0110 Rev.1.10 Sep 28, 2009

Specifications for R8C/36A Group (1)

DTC (Data Transfer Controller)

REJ03B0265-0110 Rev.1.10 Sep 28, 2009

Specifications for R8C/36A Group (2)

1 (shared with I2C bus)

1 (shared with SSU)

Operating Ambient Temperature

Hardware LIN: 1 (timer RA, UART0)

REJ03B0265-0110 Rev.1.10 Sep 28, 2009

Product List for R8C/36A Group

Current of Sep. 2009

(D): Under development

Part Number, Memory Size, and Package of R8C/36A Group

REJ03B0265-0110 Rev.1.10 Sep 28, 2009

Figure 1.2 shows a Block Diagram.

System clock generation

I2C bus or SSU

Low-speed on-chip oscillator

Voltage detection circuit

R8C CPU core

REJ03B0265-0110 Rev.1.10 Sep 28, 2009

Pin Assignment (Top View)

REJ03B0265-0110 Rev.1.10 Sep 28, 2009

Pin Name Information by Pin Number (1)

REJ03B0265-0110 Rev.1.10 Sep 28, 2009

Pin Name Information by Pin Number (2)

REJ03B0265-0110 Rev.1.10 Sep 28, 2009

Tables 1.6 and 1.7 list Pin Functions.

Pin Functions (1)

XCIN clock input

INT interrupt input

Connect this pin to VCC via a resistor.

Timer RA I/O pin.

Timer RD I/O pins.

External clock input pin.

Timer RF input pin.

Reception control output pin.

I2C mode clock I/O pin.

I2C mode data I/O pin.

REJ03B0265-0110 Rev.1.10 Sep 28, 2009

Pin Functions (2)

Analog input pins to A/D converter.

D/A converter output pins.

Comparator B analog voltage input pins.

I/O: Input and output

REJ03B0265-0110 Rev.1.10 Sep 28, 2009

Clock I/O pin.

CMOS I/O ports. Each port has an I/O select direction

2. Central Processing Unit (CPU)

Central Processing Unit (CPU)

R0H (high-order of R0) R0L (low-order of R0)

Data registers (1)

Address registers (1)

Interrupt table register

The 4 high order bits of INTB are INTBH and

User stack pointer

Interrupt stack pointer

Static base register

REJ03B0265-0110 Rev.1.10 Sep 28, 2009