Int. J. Power Electronics, Vol. 3, No.

1, 2011

A simple carrier-based neutral point potential

regulator for three-level diode clamped inverter
P.K. Chaturvedi* and Shailendra Jain
Department of Electrical Engineering,
MANIT, Bhopal (MP) 462051, India
E-mail: pc220774@gmail.com
E-mail: sjain68@gmail.com
*Corresponding author

Pramod Agrawal
Department of Electrical Engineering,
IIT, Roorkee 247667, India
E-mail: pramgfee@iitr.ernet.in
Abstract: Three-level diode clamped inverter is a proven technology nowadays
in medium and high power applications. Despite of its several advantages such
as harmonic reduction and achieving high voltage and high power capabilities
without series and parallel connections of switching devices, neutral point
potential (NPP) variation is the inherent problem with this topology. This paper
presents a simple NPP regulator based on addition of offset voltage to the
reference sinusoidal voltages. This not only regulates the NPP, but also reduces
the output voltage and current harmonics of the inverter. Simultaneously,
second harmonic get reduced which may otherwise produce torque pulsations,
harmonic currents and power losses. Simulation and experimental results have
been presented to validate the concept.
Keywords: DC link voltage; diode clamped inverter; neutral point potential
regulator; sinusoidal pulse width modulation; SPWM; three-level inverter;
offset voltage.
Reference to this paper should be made as follows: Chaturvedi, P.K., Jain, S.
and Agrawal, P. (2011) A simple carrier-based neutral point potential regulator
for three-level diode clamped inverter, Int. J. Power Electronics, Vol. 3,
No. 1, pp.125.
Biographical notes: P.K. Chaturvedi received his BE and ME from SATI,
Vidisha (MP), India, in 1996 and 2001 respectively. He has been with the
Department of Electrical Engineering as a Lecturer at SATI, Vidisha (MP),
India. Currently, he is working towards his PhD at MANIT, (Deemed
University), Bhopal, India. His field of interest is the multilevel inverters.
Shailendra Jain received his BE from SATI, Vidisha (MP), India, in 1990, his
ME from SGSITS, Indore, India, in 1994 and his PhD from the Indian Institute
of Technology, Roorkee, India, in 2003. He was a Postdoctorate Fellow at the
University of Western Ontario, Canada in 2007. Currently, he is an Assistant
Professor in the Department of Electrical Engineering at Maulana Azad
NIT (Deemed University), Bhopal, India. His fields of interest include power
electronics, electrical drives, active power filters, fuel cell technology and high
power factor converters.
Copyright 2011 Inderscience Enterprises Ltd.

P.K. Chaturvedi et al.

Pramod Agrawal received his BE, ME and PhD in Electrical Engineering
from the University of Roorkee, Roorkee, India, in 1983, 1985 and 1995
respectively. Currently, he is a Professor in the Electrical Engineering
Department of the Indian Institute of Technology, Roorkee, India. He was a
Postdoctoral Fellow at the University du Quebec, Montreal, QC, Canada,
from 1999 to 2000. He has published many papers in various national and
international journals and conferences. His fields of specialisation are electrical
machines, power electronics, microprocessor- and microcomputer-controlled
AC/DC drives, active power filters and high power factor converters.

Introduction

Three-level diode clamped or neutral point clamped inverter has become a widely
acceptable converter topology in various industrial applications such as static var
compensation, rolling mills, marine and traction drives, AC power supplies, etc. As
compared to two-level inverter, this topology reduces the current and voltage harmonics
and also reduces the stress on devices for the same load power and voltage ratings. If
employed in drives, it reduces the common mode voltages resulting in a stress reduction
on motor bearings and winding insulation. One of the major inherent problems with the
neutral point clamped inverter is the unbalanced voltages across DC link capacitors.
Ideally, the voltages of two series connected DC link capacitors must be half of the DC
link voltage, i.e., the neutral point voltage should be tightly regulated or to be set to
zero. Unbalanced DC link voltage results in the oscillations in neutral point voltage
and requires increased DC bus capacitance. It also distorts the inverter output voltage
(Marchesoni et al., 2005; Bendre et al., 2006; Tallam et al., 2004; Song et al., 2003).
The choice of the modulation scheme plays an important role in neutral point voltage
control. Every scheme tries to turn on and off the appropriate device to charge and
discharge the capacitors such that two DC capacitor voltages are balanced with a
minimum ripple component. Several publications have discussed the solutions to this
problem (Bendre et al., 2006; Tallam et al., 2004; Song et al., 2003; Boroyevich et al.,
2002; Newton and Summer, 1997; Bendre and Venkataramanan, 2006). These solutions
may be classified broadly into two categories. The first category is based upon space
vector modulation (SVM) in which redundant switching states of the converter is used to
balance the capacitor voltages. However, the relationship between neutral point voltage
and inverter switching states is very complicated so it is not easy to balance the neutral
point voltage exactly based on redundant switching states selection (Song et al., 2003).
While in the second category, a zero sequence voltage is added to the modulating
signal, using carrier-based PWM scheme. In some schemes, knowledge of load power
factor angle or the direction of instantaneous power flow is required which is difficult
to implement in transient conditions (Song et al., 2003). Other schemes require
measurement of both DC voltages and load currents (Boroyevich et al., 2002; Newton
and Summer, 1997; Bendre et al., 2006). The concept of using analytical solution of zero
sequence voltages for neutral point voltage control is discussed in Song et al. (2003) and
Boroyevich et al. (2002, 2003). Because there are a large number of expressions for zero
sequence voltage for many sectors, the implementation may be cumbersome. There is a
close relationship between zero sequence voltage and switching states of SVM; injection
of zero sequence voltage schemes can be applied to both SVM and carrier-based

A simple carrier-based neutral point potential regulator

modulation (Newton and Summer, 1997). Li et al. (2007) reported sinusoidal pulse width
modulation (SPWM) technique with carrier disposed vertically to control neutral point
potential (NPP).
This paper presents the design and implementation of a simple NPP regulator based
upon addition of offset voltage to the reference voltages. The offset voltage required
for this method is calculated using the proposed method. This requires the difference
between two DC link capacitor voltages for neutral point control implementation without
measuring the power factor angle. The basic idea behind this concept is to control the
charging and discharging of two capacitors by suitably modifying the modulating signal.
Furthermore, a real-time capacitor voltage balancing algorithm is proposed which is
easier to be implemented without the need of load power factor angle. The simulated
and experimental results of the proposed scheme are presented to show its effectiveness.
Experimental implementation has been performed using dSPACE DS 1104.

Circuit configuration and control signal generation

The basic circuit topology of the three-phase diode clamped three-level inverter (neutral
point clamped) is shown in Figure 1. The circuit consists of two DC link capacitors,
12 power switches and six clamping diodes. The middle point of the DC bus capacitors is
known as neutral point 0. The main feature of this topology is the clamping diodes
which clamp the switch voltage to half of the DC bus voltage, reducing the voltage stress
of the switching devices. The output voltage has three different states: (+, 0, ) and
corresponding output phase voltages are (+Vdc/2, 0 and Vdc/2) where Vdc/2 is the voltage
across each capacitor. Switching states to synthesise three-level output voltage for phase
a are defined in Table 1. Because each phase can generate three values of voltage, total
number of switching states obtained is 33 = 27. Figure 2 explains the principle of pulse
generation for each switch. Modulating signals Va, Vb and Vc are compared with
triangular carrier signals at every instant for obtaining the control pulses for each device
as shown in Figure 2(a).
Figure 1

Structure of three-phase, three-level diode clamped inverter

4
Figure 2

P.K. Chaturvedi et al.

Generation of pulses for three-level diode clamped inverter, (a) carrier and modulating
waveforms (b) control pulses for the upper two switches in each phase leg

(a)

(b)
Table 1

Switching states for phase a of three-level diode clamped inverter

Sa2

Sa1

Sa2

Switching states

Output phase voltage (Va0)

+Vdc/2

Vdc/2

Sa1

For example, comparison of modulating wave, Va (or Vb or Vc), of phase a (or b or

c), with carrier 1 produces the control signal Sa1 (or Sb1 or Sc1) and that with carrier 2
produces the control signal Sa2 (or Sb2 or Sc2). Control pulses for switches Sa1, Sa2, Sb1,
Sb2, Sc1 and Sc2 are shown in Figure 2(b). Pulses for switches Sa1', Sa2', Sb1', Sb2', Sc1'
and Sc2' are complementary to the pulses Sa1, Sa2, Sb1, Sb2, Sc1 and Sc2 respectively.
Comparison of modulating wave with carrier wave is explained in Figure 3 for phase a.

A simple carrier-based neutral point potential regulator

Figure 3

Generation of pulses for three-level diode clamped inverter and phase voltage
(see online version for colours)

Concept of NPP variation

The output phase voltage of three-level diode clamped inverter contains three states as
given in Table 1. Neutral point is connected to the capacitor midpoint for the switching
state 0. During this period, current is drawn from neutral point. It will cause one
capacitor to charge while other to discharge. Average neutral point current is to be
maintained zero and NPP (difference between voltages across two capacitors) is constant
under normal operating conditions over a modulating period. Under some transient
conditions or load imbalance, the average neutral point current may have non-zero value
causing NPP variation. The main reason for NPP variation is the unequal charge
distribution among two DC link capacitors. This unequal charge distribution may be due
to unequal extraction of current from two capacitors. The charging and discharging of
two capacitors are shown in Figures 4 and 5 for switching states (+00) and (0--). These
switching states for phase a are defined in Table 1. Arrows show the flow of current
from capacitor midpoint.

P.K. Chaturvedi et al.

Figure 4

Current flow path in the switching state of (+00)

Figure 5

Current flow path in the switching state of (0--)

From these figures, unequal charging and discharging of capacitor current is clearly
shown for identical line-to-line voltages across load. Therefore, it may be concluded that
switching of different devices results in different capacitor current profile affecting the
NPP and also neutral point current as shown in Figure 12 in Section 4. Voltages appeared
across each switching device differ in both the cases and some devices may be
overstressed. Neutral current flows into and out of neutral point or midpoint of DC link in
these two states as shown in Figures 4 and 5 respectively. As a result, output line voltages
will contain lower order harmonic contents and significant second harmonics as given in
Ogasawara et al. (1993).

A simple carrier-based neutral point potential regulator

NPP control strategy

A number of papers are available on NPP control techniques. Among these techniques,
SPWM-based technique is simpler and easier to understand with the equivalent
performance as in the case of SVM. Celanovic et al. (2000) and Liu et al. (1991)
presented the method of NPP control with space vector PWM.Basically, the NPP is the
difference between the upper and lower DC bus capacitor voltages or voltage at the
midpoint of two capacitors. It should be ideally zero otherwise large voltage ripples will
be present in DC input voltage to the diode clamped inverter resulting in an increased
lower order harmonics in the output voltage. The basic concept of NPP control is the
charge balance control in the neutral point. Some authors have proposed the method of
adding DC offset voltage to the sinusoidal modulating signal which transfers the amount
of power flow from one capacitor to other. Shifting of DC offset voltage, upper or lower
side, will result in controlled charging and discharging of the upper and lower capacitors.
To implement this technique, only the direction of power flow through neutral point is
required. Depending upon this power flow direction, appropriate amount of DC offset is
calculated and added to the sinusoidal modulating signal to compensate for any
imbalance between two capacitor voltages. But if the sinusoidal signal is too large in
magnitude, then this method has no significant effect on NPP control. In such cases,
ripple current in DC link depends upon load impedance and load power factor. In the
present work, the above concept is used with only difference that in place of adding a
constant DC offset voltage, a variable offset voltage is to be added which will effectively
compensate the charge balancing of two capacitors.
Figure 6 shows the control block diagram of NPP regulator. It consists of two DC
voltage sensors (Vdc1 and Vdc2) to calculate the NPP (Vnpp) which is the difference
between Vdc1 and Vdc2.
Vnpp = Vdc1 Vdc2
Figure 6

Control block diagram of NPP regulator

(1)

P.K. Chaturvedi et al.

This difference is compared with desired value of neutral point voltage which is zero for
complete control. Error in neutral point voltage is then processed through PI regulator.
After processing through PI regulator, a common mode offset voltage (Voffset) is
generated which is added to the actual three-phase reference sinusoidal voltages.
Voffset =

{( Vdc1 Vdc2 ) Vnpp* } K p + Ki / s

(2)

For successful implementation of NPP control, average NP current should be controlled

to be zero. Parameters of PI controller are found by first keeping Ki equal to zero and
adjusting the proportional gain Kp to obtain DC voltage ripples less than 3%, observing
overshoot and settling times and average neutral point current equal to zero. Then, Ki is
adjusted to optimise the values of these PI parameters. The PI parameters obtained
through trial and error method are Kp = 0.1, Ki = 0.01. The controller bandwidth can be
increased by increasing the proportional gain of PI controller, but at the cost of degrading
the harmonic profile of the inverter output voltage.
Figure 7

Actual modulating signal, offset voltage and modified modulating signal with regulator
(see online version for colours)

New reference modulating signals are:

Vabc* = Vabc Voffset

(3)

where Vabc is the actual modulating signal. Actual reference voltages, offset voltages
generated and new reference voltage waves are shown in Figure 7. These new threephase reference voltages are compared with two triangular carrier waves at higher carrier
frequency to generate control signals for inverter switches as shown in Figure 8. A
comparison can be made between Figures 2 and 8 regarding the pulse generation without
and with regulator. Addition of offset voltage results in increased switching frequency of
inverter resulting in improved harmonic profile. The main principle behind this control
concept is that if there is a variation in NPP detected by the controller, it will add offset

A simple carrier-based neutral point potential regulator

voltage to the reference voltage wave. This offset voltage results in a current to flow
through neutral point to redistribute the charge among two capacitors to balance the
voltages across two capacitors.
Figure 8

Generation of control pulses with regulator, (a) comparison of one-phase reference

voltage with carrier wave (b) control pulses for the upper two switches for each phase
leg (see online version for colours)

(a)

(b)

Simulation results

The proposed control strategy has been simulated in MATLAB and Simulink
environment using SimPowerSystem toolbox. Simulation parameters are given in
Table 2.

10

P.K. Chaturvedi et al.

Table 2

Simulation parameters

DC link voltage

600 volts

Load line-line voltage

415 volts

Output frequency

50 Hz

Load power

5.6 kW

Load power factor

0.89

Load resistance

15

Load inductance

24.2 mH

DC link capacitor

2,200 F

Switching frequency

2 kHz

Figures 9 and 10 show the inverter line voltage and load current with and without
regulator. As observed, fundamental value is increased in both voltage and current.
Table 3 gives the simulation performance of the regulator which clearly indicates
reduction in average NPP from 3.163 volts to almost zero volts for a DC link voltage
of 600 volts. Figure 11 shows the currents through four switching devices of leg a
without and with regulator. The effect of the regulator on charging currents is clearly
seen in Figure 11(b). Capacitor charging and discharging current profiles are shown in
Figure 12. The difference in positive and negative cycles of currents with the same peak
amplitudes results in redistribution of charges among two capacitors for voltage
balancing. Figure 13 shows Vdc1 and Vdc2, NPP, line voltage (Vab), line current (ia) and
capacitor currents ic1 and ic2 without and with regulator. As seen from Figure 13(b), NPP
is almost zero and contains very small variations. Also in line voltage waveforms, the
steps become more symmetrical due to voltage balancing, although small amount of low
order harmonics (fifth and seventh) are injected which may be suppressed by using
suitable passive filters.
Table 3

Simulation performance

Parameters
Fundamental value of Van
Fundamental value of Vab

Without regulator

With regulator

300.3 volts

313.8 volts

520 volts

541.4 volts

Fundamental value of ia

17.85 amps

18.78 amps

RMS load line voltage (Vab)

389.9 volts

414.5 volts

RMS load current (ia)

12.63 amps

13.54 amps

Average NPP

3.163 volts

0.0001 volts

RMS NPP

0.08 volts

0.02 volts

10.71 amps

8.556 amps

THD in Van

39.31%

34.15%

THD in inverter Vab

20.46%

11.36%

THD in ia

1.27%

3.49%

RMS neutral point current

A simple carrier-based neutral point potential regulator

Figure 9

11

Line voltage (Vab) and its harmonic spectrum, (a) without regulator (b) with regulator

(a)

(b)

Figure 10 Load current (ia) and its harmonic spectrum, (a) without regulator (b) with regulator

(a)

(b)

The performance of the regulator has been checked by creating large imbalance (around
15%, Vdc1 = 30.8 volts and Vdc2 = 65.9 volts). The regulator also works well under this
condition. Table 5 in the paper gives the various conditions of DC link voltages under
unbalanced and balanced capacitor voltages. PI controller will not be saturated up to this
limit experimentally. It only saturates if the two DC link capacitor voltages are made
highly unbalanced (above 60%, i.e., Vdc1 20 volts and Vdc2 80 volts). Beyond this
range, the NPP cannot be controlled and it will never be zero.

12

P.K. Chaturvedi et al.

Figure 11 Currents through switching devices of phase leg a, (a) without regulator
(b) with regulator (see online version for colours)

(a)

(b)

Figure 12 Capacitor currents profile, (a) without regulator (b) with regulator (see online version
for colours)

(a)

(b)

Figure 13 DC link voltages (Vdc1 and Vdc2), NPP, load voltage, load current and capacitor
currents, (a) without regulator (b) with regulator (see online version for colours)

(a)

(b)

A simple carrier-based neutral point potential regulator

13

Figure 14 gives two DC link voltages and NPP without and with regulator, clearly
indicating the effect of the regulator. Without regulator, the average NPP is positive
non-zero value (3.163 volts) with a DC component of 2.9 volts, and upon the application
of the regulator, the average NPP and DC component become zero with reduced
NPP variations as shown in this figure. Transient response of controller is studied by
increase/decrease in load at 0.2 and 0.4 sec. NPP is seen to be almost unchanged as seen
in Figure 15.
Figure 14 DC link voltages (Vdc1 and Vdc2) and NPP, (a) without regulator (b) with regulator

(a)

(b)

Figure 15 DC voltages, NPP, Vab, ia and capacitor currents with regulator when load is doubled at
0.2 sec and restored at 0.4 sec (see online version for colours)

During load changing, NPP regulator works well and NPP is maintained at the same level
as before load changing. From Table 3, it is clear that the average NPP is zero. Current ia
is slightly distorted when using the regulator due to the redistribution of charges between

14

P.K. Chaturvedi et al.

the capacitors. However, its THD is still within IEEE 519 standard limits of 5% with
increased fundamental value as can be observed from Figure 10 and Table 3. Due to the
redistribution of charges and balancing of DC link, the ripple voltage in DC link voltage
is reduced to 4.7% for a capacitor of 2,200 F and 2.8% for a capacitor of 4,000 F. All
the above results have been obtained without any filter. Performance can be further
improved by using suitable passive filter.

Experimental results

A prototype of three-phase, three-level, diode clamped inverter is developed for

experimental verification. Figure 16 shows the experimental schematic of NPP regulator.
The parameters selected for experimental study are shown in Table 4. Control technique
is implemented using dSPACE DS 1104 DSP board which is based on digital signal
processor board TMS320F240.
Figure 16 Experimental set-up for NPP regulator (see online version for colours)

Table 4

Experimental parameters

DC link voltage

100 volts

Load resistance

45

Load inductance

5.2 mH

DC link capacitor

2,200 F

Switching frequency

2 kHz

A simple carrier-based neutral point potential regulator

15

As shown in Figure 16, two DC voltages are first sensed using ISO 122 and given to
DS 1104 board where NPP (Vnp) is derived. After processing through summer 1 and
PI regulator, offset voltage Voffset is obtained. The modified reference modulating
signals, Vabc*, are obtained after processing through summer 2. These modified
modulating signals are then compared with two triangular carrier waves to generate
control signals to be given to three-level, three-phase, diode clamped inverter module.
Figure 17 shows the actual modulating sinusoidal signals, offset voltage, modified
modulating signals and carrier signals in real-time on dSPACE control desk platform.
Figure 17 Control desk layouts, (a) actual modulating sinusoidal signals (b) offset voltage
to be added (c) modified modulating signals (d) carrier signals (see online version
for colours)
(a)

Va Vb Vc

(b)

Va* Vb* Vc*

(c)

(d)

Voffset

Initially, DC link voltage is kept 100 volts with equal distribution among two
DC capacitors. An unbalance in two capacitor voltages (Vdc1 = 30.8 volts and
Vdc2 = 65.9 volts) is created to show the effect of variation in DC link voltage without
regulator as shown in Figure 18(a). Waveforms of line voltages, frequency spectrum of
line voltage (Vab), DC link voltages, and NPP without and with regulator are shown in
Figures 18(a) and 18(b) respectively.
Significant second harmonics exist in inverter output voltage due to unbalanced
DC link condition with reduced fundamental component and higher THD. Proposed
NPP regulator effectively balances the voltages across two capacitors (49.3 volts and
49.1 volts) resulting in improved line voltage with increased fundamental voltage
(from 41.6 volts to 59.2 volts) and reduced THD (from 38% to 22.8%) with almost zero
NPP as shown in Figure 18(b). Figure 19 shows the phase voltages and phase currents for
loaded inverter under unbalanced and balanced conditions. It is clear from this figure that
due to unbalanced loading, positive and negative cycles are not equal and have a DC
component, but after balancing, these become almost equal.
Three-phase load voltages and currents are shown in Figure 20 for unbalanced and
balanced DC link. Voltages and currents become very near to sinusoidal under balanced
condition. Capacitor voltages (Vdc1, Vdc2) and NPP are shown in Figure 21. Under this

16

P.K. Chaturvedi et al.

condition, frequency spectrum of load voltage and load current under unbalanced and
balanced conditions for one line (Vab and ia) are shown in Figures 22 and 23 respectively.
THD in both voltages and currents are below 5% under balanced DC link voltages
obtained employing NPP regulator. Second harmonics due to unbalance in DC link
voltages does not exist under balanced DC link condition which otherwise results in
torque pulsations, harmonic currents and power losses in AC drives applications.

volts 10

Figure 18 Line voltages, frequency spectrum of line voltage Vab and DC link voltages
(control desk layouts), (a) without regulator at no-load (b) with regulator at no-load
(see online version for colours)

time (sec)

(a)

A simple carrier-based neutral point potential regulator

17

volts 10

Figure 18 Line voltages, frequency spectrum of line voltage Vab and DC link voltages (control
desk layouts), (a) without regulator at no-load (b) with regulator at no-load (continued)
(see online version for colours)

time (sec)

(b)

18

P.K. Chaturvedi et al.

Figure 19 Inverter phase voltages and currents, (a) unbalanced DC link condition (b) balanced DC
link condition

(a)

(b)
Notes: CH1, CH3, CH5: phase voltages Van, Vbn, Vcn (scale: 20 volts/div)
CH4, CH6, CH2: phase currents ia, ib, ic (scale: 5 amps/div)

A simple carrier-based neutral point potential regulator

19

Figure 20 Line-to-line voltages and currents, (a) unbalanced DC link condition for inductive load
(b) balanced DC link condition for inductive load

(a)

(b)
Notes: CH1, CH3, CH5: phase voltages Van, Vbn, Vcn (scale: 20 volts/div)
CH4, CH6, CH2: phase currents ia, ib, ic (scale: 5 amps/div)

20

P.K. Chaturvedi et al.

Figure 21 Layouts of control desk of dSPACE DS 1104, (a) unbalanced DC link conditions at
no-load (b) balanced DC link conditions at no-load (see online version for colours)

(a)

(b)

Figure 22 Harmonic spectrums of (a) load voltage, Vab, and (b) load current, ia, under loaded
inverter and unbalanced DC link voltages

(a)

(b)

Figure 23 Harmonic spectrums of (a) load voltage, Vab, and (b) load current, ia, under loaded
inverter and balanced DC link

(a)

(b)

A simple carrier-based neutral point potential regulator

21

Transient response of NPP regulator is observed by switching response of inverter

under no-load and loading conditions as shown in Figures 24 and 25 respectively.
Capacitor voltages become balanced on the application of NPP regulator within 200 ms.
Upon the application of the load, capacitor voltages become unequal (Vdc1 = 42.2 volts
and Vdc2 = 51.9 volts) due to unbalanced loading which becomes equal after the
application of the regulator as shown in Figure 25. As observed in Figure 26, initially,
DC link is balanced which becomes unbalanced due to intentional load unbalancing.
Upon the application of NPP regulator, DC link is again balanced. These results are
comparable with simulation results shown in Figure 14.
Another way of presentation of DC link voltages and NPP is given in Figure 27,
which is showing that two capacitor voltages were balanced initially and becomes
unbalanced by adding a resistor in parallel with one capacitor. After the NPP regulator is
activated, capacitor voltages are becoming balanced and their difference (NPP) is almost
zero as shown in Figure 27(b). Table 5 gives the values of two capacitor voltages for
different circuit conditions.
Figure 24 Inverter on no-load, unbalanced to balanced condition

22

P.K. Chaturvedi et al.

Figure 25 Inverter on-load, initially unbalanced and after some time balanced with the application
of the regulator

Figure 26 DC link voltages from balanced to unbalanced and unbalanced to balanced

A simple carrier-based neutral point potential regulator

Figure 27 Capacitor voltage waveforms, (a) balanced to unbalanced mode (b) unbalanced to
balanced mode

Vdc1
Vdc2

(a)

Vdc1
Vdc2

(b)
Note: CH1: Vdc1, 20 volts/div, CH3: Vdc2, 20 volts/div, 100 ms/div

23

24

P.K. Chaturvedi et al.

Table 5

DC voltages for different circuit conditions

Circuit conditions
No-load

On-load

Vdc1 (volts)

Vdc2 (volts)

Vdc (volts)

50

50

100

Without regulator

30.8

65.9

96.7

With regulator

49.3

49.1

98.4

Without regulator

42.2

51.9

94.1

With regulator

46.6

46.6

93.2

Inverter OFF

Conclusions

A simple NPP regulator using multiple carriers is developed for a three-level diode
clamped inverter, based on addition of variable offset voltage to the modulating signal.
It does not need complex calculations involved in SVM technique. Simulation and
experimental results have been presented to validate the effectiveness of the regulator.
The regulator not only balances the DC link voltages, but also maintains the harmonic
contents in load voltage and load current well within the limits imposed by IEEE 519
standard. Various operating conditions of load and DC link voltage are investigated. The
average value of NPP is reduced to zero using the regulator.

References
Bendre, A. and Venkataramanan, G. (2006) Neutral current ripple minimization in a three-level
rectifier, IEEE Trans. on Industry Applications, Vol. 42, No. 2, pp.582590.
Bendre, A., Venkataramanan, G., Srinivasan, V. and Rosene, D. (2006) Modeling and design of a
neutral point voltage regulator for a three level diode clamped inverter using multiple carrier
modulation, IEEE Trans. on Industrial Electronics, Vol. 532, No. 3, pp.718726.
Boroyevich, D., Pou, J. and Pindado, R. (2002) New feed-forward space vector PWM method to
obtain balanced AC voltages in a three level neutral point clamped converter, IEEE Trans. on
Industrial Electronics, Vol. 49, No. 5, pp.10261034.
Boroyevich, D., Pou, J. and Pindado, R. (2003) Effects of imbalanced and nonlinear loads on the
voltage balance of a neutral point clamped inverter, Conference Record of the 2003 Industry
Applications Annual Meetings.
Celanovic, N. and Boroyevich, D. (2000) A comprehensive study of neutral point voltage
balancing problem in three-level neutral point clamped voltage source PWM inverters, IEEE
Trans. on Power Electronics, Vol. 15, pp.242249.
Li, J. et al. (2007) A novel carrier based PWM method for 3-level NPC inverter utilizing control
freedom degree, IEEE NPSC Conf. Rec., pp.18991904.
Liu, H.L., Choi, N.S. and Cho, G.H. (1991) DSP based space vector PWM for three-level inverter
with DC link voltage balancing, IEEE IECON Conf. Rec., Vol. 1, pp.197203.
Marchesoni, M., Segarich, P. and Soressi, E. (2005) A new control strategy for neutral point
clamped active rectifiers, IEEE Trans. on Industrial Electronics, Vol. 52, No. 2, pp.462470.
Newton, C. and Summer, M. (1997) Neutral point control for multilevel inverters: theory, design
and operational limitations, Proc. of IEEE IAS Annual Meeting, New Orleans, Louisiana.
Ogasawara, S. and Akagi, H. (1993) Analysis of variation of neutral point potential in neutral
point clamped voltage source PWM inverter, Proc. IEEE Industrial Appl. Soc. Conf. Rec.,
pp.965970.

A simple carrier-based neutral point potential regulator

25

Song, Q., Liu, W., Yu, Q., Xie, X. and Wang, Z. (2003) A neutral point potential balancing
algorithm for three level NPC inverters using analytically injected zero sequence voltage,
Proc. of Applied Power Electronics Conferences, pp.228233.
Tallam, R.M., Naik, R. and Nondahl, T. (2004) A carrier based PWM scheme for neutral point
voltage balancing in three level inverters, Proc. of Applied Power Electronics Conferences,
pp.16751680.