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Top Ten: Common Analog IC Layout Tips-and-Tricks

2011/04/28 JJWIKNER CAD, TOP TEN 10 COMMENTS
A er some Easter holidays and other resting period (Im on paternal leave and rushing a er three
children).
This top ten list can probably be super-duper long there are certainly quite a lot of tips-and-tricks for
analog IC layout. I picked ten tips o-the-shelf and presented them in todays list. Any (well, almost any
) of your comments are of course very appreciated.
The list is not sorted.

#10: Do not lay the transistors out as they are placed in the schematics
Quite o en you stare a li le bit too much on the schematics when you do your layout. A classical
example is a cascade of dierential ampliers. In the schematics you typically have your dierential
pair, active load, etc., in each sub-amplier. You lay out according to the schematics and you put your
input terminals to the le and your output terminals to the right. Then you start hooking the cascaded
stages up and there it starts to get messed up. You start to cross wires back-and-forth to t the input
to output terminals. It is much be er to rotate the amplier 90 degrees and then put the input
terminals to the le and outputs to the right. Then you can more or less put the stages adjacent and
automatically hook up.
There are more things like this spend some more time on what you actually have in the schematics
and do not follow it too much in detail (from a placement point of view).
#9: Matching
Matching is very important we all know that. Any small variations in transistor sizes might give you
large variations in terms of voltage or current dependent on gain and architecture. So, essentially, this
bullet is stating the obvious do not forget to match your circuit. The question though is how should
you match? We have those well-known interdigitized and common-centroid approaches, where one
interleaves in one or two dimensions in order to spread out the statistical variation to more than one
transistor.
However, what about these things:
avoid metal on top of the gate
orient all transistors (that should be matched) such that the current ows in the same physical
direction
proximity eects, i.e., the edges should also match
shallow trench isolation, i.e., do not put the combined active area edges to far from the gates (that

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is, do not place the transistors in too large islands)

and much, much more.
#8: Add rubberband options and spares
Unless you do RAMs or other very regular structures that need to be laid out very dense in order to
reach high density, you should denitely think of rubberband options and spares. There are three
aspects of this:
You need to do a metal mask change i.e., a bug is detected in your design once chip is back in
bench and you need to hook up an additional inverter or so somewhere. To save money, you just
want to change the (upper) metal layers on your wafer. However, if the spare inverter is not there
to begin with you need to pay quite a few extra k$.
Five hours before tape-out you realize you want some more driving capability in one of your
ampliers, just a li le bit of extra current. Unfortunately, since you have done a dense design,
adding that extra transistors forces you to do a substantial redesign of your layout.
There is a misunderstanding between PNR/RTL and analog macro and you need to do some digital
encoding for some control wires. Running an ECO on the digital core takes too much time and you
have to do a manual, digital place-and-route inside the analog macro.
For all of these cases it would be very nice to have extra circuitry already at hand in your layout.
Remember that normally you are not really doing the most dense layouts in the market. Especially
for the rst test runs this is not the case, area and cost optimization follows later on. First, it is about
time-to-market, and to be able to do quick changes to your design is very important. Layout can be
quite tedious, even if you have an experienced layout engineer at hand, there will be communication
required that takes time.
So add extra transistors/resistors/capacitors, extra inverters/nand/nor/gates, why not even an extra
amplier? You can even make them programmable (remember one of the other lists) such that you can
add/increase through so ware.
#7: Electromigration
Modern consumer-market temperature specications actually stretches beyond 125 degrees. It could
very well be 150 degrees. The tough requirements on metal wire widths for these temperatures get
even more tougher. In some cases, the design kit is not really characterized at these frequencies, but
instead data relies on linear extrapolation of other data points.
Notice also that you might want to run some simulations and bench tests outside the spec points in
order to characterize the circuit be er. Thereby, why not design your circuit to meet also those
external corners.
So, in short do not forget to make your wires extra-wide.
#6: Parasitic capacitances
Of course, some of these bullets would get explained/resolved by running proper physical verication
and post-extract simulations. However, quite o en you do become a bit sloppy, you do some minor
checks rst on your sub levels and for the upper levels the extracted netlists do become quite big and
time-consuming to simulate.
So, main two tips:
avoid routing wires on top of high-gain nodes. This might give you a strong capacitive coupling
that could have signicant impact on performance
remember that the capacitive side-wall coupling between drain and source could become quite
large if you stack many vias on top of eachother in order to reach a higher level metal.
#5: Metal ll and other density checks
More or less to guarantee high yield one wants a certain density in certain regions on the chip. These

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regions are mostly windows that are moved around the chip and the physical verication (pv) tool
checks for density in that window. This could have the nasty property that once you are happy with
your density checks in your local sub block, it might turn out that you have too high (or too low)
density once you instantiate your block in the top level design. Annoying, but mostly solveable by
changing the pv deck to have ner stepping between the windows being swept over your design. It
could take slightly more time to run, but denitely quicker than running on the top level.
The tip here is to not be afraid to add ll structures in your subcircuits (as long as you know that you
will not need that space for routing or so). This will further improve matching. Assume, for example,
that you have a time-interleaved ADC where all parallel channels should be matched properly. Here,
you want to add ll structures for each channel rather than adding them on the top level ADC.
#4: Floorplanning do not miss the whole picture
This is of course also well-known, but yet the problem with oorplanning is that mostly not all
people are involved in the oorplanning process. This makes sense too of course, but eventhough you
are only doing one small block in the overall design, maintain a good view of the overall system. How
can your block be done such that the overall design benets from that? For example, by rotating some
components in your block you will help the top-level routing, avoid bends, etc. Remember that the
top-level responsible, in case (s)he is stressed, (s)he will mainly focus on your ports and hook them up
according to instructions. Too o en, Ive seen, for example, bias current wires being routed
back-and-forth since the overall picture has not been considered. This causes extra resistance and
noise.
#3: Think digital
The canyon between analog and digital design seems to become even wider the layout tools are
fundamentally dierent, the design style is fundamentally dierent, the simulators dierent, etc., etc.
So no wonder it is so dicult to interface between them
My message here though is to think digital, at least from a oorplanning and perimeter point-of-view:
Route your wires on digital routing grid
Use same widths for supply wires, and signals on the boundary that needs to interact with digital
core
Make your design as regular as possible, let your (wild) target be to place-and-route your analog
design using a digital back-end tool (!)
Jump back-and-forth between the two dierent worlds to mutually understand the complexities at
both ends. How can an analog macro be inserted (and properly veried) in the digital PNR? How
can a digital macro be inserted (and properly veried) in the analog ow?
#2: Strengthen metal, etc.
You have a couple of dierent bullets (#5 and #7) that motivates this one and maybe one that
contradicts (#6). Anyway, the idea here is that if you have a layout in which you have plenty of routing
that needs to be strengthened, say reducing resistance or so. Spend some hours to develop a script
that enables you to draw the interconnections in say metal 1. Then in cadence virtuoso, at least, you
have a functionality that enables you to do layer manipulations. You could for example create a metal 3
layer which is an xor between metal 1 and metal 2. Using this approach, you can automatically
generate support layers to your existing metal layers. Further on, you can also program the tool to nd
where two metals overlap and automatically insert vias in that region.
#1: Re-use and re-congurability
We slightly touched upon this bullet earlier (rubberband #8). The idea here though is for the wider
scope: how can your circuit be re-used in dierent environments/designs/chips. Still, as outlined in
bullet #4, we must not loose the whole picture, but yet we can probably layout one circuit to be reused
by adding some redundancy. Normally, the area penalty is not that high and the design time you save
could be quite signicant. Chip area can be expensive, but so is lost hours to the market.

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So, same message as I have been mentioning before: think porting. How can you move your design
from one process to another in the shortest possible time? There are some so ware tools out there to
simplify life for you and why not spend some time investigating them?
Any other ideas?

10 thoughts on Top Ten: Common Analog IC

Layout Tips-and-Tricks
Magnus the Magnicent
2011/04/28 at 19:29
Looking through my rose tinted glasses-o-so ware; what about designing for ease of verication?
Perhaps somehow making intermediate signals available for probing and verication?
By routing them on the top metal layer or an unbonded pad or something?
(Warning: I may be too damaged from so ware exposure to comment on these things)
Reply
jjwikner
2011/04/28 at 20:06
True you are right thats a very good (probe) point. Design for testability is indeed crucial for
debugging.
Not too bad for being a so ware guy!
Reply
pakEMC
2012/03/11 at 04:41
Is there is any good document or book that you can refer here for a person who wants to perform
layout for his circuit for the rst time. Secondly, in digital layout I have seen that each gate is designed
with a large VDD and GND metal regions (at the top and the bo om respectively) and the rest of the
circuit in between. Should we follow the same method for analog circuits such as OTA,Opamps, lters
etc?
Reply
jjwikner
2012/03/11 at 06:35
Nearly all analog text books contain a couple of chapters with analog design tips-and-tricks and so
called best practices. I have never come across a good book, and I have now and then picked up
some tips from the Internet. For example, h p://www.eda-utilities.com
/CMOS_Transistor_Layout_KungFu.pdf, and many more. Google for best practices, etc.
In short you should guarantee good supply and bulk connections to your circuit. That could mean
you end up with a design as you describe. VDD on top and VSS on ground. However, the
digital standard cell is typically implemented to be bu ed to the next cell, and hence for simplicity

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this is the case. In the analog world, you could think several rails and possibly violate the regularity
a bit. For higher-level integration though, it makes sense to follow some guidelines, such that your
block can easily be hooked up on next level.
For me the tricky things with analog layout is the
mismatch orientation, dummies, etc.
current density considerations in wires for high currents
ESD
isolation, several PSUBs, Taps, etc. require guard rings that occupy space
modularity: analog design typically requires redesign and you want to minimize your layout
eorts. How do you cope with this?
The best book is Practice, practice, practice, by your self
Reply
AfridiTech
2012/03/11 at 10:30
Thanks for the reply jjwikner.
Actually i am implementing a CT 2nd order Delta-Sigma modulator , now the issue is that I have
a lot of mixed signal components, so I cant simply follow the digital design guidelines that is
bu ing a cell to another cell. So the major confusion I am having right now is that should I
design layout cells based on a single function or based on digital or analog functionality. for
example I have a latched comparator (single bit quantizer), which contains a comparator circuit
with a regenerative circuit, and then NAND gates for latched output. So should I design all of
this together in a single cell, or should I treat NAND gate and the comparator completely
separate and then connect them at a higher level.
I hope my question is giving some sense.
jjwikner
2012/03/11 at 11:40
Hi again,
I guess it also depends on the supplies you have at hand. You probably have a low-voltage
analog supply and a low-voltage digital supply at hand. Connecting the analog low-voltage to
the spiky NAND/regen latch could be a bit hazardous. I would suggest thinking three segments:
analog comparator in one island, than the regenerative latch in another connecting to a noisy
analog supply in one island and then the digital part/island coming in. In any case, while
integrating your converter on the top level, you want a solid digital interface, typically inserting
a levelshi er+latch at the boundary between analog and digital.
In general, as mentioned in some of the bullets above, you should think a couple of extra times
on how the signal ow is through your circuit. For example the dierential ampliers, quite
o en, by rotating them 90 degrees solves a lot of problems (this sounds a bit strange, but a bit
o en one startes too much at the schematics when doing the layout.
And dont forget the guard rings as well as isolation between the dierent supplies!
Vikas
2012/08/10 at 07:28
Hi jjwikner,

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Good article to summarize the key points in mixed-signal IC layout.

I have a question regarding current direction matching. You say that the physical current direction
through matched devices should be same, but if the MOS has many ngers and is laid out as
S-D-S-D-S, i.e alternate source and drain, the current direction is inherently opposite when owing
from source to drain. Do you mean this because of mask misalignment ? in which case the
conguration S-D will have dierent characteristics than D-S.
Thanks,
Vikas
Reply
jjwikner
2012/08/10 at 13:00
Dear Vikas,
thanks for your comment. Yes, you are right that the sub-transistors (say M1.m1 M1.m2, M1.m3,
etc.) of each ngered transistor will see dierent directions.
However, remember that you are matching the overall M1 with an M2. If you maintain the same
conguration for M2 as for M1 (summing up all sub-transistors) you eectively match them, even
though M1.m1 and M1.m2 are not matched.
Sigma dierence between M1 and M2 decreases, but potentially not to its minimum value.
Thanks
Reply

2013/07/16 at 12:31
In my opinion you should add a picture from each part of text.
Thanks,
Vadim
Reply
jjwikner
2013/07/16 at 15:19
Thanks for the input Vadim. I have this on my to-do-list, unfortunately I just need to nd some
more time to launch cadence and create those illustrative examples.
Reply

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