Since further explaining the details of the electric design does not make much sense, unless they

know
some of the basics, in this sequel will address the technology that we have met in the first part.

The basis of CMOS Technology is the P-type substrate - it is silicon, which were added 3-valence
elements such as boron or aluminum. This creates an excess of "holes" in the semiconductor and it
becomes conductive. In this first step, the substrate is placed on the oxide, whose role is to isolate the
substrate from the conductive layer to be subsequently applied to it.

The next step is to open the true oxide that will subsequently be implanted with the low-doped
semiconductor inverted, the n-type. The opening is done photolithographic process, in that the oxide
smeared photo-lacquer, which is then illuminated by ultraviolet rays. Where the fallen light, easy to take
off gives a chemical process (acid it breaks), and where the light did not fall, lacquer remains. Lacquer,
however, is removed and the oxide located below the varnish, so that in these places the substrate in
direct contact with air.

In this step, in the opening, which was obtained after the second step, creating an inverse type
semiconductor (n-type). This is done by inserting the 5-valence carbon (mainly phosphorus) into the
opening, wherein the concentration of 5-valent atoms must be greater than the pre-existing
concentrations of 3-valent atoms. The procedure is done in two steps - first 5-wave. atoms passes at the
p-type substrate, and then the material is heated, so that these atoms are diffused deeper into the
substrate. With a depth decreasing concentrations of 5-valent atoms, and the depth of the new nsubstrate (in English usually called n-well) there is, where the concentration of 5-valent atoms becomes
equal to the concentration of 3-valent atoms.Typically, in addition to the n-substrate and expands due to
the heating side, and the n-well to an amount always greater than that provided for the mask.

Having made the inverse layer (n-well), in this step, holes are made for the transistors, both of the NMOStype, and the PMOS-type. The painting is one mistake - opening for n-well can not possibly be the same
slot PMOS transistor (which is always much smaller than the n-well), but it would be - if we want to be fair
- opening from the previous step had to close, and only then re-open for both types of transistors. For this
step, use a mask for the diffusion, or rather, it's about two masks and two-step (n-diffusion and pdiffusion).

In this step, the entire surface of the oxide layer is applied. The step is similar to the first step, only the
applied layer is much smaller - "field oxide" in the first step is of some 200-300 nm thick, while the layer is
in the order of about 10 nanometers. This layer will later be isolation for "gate" -electrode MOS
transistors, and its small thickness is desirable - which is lower layer, the lower the voltage required to
manage the channel below the gate. On the other hand, it is a danger - as a thin layer, the electrical
charge it easier to break down and thus irreversibly destroys transistors and thus large parts of
assemblies. This can occur during operation of the chip, if the transistor comes high voltage pulse (ESD
effect), but already during production, when during polishing, friction may arise static charges, which
penetrate the insulation and thus destroy the transistors (ie. The antenna effects, Eng . antenna effects).

After the applied gate-oxide, the following step is applied to polysilicon. This is a material of which
consists of gate MOS transistors. Gate can be imagined as a counter, which decides whether the current
between the other two electrodes of transistors (source and drain) to run or not. It is a conductive
material, but with much higher specific resistance than in the case of metals, and as a guide only used in
exceptional cases. Because of its large specific resistance is used as the material for the chip resistors,
especially in analog microelectronics.

In this step, via photolithography illuminates the mask polysilicon, which is selectively chosen areas of the
polysilicon, and the gate oxide underneath, which will remain preserved, while the rest of corrosive acid
and Sapir from the chip. So we get gate transistors and Dielektrikum below it, while the rest of the surface
in contact with air and thus available for further steps in the production. As we said, polysilicon is
conductive material, but with a much larger specific resistance of metallic conductors. What is in this
picture do not see (because we need it for 3D graphics), it is the fact that polysilicon can be used for the

electrical connections within, ie, he in any case can go through field-oxide-a, and there are technologies
in which, eg. two-gate and can directly connect polysilicon. This is the case for older and / or cheaper
technology, which have only one or two metal layers are available, but no electrical connection would be
impossible polysilicon.
In addition, each gate always goes beyond the hole diffusion and exceed the field-oxide, and the reason
that we will see in the following steps.

In this step, - a process which is completely similar to that we have described in the creation of the n-welland - generating an inverse layers in a p-substrate and n-well in which the terminals are "source"
("source") and the "drain "(" drain ") MOS transistor.The principle of operation of transistors is that it works
as a switch, in which the current flows between the "source" and "drain" terminal, and the voltage on the
gate in deciding whether the current flow or not. For the operation of transistors is absolutely essential
that the "source" and "drain" isolated from one another, so that - to go back to the explanation that we
have promised in the previous step - why polysilicon must exceed the field-oxide - each hole diffusion ,
which serves to create the MOS-transistors, must be divided into two mutually insulated parts.
Although presented as a single step, it is actually a two-step process - n-diffusion and p-diffusion are
produced in two steps. "P +" and "n" in the figure are also its meaning - this is to say that the
concentration of majority carriers is much greater than is the case with p-substrate and n-well-a (in which
would, at the same convention , mark the "p" and "n"). The concentration is in the "P +" and "n +" diffusion
of some 3 orders of magnitude (ie. About 1000 times) greater than that of the substrate p-well and nCDs.

In this step, the story is quite short - the whole area closes dielekrikom (nitride), to isolate and thus allow
the deposition of metal over the dielectric.

In this step, holes are made to contact, in that the next step will come to the metal and thus to create an
electrical connection to the individual terminals.Contacts are typically squares of a fixed size, and their
size depends on the technology. In addition, some technologies it is possible to use the so-called.contact
strips (Eng. Contact bar), wherein the width of the fixed contact, while the length can be varied. It is often
the case with technologies that are accompanied by high current (Eng. Power Technologies), for example,

with chips in the automotive industry.When contacts must always be careful to carry out current flow
through them, to avoid large heating and thereby melting, ie. Breakdown. Contacts have much higher
resistivity than metals, it is important that the use of the contacts, ie. The transition from one level to
another metal, to a minimum. Additionally, the newer technologies, the small size, and there is a problem
of reliability of contacts, ie. It is not always sure whether the holes provided for the contact actually
present. Although the probability of something very small, such a defect in the production of the chip may
cause the manufactured chip becomes scrap. For this reason, often use the so-called.redundant contacts,
ie. at each transition from one conductor to another must use a minimum of two contacts. If, for example,
the probability that one contact to schedule a 1% (it is far smaller, just as an example), with the likelihood
of redundant contacts is reduced to 0.01%.

About this step does not have as much to say - the entire surface is applied to the metal, which is used to
connect the terminal impedance HF-capable individual elements. Metal enters the holes that have been
made to contact and thus connects the two levels of guide. As guides are used mostly copper and
aluminum. Since this is a fairly soft materials, softer than the dielectric, which is next to them, it is
necessary to take into account the mechanical properties of the material in the production. To us,
however, in this introduction led too far, and on another occasion.

In this last step, the lithography process to illuminate the surface of the chip (this time using a metal
mask), and the result is that the metal remains only where the photo-lacquer on the surface illuminated,
while the rest is washed acid.
It should be noted that, in contrast to the image, the actual technology of polysilicon never connects with
the metal gate in, but running outside the polysilicon gate and there connects with the metal.
This actual production process is not over. As mentioned above, in the production of the most commonly
used several levels of metal, thus making it possible to reduce the size of the chip, since the use of the
vertical connections can minimize the area required for the performance bond required by the chip. As
these further layers of metal are working on the same principle as the former, further disclosure would not
have made any additional information.
In the latest technologies, most often those used for the production of digital circuits, used to five layers of
metal.These are called. routing levels, and they are used to derive connectivity components. These thin
metal layers are lower, while above them are coming thick layers of metals, which are used to connect
power and ground (Eng. Power and ground). Thick layers of metal have, because of its cross-section, a
much smaller specific resistance and voltage loss and dissipation (heat losses) are therefore much
smaller. Such metals, however, are not suitable for performing signal connection, and as the minimum
width is very large, and would require a much larger area for the implementation of the chip.

This concludes this series of contributions. I hope it is for all those who are interested in this subject, and
so far they did not know much, these contributions will be a good introduction to the subject matter. All
comments, suggestions and criticisms are welcome!