Beruflich Dokumente
Kultur Dokumente
Features
Options
VDD1/VDD2/VDDCA/VDDQ: 1.8V/1.2V/1.2V/1.2V
Array configuration
256 Meg x 64 (QDP)
Packaging
15mm x 15mm, 216-ball PoP FBGA package
Operating temperature range
From 30C to +85C
256 Meg x 64
16Gb
Configuration
Row addressing
16K A[13:0]
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216b_16gb_2c0f_mobile_lpddr3.pdf Rev. B 09/14 EN
1K A[9:0]
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2014 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
Clock Rate
(MHz)
Data Rate
(Mb/s/pin)
READ Latency
GD
800
1600
12
JD
933
1866
12
Total
Density
Configuration
Ranks
Channels
Package
Size
Ball
Pitch
EDFA164A1PB-GD-F-D
EDFA164A1PB-GD-F-R
16Gb
256 Meg x 64
15mm x 15mm
(1.0 mm MAX height)
0.50mm
EDFA164A1PK-JD-F-D
EDFA164A1PK-JD-F-R
EDFA164A1PK-GD-F-D
EDFA164A1PK-GD-F-R
16Gb
256 Meg x 64
15mm x 15mm
(0.8 mm MAX height)
0.50mm
A1 64
PB - GD - F - D
Packing Media
Micron Technology
Type
D = Packaged device
Environment Code
Product Family
F = Lead-free (RoHS-compliant)
and halogen-free
Speed
Density/Chip Select
GD = 1600 Mbps
JD = 1866 Mbps
A1 = 16Gb/4-CS (2-CS/channel)
Package
PB = BGA for PoP
PK = BGA for Pop
Organization
64 = x64
Revision
Note:
1. The characters highlighted in gray indicate the physical part marking found on the device.
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
2014 Micron Technology, Inc. All rights reserved.
Contents
Ball Assignments ............................................................................................................................................
Ball Descriptions ............................................................................................................................................
Package Block Diagrams .................................................................................................................................
Package Dimensions .......................................................................................................................................
MR0MR3, MR5MR8, MR11 Contents ............................................................................................................
IDD Specifications Quad Die, Dual Channel ...................................................................................................
Pin Capacitance .............................................................................................................................................
AC Timing ......................................................................................................................................................
LPDDR3 Array Configuration ..........................................................................................................................
General Notes ............................................................................................................................................
Functional Description ...................................................................................................................................
Simplified Bus Interface State Diagram ............................................................................................................
Power-Up and Initialization ............................................................................................................................
Voltage Ramp and Device Initialization .......................................................................................................
Initialization After Reset (Without Voltage Ramp) ........................................................................................
Power-Off Sequence .......................................................................................................................................
Uncontrolled Power-Off Sequence ..............................................................................................................
Standard Mode Register Definition ..................................................................................................................
Mode Register Assignments and Definitions ................................................................................................
Commands and Timing ..................................................................................................................................
ACTIVATE Command .....................................................................................................................................
8-Bank Device Operation ............................................................................................................................
Read and Write Access Modes .........................................................................................................................
Burst READ Command ...................................................................................................................................
tDQSCK Delta Timing .................................................................................................................................
Burst WRITE Command ..................................................................................................................................
Write Data Mask .............................................................................................................................................
PRECHARGE Command .................................................................................................................................
Burst READ Operation Followed by PRECHARGE .........................................................................................
Burst WRITE Followed by PRECHARGE .......................................................................................................
Auto Precharge ...........................................................................................................................................
Burst READ with Auto Precharge .................................................................................................................
Burst WRITE with Auto Precharge ...............................................................................................................
REFRESH Command ......................................................................................................................................
REFRESH Requirements .............................................................................................................................
SELF REFRESH Operation ...............................................................................................................................
Partial-Array Self Refresh (PASR) Bank Masking .........................................................................................
Partial-Array Self Refresh Segment Masking ..............................................................................................
MODE REGISTER READ .................................................................................................................................
MRR Following Idle Power-Down State ........................................................................................................
Temperature Sensor ...................................................................................................................................
DQ Calibration ...........................................................................................................................................
MODE REGISTER WRITE ................................................................................................................................
MRW RESET Command ..............................................................................................................................
MRW ZQ Calibration Commands ................................................................................................................
ZQ External Resistor Value, Tolerance, and Capacitive Loading .....................................................................
MRW CA Training Mode ...........................................................................................................................
MRW - Write Leveling Mode ........................................................................................................................
On-Die Termination (ODT) .............................................................................................................................
ODT Mode Register ....................................................................................................................................
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10
10
12
13
15
17
21
22
29
29
30
32
34
34
36
37
37
38
38
47
48
48
49
50
52
56
60
61
62
63
64
64
65
67
70
72
73
73
75
76
77
78
79
80
81
84
84
86
88
88
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2014 Micron Technology, Inc. All rights reserved.
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2014 Micron Technology, Inc. All rights reserved.
List of Figures
Figure 1: Marketing Part Number Chart ............................................................................................................ 2
Figure 2: 216-Ball Dual-Channel FBGA 4 x 4Gb Die ...................................................................................... 10
Figure 3: Quad-Die, Dual-Channel Package Block Diagram ............................................................................. 12
Figure 4: 216-Ball FBGA (15mm x 15mm) EDFA164A1PB .............................................................................. 13
Figure 5: 216-Ball FBGA (15mm x 15mm) EDFA164A1PK .............................................................................. 14
Figure 6: Functional Block Diagram ............................................................................................................... 31
Figure 7: Simplified State Diagram ................................................................................................................. 33
Figure 8: Voltage Ramp and Initialization Sequence ........................................................................................ 36
Figure 9: Command and Input Setup and Hold ............................................................................................... 47
Figure 10: CKE Input Setup and Hold ............................................................................................................. 47
Figure 11: ACTIVATE Command .................................................................................................................... 48
Figure 12: tFAW Timing .................................................................................................................................. 49
Figure 13: READ Output Timing ..................................................................................................................... 50
Figure 14: Burst READ RL = 12, BL = 8, tDQSCK > tCK ................................................................................... 50
Figure 15: Burst READ RL = 12, BL = 8, tDQSCK < tCK ................................................................................... 51
Figure 16: Burst READ Followed by Burst WRITE RL = 12, WL = 6, BL = 8 ....................................................... 51
Figure 17: Seamless Burst READ RL = 6, BL = 8, tCCD = 4 .............................................................................. 52
Figure 18: tDQSCKDL Timing ........................................................................................................................ 53
Figure 19: tDQSCKDM Timing ....................................................................................................................... 54
Figure 20: tDQSCKDS Timing ......................................................................................................................... 55
Figure 21: Data Input (WRITE) Timing ........................................................................................................... 56
Figure 22: Burst WRITE ................................................................................................................................. 57
Figure 23: Method for Calculating tWPRE Transitions and Endpoints ............................................................... 57
Figure 24: Method for Calculating tWPST Transitions and Endpoints ............................................................... 58
Figure 25: Burst WRITE Followed by Burst READ ............................................................................................ 58
Figure 26: Seamless Burst WRITE WL = 4, BL = 8, tCCD = 4 ............................................................................ 59
Figure 27: Data Mask Timing ......................................................................................................................... 60
Figure 28: Write Data Mask Second Data Bit Masked .................................................................................... 60
Figure 29: Burst READ Followed by PRECHARGE BL = 8, RU(tRTP(MIN)/tCK) = 2 ........................................... 62
Figure 30: Burst WRITE Followed by PRECHARGE BL = 8 .............................................................................. 63
Figure 31: LPDDR3 Burst READ with Auto Precharge .................................................................................... 64
Figure 32: Burst WRITE with Auto Precharge BL = 8 ...................................................................................... 65
Figure 33: REFRESH Command Timing .......................................................................................................... 69
Figure 34: Postponing REFRESH Commands .................................................................................................. 69
Figure 35: Pulling In REFRESH Commands .................................................................................................... 69
Figure 36: All-Bank REFRESH Operation ........................................................................................................ 71
Figure 37: Per-Bank REFRESH Operation ....................................................................................................... 71
Figure 38: SELF REFRESH Operation .............................................................................................................. 73
Figure 39: MRR Timing .................................................................................................................................. 75
Figure 40: READ to MRR Timing .................................................................................................................... 76
Figure 41: Burst WRITE Followed by MRR ...................................................................................................... 76
Figure 42: MRR After Idle Power-Down Exit .................................................................................................... 77
Figure 43: Temperature Sensor Timing ........................................................................................................... 78
Figure 44: MR32 and MR40 DQ Calibration Timing ......................................................................................... 79
Figure 45: MODE REGISTER WRITE Timing ................................................................................................... 80
Figure 46: MODE REGISTER WRITE Timing for MRW RESET .......................................................................... 81
Figure 47: ZQ Timings ................................................................................................................................... 83
Figure 48: CA Training Timing ....................................................................................................................... 84
Figure 49: Write-Leveling Timing ................................................................................................................... 87
Figure 50: Functional Representation of On-Die Termination .......................................................................... 88
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List of Tables
Table 1: Configuration Addressing ................................................................................................................... 1
Table 2: Key Timing Parameters ....................................................................................................................... 2
Table 3: Part Number Description .................................................................................................................... 2
Table 4: Ball/Pad Descriptions ....................................................................................................................... 11
Table 5: Mode Register Contents .................................................................................................................... 15
Table 6: IDD Specifications ............................................................................................................................. 17
Table 7: IDD6 Partial-Array Self Refresh Current at 45C .................................................................................... 20
Table 8: IDD6 Partial-Array Self Refresh Current at 85C .................................................................................... 20
Table 9: Input/Output Capacitance ................................................................................................................ 21
Table 10: AC Timing ...................................................................................................................................... 22
Table 11: Voltage Ramp Conditions ................................................................................................................ 34
Table 12: Initialization Timing Parameters ...................................................................................................... 36
Table 13: Power Supply Conditions ................................................................................................................ 37
Table 14: Power-Off Timing ............................................................................................................................ 37
Table 15: Mode Register Assignments ............................................................................................................. 38
Table 16: MR0 Device Feature 0 (MA[7:0] = 00h) .............................................................................................. 39
Table 17: MR0 Op-Code BIt Definitions .......................................................................................................... 39
Table 18: MR1 Device Feature 1 (MA[7:0] = 01h) .............................................................................................. 40
Table 19: MR1 Op-Code Bit Definitions .......................................................................................................... 40
Table 20: Burst Sequence ............................................................................................................................... 40
Table 21: MR2 Device Feature 2 (MA[7:0] = 02h) .............................................................................................. 40
Table 22: MR2 Op-Code Bit Definitions .......................................................................................................... 41
Table 23: LPDDR3 READ and WRITE Latency ................................................................................................. 41
Table 24: MR3 I/O Configuration 1 (MA[7:0] = 03h) ......................................................................................... 42
Table 25: MR3 Op-Code Bit Definitions .......................................................................................................... 42
Table 26: MR4 Device Temperature (MA[7:0] = 04h) ........................................................................................ 42
Table 27: MR4 Op-Code Bit Definitions .......................................................................................................... 42
Table 28: MR5 Basic Configuration 1 (MA[7:0] = 05h) ...................................................................................... 43
Table 29: MR5 Op-Code Bit Definitions .......................................................................................................... 43
Table 30: MR6 Basic Configuration 2 (MA[7:0] = 06h) ...................................................................................... 43
Table 31: MR6 Op-Code Bit Definitions .......................................................................................................... 43
Table 32: MR7 Basic Configuration 3 (MA[7:0] = 07h) ...................................................................................... 43
Table 33: MR7 Op-Code Bit Definitions .......................................................................................................... 43
Table 34: MR8 Basic Configuration 4 (MA[7:0] = 08h) ...................................................................................... 43
Table 35: MR8 Op-Code Bit Definitions .......................................................................................................... 44
Table 36: MR9 Test Mode (MA[7:0] = 09h) ....................................................................................................... 44
Table 37: MR10 Calibration (MA[7:0] = 0Ah) ................................................................................................... 44
Table 38: MR10 Op-Code Bit Definitions ........................................................................................................ 44
Table 39: MR11 ODT Control (MA[7:0] = 0Bh) ................................................................................................. 45
Table 40: MR11 Op-Code Bit Definitions ........................................................................................................ 45
Table 41: MR16 PASR Bank Mask (MA[7:0] = 010h) .......................................................................................... 45
Table 42: MR16 Op-Code Bit Definitions ........................................................................................................ 45
Table 43: MR17 PASR Segment Mask (MA[7:0] = 011h) .................................................................................... 45
Table 44: MR17 PASR Segment Mask Definitions ............................................................................................ 45
Table 45: MR17 PASR Row Address Ranges in Masked Segments ...................................................................... 46
Table 46: MR63 RESET (MA[7:0] = 3Fh) MRW Only ....................................................................................... 46
Table 47: Reserved Mode Registers ................................................................................................................. 46
Table 48: Bank Selection for PRECHARGE by Address Bits ............................................................................... 61
Table 49: PRECHARGE and Auto Precharge Clarification ................................................................................. 66
Table 50: REFRESH Command Scheduling Separation Requirements .............................................................. 68
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2014 Micron Technology, Inc. All rights reserved.
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2014 Micron Technology, Inc. All rights reserved.
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Ball Assignments
Figure 2: 216-Ball Dual-Channel FBGA 4 x 4Gb Die
1
NC
VSS_A/B
VDD2
_A/B
VSS_A/B
NC
DQ31_A
VDD1
_A/B
DQ16_B
DQ17_B
VDDQ
_A/B
DQ18_B DQ19_B
DQ28_A DQ27_A
VDDQ
_A/B
DQ24_A
VDDQ
_A/B
10
11
12
13
14
15
16
17
18
19
DQS3
_c_A
DQS3
_t_A
DM3_A DQ14_A
VDDQ
_A/B
DQ12_A
VDD2
_A/B
VDDQ
_A/B
DQ9_A
DQS1
_t_A
DQS1
_c_A
20
21
22
23
24
25
VREFDQ
_A
VSS_A/B
VDDQ
_A/B
VSS_A/B
DQS0
_t_A
DQ7_A
ODT_A
VDD2
_A/B
NC
DM0_A
DQS0
_c_A
VDDQ
_A/B
26
27
DQ6_A DQ4_A
DQ5_A
DQ3_A
28
29
VSS_A/B
NC
VDD1
_A/B
VSS_A/B
DQ2_A
VDD2
_A/B
DQ1_A
VDDQ
_A/B
VSS_A/B DQ0_A
VSS_A/B DQ20_B
VDDQ
_A/B
DM2_A
VDDQ
_A/B
DQS2
_t_A
DQS2
_c_A
DQ21_B
DQ22_B DQ23_B
VSS_A/B
VDDQ
_A/B
DQS2
_c_B
DQS2
_t_B
DQ20_A DQ21_A
DM2_B
DQ0_B
DQ19_A VSS_A/B
VSS_A/B DQ23_A
VDDQ
_A/B
VDDQ
_A/B
DQ22_A
H
J
DQ1_B VSS_A/B
DQ2_B
DQ3_B
VDDQ
_A/B
VDD2
_A/B
DQ4_B VSS_A/B
VSS_A/B CA0_B
DQ6_B DQ5_B
VDDCA
_A/B
CA1_B
DQS0
_t_B
DQ7_B
VREFCA
_B
CA2_B
DQS0
_c_B
DM0_B
VSS_A/B CA3_B
VDDQ
_A/B
NC
CA4_B CS1_n_B
CS0_n_B CKE1_B
VSS_A/B VREFDQ
_B
AA
VSS_A/B
VDD2
_A/B
AB
VDD2
_A/B
AC
VDDQ
_A/B
AD
DQS1
_c_B
AE
ODT_B
CK_t_B
CK_c_B
AB
DM1_B
VDDCA
_A/B
CA5_B
AC
DQS1
_t_B
CA7_B
CA6_B
AD
CA8_B
VDDCA
_A/B
AE
VSS_A/B CA9_B
AF
VDDQ
_A/B
AG
DQ10_B DQ11_B
NC
AA
DQ9_B
VSS_A/B
VDD1
_A/B
VSS_A/B CKE0_B
AF
AJ
VDD2
_A/B
DQ8_B VSS_A/B
AH
DQ18_A
DQ16_A DQ17_A
VDD1
_A/B
VDD2
_A/B
VSS_A/B DQ12_B
DQS3
_t_B
VDDQ
_A/B
DQ14_B
VDDQ
_A/B
VSS_A/B
DQS3
_c_B
DQ30_B VSS_A/B
VDD2
_A/B
VREFCA
_A
VDD1
_A/B
NC
15
16
VDDQ
_A/B
DQ26_B DQ27_B
10
11
VDDQ
_A/B
12
13
14
VDDCA
_A/B
NC
ZQ_B
AG
CA1_A
VDD2
_A/B
VSS_A/B
AH
CA0_A
VSS_A/B
NC
AJ
28
29
CA9_A
VSS_A/B CA7_A
CA6_A
CK_c_A
CA2_A
ZQ_A
CA8_A
VDDCA
_A/B
CA5_A
VDDCA
_A/B
17
18
19
20
26
27
21
22
23
24
25
Channel B
Supply
Ground
Ball Descriptions
The ball/pad description table below is a comprehensive list of signals for the device
family. All signals listed may not be supported on this device. See ball assignments for
information specific to this device.
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Type
Description
CA[9:0]_A,
CA[9:0]_B
Input
Command/address inputs: Provide the command and address inputs according to the
command truth table. A separate CA[9:0] is provided for each channel (A and B).
CK_t_B, CK_t_A
CK_c_B, CK_c_A
Input
Clock: Differential clock inputs. All CA inputs are sampled on both rising and falling
edges of CK. CS and CKE inputs are sampled at the rising edge of CK. AC timings are
referenced to clock. A separate CK_t/CK_c is provided for each channel (A and B).
CKE[1:0]_A,
CKE[1:0]_B
Input
Clock enable: CKE HIGH activates and CKE LOW deactivates the internal clock signals,
input buffers, and output drivers. Power-saving modes are entered and exited via CKE
transitions. CKE is considered part of the command code. CKE is sampled on the rising
edge of CK. A separate CKE is provided for each channel (A and B).
CS[1:0]_n_A,
CS[1:0]_n_B
Input
Chip select: Considered part of the command code and is sampled on the rising edge
of CK. A separate CS_n is provided for each channel (A and B).
DM[3:0]_B,
DM[3:0]_A
Input
Input data mask: Input mask signal for write data. Although DM balls are input-only,
the DM loading is designed to match that of DQ and DQS balls. DM[3:0] is DM for each
of the four data bytes, respectively. A separate DM[3:0] is provided for each channel (A
and B).
ODT_B, ODT_A
Input
On-die termination: Enables and disables termination on the DRAM DQ bus according
to the specified mode register settings. For packages that do not support ODT, the ODT
signal may be grounded internally. A separate ODT provided for each channel (A and
B).
DQ[31:0]_B,
DQ[31:0]_A
I/O
Data input/output: Bidirectional data bus. A separate DQ[11:0] is provided for each
channel (A and B).
DQS[3:0]_t_B,
DQS[3:0]_t_A,
DQS[3:0]_c_B,
DQS[3:0]_c_A
I/O
Data strobe: Bidirectional (used for read and write data) and complementary (DQS_t
and DQS_c). It is edge-aligned output with read data and centered input with write data. DQS[3:0]_t/DQS[3:0]_c is DQS for each of the four data bytes, respectively. A separate DQS[3:0]_t and DQS[3:0]_c is provided for each channel (A and B).
VDDQ
Supply
VSSQ
Supply
VDDCA
Supply
VSSCA
Supply
VDD1
Supply
VDD2
Supply
VSS
Supply
Common ground.
VREFCA_B, VREFCA_A
VREFDQ_B, VREFDQ_A
Supply
ZQ_B, ZQ_A
Reference
External reference ball for output drive calibration: This ball is tied to an external
240 resistor (RZQ), which is tied to VSSQ. A separate ZQ is provided for each channel (A
and B).
DNU
NC
(NC)
No connect: Balls indicated as (NC) are no connects; however, they could be connected
together internally.
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VDD1_A/B
VDD2_A/B
VSS_A/B
VDDCA_A/B
VREFCA_A, B
VREFDQ_A, B
CS1_n_A
CKE1_A
ZQ_A
CS0_n_A
CKE0_A
CK_t_A
CK_c_A
LPDDR3
Die 2
LPDDR3
Die 0
DM[3:0]_A
CA[9:0]_A
ODT_A
ODT
DQ[31:0]_A,
DQS[3:0]_t_A,
DQS[3:0]_c_A
ODT
VSS
CS1_n_B
CKE1_B
ZQ_B
CS0_n_B
CKE0_B
CK_t_B
CK_c_B
LPDDR3
Die 1
LPDDR3
Die 3
DM[3:0]_B
CA[9:0]_B
ODT_B
ODT
ODT
VSS
Note:
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DQ[31:0]_B,
DQS[3:0]_t_B,
DQS[3:0]_c_B
1. The ODT input is connected to rank 0. The ODT input to rank 1 is connected to VSS in the
package.
12
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2014 Micron Technology, Inc. All rights reserved.
Package Dimensions
Figure 4: 216-Ball FBGA (15mm x 15mm) EDFA164A1PB
15.0 0.1
0.20 S B
15.0 0.1
Index mark
0.20 S A
0.10 S
0.90 0.10
S
0.10 S
0.25 0.05
0.05 M S AB
0.5
14.0
A
Index mark
0.5
14.0
Notes:
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0.20 S B
15.0 0.1
Index mark
0.20 S A
0.10 S
0.72 0.08
S
0.10 S
0.25 0.05
0.05 M S AB
0.5
14.0
A
Index mark
0.5
14.0
Notes:
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OP7
OP6
OP5
OP4
OP3
OP2
OP1
OP0
MR0
EDFA164A1PK
EDFA164A1PB
MR1
EDFA164A1PK
EDFA164A1PB
MR2
EDFA164A1PK
EDFA164A1PB
OP[3:0] RL and WL
0100b: RL = 6: WL = 3
0110b: RL = 8; WL = 4 (default)
0111b: RL = 9; WL = 5
1000b: RL = 10; WL = 6
1001b: RL = 11; WL = 6
1010b: RL = 12; WL = 6
All others: Reserved
OP4 nWRE
0b: Enable nWR programming 9 (default)
1b: Enable nWRE programming > 9
OP6 WL select
0b: Select WL Set A (default)
1b: Reserved
OP7 Write leveling
0b: Write leveling mode disabled (default)
1b: Write leveling mode enabled
MR3
EDFA164A1PK
EDFA164A1PB
OP[3:0] DS
0000b: Reserved
0001b: 34.3 Ohms TYP
0010b: 40 Ohms TYP (default)
0011b: 48 Ohms TYP
All others: Reserved
MR5
EDFA164A1PK
EDFA164A1PB
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216b_16gb_2c0f_mobile_lpddr3.pdf Rev. B 09/14 EN
15
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2014 Micron Technology, Inc. All rights reserved.
OP7
OP6
OP5
OP4
OP3
OP2
OP1
OP0
MR6
EDFA164A1PK
EDFA164A1PB
MR7
EDFA164A1PB
EDFA164A1PK
MR8
I/O Width
Density
Type
EDFA164A1PK
EDFA164A1PB
00b: x32
0110b: 4Gb
11b: S8
MR11
EDFA164A1PK
EDFA164A1PB
OP[1:0]
DQ ODT
00b; Disabled (default)
01b: Reserved
10b: RZQ/2
11b: RZQ/1
OP2 PD control (power-down control)
0b: ODT disabled by DRAM during power-down
1b: ODT enabled by DRAM during power-down
Note:
PDF: 09005aef85b4b06b
216b_16gb_2c0f_mobile_lpddr3.pdf Rev. B 09/14 EN
1. The contents of MR0MR3, MR5MR8, and MR11 will reflect information specific to
each in these packages.
16
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2014 Micron Technology, Inc. All rights reserved.
Supply
1866
1600
1333
IDD01
VDD1
16
16
16
IDD02
VDD2
120
120
120
IDD0,in
VDDCA + VDDQ
6.0
6.0
6.0
IDD2P1
VDD1
1.6
1.6
1.6
IDD2P2
VDD2
3.6
3.6
3.6
IDD2P,in
VDDCA + VDDQ
0.4
0.4
0.4
IDD2PS1
VDD1
1.6
1.6
1.6
IDD2PS2
VDD2
3.6
3.6
3.6
IDD2PS,in
VDDCA + VDDQ
0.4
0.4
0.4
IDD2N1
VDD1
1.6
1.6
1.6
IDD2N2
VDD2
60
52
44
IDD2N,in
VDDCA + VDDQ
12
12
12
IDD2NS1
VDD1
1.6
1.6
1.6
IDD2NS2
VDD2
16
16
16
IDD2NS,in
VDDCA + VDDQ
12
12
12
VDD1
2.8
2.8
2.8
IDD3P1
IDD3P2
VDD2
22
22
22
IDD3P,in
VDDCA + VDDQ
0.4
0.4
0.4
PDF: 09005aef85b4b06b
216b_16gb_2c0f_mobile_lpddr3.pdf Rev. B 09/14 EN
Unit Parameter/Condition
mA
mA
mA
mA
mA
All devices in idle non power-down standby current with clock stop
CK_t = LOW, CK_c = HIGH; CKE is HIGH;
CS_n is HIGH; All banks are idle;
CA bus inputs are STABLE;
Data bus inputs are STABLE;
ODT is disabled
mA
17
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2014 Micron Technology, Inc. All rights reserved.
Supply
1866
1600
1333
VDD1
2.8
2.8
2.8
IDD3PS2
VDD2
22
22
22
IDD3PS,in
VDDCA + VDDQ
0.4
0.4
0.4
IDD3N1
VDD1
4.0
4.0
4.0
IDD3N2
VDD2
80
68
60
IDD3N,in
VDDCA + VDDQ
12
12
12
IDD3NS1
VDD1
4.0
4.0
4.0
IDD3NS2
VDD2
32
32
32
IDD3NS,in
VDDCA + VDDQ
12
12
12
IDD4R1
VDD1
4.0
4.0
4.0
IDD4R2
VDD2
540
460
400
IDD4R,in
VDDCA
6.0
6.0
6.0
IDD4W1
VDD1
4.0
4.0
4.0
IDD4W2
VDD2
560
480
420
IDD4W,in
VDDCA + VDDQ
6.0
6.0
6.0
PDF: 09005aef85b4b06b
216b_16gb_2c0f_mobile_lpddr3.pdf Rev. B 09/14 EN
18
Unit Parameter/Condition
mA
mA
mA
All devices in active non power-down standby current with clock stop
CK_t = LOW, CK_c = HIGH; CKE is HIGH;
CS_n is HIGH; One bank is active;
CA bus inputs are STABLE;
Data bus inputs are STABLE;
ODT is disabled
mA
mA
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2014 Micron Technology, Inc. All rights reserved.
Supply
1866
1600
1333
VDD1
56
56
56
IDD52
VDD2
300
300
300
IDD5,in
VDDCA + VDDQ
6.0
6.0
6.0
IDD5AB1
VDD1
4.0
4.0
4.0
IDD5AB2
VDD2
40
36
32
IDD5AB,in
VDDCA + VDDQ
6.0
6.0
6.0
IDD5PB1
VDD1
4.0
4.0
4.0
IDD5PB2
VDD2
40
36
32
IDD5PB,in
VDDCA + VDDQ
6.0
6.0
6.0
IDD81
VDD1
64
64
64
IDD82
VDD2
24
24
24
IDD8,in
VDDCA + VDDQ
48
48
48
Notes:
PDF: 09005aef85b4b06b
216b_16gb_2c0f_mobile_lpddr3.pdf Rev. B 09/14 EN
Unit Parameter/Condition
mA
mA
mA
1. Published IDD values are the maximum of the distribution of the arithmetic mean.
2. IDD current specifications are tested after the device is properly initialized.
19
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1/2 array
1/4 array
1/8 array
VDD1
920
VDD2
3520
VDDCA + VDDQ
40
VDD1
600
VDD2
2000
VDDCA + VDDQ
40
VDD1
440
VDD2
1200
VDDCA + VDDQ
40
VDD1
360
VDD2
840
VDDCA + VDDQ
40
Note:
Parameters/Conditions
All devices in self refresh
CK_t = LOW, CK_c = HIGH;
CKE is LOW;
CA bus inputs are STABLE;
Data bus inputs are STABLE;
ODT is disabled
1/2 array
1/4 array
1/8 array
VDD1
3800
VDD2
12,000
VDDCA + VDDQ
48
VDD1
3000
VDD2
7200
VDDCA + VDDQ
48
VDD1
2600
VDD2
5200
VDDCA + VDDQ
48
VDD1
2400
VDD2
4000
VDDCA + VDDQ
48
Note:
PDF: 09005aef85b4b06b
216b_16gb_2c0f_mobile_lpddr3.pdf Rev. B 09/14 EN
Parameters/Conditions
All devices in self refresh
CK_t = LOW, CK_c = HIGH;
CKE is LOW;
CA bus inputs are STABLE;
Data bus inputs are STABLE;
ODT is disabled
20
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Pin Capacitance
Table 9: Input/Output Capacitance
Part Number
Parameter
Symbol
Min
Max
Unit
Notes
EDFA164A1PB
EDFA164A1PK
CCK
1.5
3.6
pF
1, 2
EDFA164A1PB
EDFA164A1PK
CI1
1.5
3.6
pF
1, 2
EDFA164A1PB
EDFA164A1PK
CI2
0.5
3.0
pF
1, 2
EDFA164A1PB
EDFA164A1PK
CIO
2.5
5.5
pF
1, 2, 3
EDFA164A1PB
EDFA164A1PK
Input/output capacitance, ZQ
CZQ
0.0
6.0
pF
1, 2, 3
Notes:
PDF: 09005aef85b4b06b
216b_16gb_2c0f_mobile_lpddr3.pdf Rev. B 09/14 EN
1. This parameter is not subject to production testing. It is verified by design and characterization.
2. These parameters are measured on f = 100 MHz, VOUT = VDDQ/2, TA = +25 C.
3. DOUT circuits are disabled.
21
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AC Timing
Table 10: AC Timing
Notes 13 apply to all parameters and conditions
Parameter
Data Rate
Symbol
Min/Max
1333
1600
1866
Unit
667
800
933
MHz
tCK(avg)
MIN
1.5
1.25
1.071
ns
tCH(avg)
tCL(avg)
tCK(abs)
tCH(abs)
tCL(abs)
Maximum frequency
Notes
Clock Timing
MAX
100
MIN
0.45
MAX
0.55
MIN
0.45
MAX
PDF: 09005aef85b4b06b
216b_16gb_2c0f_mobile_lpddr3.pdf Rev. B 09/14 EN
tJIT(per),
al-
lowed
tJIT(cc),
allowed
tJIT(duty),
al-
tCK(avg)
tCK(avg)
0.55
tCK(avg)
MIN
MIN
0.43
MAX
0.57
MIN
0.43
MAX
0.57
tCK(avg)
MIN
80
70
-60
MAX
80
70
60
MAX
160
140
120
MIN
min((tCH(abs),min - tCH(avg),min),
(tCL(abs),min - tCL(avg),min))
tCK(avg)
MAX
max((tCH(abs),max - tCH(avg),max),
(tCL(abs),max - tCL(avg),max))
tCK(avg)
lowed
tERR(2per),
MIN
allowed
MAX
118
103
88
tERR(3per),
MIN
140
122
-105
allowed
MAX
140
122
105
tERR(4per),
MIN
155
136
-117
allowed
MAX
155
136
117
tERR(5per),
MIN
168
147
-126
allowed
MAX
168
147
126
tERR(6per),
MIN
177
155
-133
allowed
MAX
177
155
133
tERR(7per),
MIN
186
163
-139
allowed
MAX
186
163
139
118
22
103
ns
tCK(avg)
-88
ps
ps
ps
ps
ps
ps
ps
ps
ps
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Data Rate
Symbol
Min/Max
tERR(8per),
MIN
allowed
MAX
193
169
145
tERR(9per),
MIN
200
175
-150
allowed
MAX
200
175
150
tERR(10per),
MIN
205
180
-154
allowed
MAX
205
180
154
tERR(11per),
MIN
210
184
-158
allowed
MAX
210
184
158
tERR(12per),
MIN
215
188
-161
allowed
MAX
215
188
161
tERR(nper),
MIN
1333
1600
1866
Unit
193
169
-145
ps
tERR(nper),allowed
MIN = (1 +
0.68ln(n)) tJIT(per), allowed MIN
allowed
Notes
ps
ps
ps
ps
ps
tERR
MAX
ZQ Calibration Parameters
tZQINIT
MIN
tZQCL
MIN
ns
tZQCS
MIN
ns
tZQRESET
MIN
ns
tDQSCK
MIN
2500
ps
MAX
5500
READ
Parameters4
tDQSCKDS
MAX
265
220
220
ps
tDQSCKDM
MAX
593
511
511
ps
tDQSCKDL
MAX
733
614
614
ps
tDQSQ
MAX
165
135
135
DQS-DQ skew
ps
tQSH
MIN
tCH(abs)
tQSL
MIN
tCL(abs)
tQH
MIN
ps
READ preamble
tRPRE
MIN
0.9
tCK(avg)
8, 9
READ postamble
tRPST
0.3
tCK(avg)
8, 10
PDF: 09005aef85b4b06b
216b_16gb_2c0f_mobile_lpddr3.pdf Rev. B 09/14 EN
tLZ(DQS)
tLZ(DQ)
tHZ(DQS)
tHZ(DQ)
MIN
- 0.05
tCK(avg)
- 0.05
tCK(avg)
MIN
tDQSCK
(MIN) - 300
ps
MIN
tDQSCK
(MIN) - 300
ps
MAX
tDQSCK
(MAX) - 100
ps
ps
tDQSCK
MAX
23
(MAX) + (1.4
(MAX))
tDQSQ
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Symbol
Min/Max
tDH
Data Rate
1333
1600
1866
Unit
MIN
175
150
150
ps
tDS
MIN
175
150
150
ps
tDIPW
MIN
0.35
tCK(avg)
tDQSS
MIN
0.75
tCK(avg)
MAX
1.25
tDQSH
MIN
0.4
tCK(avg)
tDQSL
MIN
0.4
tCK(avg)
tDSS
MIN
0.2
tCK(avg)
tDSH
MIN
0.2
tCK(avg)
Write postamble
tWPST
MIN
0.4
tCK(avg)
Write preamble
tWPRE
MIN
0.8
tCK(avg)
tCKE
MIN
tCK(avg)
tISCKE
MIN
0.25
tCK(avg)
11
tIHCKE
0.25
tCK(avg)
12
tCPDED
tCK(avg)
WRITE
Notes
Parameters4
MIN
MIN
Parameters4
tISCA
MIN
175
150
150
ps
13
tIHCA
MIN
175
150
150
ps
13
tISCS
MIN
290
270
270
ps
13
tIHCS
MIN
290
270
270
ps
13
tIPWCA
MIN
0.35
tCK(avg)
tIPWCS
MIN
0.7
tCK(avg)
MAX
100
ns
MIN
18
MIN
2.5
PDF: 09005aef85b4b06b
216b_16gb_2c0f_mobile_lpddr3.pdf Rev. B 09/14 EN
tCKb
tISCKEb
24
ns
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2014 Micron Technology, Inc. All rights reserved.
Parameter
Symbol
Min/Max
tIHCKEb
MIN
2.5
ns
tISb
MIN
1150
ps
tIHb
MIN
1150
ps
tDQSCKb
MIN
ns
1333
1600
1866
Unit
MAX
10
tDQSQb
MAX
1.2
ns
tMRW
MIN
10
tCK(avg)
tMRD
MIN
ns
tMRR
MIN
tCK(avg)
Additional time after tXP has expired until MRR command may
be issued
tMRRI
MIN
READ latency
RL
MIN
10
12
12
tCK(avg)
WL
MIN
tCK(avg)
tRC
MIN
ns
tCKESR
MIN
ns
tXSR
MIN
ns
tXP
MIN
ns
CAS-to-CAS delay
tCCD
MIN
tCK(avg)
tRTP
MIN
ns
RAS-to-CAS delay
tRCD
MIN
ns
Notes
tRCD
(MIN)
ns
Core Parameters17
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216b_16gb_2c0f_mobile_lpddr3.pdf Rev. B 09/14 EN
tRAS
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Data Rate
Symbol
Min/Max
tRPpb
MIN
ns
tRPpab
MIN
ns
tRAS
MIN
ns
MAX
70
tWR
MIN
ns
tWTR
MIN
ns
tRRD
MIN
ns
tFAW
MIN
ns
tDPD
MIN
500
tODTon
MIN
1.0
ns
MAX
2.25
tODToff
MIN
1.0
tAODTon
MAX
tAODToff
MIN
tODTd
MAX
12
ns
tODTe
MAX
12
ns
tCAMRD
MIN
20
tCK(avg)
tCAENT
MIN
10
tCK(avg)
tCAEXT
MIN
10
tCK(avg)
tCACKEL
MIN
10
tCK(avg)
tCACKEH
MIN
10
tCK(avg)
tADR
MAX
20
ns
1333
1600
1866
Unit
Notes
ODT Parameters
MAX
ns
2.25
tDQSCK
+ 1.4 tDQSQmax +
tCK(avg,min)
tDQSCKmin
- 300 - 0.5tCK(avg,min)
ps
ps
CA Training Parameters
PDF: 09005aef85b4b06b
216b_16gb_2c0f_mobile_lpddr3.pdf Rev. B 09/14 EN
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Data Rate
Symbol
Min/Max
tMRZ
MIN
ns
CA calibration command to CA
calibration command delay
tCACD
MIN
RU(tADR/tCK) + 2
tCK(avg)
tWLDQSEN
MIN
25
ns
MAX
1333
1600
1866
Unit
Notes
tWLMRD
MIN
40
MAX
MIN
MAX
20
ns
tWLO
tWLH
MIN
205
175
150
ns
tWLS
MIN
205
175
150
ns
tDQSCK
MAX
tRCD
MIN
tRCD
tRC
MIN
tRC
tRAS
MIN
tRAS
MIN
tRP
MIN
tRRD
ns
tRP
tRRD
Notes:
PDF: 09005aef85b4b06b
216b_16gb_2c0f_mobile_lpddr3.pdf Rev. B 09/14 EN
5620
+ 1.875
+ 1.875
+ 1.875
+ 1.875
+ 1.875
ps
ns
ns
ns
ns
ns
1. Frequency values are for reference only. Clock cycle time (tCK) is used to determine device capabilities.
2. All AC timings assume an input slew rate of 2 V/ns.
3. Measured with 4 V/ns differential CK_t/CK_c slew rate and nominal VIX.
4. READ, WRITE, and input setup and hold values are referenced to VREF.
5. tDQSCKDS is the absolute value of the difference between any two tDQSCK measurements (in a byte lane) within a contiguous sequence of bursts in a 160ns rolling window.
tDQSCKDS is not tested and is guaranteed by design. Temperature drift in the system is
<10C/s. Values do not include clock jitter.
6. tDQSCKDM is the absolute value of the difference between any two tDQSCK measurements (in a byte lane) within a 1.6s rolling window. tDQSCKDM is not tested and is
guaranteed by design. Temperature drift in the system is <10C/s. Values do not include
clock jitter.
7. tDQSCKDL is the absolute value of the difference between any two tDQSCK measurements (in a byte lane) within a 32ms rolling window. tDQSCKDL is not tested and is
guaranteed by design. Temperature drift in the system is <10C/s. Values do not include
clock jitter.
27
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VTT + Y mV
VOH - X mV
VOH - 2x X mV
tLZ(DQS), tLZ(DQ)
actual wave
rm
fo
VTT
X
2x X
VTT + 2x Y mV
tHZ(DQS), tHZ(DQ)
VTT
Y
2x Y
VTT - Y mV
VOL + 2x X mV
VTT - 2x Y mV
VOL + X mV
T1 T2
Start driving point = 2 T1 - T2
VOL
T1 T2
End driving point = 2 T1 - T2
9. Measured from the point when DQS begins driving the signal, to the point when DQS
begins driving the first rising strobe edge.
10. Measured from the last falling strobe edge of DQS to the point when DQS finishes driving the signal.
11. CKE input setup time is measured from CKE reaching a HIGH/LOW voltage level to
CK crossing.
12. CKE input hold time is measured from CK crossing to CKE reaching a HIGH/LOW voltage
level.
13. Input setup/hold time for signal (CA[9:0], CS_n).
14. To ensure device operation before the device is configured, a number of AC boot timing
parameters are defined in this table. Boot parameter symbols have the letter b appended (for example, tCK during boot is tCKb).
15. Mobile LPDDR3 devices set some mode register default values upon receiving a RESET
(MRW) command, as specified in Mode Register Definition.
16. The output skew parameters are measured with default output impedance settings using the reference load.
17. The minimum tCK column applies only when tCK is greater than 6ns.
PDF: 09005aef85b4b06b
216b_16gb_2c0f_mobile_lpddr3.pdf Rev. B 09/14 EN
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General Notes
Throughout the data sheet, figures and text refer to DQs as DQ. DQ should be interpreted as any or all DQ collectively, unless specifically stated otherwise.
DQS and CK should be interpreted as DQS_t, DQS_c and CK_t, CK_c, respectively,
unless specifically stated otherwise. BA and "CA" include all BA and CA pins, respectively, used for a given density.
Complete functionality may be described throughout the entire document. Any page or
diagram may have been simplified to convey a topic and may not be inclusive of all requirements.
Timing diagrams reflect a single-channel device.
In timing diagrams, CMD is used as an indicator only. Actual signals occur on CA[9:0].
VREF indicates V REFCA and V REFDQ.
Any specific requirement takes precedence over a general statement.
Any functionality not specifically stated herein is considered undefined, illegal, is not
supported, and will result in unknown operation.
PDF: 09005aef85b4b06b
216b_16gb_2c0f_mobile_lpddr3.pdf Rev. B 09/14 EN
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Functional Description
Mobile LPDDR3 is a high-speed SDRAM internally configured as an 8-bank memory device. LPDDR3 uses a double data rate architecture on the command/address (CA) bus
to reduce the number of input pins in the system. The 10-bit CA bus is used to transmit
command, address, and bank information. Each command uses one clock cycle, during
which command information is transferred on both the rising and falling edges of the
clock.
LPDDR3 uses a double data rate architecture on the DQ pins to achieve high-speed operation. The double data rate architecture is essentially an 8n prefetch architecture with
an interface designed to transfer two data bits per DQ every clock cycle at the I/O pins.
A single read or write access for LPDDR3 effectively consists of a single 8n-bit-wide,
one-clock-cycle data transfer at the internal SDRAM core and eight corresponding nbit-wide, one-half-clock-cycle data transfers at the I/O pins.
Read and write accesses to the device are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence.
Accesses begin with the registration of an ACTIVATE command followed by a READ or
WRITE command. The address and BA bits registered coincident with the ACTIVATE
command are used to select the row and bank to be accessed. The address bits registered coincident with the READ or WRITE command are used to select the bank and the
starting column location for the burst access.
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CK_t
CK_c
CKE
Clock
generator
CA[9:0]
Row
address
buffer
and
refresh
counter
Row decoder
Mode
register
Sense amp.
Control logic
CS_n
Address/command decoder
Bank n
Column decoder
Column
address
buffer
and
burst
counter
Latch circuit
DQS_t, DQS_c
DM
ODT
DQ
PDF: 09005aef85b4b06b
216b_16gb_2c0f_mobile_lpddr3.pdf Rev. B 09/14 EN
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PDF: 09005aef85b4b06b
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3RZHU
DSSOLHG
'HHS
SRZHUGRZQ
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Notes:
PDF: 09005aef85b4b06b
216b_16gb_2c0f_mobile_lpddr3.pdf Rev. B 09/14 EN
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2014 Micron Technology, Inc. All rights reserved.
Applicable Conditions
Ta is reached
Notes:
Beginning at Tb, CKE must remain LOW for at least tINIT1, after which CKE can be asserted HIGH. The clock must be stable at least tINIT2 prior to the first CKE LOW-toHIGH transition (Tc). CKE, CS_n, and CA inputs must observe setup and hold requirements (tIS, tIH) with respect to the first rising clock edge and to subsequent falling and
rising edges.
If any MRRs are issued, the clock period must be within the range defined for tCKb.
MRWs can be issued at normal clock frequencies as long as all AC timings are met.
Some AC parameters (for example, tDQSCK) could have relaxed timings (such as
tDQSCKb) before the system is appropriately configured. While keeping CKE HIGH,
NOP commands must be issued for at least tINIT3 (Td). The ODT input signal may be in
PDF: 09005aef85b4b06b
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2014 Micron Technology, Inc. All rights reserved.
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2014 Micron Technology, Inc. All rights reserved.
Tb
tINIT2
Tc
Td
Te
Tf
Tf
Tg
CK_t/CK_c
tINIT0
Supplies
tINIT1
tINIT3
CKE
tINIT4
tISCKE
CA
RESET
tZQINIT
tINIT5
MRR
CA
Training
MRW
ZQ_CAL
Valid
DQ
ODT
Valid
Notes:
Min
Max
Unit
tINIT0
Comment
20
ms
tINIT1
100
ns
tINIT2
tCK
tINIT3
200
tINIT4
tINIT5
10
tZQINIT
ZQ initial calibration
tCKb
18
100
ns
1. The tINIT0 maximum specification is not a tested limit and should be used as a general
guideline. For voltage ramp times exceeding tINIT0 MAX, please contact the factory.
2. If the DAI bit is not read via MRR, the device will be in the idle state after tINIT5 (MAX)
has expired.
Notes:
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Power-Off Sequence
The following procedure is required to power off the device.
While powering off, CKE must be held LOW; all other inputs must be between V ILmin
and V IHmax. The device outputs remain at High-Z while CKE is held LOW.
DQ, DM, and DQS voltage levels must be between V SSQ and V DDQ during the power-off
sequence to avoid latch-up. CK, CS_n, and CA input levels must be between V SSCA and
VDDCA during the power-off sequence to avoid latch-up.
Tx is the point where any power supply drops below the minimum value specified in
the Recommended DC Operating Conditions table.
Tz is the point where all power supplies are below 300mV. After Tz, the device is powered off.
Table 13: Power Supply Conditions
Between...
Applicable Conditions
Tx and Tz
Notes:
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37
Symbol
Min
Max
Unit
tPOFF
sec
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2014 Micron Technology, Inc. All rights reserved.
Access
OP7
OP6
OP5
RL3
WL-B
RFU
OP4
OP3
OP2
RZQI
OP1
RFU
OP0
DAI
Link
Go to MR0
00h
Device info
01h
Device feature 1
02h
Device feature 2
03h
I/O config-1
04h
SDRAM refresh
rate
05h
Basic config-1
Manufacturer ID
Go to MR5
06h
Basic config-2
Revision ID1
Go to MR6
07h
Basic config-3
Revision ID2
Go to MR7
08h
Basic config-4
09h
Test mode
10
0Ah
I/O calibration
11
0Bh
ODT
1215
0Ch0Fh
Reserved
RFU
Go to MR12
16
10h
PASR_Bank
Go to MR16
RFU
WL
Select
RFU
nWRE
BL
Go to MR1
RL and WL
Go to MR2
DS
Go to MR3
RFU
RFU
TUF
I/O width
Refresh rate
Density
Type
Go to MR8
Go to MR9
Calibration code
RFU
Go to MR4
Go to MR10
DQ ODT
Go to MR11
17
11h
PASR_Seg
Go to MR17
1831
12h1Fh
Reserved
RFU
Go to
MR18MR31
32
20h
DQ calibration
pattern A
3339
21h27h
Do not use
40
28h
DQ calibration
pattern B
41
29h
CA training 1
42
2Ah
CA training 2
4347
2Bh2Fh
Do not use
CA training 3
Reserved
RFU
48
30h
4962
31h3Eh
PDF: 09005aef85b4b06b
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Go to MR33
Go to MR43
38
Go to MR49
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2014 Micron Technology, Inc. All rights reserved.
3Fh
64255
40hFFh
Access
OP7
OP6
OP5
OP4
OP3
OP2
OP1
OP0
Link
RESET
Go to MR63
Reserved
RFU
Go to MR64
Notes:
OP6
OP5
RL3
WL-B
RFU
OP4
OP3
OP2
RZQI
OP1
RFU
OP0
DAI
Tag
Type
OP
Definition
DAI
Read-only
OP0
RZQI1
Read-only
OP[4:3]
WL Set B support
WL-B
Read-only
OP[6]
RL3
Read-only
OP[7]
RL3 support
Notes:
PDF: 09005aef85b4b06b
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1. RZQI will be set upon completion of the MRW ZQ INITIALIZATION CALIBRATION command.
2. If ZQ is connected to VDDCA to set default calibration, OP[4:3] must be set to 01. If ZQ is
not connected to VDDCA, either OP[4:3] = 01 or OP[4:3] = 10 may indicate a ZQ pin assembly error.
3. In the case of a possible assembly error, the device will default to factory trim settings
for RON and will ignore ZQ CALIBRATION commands. In either case, the system may not
function as intended.
4. If the ZQ self-test returns a value of 11b, it indicates that the device has detected a resistor connection to the ZQ pin. However, that result cannot be used to validate the ZQ
resistor value or that the ZQ resistor tolerance meets the specified limit of 240
39
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OP6
OP5
OP4
OP3
OP2
OP1
RFU
OP0
BL
Type
OP
BL
Write-only
OP[2:0]
nWR
Write-only
OP[7:5]
Notes:
Definition
Notes
1, 2
1. The programmed value in the nWR register is the number of clock cycles that determine
when to start the internal precharge operation for a WRITE burst with AP enabled. It is
determined by RU (tWR/tCK).
2. The range of nWR is extended (MR2 OP[4] = 1) by using an extra bit (nWRE) in MR2.
C1
C0
0b
0b
0b
0b
1b
0b
1b
0b
0b
1b
1b
0b
Note:
BL
OP6
OP5
OP4
WR Lev
WL Sel
RFU
nWRE
PDF: 09005aef85b4b06b
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OP3
OP2
OP1
OP0
RL and WL
40
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Type
OP
Write-only
OP[3:0]
Definition
If OP[6] = 0 (default, WL Set A)
0001b: RL3/WL1 (166 MHz)1
0100b: RL6/WL3 (400 MHz)
0110b: RL8/WL4 (533 MHz)
0111b: RL9/WL5 (600 MHz)
1000b: RL10/WL6 (667 MHz, default)
1001b: RL11/WL6 (733 MHz)
1010b: RL12/WL6 (800 MHz)
1100b: RL14/WL8 (933 MHz)
1110b: RL16/WL8 (1066 MHz)
All others: Reserved
If OP[6] = 1 (WL Set B)
0001b: RL3/WL1 (166 MHz)1
0100b: RL6/WL3 (400 MHz)
0110b: RL8/WL4 (533 MHz)
0111b: RL9/WL5 (600 MHz)
1000b: RL10/WL8 (667 MHz, default)
1001b: RL11/WL9 (733 MHz)
1010b: RL12/WL9 (800 MHz)
1100b: RL14/WL11 (933 MHz)
1110b: RL16/WL13 (1066 MHz)
All others: Reserved
nWRE
Write-only
OP[4]
WL select
Write-only
OP[6]
WR Lev
Write-only
OP[7]
Notes:
333
800
1066
1200
1333
1466
1600
1866
2133
tCK(ns)
2.5
1.875
1.67
1.5
1.36
1.25
1.071
0.938
RL
10
11
12
14
16
WL (Set A)
WL (Set B)
11
13
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OP6
OP5
OP4
OP3
OP2
RFU
OP1
OP0
OP1
OP0
DS
Type
OP
Write-only
OP[3:0]
Definition
0001b: 34.3 typical
0010b: 40 typical (default)
0011b: 48 typical
0100b: Reserved
0110b: Reserved
1001b: 34.3 pull-down, 40 pull-up
1010b: 40 pull-down, 48 pull-up
1011b: 34.3 pull-down, 48 pull-up
All others: Reserved
OP6
OP5
OP4
OP3
RFU
TUF
OP2
OP
SDRAM refresh
rate
Read-only
OP[2:0]
Read-only
OP7
Notes:
PDF: 09005aef85b4b06b
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Definition
000b: SDRAM low-temperature operating limit exceeded
001b: 4 tREFI, 4 tREFIpb, 4 tREFW
010b: 2 tREFI, 2 tREFIpb, 2 tREFW
011b: 1 tREFI, 1 tREFIpb, 1 tREFW (85C)
100b: 0.5 tREFI, 0.5 tREFIpb, 0.5 tREFW, no AC timing derating
101b: 0.25 tREFI, 0.25 tREFIpb, 0.25 tREFW, no AC timing derating
110b: 0.25 tREFI, 0.25 tREFIpb, 0.25 tREFW, timing derating required
111b: SDRAM high-temperature operating limit exceeded
0b: OP[2:0] value has not changed since last read of MR4
1b: OP[2:0] value has changed since last read of MR4
1.
2.
3.
4.
5.
6.
42
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2014 Micron Technology, Inc. All rights reserved.
OP6
OP5
OP4
OP3
OP2
OP1
OP0
OP1
OP0
OP2
OP1
OP0
OP2
OP1
Manufacturer ID
Type
OP
Definition
Read-only
OP[7:0]
0000 0011b:
All others: Reserved
OP6
OP5
OP4
OP3
OP2
Revision ID1
Note:
1. MR6 is vendor-specific.
Type
OP
Definition
Read-only
OP[7:0]
OP6
OP5
OP4
OP3
Revision ID2
Type
OP
Read-only
OP[7:0]
Definition
RFU
1. MR7 is vendor-specific.
OP6
I/O width
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OP5
OP4
OP3
Density
43
OP0
Type
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2014 Micron Technology, Inc. All rights reserved.
Type
OP
Type
Read-only
OP[1:0]
Definition
11b: LPDDR3
All other states reserved
Density
Read-only
OP[5:2]
0110b: 4Gb
1110b: 6Gb
0111b: 8Gb
1101b: 12Gb
1000b: 16Gb
1001b: 32Gb
All others: Reserved
I/O width
Read-only
OP[7:6]
00b: x32
01b: x16
All others: Reserved
OP6
OP5
OP4
OP3
OP2
OP1
OP0
OP2
OP1
OP0
OP6
OP5
OP4
OP3
Calibration code
Write-only
Notes:
PDF: 09005aef85b4b06b
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OP
OP[7:0]
Definition
0xFF: CALIBRATION command after initialization
0xAB: Long calibration
0x56: Short calibration
0xC3: ZQ reset
All others: Reserved
1. The device ignores calibration commands when a reserved value is written into MR10.
2. See AC Timing table for the calibration latency.
3. If ZQ is connected to VSSCA through RZQ, either the ZQ calibration function (see MRW ZQ
CALIBRATION Command) or default calibration (through the ZQ RESET command) is supported. If ZQ is connected to VDDCA, the device operates with default calibration and ZQ
CALIBRATION commands are ignored. In both cases, the ZQ connection must not change
after power is supplied to the device.
4. Devices that do not support calibration ignore the ZQ CALIBRATION command.
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OP6
OP5
OP4
OP3
Reserved
OP2
OP1
PD CTL
OP0
DQ ODT
Type
OP
DQ ODT
Write-only
OP[1:0]
PD control
Write-only
OP[2]
Note:
Definition
00b: Disable (default)
01b: RZQ/4 (Note1)
10b: RZQ/2
11b: RZQ/1
00b: ODT disabled by DRAM during power-down (default)
01b: ODT enabled by DRAM during power-down
1. RZQ/4 is supported for LPDDR3-1866 and LPDDR3-2133 devices. RZQ/4 support is optional for LPDDR3-1333 and LPDDR3-1600 devices. Consult Micron specifications for RZQ/4
support for LPDDR3-1333 and LPDDR3-1600.
OP6
OP5
OP4
OP3
OP2
OP1
OP0
Type
OP
Write-only
OP[7:0]
Definition
0b: Refresh enable to the bank = unmasked (default)
1b: Refresh blocked = masked
OP6
OP5
OP4
OP3
OP2
OP1
OP0
Type
OP
Write-only
OP[7:0]
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Definition
0b: Refresh enable to the segment = unmasked (default)
1b: Refresh blocked = masked
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6Gb2, 8Gb,
12Gb2 & 16Gb
32Gb
R[13:11]
R[14:12]
TBD
Segment
OP
Segment Mask
XXXXXXX1
000b
XXXXXX1X
001b
XXXXX1XX
010b
XXXX1XXX
011b
XXX1XXXX
100b
XX1XXXXX
101b
X1XXXXXX
110b
1XXXXXXX
111b
Notes:
OP6
OP5
OP4
OP3
OP2
OP1
OP0
X or 0xFCh
Note:
1. For additional information on MRW RESET, see the Mode Register Write (MRW) section.
MA
Address
Restriction
MR[12:15]
MA[7:0]
0Ch-0Fh
Reserved
Reserved
MR[18:31]
12h1Fh
Reserved
Reserved
MR[33:39]
21h27h
DNU
DNU
MR[43:47]
2Bh2Fh
DNU
DNU
MR[49:62]
31h3Eh
Reserved
Reserved
MR[64:255]
40hFFh
Reserved
Reserved
Note:
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OP7
OP6
OP5
OP4
OP3
OP2
OP1
OP0
46
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T0
T1
T2
T3
tIS tIH
tIS tIH
CK_c
CK_t
CS_n
VIL(DC)
VIL(AC)
VIH(AC)
tIS tIH
CA[9:0]
CA
rise
CA
fall
CA
rise
NOP
CMD
VIH(DC)
tIS tIH
CA
fall
Command
CA
rise
CA
fall
NOP
Dont Care
CA
rise
CA
fall
Command
Transitioning data
1. Setup and hold conditions also apply to the CKE pin. For timing diagrams related to the
CKE pin, see the Power-Down section.
Note:
T0
T1
Tx
Tx + 1
CK_c
CK_t
tIHCKE
CKE
VIHCKE
tISCKE
tIHCKE
VILCKE
VILCKE
tISCKE
VIHCKE
PDF: 09005aef85b4b06b
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1. After CKE is registered LOW, the CKE signal level is maintained below VILCKE for tCKE
specification (LOW pulse width).
2. After CKE is registered HIGH, the CKE signal level is maintained above VIHCKE for tCKE
(HIGH pulse width).
47
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ACTIVATE Command
The ACTIVATE command is issued by holding CS_n LOW, CA0 LOW, and CA1 HIGH at
the rising edge of the clock. The bank addresses BA[2:0] are used to select the desired
bank. Row addresses are used to determine which row to activate in the selected bank.
The ACTIVATE command must be applied before any READ or WRITE operation can be
executed. The device can accept a READ or WRITE command at tRCD after the ACTIVATE command is issued. After a bank has been activated, it must be precharged before
another ACTIVATE command can be applied to the same bank. The bank active and
precharge times are defined as tRAS and tRP, respectively. The minimum time interval
between successive ACTIVATE commands to the same bank is determined by the RAS
cycle time of the device (tRC). The minimum time interval between ACTIVATE commands to different banks is tRRD.
Figure 11: ACTIVATE Command
CK_c
CK_t
CA[9:0]
Bank n
row addr Row addr
Bank m
Bank n
row addr Row addr col addr
Col addr
Bank n
row addr Row addr
Bank n
tRRD
tRCD
tRP
tRAS
tRC
CMD
ACTIVATE
ACTIVATE
NOP
READ
PRECHARGE
NOP
NOP
ACTIVATE
1. A PRECHARGE ALL command uses tRPab timing, and a single-bank PRECHARGE command uses tRPpb timing. In this figure, tRP denotes either an all-bank PRECHARGE or a
single-bank PRECHARGE.
Note:
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Tn+
Tm
Tm+
Tx
Tx+
Ty
Ty + 1
Ty + 2
Tz
Tz + 1
Tz + 2
CK_c
CK_t
CA[9:0]
Bank Bank
A
A
Bank Bank
B
B
tRRD
CMD ACTIVATE
NOP
Bank Bank
C
C
tRRD
ACTIVATE
NOP
Bank Bank
D
D
Bank Bank
E
E
tRRD
ACTIVATE
NOP
ACTIVATE
NOP
NOP
NOP
ACTIVATE
NOP
tFAW
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tCH
tCL
RL
RL + BL/ 2
CK_c
CK_t
tHZ(DQS)
tDQSCK
tLZ(DQS)
tRPST
tRPRE
DQS_c
DQS_t
tQH
tQH
tDQSQmax
tDQSQmax
DOUT
DQ
DOUT
DOUT
DOUT
tLZ(DQ)
DOUT
DOUT
DOUT
DOUT
tHZ(DQ)
Transitioning data
Note:
T1
T2
T12
Ta-1
Ta
Ta+1
Ta+2
Ta+3
Ta+4
CK_c
CK_t
RL = 12
CA[9:0]
CMD
Bank n
col addr
Col addr
READ
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
tDQSCK
DQS_c
DQS_t
DQ
DOUTA0
DOUTA1
DOUTA2
DOUTA3
DOUTA4
DOUTA5
DOUTA6
DOUTA7
Transitioning data
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T1
T2
T12
T13
T14
T15
T16
T17
CK_c
CK_t
RL = 12
CA[9:0]
Bank n
col addr
CMD
Col addr
READ
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
tDQSCK
DQS_c
DQS_t
DQ
DOUTA0
DOUTA1
DOUTA2
DOUTA3 DOUTA4
DOUTA5
DOUTA6
DOUTA7
Transitioning data
T1
T2
T12
Ta - 1
Ta
Ta + 1
Ta + 2
Ta + 3
Ta + 4
Ta + 9
Ta + 10
CK_c
CK_t
RL = 12
CA[9:0]
CMD
Bank n
col addr
BL/2
WL = 6
Bank n
col addr
Col addr
READ
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Col addr
WRITE
tDQSCK
NOP
NOP
NOP
tDQSSmin
DQS_c
DQS_t
DQ
DOUTA0
DOUTA1
DOUTA2
DOUTA3
DOUTA4
DOUTA5
DOUTA6
DOUTA7
DIN A0
DIN A1
DIN
Transitioning Data
The minimum time from the burst READ command to the burst WRITE command is
defined by the read latency (RL) and the burst length (BL). Minimum READ-to-WRITE
latency is RL + RU(tDQSCK(MAX)/tCK) + BL/2 + 1 - WL clock cycles.
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T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
CK_c
CK_t
RL = 6
CA[9:0]
tCCD
CMD
Bank n
Col addr b
col addr b
Bank n
Col addr a
col addr a
READ
tCCD
=4
NOP
NOP
NOP
READ
Bank n
Col addr c
col addr c
Bank n
Col addr d
col addr d
=4
NOP
NOP
NOP
READ
NOP
NOP
NOP
READ
NOP
NOP
NOP
DQS_c
DQS_t
DQ
DOUTA0
DOUTA1
DOUTA2
DOUTA3
DOUTA4
DOUTA5
DOUTA6
DOUTA7
DOUTB0
DOUTB1
DOUTB2
DOUTB3
DOUTB4
DOUTB5
DOUTB6
DOUTB7
DOUTC0
DOUTC1
Transitioning data
The seamless burst READ operation is supported by enabling a READ command at every fourth clock cycle for BL = 8 operation. This operation is supported as long as the
banks are activated, whether the accesses read the same or different banks.
tDQSCK
Delta Timing
To allow the system to track variations in tDQSCK output across multiple clock cycles,
three parameters are provided: tDQSCKDL (delta long), tDQSCKDM (delta medium),
and tDQSCKDS (delta short). Each of these parameters defines the change in tDQSCK
over a short, medium, or long rolling window, respectively. The definition for each
tDQSCK-delta parameter is shown in the figures below.
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Tn + 1
Tn + 2
Tn + 9
Tn + 10
Ta
Ta + 1
Ta + 12
CK_c
CK_t
RL = 10
CA
[9:0]
Bankn
Col addr
col addr
CMD
READ
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
tDQSCKn
DQS_c
DQS_t
DQ
DOUTA0
DOUTA1
32ms maximum
Tm
Tm + 1
Tm + 2
Tm + 9
Tm + 10
Tb
Tb + 1
Tb + 2
CK_c
CK_t
RL = 10
CA
[9:0]
Bankn
Col addr
col addr
CMD
READ
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
tDQSCKm
DQS_c
DQS_t
DQ
DOUTA0
DOUTA1
32ms maximum
Transitioning data
Notes:
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Tn
Tn + 1
Tn + 2
Tn + 9
Tn + 10
Ta
Ta + 1
Ta + 2
CK_c
CK_t
RL = 10
CA
[9:0]
Bank n
col addr
CMD
Col addr
READ
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
tDQSCKn
DQS_c
DQS_t
DQ
DOUTA0
DOUTA1
DOUTA2
DOUTA3
DOUTA4
1.6s maximum
Tm
Tm + 1
Tm + 2
Tm + 9
Tm + 10
Tb
Tb + 1
Tb + 2
CK_c
CK_t
RL = 10
CA
[9:0]
Bank n
col addr
CMD
Col addr
READ
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
tDQSCKm
DQS_c
DQS_t
DQ
DOUTA0
DOUTA1
DOUTA2
DOUTA3
DOUTA4
1.6s maximum
Transitioning data
Notes:
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Tn + 1
Tn + 2
Tn + 9
Tn + 10
Ta
Ta + 1
Ta + 2
CK_c
CK_t
RL = 10
CA
[9:0]
Bank n
col addr
CMD
Col addr
READ
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
tDQSCKn
DQS_c
DQS_t
DQ
DOUTA0
DOUTA1
DOUTA2
DOUTA3 DOUTA4
160ns maximum
Tm
Tm + 1
Tm + 2
Tm + 9
Tm + 10
Tb
Tb + 1
Tb + 2
CK_c
CK_t
RL = 10
CA
[9:0]
Bank n
col addr
CMD
Col addr
READ
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
tDQSCKm
DQS_c
DQS_t
DQ
DOUTA2
DOUTA3
DOUTA4
DOUTA5
DOUTA6
DOUTA7
DOUTA0
DOUTA2
DOUTA3
DOUTA4
DOUTA5
DOUTA6
DOUTA2
DOUTA3
DOUTA4
DOUTA5
DOUTA6
DOUTA7
160ns maximum
Transitioning data
Notes:
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tDQSH
tDQSL
tWPST
DQS_c
DQS_t
tWPRE
VIH(AC)
DQ
VIH(AC)
VIH(DC)
DIN
VIL(AC) tDS
tDH
DIN
VIL(DC)
tDS
tDH
DIN
tDS
tDH
VIH(DC)
DIN
VIL(AC) tDS
VIH(AC)
VIH(DC)
VIH(AC)
VIH(DC)
VIL(AC)
VIL(DC)
VIL(AC)
VIL(DC)
tDH
VIL(DC)
DM
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Dont Care
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Ta
Ta + 1
...
Ta + 5
Tx
Tx + 1
Ty
Ty + 1
CK_c
CK_t
WL
CA[9:0]
CMD
Bank n
col addr
Col addr
WRITE
NOP
NOP
tDQSS
DIN A0
tDQSS
(MIN)
DQ
NOP
tDSS
(MAX)
DQ
Case 2: tDQSS (MIN)
DQS_c
DQS_t
Bank n
tDSH
DIN A0
NOP
tDSS
DIN A1
DIN A6
NOP
PRECHARGE
ACTIVATE
NOP
tWR
tRP
tWR
tRP
DIN A7
tDSH
DIN A1
DIN A2
DIN A7
Dont Care
Transitioning Data
CK_c
T1
begins
tWPRE
DQS_t - DQS_c
0V
tWPRE
T2
Resulting differential
signal relevant for
tWPRE specification
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tWPRE
57
ends
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CK_c
tWPST
DQS_t - DQS_c
0V
Resulting differential
signal relevant for
tWPST specification
T1
begins
tWPST
T2
ends
tWPST
Tx
Tx + 1
Tx + 2
Tx + 5
Tx + 9
Tx + 10
Tx + 11
CK_c
CK_t
RL
WL
CA[9:0]
Bank m
Col addr a
col addr a
Bank n
Col addr b
col addr b
tWTR
CMD
WRITE
NOP
NOP
NOP
NOP
NOP
READ
NOP
NOP
DQS_c
DQS_t
DQ
DIN A0
DIN A1
DIN A7
Dont Care
Notes:
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Transitioning Data
1. The minimum number of clock cycles from the burst WRITE command to the burst READ
command for any bank is [WL + 1 + BL/2 + RU(tWTR/tCK)].
2. tWTR starts at the rising edge of the clock after the last valid input data.
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T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
CK_c
CK_t
WL = 4
CA[9:0]
Bankm
Col addr a
col addr a
tCCD
CMD
WRITE
Bankn
Col addr b
col addr b
Bankn
Col addr c
col addr c
Bankn
Col addr d
col addr d
=4
NOP
NOP
NOP
WRITE
NOP
NOP
NOP
WRITE
NOP
NOP
NOP
WRITE
NOP
DQS_c
DQS_t
DQ
DIN A0
DIN A1
DIN A2
DIN A3
DIN A4
DIN A5
DIN A6
DIN A7
DIN B0
DIN B1
DIN B2
DIN B3
DIN B4
DIN B5
Dont Care
Note:
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DIN B6
DIN B7
DIN C0
DIN C1
Transitioning Data
1. The seamless burst WRITE operation is supported by enabling a WRITE command every
four clocks for BL = 8 operation. This operation is supported for any activated bank.
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DQ
tDS
VIH(AC)
tDH
VIH(DC) VIH(AC)
tDS
tDH
VIH(DC)
DM
VIL(AC)
VIL(DC) VIL(AC)
VIL(DC)
Dont Care
WL
CMD
Case 1:
WRITE
t DQSS
(MIN)
tDQSS
(MIN)
DQS_t
DQS_c
DOUT 1
DQ
DOUT 0
DOUT 2 DOUT 3
DOUT 7
DM
tDQSS
(MAX)
DQS_t
DQS_c
DOUT 1
DQ
DOUT 0
DM
Dont Care
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PRECHARGE Command
The PRECHARGE command is used to precharge or close a bank that has been activated. The PRECHARGE command is initiated with CS_n LOW, CA0 HIGH, CA1 HIGH,
CA2 LOW, and CA3 HIGH at the rising edge of the clock. The PRECHARGE command
can be used to precharge each bank independently or all banks simultaneously. The AB
flag and the bank address bits BA0, BA1, and BA2 are used to determine which bank(s)
to precharge. The precharged bank(s) will be available for subsequent row access tRPab
after an all-bank PRECHARGE command is issued, or tRPpb after a single-bank PRECHARGE command is issued.
To ensure that LPDDR3 devices can meet the instantaneous current demand required
to operate, the row precharge time (tRP) for an all bank PRECHARGE (tRPab) will be longer than the row precharge time for a single-bank PRECHARGE (tRPpb). ACTIVATE to
PRECHARGE timing is shown in the ACTIVATE Command figure.
Table 48: Bank Selection for PRECHARGE by Address Bits
AB (CA4r)
BA2 (CA9r)
BA1 (CA8r)
BA0 (CA7r)
Precharged Bank(s)
8-Bank Device
Bank 0 only
Bank 1 only
Bank 2 only
Bank 3 only
Bank 4 only
Bank 5 only
Bank 6 only
Bank 7 only
Dont Care
Dont Care
Dont Care
All banks
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T0
T1
Tx
Tx + 1
Tx + 2
Tx + 3
Tx + 4
Tx + 5
CK_c
CK_t
RL
CA[9:0]
Bank m
col addr a Col addr a
Bank m
Row addr
row addr
Bank m
tRP
tRTP
CMD
READ
NOP
NOP
PRECHARGE
NOP
NOP
NOP
ACTIVATE
NOP
DQS_c
DQS_t
DQ
DOUTA0
DOUTA1
DOUTA2
DOUTA3
DOUTA4
DOUTA5
DOUTA6
DOUTA7
Transitioning Data
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Tx
Tx + 1
Tx + 4
Tx + 5
Ty
Ty + 1
Tz
Tz + 1
CK_c
CK_t
WL
CA[9:0]
Bankn
col addr
Col addr
tRP
tWR
CMD
WRITE
Bankn
NOP
NOP
tDQSS
NOP
NOP
(MAX)
PRECHARGE
NOP
ACTIVATE
NOP
DQS_c
DQS_t
DQ
tDQSS
DIN A0
DIN A5
DIN A6
DIN A1
DIN A6
DIN A7
DIN A7
(MIN)
DQS_c
DQS_t
DQ
DIN A0
Dont Care
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Transitioning Data
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T1
Tx
Tx + 1
Tx + 2
Tx + 3
Tx + 4
Tx + 5
CK_c
CK_t
RL
CA[9:0]
Bankm
Col addr a
col addr a
Bankm
Row addr
row addr
tRTP
CMD
READ w/AP
NOP
tRPpb
NOP
NOP
NOP
NOP
NOP
ACTIVATE
NOP
DQS_c
DQS_t
DQ
DOUT A0
DOUT A1
DOUT A2
DOUT A3
DOUT A4
DOUT A5
DOUT A6
DOUT A7
Transitioning Data
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Tx
Tx + 1
...
Tx + 5
Ty
Ty + 1
Tz
Tz + 1
CK_c
CK_t
WL
CA[9:0]
Bankn
col addr
Col addr
tWR
CMD
WRITE
NOP
NOP
NOP
NOP
tRPpb
NOP
NOP
ACTIVATE
NOP
DQS_t
DQS_c
DQ
DIN A0
DIN A1
DIN A6
DIN A7
Dont Care
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Transitioning Data
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WRITE
WRITE w/AP
To Command
RU(tRTP/tCK))
-4
PRECHARGE ALL
RU(tRTP/tCK))
-4
PRECHARGE ALL
-4+
Notes
CLK
CLK
1, 2
1
1
RU(tRPpb/
BL/2 + MAX(4,
tCK)
Illegal
RL + BL/2 + RU(tDQSCKmax/tCK) - WL + 1
Illegal
BL/2
3
RU(tWR/tCK)
+1
WL + BL/2 +
PRECHARGE ALL
WL + BL/2 + RU(tWR/tCK) + 1
CLK
1
1
CLK
WL + BL/2 +
RU(tWR/tCK)
WL + BL/2 +
RU(tWR/tCK)
Illegal
BL/2
Illegal
PRECHARGE
ALL
RU(tRTP/tCK))
Unit
PRECHARGE ALL
PRECHARGE
PRECHARGE ALL
PRECHARGE
PRECHARGE ALL
Notes:
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+1+
1
RU(tRPpb/tCK)
WL + BL/2 +
+1
RU(tWTR/tCK)
+1
3
CLK
1
1
CLK
1
1
1. For a given bank, the PRECHARGE period should be counted from the latest PRECHARGE
command, which will be either a one-bank PRECHARGE command or a PRECHARGE ALL
command, issued to that bank. The PRECHARGE period is satisfied after tRP, depending
on the latest PRECHARGE command issued to that bank.
2. Any command issued during the specified minimum delay time is illegal.
3. After a READ with auto precharge command, seamless READ operations to different
banks are supported. After a WRITE with auto precharge command, seamless WRITE operations to different banks are supported. READ with auto precharge and WRITE with
auto precharge commands must not be interrupted or truncated.
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REFRESH Command
The REFRESH command is initiated with CS_n LOW, CA0 LOW, CA1 LOW, and CA2
HIGH at the rising edge of the clock. Per-bank REFRESH is initiated with CA3 LOW at
the rising edge of the clock. All-bank REFRESH is initiated with CA3 HIGH at the rising
edge of the clock.
A per-bank REFRESH command (REFpb) performs a per-bank REFRESH operation to
the bank scheduled by the bank counter in the memory device. The bank sequence for
per-bank REFRESH is fixed to be a sequential round-robin: 0-1-2-3-4-5-6-7-0-1-.... The
bank count is synchronized between the controller and the SDRAM by resetting the
bank count to zero. Synchronization can occur upon issuing a RESET command or at
every exit from self refresh.
A bank must be idle before it can be refreshed. The controller must track the bank being
refreshed by the per-bank REFRESH command.
The REFpb command must not be issued to the device until the following conditions
have been met (see the REFRESH Command Scheduling Separation Requirements table):
tRFCab
The target bank is inaccessible during per-bank REFRESH cycle time (tRFCpb); however, other banks within the device are accessible and can be addressed during the cycle.
During the REFpb operation, any of the banks other than the one being refreshed can
be maintained in an active state or accessed by a READ or WRITE command. When the
per-bank REFRESH cycle has completed, the affected bank will be in the idle state.
After issuing REFpb, the following conditions must be met (see the REFRESH Command Scheduling Separation Requirements table):
tRFCpb
tRFCpb
An all-bank REFRESH command (REFab) issues a REFRESH command to all banks. All
banks must be idle when REFab is issued (for instance, by issuing a PRECHARGE ALL
command prior to issuing an all-bank REFRESH command). REFab also synchronizes
the bank count between the controller and the SDRAM to zero. The REFab command
must not be issued to the device until the following conditions have been met (see the
REFRESH Command Scheduling Separation Requirements table):
tRFCab has been satisfied following the prior REFab command
tRFCpb has been satisfied following the prior REFpb command
tRP has been satisfied following the prior PRECHARGE commands
When an all-bank REFRESH cycle has completed, all banks will be idle. After issuing REFab:
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Minimum
Delay From
tRFCab
REFab
To
Notes
REFab
ACTIVATE command to any bank
REFpb
tRFCpb
REFpb
REFab
ACTIVATE command to same bank as REFpb
REFpb
tRRD
REFpb
ACTIVATE
REFpb
Note:
In general, an all bank REFRESH command needs to be issued to the device regularly
every tREFI interval. To allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh interval is provided for postponing
and pulling in the refresh command. A maximum of eight REFRESH commands can be
postponed during operation of the device, but at no point in time are more than a total
of eight REFRESH commands allowed to be postponed. In the case where eight REFRESH commands are postponed in a row, the resulting maximum interval between the
surrounding REFRESH commands is limited to 9 tREFI. A maximum of eight additional REFRESH commands can be issued in advance (pulled in), with each one reducing
the number of regular REFRESH commands required later by one. Note that pulling in
more than eight REFRESH commands in advance does not reduce the number of regular REFRESH commands required later; therefore, the resulting maximum interval between two surrounding REFRESH commands is limited to 9 x tREFI. At any given time, a
maximum of 16 REFRESH commands can be issued within 2 x tREFI.
For per bank refresh, a maximum of 8 8 per bank REFRESH commands can be postponed or pulled in for scheduling efficiency. At any given time, a maximum of 2 8 per
bank REFRESH commands may be issued within 2 tREFI.
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T1
REF
NOP
Ta0
Ta1
Tb0
Tb1
Tb2
Tb3
Vaild
Vaild
Vaild
Vaild
Tc0
Tc1
Tc2
Tc3
REF
Vaild
Vaild
Vaild
CK_c
CK_t
CMD
NOP
REF
tRFC
NOP
tRFC
NOP
Vaild
(MIN)
tREFI
(MAX 9 tREF)
1. Only NOP commands are allowed after the REFRESH command is registered until tRFC
(MIN) expires.
2. The time interval between two REFRESH commands may be extended to a maximum of
9 tREFI.
Notes:
tREFI
tREFI
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T0
T1
T2
T3
T4
Tx
Tx + 1
Ty
Ty + 1
CK_c
CK_t
CA[9:0]
CMD
AB
PRECHARGE
NOP
NOP
REFab
tRPab
NOP
NOP
REFab
tRFCab
Any
tRFCab
T1
Tx
Tx + 1
Tx + 2
Ty
Ty + 1
Tz
Tz + 1
CK_c
CK_t
CA[9:0]
CMD
Bank 1
Row A
AB
PRECHARGE
NOP
NOP
tRPab
REFpb
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tRFCpb
REFRESH to bank 1
REFRESH to bank 0
Notes:
ACTIVATE
REFpb
tRFCpb
Row A
ACTIVATE command
to bank 1
1. In the beginning of this example, the REFpb bank counter points to bank 0.
2. Operations to banks other than the bank being refreshed are supported during the
tRFCpb period.
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CK
tCPDED
tIHCKE
tIHCKE
CKE
tISCKE
tISCKE
CS_n
tCKESR (MIN)
CMD
Valid Enter
SR
tXSR (MIN)
Exit
SR
NOP NOP
1. Input clock frequency can be changed or stopped during self refresh, provided that
upon exiting self-refresh, a minimum of two cycles of stable clocks are provided, and the
clock frequency is between the minimum and maximum frequencies for the particular
speed grade.
2. The device must be in the all-banks-idle state prior to entering self refresh mode.
3. tXSR begins at the rising edge of the clock after CKE is driven HIGH.
4. A valid command can be issued only after tXSR is satisfied. NOPs must be issued during
tXSR.
Notes:
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Segment 0
Segment 1
Segment 2
Segment 3
Segment 4
Segment 5
Segment 6
Segment 7
Note:
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1. This table provides values for an eight-bank device with REFRESH operations masked to
banks 1 and 7 and to segments 2 and 7.
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T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
CK_c
CK_t
RL = 8
CA[9:0]
Register
A
Register
A
Register
B
Register
B
tMRR
tMRR
CMD
MRR1
NOP2
NOP2
NOP2
MRR1
NOP2
NOP2
NOP2
Valid
Valid
Valid
Valid
Valid
Valid
Valid
DQS_c
DQS_t
DQ[7:0]3
DOUTA
DOUTB
DQ[MAX:8]
Transitioning data
Undefined
1. MRRs to DQ calibration registers MR32 and MR40 are described in the DQ Calibration
section.
2. Only the NOP command is supported during tMRR.
3. Mode register data is valid only on DQ[7:0] on the first beat. Subsequent beats contain
valid but undefined data. DQ[MAX:8] contain valid but undefined data for the duration
of the MRR burst.
4. Minimum MRR to write latency is RL + RU(tDQSCK (MAX)/tCK) + 8/2 + 1 - WL clock cycles.
5. Minimum MRR to MRW latency is RL + RU(tDQSCK (MAX)/tCK) + 8/2 + 1 clock cycles.
6. In this example, RL = 8 for illustration purposes only.
Notes:
After a prior READ command, the MRR command must not be issued before BL/2 clock
cycles have completed. Following a WRITE command, the MRR command must not be
issued before WL + 1 + BL/2 + RU( tWTR/tCK) clock cycles have completed, as READ
bursts and WRITE bursts must not be truncated my MRR.
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T1
Tx
Tx+1
Tx+2
Tx+3
Tx+4
Tx+5
Tx+6
Tx+7
Tx+8
Tx+9
CK_c
CK_t
RL
CA[9:0]
Register
B
Register
B
tMRR
CMD
READ
NOP1
NOP1
NOP1
NOP1
MRR
NOP1
NOP1
Valid
DQS_c
DQS_t
DQ[7:0]
DOUT A0
DOUT A1
DOUT A2
DOUT A3
DOUT A0
DOUT A1
DOUT A2
DOUT A3
DQ[MAX:8]
DOUT A0
DOUT A1
DOUT A2
DOUT A3
DOUT A0
DOUT A1
DOUT A2
DOUT A3
DOUT B
Transitioning data
Notes:
Undefined
1. The minimum number of clock cycles from the burst READ command to the MRR command is BL/2.
2. Only the NOP command is supported during tMRR.
Tx
Tx+1
Tx+2
Tx+3
Tx+4
Tx+5
Tx+6
Ty
Ty+1
Ty+2
CK_c
CK_t
WL
CA[9:0]
Bankn
col addr a
RL
Col
addr a
Register
B
Register
B
t WTR
CMD
Valid
WRITE
tMRR
MRR1
NOP2
NOP2
DQS_c
DQS_t
DQ
DIN A0
DIN A1
DIN A2
DIN A3
DIN A4
DIN A5
DIN A6
DIN A7
Transitioning data
Notes:
1. The minimum number of clock cycles from the burst WRITE command to the MRR command is [WL + 1 + BL/2 + RU(tWTR/tCK)].
2. Only the NOP command is supported during tMRR.
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tCKE (MIN)
CKE
tISCKE
CS_n
tXP(MIN)
CMD
Exit
PD
tMRRI
NOP
NOP
Valid1
Valid1 Valid1
tMRR
MRR
Valid
Valid
Dont Care
Note:
Temperature Sensor
LPDDR3 devices feature a temperature sensor whose status can be read from MR4. This
sensor can be used to determine an appropriate refresh rate, determine whether AC
timing derating is required in the extended temperature range, and/or monitor the operating temperature. Either the temperature sensor or the device operating temperature
can be used to determine whether operating temperature requirements are being met
(see the Operating Temperature Range table).
Temperature sensor data can be read from MR4 using the mode register read protocol.
Upon exiting self-refresh or power-down, the device temperature status bits will be no
older than tTSI.
When using the temperature sensor, the actual device case temperature may be higher
than the operating temperature specification that applies for the standard or extended
temperature ranges (see the Operating Temperature Range table). For example, T CASE
could be above 85C when MR4[2:0] equals 011b.
To ensure proper operation using the temperature sensor, applications must accommodate the following table.
Table 52: Temperature Sensor Definitions and Operating Conditions
Parameter
Description
Symbol
Min/Max
Value
Unit
System temperature
gradient
Maximum temperature gradient experienced by the memory device at the temperature of interest over a range of 2C
TempGradient
MAX
System-dependent
C/s
ReadInterval
MAX
System-dependent
ms
Temperature sensor
interval
tTSI
MAX
32
ms
System response
delay
SysRespDelay
MAX
System-dependent
ms
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Description
Device temperature
margin
Symbol
Min/Max
Value
Unit
TempMargin
MAX
These devices accommodate the temperature margin between the point at which the
device temperature enters the extended temperature range and the point at which the
controller reconfigures the system accordingly. To determine the required MR4 polling
frequency, the system must use the maximum TempGradient and the maximum response time of the system according to the following equation:
TempGradient (ReadInterval + tTSI + SysRespDelay) 2C
Device
Temp
Margin
ient
Grad
Temp
2C
MR4
Trip Level
tTSI
MR4 = 0x03
MR4 = 0x86
MR4 = 0x86
MR4 = 0x86
MR4 = 0x06
Time
SysRespDelay
MRR MR4 = 0x86
DQ Calibration
LPDDR3 devices feature a DQ calibration function that outputs one of two predefined
system timing calibration patterns. An MRR operation to MR32 (pattern A) or and MRR
operation to MR40 (pattern B) will return the specified pattern on DQ0 and DQ8for
x32 devices, on DQ0, DQ8, DQ16 and DQ24.
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T1
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
CK_c
CK_t
RL = 6
Reg 40 Reg 40
tMRR
CMD
MRR
tMRR
=4
NOP1
NOP1
NOP1
=4
NOP1
NOP
MRR
NOP1
NOP1
DQS_c
DQS_t
Pattern A
Pattern B
DQ0
DQ[7:1]
DQ8
DQ[15:9]
DQ16
DQ[23:17]
DQ24
DQ[31:25]
x16
x32
Transitioning data
Pattern
MR#
Bit
Time
0
Bit
Time
1
Bit
Time
2
Bit
Time
3
Bit
Time
4
Bit
Time
5
Bit
Time
6
Bit
Time
7
Pattern
A
MR32
Pattern
B
MR40
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T1
T2
Tx
Tx + 1
Tx + 2
Ty 1
Ty + 1
Ty + 2
CK_c
CK_t
tMRW
CA[9:0]
CMD
tMRW
MR addr MR data
MRW
MR addr MR data
NOP2
NOP2
NOP2
MRW
NOP2
Valid
Notes:
MRW can be issued only when all banks are in the idle precharge state. One method of
ensuring that the banks are in this state is to issue a PRECHARGE ALL command.
Command
Intermediate State
Next State
MRR
MRW
MRW (RESET)
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Command
Intermediate State
Next State
Bank(s) active
MRR
Bank(s) active
MRW
Not allowed
Not allowed
MRW (RESET)
Not allowed
Not allowed
Td
Te
CK_t
CK_c
CKE
CA[9:0]
FCh
CMD
FCh
FCh
Reg
B
FCh
MRW
(Optional)
MRW
Reg
B
MRR
tINIT3
tINIT4
CS_n
Optional CA/CMD
Optional CS_n
1. Optional MRW RESET command and optional CS_n assertion are allowed. When the optional MRW RESET command is used, tINIT4 starts at Td'.
Note:
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Where T sens = MAX (dRONdT) and V sens = MAX (dRONdV) define temperature and voltage sensitivities.
For example, if T sens = 0.75%/C, V sens = 0.20%/mV, T driftrate = 1C/sec, and V driftrate =
15 mV/sec, then the interval between ZQCS commands is calculated as:
1.5
= 0.4s
(0.75 1) + (0.20 15)
A ZQ calibration command can be issued only when the device is in the idle state with
all banks precharged.
No other activities can be performed on the data bus during calibration periods
(tZQINIT, tZQCL, or tZQCS). The quiet time on the data bus helps to accurately calibrate
output impedance. There is no required quiet time after the ZQRESET command. If
multiple devices share a single ZQ resistor, only one device can be calibrating at any given time. After calibration is complete, the ZQ ball circuitry is disabled to reduce power
consumption.
In systems sharing a ZQ resistor among devices, the controller must prevent tZQINIT,
and tZQCL overlap between the devices. ZQRESET overlap is acceptable. If the
ZQ resistor is absent from the system, ZQ must be connected to V DDCA. In this situation,
the device must ignore ZQ calibration commands, and the device will use the default
calibration settings.
tZQCS,
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T1
T2
T3
T4
T5
Tx
Tx + 1
Tx + 2
CK_c
CK_t
CA[9:0]
MR addr MR data
ZQINIT
tZQINIT
CMD
MRW
NOP
NOP
NOP
NOP
NOP
Valid
NOP
NOP
Valid
NOP
NOP
Valid
NOP
NOP
Valid
ZQCS
tZQCS
CMD
MRW
NOP
NOP
NOP
ZQCL
tZQCL
CMD
MRW
NOP
NOP
NOP
ZQRESET
tZQRESET
CMD
MRW
NOP
Notes:
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NOP
NOP
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MRW#42
(optional)4
CA[9:0]
MRW#42
(CA cal.Exit)
MRW#42
(optional)4
CS_n
CKE
tCACKEL
tCAMRD
tCAENT
tCACD
tADR
tADR
tCACKEH
tCAEXT
tMRZ
Even
DQ
CAx
R
CAy
R
Odd
DQ
CAx
R#
CAy
R#
Optional CA
Notes:
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Optional CS_n
Dont Care
1. Unused DQ must be valid HIGH or LOW during data output period. Unused DQ may
transition at the same time as the active DQ. DQS must remain static and not transition.
2. CA to DQ mapping change via MR 48 omitted here for clarity of the timing diagram.
Both MR41 and MR48 training sequences must be completed before exiting the training
mode (MR42). To enable a CA to DQ mapping change, CKE must be driven HIGH prior to
issuance of the MRW 48 command. (See the steps in the CA Training Sequence section
for details.)
3. Because data-out control is asynchronous and will be an analog delay from when all the
CA data is available, tADR and tMRZ are defined from the falling edge of CK.
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The device may not properly recognize a MODE REGISTER WRITE command at normal
operation frequency before CA training is finished. Special encodings are provided for
CA training mode enable/disable.
MR41 and MR42 encodings are selected so that rising-edge and falling-edge values are
the same. The device will recognize MR41 and MR42 at normal operation frequency
even before CA timing adjustments have been made. Calibration data will be output
through DQ pins. CA to DQ mapping is described in the CA to DQ mapping (CA training
mode enabled with MR41) table.
After timing calibration with MR41 is finished, issue MRW to MR48 and calibrate the remaining CA pins (CA4 and CA9) using (DQ0/DQ1and DQ8/DQ9) as calibration data
output pins (see the CA to DQ mapping (CA training mode enabled with MR48) table).
Table 55: CA Training Mode Enable (MR41 (29H, 0010 1001b), OP = A4H (1010 0100b))
Clock Edge
CA0
CA1
CA2
CA3
CA4
CA5
CA6
CA7
CA8
CA9
CK rising edge
CK falling edge
Table 56: CA Training Mode Disable (MR42 (2AH, 0010 1010b), OP = A8H(1010 1000b))
Clock Edge
CA0
CA1
CA2
CA3
CA4
CA5
CA6
CA7
CA8
CA9
CK rising edge
CK falling edge
CA0
CA1
CA2
CA3
CA5
CA6
CA7
CA8
CK rising edge
DQ0
DQ2
DQ4
DQ6
DQ8
DQ10
DQ12
DQ14
CK falling edge
DQ1
DQ3
DQ5
DQ7
DQ9
DQ11
DQ13
DQ15
Note:
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Table 58: CA Training Mode Enable (MR48 (30H, 0011 0000b), OP = C0H (1100 0000b))
Clock Edge
CA0
CA1
CA2
CA3
CA4
CA5
CA6
CA7
CA8
CA9
CK rising edge
CK falling edge
CA4
CA9
CK rising edge
DQ0
DQ8
CK falling edge
DQ1
DQ9
Note:
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tWLH
tWLS
tWLH
CK_t
CK_c
CAs
CMD
CA
CA
MRW
CA
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
CA
MRW
NOP
NOP
NOP
Valid
tWLDQSEN
DQS_t
DQS_c
DQ
tWLMRD
tWLO
tDQSL
tWLO
tMRD
tDQSH
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ODT
To other
circuitry
such as
RCV,
...
VDDQ
RTT
Switch
DQ, DQS, DM
The switch is enabled by the internal ODT control logic, which uses the external ODT
pin and other control information. The value of R TT (ODT termination resistance value)
is determined by the settings of several mode register bits. The ODT pin will be ignored
if MR11 is programmed to disable ODT in self refresh, in deep power-down, in CKE
power-down (mode register option), and during READ operations.
Asychronous ODT
When enabled, the ODT feature is controlled asynchronously based on the status of the
ODT pin. ODT is off under any of the following conditions:
In asynchronous ODT mode, the following timing parameters apply when ODT operation is controlled by the ODT pin tODToff, tODTon.
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DQS Termination
DQ Termination
De-asserted
OFF
OFF
Asserted
ON
OFF
Read/DQ
Calibration
ZQ
Calibration
CA
Training
Write
Leveling
DQ
termination
Enabled
Disabled
Disabled
Disabled
Disabled
DQS
termination
Enabled
Disabled
Disabled
Disabled
Enabled
T1
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CK_t,
CK_c
Col add
CA[9:0]
Bank n
Col add
CMD
READ
RL = 12
DQS_t,
DQS_c
DO
0
DQ
DO
1
DO
2
DO
3
DO
4
DO
5
DO
6
DO
7
tDQSCK
ODT
DRAM_RTT
ODTon
ODToff
tODToff
tODTon
(MIN)
tODToff
(MIN)
tODTon
(MIN)
(MAX)
Dont Care
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T1
Tm-3
Tm-2
Tm-1
Tm
Tm+1
Tm+2
Tm+3
Tm+4
Tm+5
Tm+6
Tm+7
Tm+8
Tm+9
CK_t,
CK_c
Col add
CA[9:0]
Bank n
Col add
CMD
READ
RL = m
tHZ(DQS)
BL/2
DQS_t,
DQS_c
DO
0
DQ
DO
1
DO
2
DO
3
DO
4
DO
5
DO
6
DO
7
tDQSCK
ODT
ODTon
DRAM_RTT
ODToff
tAODToff
ODTon
tAODTon
Dont Care
Notes:
1. The automatic RTT turn-off delay, tAODToff, is referenced from the rising edge of RL - 2
clock at Tm-2.
2. The automatic RTT turn-on delay, tAODTon, is referenced from the rising edge of RL +
BL/2 clock at Tm+4.
Figure 53: ODT Timing During Power-Down, Self Refresh, Deep Power-Down Entry/Exit
T0
T1
T2
T3
Tm-1
Tm-2
Tm
Tm+1
Tm+2
Tn
CK_t,
CK_c
CKE
ODT
DRAM_RTT
ODTon
ODToff
tODTd
ODTon
tODTe
Dont Care
Note:
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Power-Down
Power-down is entered synchronously when CKE is registered LOW and CS_n is HIGH
at the rising edge of clock. A NOP command must be driven in the clock cycle following
the POWER-DOWN command. CKE must not go LOW while MRR, MRW, READ, or
WRITE operations are in progress. CKE can go LOW while any other operations, such as
ROW ACTIVATION, PRECHARGE, AUTO PRECHARGE, or REFRESH are in progress, but
the power-down IDD specification is not applied until such operations are complete.
Entering power-down deactivates the input and output buffers, excluding CKE. To ensure enough time to account for internal delay on the CKE signal path, two NOP commands are required after CKE is driven LOW. this timing period is defined as tCPDED.
CKE LOW results in deactivation of input receivers after tCPDED has expired. In powerdown mode, CKE must be held LOW; all other input signals are Dont Care. CKE LOW
must be maintained until tCKE is satisfied, and V REFCA must be maintained at a valid
level during power-down.
VDDQ can be turned off during power-down. If V DDQ is turned off, V REFDQ must also be
turned off. Prior to exiting power-down, both V DDQ and V REFDQ must be within their respective minimum/maximum operating ranges (see the AC and DC Operating Conditions section).
No refresh operations are performed in power-down mode. The maximum duration in
power-down mode is only limited by the refresh requirements outlined in the REFRESH
Command section.
The power-down state is exited when CKE is registered HIGH. The controller must drive
CS_n HIGH in conjunction with CKE HIGH when exiting the power-down state. CKE
HIGH must be maintained until tCKE is satisfied. A valid, executable command can be
applied with power-down exit latency tXP after CKE goes HIGH. Power-down exit latency is defined in the AC Timing table.
If power-down occurs when all banks are idle, this mode is referred to as idle powerdown; if power-down occurs when a row is active in any bank, this mode is referred to
as active power-down. For the description of ODT operation and specifications during
power-down entry and exit, see the On-Die Termination section.
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CK
tCPDED
tIHCKE
tIHCKE
tCKE
(MIN)
CKE
tISCKE
tISCKE
CS_n
tCKE
tXP
(MIN)
Exit
PD
(MIN)
Dont Care
Note:
1. Input clock frequency can be changed or the input clock stopped during power-down,
provided that the clock frequency is between the minimum and maximum specified frequencies for the speed grade in use and that prior to power-down exit, a minimum of
two stable clocks complete.
tCKE
tCKE
tCKE
CKE
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CK_c
CK_t
tCKE
tCKE
tCKE
tCKE
CKE
tXP
tXP
tREFI
CMD
REFRESH
Note:
REFRESH
1. The pattern shown can repeat over an extended period of time. With this pattern, all
AC and DC timing and voltage specifications with temperature and voltage drift are ensured.
T1
T2
Tx
Tx + 1
Tx + 2
Tx + 3
Tx + 4
Tx + 5
Tx + 6
Tx + 7
Tx + 8
Tx + 9
CK_c
CK_t
RL
tISCKE
CKE1, 2
CMD
READ
DQ
DQS_c
DQS_t
Notes:
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1. CKE must be held HIGH until the end of the burst operation.
2. CKE can be registered LOW at {RL + RU[tDQSCK(MAX)/tCK] + BL/2 + 1} clock cycles after
the clock on which the READ command is registered.
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T1
T2
Tx
Tx + 1
Tx + 2
Tx + 3
Tx + 4
Tx + 5
Tx + 6
Tx + 7
Tx + 8
Tx + 9
CK_c
CK_t
tISCKE
BL/23
RL
CKE1, 2
CMD
PRE4
READ w/AP
DQ
DQS_c
DQS_t
Notes:
1. CKE must be held HIGH until the end of the burst operation.
2. CKE can be registered LOW at [RL + RU(tDQSCK/tCK) + BL/2 + 1] clock cycles after the
clock on which the READ command is registered.
3. BL/2 with tRTP = 7.5ns and tRAS (MIN) is satisfied.
4. Start internal PRECHARGE.
T1
Tm
Tm + 1
Tm + 2
Tm + 3
Tm + 4
Tm + 5
Tx
Tx + 1
Tx + 2
Tx + 3
Tx + 4
CK_c
CK_t
WL
tISCKE
BL/2
CKE1
tWR
CMD
WRITE
DIN
DQ
DIN
DIN
DIN
DIN
DIN
DIN
DIN
DQS_c
DQS_t
Note:
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1. CKE can be registered LOW at [WL + 1 + BL/2 + RU(tWR/tCK)] clock cycles after the clock
on which the WRITE command is registered.
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T1
Tm
Tm + 1
Tm + 2
Tm + 3
Tm + 4
Tm + 5
Tx
Tx + 1
Tx + 2
Tx + 3
Tx + 4
CK_c
CK_t
WL
tISCKE
BL/2
CKE1
tWR
CMD
PRE2
WRITE w/AP
DQ
DIN
DIN
DIN
DIN
DIN
DIN
DIN
DIN
DQS_c
DQS_t
1. CKE can be registered LOW at [WL + 1 + BL/2 + RU(tWR/tCK) + 1] clock cycles after the
WRITE command is registered.
2. Start internal PRECHARGE.
Notes:
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
CK_c
CK_t
tISCKE
CKE1
tIHCKE
CMD
REFRESH
Note:
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1. CKE can go LOW tIHCKE after the clock on which the REFRESH command is registered.
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T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
CK_c
CK_t
tISCKE
CKE1
tIHCKE
CMD
ACTIVATE
1. CKE can go LOW at tIHCKE after the clock on which the ACTIVATE command is registered.
Note:
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
CK_c
CK_t
tISCKE
CKE1
tIHCKE
CMD
PRE
Note:
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1. CKE can go LOW tIHCKE after the clock on which the PRECHARGE command is registered.
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CK_c
T0
T1
T2
Tx
Tx + 1
Tx + 2
Tx + 3
Tx + 4
Tx + 5
CK_t
Tx + 6
Tx + 7
Tx + 8
Tx + 9
tISCKE
RL
CKE1
CMD
MRR
DQ
DQS_c
DQS_t
1. CKE can be registered LOW at [RL + RU(tDQSCK/tCK)+ BL/2 + 1] clock cycles after the
clock on which the MRR command is registered.
Note:
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
CK_c
CK_t
tISCKE
CKE1
tMRW
CMD
MRW
1. CKE can be registered LOW tMRW after the clock on which the MRW command is registered.
Note:
Deep Power-Down
Deep power-down (DPD) is entered when CKE is registered LOW with CS_n LOW, CA0
HIGH, CA1 HIGH, and CA2 LOW at the rising edge of the clock. All banks must be in the
idle state with no activity on the data bus prior to entering DPD mode. During DPD,
CKE must be held LOW. The contents of the device will be lost upon entering DPD
mode.
In DPD mode, all input buffers except CKE, all output buffers, and the power supply to
internal circuitry are disabled within the device. To ensure that there is enough time to
account for internal delay on the CKE signal path, two NOP commands are required after CKE is driven LOW; this timing period is defined as tCPDED. CKE LOW will result in
deactivation of command and address receivers after tCPDED has expired. V REFDQ can
be at any level between 0 and V DDQ, and V REFCA can be at any level between 0 and V DDCA
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CK
tIHCKE
tCPDED
2 tCK (MIN)
tINIT31, 2
CKE
tISCKE
tISCKE
CS_n
tRP
CMD
tDPD
NOP Enter
DPD NOP
Exit
DPD
NOP
NOP
RESET
Dont Care
Notes:
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Input Clock Frequency Changes and Clock Stop with CKE HIGH
During CKE HIGH, the device supports input clock frequency changes and clock stop
under the following conditions:
Refresh requirements are met
Any ACTIVATE, READ, WRITE, PRECHARGE, MRW, or MRR commands have completed, including any associated data bursts, prior to changing the frequency
Related timing conditions, tRCD, tWR, tWRA, tRP, tMRW, tMRR, and so on, are met
CS_n must be held HIGH
Only REFab or REFpb commands can be in process
The device is ready for normal operation after the clock satisfies tCH(abs) and tCL(abs)
for a minimum of 2 tCK + tXP.
After the input clock frequency changes, tCK (MIN) and tCK (MAX) must be met for
each clock cycle.
After the input clock frequency changes, additional MRW commands may be required
to set the WR, RL, and so on. These settings may require adjustment to meet minimum
timing requirements at the target clock frequency.
For clock stop, CK_t is held LOW and CK_c is held HIGH.
NO OPERATION Command
The NO OPERATION (NOP) command prevents the device from registering any unwanted commands issued between operations. A NOP command can be issued only at
clock cycle n when the CKE level is constant for clock cycle n - 1 and clock cycle n. A
NOP command has two possible encodings:
1. CS_n HIGH at the clock rising edge n.
2. CS_n LOW with CA0, CA1, CA2 HIGH at the clock rising edge n.
The NOP command does not terminate a previous operation that is still in process,
such as a READ burst or WRITE burst cycle.
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Truth Tables
Truth tables provide complementary information to the state diagram. They also clarify
device behavior and applicable restrictions when considering the actual state of the
banks.
Unspecified operations and timings are illegal. To ensure proper operation after an illegal event, the device must be powered down and then restarted using the specified initialization sequence before normal operation can continue.
Table 62: Command Truth Table
Notes 113 apply to entire table
Command Pins
CKE
Command
MRW
MRR
CK(n-1)
CK(n)
CS_
n
CA0
CA1
CA2
CA3
CA4
CA5
CA6
CA7
CA8
CA9
MA0
MA1
MA2
MA3
MA4
MA5
MA6
MA7
OP0
OP1
OP2
OP3
OP4
OP5
OP6
OP7
MA0
MA1
MA2
MA3
MA4
MA5
MA6
MA7
REFRESH
(per bank)
REFRESH
(all banks)
ACTIVATE
(bank)
WRITE (bank)
READ (bank)
X
X
X
L
ENTER DPD
X
L
R8
R9
R10
R11
R12
BA0
BA1
BA2
R0
R1
R2
R3
R4
R5
R6
R7
R13
R14
RFU
RFU
C1
C2
BA0
BA1
BA2
AP
C3
C4
C5
C6
C7
C8
C9
C10
C11
RFU
RFU
C1
C2
BA0
BA1
BA2
AP
C3
C4
C5
C6
C7
C8
C9
C10
C11
AB
BA0
BA1
BA2
X
L
X
H
X
H
X
H
NOP
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X
X
X
MAINTAIN PD,
SREF, DPD
(NOP)
X
H
CK
Edge
PRECHARGE
(per bank, all
banks)
NOP
CA Pins
X
X
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CA Pins
CK(n-1)
CK(n)
CS_
n
MAINTAIN PD,
SREF, DPD
ENTER POWER-DOWN
Command
X
H
X
Notes:
CA0
CA1
CA2
CA3
CA4
CA5
CA6
CA7
CA8
CA9
CK
Edge
1. All commands are defined by the current state of CS_n, CA0, CA1, CA2, CA3, and CKE at
the rising edge of the clock.
2. Bank addresses (BA) determine which bank will be operated upon.
3. AP HIGH during a READ or WRITE command indicates that an auto precharge will occur
to the bank associated with the READ or WRITE command.
4. X indicates a Dont Care state, with a defined logic level, either HIGH (H) or LOW (L).
For PD, SREF and DPD, CS_n, CK can be floated after tCPDED has been met and until the
required exit procedure is initiated as described in their respective entry/exit procedures.
5. Self refresh exit and DPD exit are asynchronous.
6. VREF must be between 0 and VDDQ during SREF and DPD operation.
7. CAxr refers to command/address bit x on the rising edge of clock.
8. CAxf refers to command/address bit x on the falling edge of clock.
9. CS_n and CKE are sampled on the rising edge of the clock.
10. The least significant column address C0 is not transmitted on the CA bus, and is inferred
to be zero.
11. AB HIGH during a PRECHARGE command indicates that an all-bank precharge will occur.
In this case, bank address is a "Don't Care."
12. RFU needs to input H or L (defined logic level).
13. When CS_n is HIGH, the CA bus can be floated.
Resetting idle
power-down
NOP
NOP
NOP
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Operation n
102
Next State
Notes
Active
power-down
Active
6, 7
Idle
power-down
Idle
6, 7
Resetting
power-down
Idle or resetting 6, 7, 8
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NOP
Operation n
Next State
Deep
power-down
Power-on
NOP
Bank(s) active
NOP
Active
power-down
NOP
Idle
power-down
12
Self refresh
12
DPD
Deep
power-down
12
Resetting
NOP
Resetting
power-down
Other states
Notes:
Notes
Self refresh
Idle
10, 11
1. Current state is the state of the device immediately prior to clock edge n.
2. All states and sequences not shown are illegal or reserved unless explicitly described
elsewhere in this document.
3. CKEn is the logic state of CKE at clock rising edge n; CKEn-1 was the state of CKE at the
previous clock edge.
4. CS_n is the logic state of CS_n at the clock rising edge n.
5. Command n is the command registered at clock edge n, and operation n is a result of
command n.
6. Power-down exit time (tXP) must elapse before any command other than NOP is issued.
7. The clock must toggle at least twice prior to the tXP period.
8. Upon exiting the resetting power-down state, the device will return to the idle state if
tINIT5 has expired.
9. The DPD exit procedure must be followed as described in Deep Power-Down.
10. Self refresh exit time (tXSR) must elapse before any command other than NOP is issued.
11. The clock must toggle at least twice prior to the tXSR time.
12. In the case of ODT disabled, all DQ output must be High-Z. In the case of ODT enabled,
all DQ must be terminated to VDDQ.
NOP
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Operation
Next State
103
Notes
Current state
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ACTIVATE
REFRESH (all banks)
Active
Begin to refresh
Begin to refresh
MR writing
MRR
Idle, MR reading
RESET
Resetting
7, 8
9, 10
PRECHARGE
Precharging
READ
Reading
WRITE
Writing
PRECHARGE
Writing
Notes
MRW
MRR
Reading
Next State
Row active
Operation
Active MR reading
Precharging
READ
Reading
11, 12
WRITE
Writing
11, 12, 13
WRITE
Writing
11, 12
READ
Reading
11, 12, 14
Power-on
MRW RESET
Resetting
7, 9
Resetting
MRR
Resetting MR reading
Notes:
1. Values in this table apply when both CKEn -1 and CKEn are HIGH, and after tXSR or tXP
has been met, if the previous state was power-down.
2. All states and sequences not shown are illegal or reserved.
3. Current state definitions:
State
Definition
Idle
The bank or banks have been precharged, and tRP has been met.
Active
A row in the bank has been activated, and tRCD has been met. No data bursts or accesses, and no register accesses, are in progress.
Reading
A READ burst has been initiated with auto precharge disabled, and
has not yet terminated.
Writing
A WRITE burst has been initiated with auto precharge disabled, and
has not yet terminated.
4. The states listed below must not be interrupted by a command issued to the same bank.
NOP commands or supported commands to the other bank should be issued on any
clock edge occurring during these states. Supported commands to the other banks are
determined by that banks current state, and the definitions given in the table: Current
State Bank n to Command to Bank m.
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Ends
when...
State
Starts with...
Precharging
Row activating
104
tRP
is met
Notes
After tRP is met, the bank is
in the idle state.
After tRCD is met, the bank
is in the active state.
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State
Starts with...
READ with
AP enabled
WRITE with
AP enabled
Registration of a WRITE
command with auto precharge enabled
tRP
is met
Notes
After tRP is met, the bank is
in the idle state.
After tRP is met, the bank is
in the idle state.
5. The states listed below must not be interrupted by any executable command. NOP commands must be applied to each positive clock edge during these states.
State
6.
7.
8.
9.
10.
11.
12.
13.
14.
Ends
when...
Starts with...
Refreshing
(per bank)
Registration of a REFRESH
(per bank) command
tRFCpb
Refreshing
(all banks)
Registration of a REFRESH
(all banks) command
tRFCab
Notes
tMRR
is met
tMRR
is met
Active MR
reading
tMRR
is met
MR writing
tMRW
Precharging
all
tRP
is met After tMRW is met, the device is in the all banks idle
state.
is met
Bank-specific; requires that the bank is idle and no bursts are in progress.
Not bank-specific; requires that all banks are idle and no bursts are in progress.
Not bank-specific.
This command may or may not be bank-specific. If all banks are being precharged, they
must be in a valid state for precharging.
If a PRECHARGE command is issued to a bank in the idle state, tRP still applies.
A command other than NOP should not be issued to the same bank while a READ or
WRITE with auto precharge is enabled.
The new READ or WRITE command could be auto precharge enabled or auto precharge
disabled.
A WRITE command can be issued only after the completion of the READ burst.
A READ command can be issued only after completion of the WRITE burst.
Operation
Any
NOP
Idle
Any
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ACTIVATE
Writing
(auto precharge
disabled)
Reading with
auto precharge
Writing with
auto precharge
Notes
Active
READ
Reading
WRITE
Writing
Precharging
9, 10, 11
PRECHARGE
Reading
(auto precharge
disabled)
Operation
MRR
READ
Reading
WRITE
Writing
7, 12
ACTIVATE
Active
PRECHARGE
Precharging
READ
Reading
7, 13
WRITE
Writing
ACTIVATE
Active
PRECHARGE
Precharging
READ
Reading
7, 14
WRITE
Writing
7, 12, 14
ACTIVATE
Active
PRECHARGE
Precharging
READ
Reading
7, 13, 14
WRITE
Writing
7, 14
ACTIVATE
Active
PRECHARGE
Precharging
Power-on
MRW RESET
Resetting
15, 16
Resetting
MRR
Resetting MR reading
Notes:
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Condition
And
Idle
tRP
And
Active
tRCD
Reading
Writing
is met
is met
4. Refresh, self refresh, and MRW commands can only be issued when all banks are idle.
5. The states listed below must not be interrupted by any executable command. NOP commands must be applied during each clock cycle while in these states:
State
Ends
when...
Starts with...
Notes
tMRR
is met
tMRR
is met
Active MR
reading
tMRR
is met
MR writing
tMRW
is met After tMRW is met, the device is in the all banks idle
state.
6. tRRD must be met between the ACTIVATE command to bank n and any subsequent
ACTIVATE command to bank m.
7. READs or WRITEs listed in the command column include READs and WRITEs with or
without auto precharge enabled.
8. This command may or may not be bank-specific. If all banks are being precharged, they
must be in a valid state for precharging.
9. MRR is supported in the row-activating state.
10. MRR is supported in the precharging state.
11. The next state for bank m depends on the current state of bank m (idle, row-activating,
precharging, or active).
12. A WRITE command can be issued only after the completion of the READ burst.
13. A READ command can be issued only after the completion of the WRITE burst.
14. A READ with auto precharge enabled or a WRITE with auto precharge enabled can be
followed by any valid command to other banks, provided that the timing restrictions in
the PRECHARGE and Auto Precharge Clarification table are met.
15. Not bank-specific; requires that all banks are idle and no bursts are in progress.
16. RESET command is achieved through the MODE REGISTER WRITE command.
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DM
DQ
Notes
Write enable
Valid
Write inhibit
1. Used to mask write data; provided simultaneously with the corresponding input data.
Note:
Symbol
Min
Max
Unit
Notes
VDD1
0.4
2.3
VDD2
0.4
1.6
VDDCA
0.4
1.6
1, 2
VDDQ
0.4
1.6
1, 3
VIN, VOUT
0.4
1.6
TSTG
55
125
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1. For information about relationships between power supplies, see the Power-Up and Initialization section.
2. VREFCA 0.6 VDDCA; however, VREFCA may be VDDCA, provided that VREFCA 300mV.
3. VREFDQ 0.7 VDDQ; however, VREFDQ may be VDDQ, provided that VREFDQ 300mV.
4. Storage temperature is the case surface temperature on the center/top side of the device. For measurement conditions, refer to the JESD51-2 standard.
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LOW: V IN V IL(DC)max
HIGH: V IN V IH(DC)min
STABLE: Inputs are stable at a HIGH or LOW level
SWITCHING: See the following three tables
CK_t
(Falling)/
CK_c
(Rising)
CK_t
(Rising)/
CK_c
(Falling)
CK_t
(Falling)/
CK_c
(Rising)
CK_t
(Rising)/
CK_c
(Falling)
CK_t
(Falling)/
CK_c
(Rising)
CK_t
(Rising)/
CK_c
(Falling)
CK_t
(Falling)/
CK_c
(Rising)
Cycle
N+1
N+2
N+3
CS_n
HIGH
HIGH
HIGH
HIGH
CA0
CA1
CA2
CA3
CA4
CA5
CA6
CA7
CA8
CA9
Notes:
CKE
CS_n
Clock Cycle
Number
Command
CA[2:0]
CA[9:3]
All DQ
Rising
Read_Rising
HLH
LHLHLHL
Falling
Read_Falling
LLL
LLLLLLL
Rising
N+1
NOP
LLL
LLLLLLL
Falling
N+1
NOP
LLL
LLLLLLL
Rising
N+2
NOP
LLL
LLLLLLL
Falling
N+2
NOP
LLL
LLLLLLL
Rising
N+3
NOP
LLL
LLLLLLL
Falling
N+3
NOP
HLH
LHLLHLH
Rising
N+4
Read_Rising
HLH
LHLLHLH
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CKE
CS_n
Clock Cycle
Number
Command
CA[2:0]
CA[9:3]
All DQ
Falling
N+4
Read_Falling
HHL
HHHHHHH
Rising
N+5
NOP
HHH
HHHHHHH
Falling
N+5
NOP
HHH
HHHHHHH
Rising
N+6
NOP
HHH
HHHHHHH
Falling
N+6
NOP
HHH
HHHHHHH
Rising
N+7
NOP
HHH
HHHHHHH
Falling
N+7
NOP
HLH
LHLHLHL
Notes:
1. Data strobe (DQS_t) is changing between HIGH and LOW with every clock cycle.
2. The noted pattern (N, N + 1...) is used continuously during IDD measurement for IDD4R.
CKE
CS_n
Clock Cycle
Number
Rising
Falling
Rising
Falling
Command
CA[2:0]
CA[9:3]
All DQ
Write_Rising
LLH
LHLHLHL
Write_Falling
LLL
LLLLLLL
N+1
NOP
LLL
LLLLLLL
N+1
NOP
LLL
LLLLLLL
Rising
N+2
NOP
LLL
LLLLLLL
Falling
N+2
NOP
LLL
LLLLLLL
Rising
N+3
NOP
LLL
LLLLLLL
Falling
N+3
NOP
LLH
LHLLHLH
Rising
N+4
Write_Rising
LLH
LHLLHLH
Falling
N+4
Write_Falling
HHL
HHHHHHH
Rising
N+5
NOP
HHH
HHHHHHH
Falling
N+5
NOP
HHH
HHHHHHH
Rising
N+6
NOP
HHH
HHHHHHH
Falling
N+6
NOP
HHH
HHHHHHH
Rising
N+7
NOP
HHH
HHHHHHH
Falling
N+7
NOP
LLH
LHLHLHL
Notes:
1. Data strobe (DQS_t) is changing between HIGH and LOW with every clock cycle.
2. Data masking (DM) must always be driven LOW.
3. The noted pattern (N, N + 1...) is used continuously during IDD measurement for IDD4W.
IDD Specifications
IDD values are for the entire operating voltage range, and all of them are for the entire
standard range, with the exception of IDD6ET, which is for the entire extended temperature range.
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tCK
=
Operating one bank active-precharge current:
(MIN); tRC = tRC (MIN); CKE is HIGH; CS_n is HIGH between valid
commands; CA bus inputs are switching; Data bus inputs are stable; ODT is disabled
Idle power-down standby current: tCK = tCK (MIN); CKE is
LOW; CS_n is HIGH; All banks are idle; CA bus inputs are switching; Data bus inputs are stable; ODT is disabled
Idle power-down standby current with clock stop: CK_t =
LOW, CK_c = HIGH; CKE is LOW; CS_n is HIGH; All banks are idle;
CA bus inputs are stable; Data bus inputs are stable; ODT is disabled
Idle non-power-down standby current: tCK = tCK (MIN); CKE is
HIGH; CS_n is HIGH; All banks are idle; CA bus inputs are switching; Data bus inputs are stable; ODT is disabled
Idle non-power-down standby current with clock stopped:
CK_t = LOW; CK_c = HIGH; CKE is HIGH; CS_n is HIGH; All banks
are idle; CA bus inputs are stable; Data bus inputs are stable; ODT
is disabled
Active power-down standby current: tCK = tCK (MIN); CKE is
LOW; CS_n is HIGH; One bank is active; CA bus inputs are switching; Data bus inputs are stable; ODT is disabled
Active power-down standby current with clock stop: CK_t =
LOW, CK_c = HIGH; CKE is LOW; CS_n is HIGH; One bank is active;
CA bus inputs are stable; Data bus inputs are stable; ODT is disabled
Active non-power-down standby current: tCK = tCK (MIN);
CKE is HIGH; CS_n is HIGH; One bank is active; CA bus inputs are
switching; Data bus inputs are stable; ODT is disabled
Active non-power-down standby current with clock stopped: CK_t = LOW, CK_c = HIGH; CKE is HIGH; CS_n is HIGH; One
bank is active; CA bus inputs are stable; Data bus inputs are stable; ODT is disabled
Operating burst READ current: tCK = tCK (MIN); CS_n is HIGH
between valid commands; One bank is active; BL = 8; RL = RL
(MIN); CA bus inputs are switching; 50% data change each burst
transfer; ODT is disabled
Operating burst WRITE current: tCK = tCK (MIN); CS_n is HIGH
between valid commands; One bank is active; BL = 8; WL = WL
(MIN); CA bus inputs are switching; 50% data change each burst
transfer; ODT is disabled
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111
Symbol
Power
Supply
IDD01
VDD1
IDD02
VDD2
IDD0,in
VDDCA, VDDQ
IDD2P1
VDD1
IDD2P2
VDD2
IDD2P,in
VDDCA, VDDQ
IDD2PS1
VDD1
IDD2PS2
VDD2
IDD2PS,in
VDDCA, VDDQ
IDD2N1
VDD1
IDD2N2
VDD2
IDD2N,in
VDDCA, VDDQ
IDD2NS1
VDD1
IDD2NS2
VDD2
IDD2NS,in
VDDCA, VDDQ
IDD3P1
VDD1
IDD3P2
VDD2
IDD3P,in
VDDCA, VDDQ
IDD3PS1
VDD1
IDD3PS22
VDD2
IDD3PS,in
VDDCA, VDDQ
IDD3N1
VDD1
IDD3N2
VDD2
IDD3N,in
VDDCA, VDDQ
IDD3NS1
VDD1
IDD3NS2
VDD2
IDD3NS,in
VDDCA, VDDQ
IDD4R1
VDD1
IDD4R2
VDD2
IDD4R,in
VDDCA
IDD4W1
VDD1
IDD4W2
VDD2
IDD4W,in
VDDCA, VDDQ
Notes
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2014 Micron Technology, Inc. All rights reserved.
tCK
=
(MIN); CKE is HIGH
All-bank REFRESH burst current:
between valid commands; tRC = tRFCab (MIN); Burst refresh; CA
bus inputs are switching; Data bus inputs are stable; ODT is disabled
All-bank REFRESH average current: tCK = tCK (MIN); CKE is
HIGH between valid commands; tRC = tREFI; CA bus inputs are
switching; Data bus inputs are stable; ODT is disabled
tCK
tCK
=
(MIN); CKE is
Per-bank REFRESH average current:
HIGH between valid commands; tRC = tREFI/8; CA bus inputs are
switching; Data bus inputs are stable; ODT is disabled
Self refresh current (30C to +85C): CK_t = LOW, CK_c =
HIGH; CKE is LOW; CA bus inputs are stable; Data bus inputs are
stable; Maximum 1x self refresh rate; ODT is disabled
Self refresh current (+85C to +105C): CK_t = LOW, CK_c =
HIGH; CKE is LOW; CA bus inputs are stable; Data bus inputs are
stable; ODT is disabled
Deep power-down current: CK_t = LOW, CK_c = HIGH; CKE is
LOW; CA bus inputs are stable; Data bus inputs are stable; ODT is
disabled
Notes:
PDF: 09005aef85b4b06b
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Symbol
Power
Supply
IDD51
VDD1
IDD52
VDD2
IDD5,in
VDDCA, VDDQ
IDD5AB1
VDD1
IDD5AB2
VDD2
IDD5AB,in
VDDCA, VDDQ
IDD5PB1
VDD1
Notes
IDD5PB2
VDD2
IDD5PB,in
VDDCA, VDDQ
IDD61
VDD1
4, 5
IDD62
VDD2
4, 5
IDD6,in
VDDCA, VDDQ
3, 4
IDD6ET1
VDD1
5, 6
IDD6ET2
VDD2
5, 6
IDD6ET,in
VDDCA, VDDQ
3, 5, 6
IDD81
VDD1
IDD82
VDD2
IDD8,in
VDDCA, VDDQ
1.
2.
3.
4.
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Typ
Max
DRAM
Unit
Notes
2
VDD1
1.70
1.80
1.95
Core power 1
VDD2
1.14
1.20
1.30
Core power 2
VDDCA
1.14
1.20
1.30
VDDQ
1.14
1.20
1.30
Notes:
1. The voltage range is for DC voltage only. DC is defined as the voltage supplied at the
DRAM and is inclusive of all noise up to 1 MHz at the DRAM package ball.
2. VDD1 uses significantly less power than VDD2.
Symbol
Min
Max
Unit
Notes
Input leakage current: For CA, CKE, CS_n, CK; Any input 0V VIN VDDCA; (All other pins not under test = 0V)
II
VREF supply leakage current: VREFDQ = VDDQ/2, or VREFCA = VDDCA/2; (All other pins not under test = 0V)
IVREF
Notes:
1. Although DM is for input only, the DM leakage must match the DQ and DQS output
leakage specification.
2. The minimum limit requirement is for testing purposes. The leakage current on VREFCA
and VREFDQ pins should be minimal.
Symbol
Min
Max
Unit
TCASE1
30
85
30
105
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1. Operating temperature is the case surface temperature at the center of the top side of
the device. For measurement conditions, refer to the JESD51-2 standard.
2. Either the device operating temperature or the temperature sensor can be used to set
an appropriate refresh rate, determine the need for AC timing derating, and/or monitor
the operating temperature (see Temperature Sensor). When using the temperature sensor, the actual device case temperature may be higher than the TCASE rating that applies
for the operating temperature range. For example, TCASE could be above +85C when
the temperature sensor indicates a temperature of less than +85C.
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Symbol
1333/1600
Min
1866/2133
Max
Min
Max
Unit
Notes
VIHCA(AC)
VREF + 0.150
Note 2
VREF + 0.135
Note 2
1, 2
VILCA(AC)
Note 2
VREF - 0.150
Note 2
VREF - 0.135
1, 2
VIHCA(DC)
VREF + 0.100
VDDCA
VREF + 0.100
VDDCA
VILCA(DC)
VSSCA
VREF - 0.100
VSSCA
VREF - 0.100
VREFCA(DC)
0.49 VDDCA
0.51 VDDCA
0.49 VDDCA
0.51 VDDCA
3, 4
Symbol
Min
Max
Unit
Notes
VIHCKE
0.65 VDDCA
Note 1
VILCKE
Note 1
0.35 VDDCA
Note:
Symbol
VIHDQ(AC)
1333/1600
1866/2133
Min
Max
Min
Max
Unit Notes
VREF + 0.150
Note 2
VREF + 0.135
Note 2
1, 2, 5
VILDQ(AC)
Note 2
VREF - 0.150
Note 2
VREF - 0.135
1, 2, 5
VIHDQ(DC)
VREF + 0.100
VDDQ
VREF + 0.100
VDDQ
VILDQ(DC)
VSSQ
VREF - 0.100
VSSQ
VREF - 0.100
Reference voltage
for DQ and DM inputs
VREFDQ(DC)
0.49 VDDQ
0.51 VDDQ
0.49 VDDQ
0.51 VDDQ
3, 4
VODTR/2 - 0.01
VDDQ
VODTR/2 + 0.01
VDDQ
VODTR/2 - 0.01
VDDQ
VODTR/2 + 0.01
VDDQ
3, 5, 6
Reference voltage
for DQ and DM inputs (DQ ODT enabled)
VREFDQ(DC)
DQODT,enabled
Notes:
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VODTR=
2RON + RTT
VDDQ
RON + RTT
VREF Tolerances
The DC tolerance limits and AC noise limits for the reference voltages V REFCA and
VREFDQ are shown below. This figure shows a valid reference voltage V REF(t) as a function
of time. V DD is used in place of V DDCA for V REFCA, and V DDQ for V REFDQ. V REF(DC) is the
linear average of V REF(t) over a very long period of time (for example, 1 second), and is
specified as a fraction of the linear average of V DDQ or V DDCA, also over a very long period of time (for example, 1 second). This average must meet the MIN/MAX requirements
in the table: Single-Ended AC and DC Input Levels for CA and CS_n Inputs. Additionally,
VREF(t) can temporarily deviate from V REF(DC) by no more than 1% V DD. V REF(t) cannot
track noise on V DDQ or V DDCA if doing so would force V REF outside these specifications.
Figure 67: VREF DC Tolerance and VREF AC Noise Limits
VDD
Voltage
VREF(AC) noise
VREF(t)
VREF(DC)max
VREF(DC)
VREF(DC)nom
VREF(DC)min
VSS
Time
The voltage levels for setup and hold time measurements V IH(AC), V IH(DC), V IL(AC), and
VIL(DC) are dependent on V REF. V REF shall be understood as V REF(DC), as defined in the
Single-Ended Requirements for Differential Signals figure.
VREF DC variations affect the absolute voltage a signal must reach to achieve a valid
HIGH or LOW, as well as the time from which setup and hold times are measured.
System timing and voltage budgets must account for V REF deviations outside this range.
The setup/hold specification and derating values must include time and voltage associated with V REF AC noise. Timing and voltage effects due to AC noise on V REF up to the
specified limit (1% V DD) are included in device timings and associated deratings.
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VDD + 0.35V
narrow pulse width
1.200V
VDD
0.750V
VIH(AC)
0.700V
VIH(DC)
0.624V
0.612V
0.600V
0.588V
0.576V
VREF + AC noise
VREF + DC error
VREF - DC error
VREF - AC noise
0.500V
VIL(DC)
0.450V
VIL(AC)
0.000V
VSS
0.750V
0.700V
VIH(AC)
VIH(DC)
0.624V
0.612V
0.600V
0.588V
0.576V
0.500V
VIL(DC)
0.450V
VIL(AC)
VSS - 0.35V
narrow pulse width
0.350V
Notes:
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VDD + 0.35V
narrow pulse width
1.200V
VDD
0.735V
VIH(AC)
0.700V
VIH(DC)
0.624V
0.612V
0.600V
0.588V
0.576V
VREF + AC noise
VREF + DC error
VREF - DC error
VREF - AC noise
0.500V
VIL(DC)
0.565V
VIL(AC)
0.000V
VSS
0.735V
0.700V
VIH(AC)
VIH(DC)
0.624V
0.612V
0.600V
0.588V
0.576V
0.500V
VIL(DC)
0.565V
VIL(AC)
VSS - 0.35V
narrow pulse width
0.350V
Notes:
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tDVAC
Differential Voltage
VIH,diff(AC)min
VIH,diff(DC)min
CK
DQS
0.0
VIL,diff(DC)max
tDVAC
1/2 cycle
VIL,diff(AC)max
Time
Symbol
Min
Max
Unit
Notes
VIH,diff(AC)
2 (VIH(AC) - VREF)
Note 1
VIL,diff(AC)
Note 1
2 (VIL(AC) - VREF)
VIH,diff(DC)
2 (VIH(DC) - VREF)
Note 1
VIL,diff(DC)
Note 1
2 (VIL(DC) - VREF)
Notes:
PDF: 09005aef85b4b06b
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1. These values are not defined; however, the single-ended signals CK and DQS must be
within the respective limits (VIH(DC)max, VIL(DC)min) for single-ended signals, and must comply with the specified limitations for overshoot and undershoot (see figure: Overshoot
and Undershoot Definition).
2. For CK, use VIH/VIL(AC) of CA and VREFCA; for DQS, use VIH/VIL(AC) of DQ and VREFDQ. If a
reduced AC HIGH or AC LOW is used for a signal group, the reduced voltage level also
applies.
3. Used to define a differential signal slew rate.
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(ps) @ VIH/
VIL,diff(AC) =
300mV1333 Mb/s
Slew Rate
(V/ns)
tDVAC
(ps) @ VIH/
VIL,diff(AC) =
300mV1600 Mb/s
tDVAC
(ps) @ VIH/VIL,diff(AC)
= 270mV1866 Mb/s
tDVAC
(ps) @ VIH/VIL,diff(AC)
= 270mV2133 Mb/s
Min
Max
Min
Max
Min
Max
Min
Max
>8.0
58
48
40
34
8.0
58
48
40
34
7.0
56
46
39
33
6.0
53
43
36
30
5.0
50
40
33
27
4.0
45
35
29
23
3.0
37
27
21
15
<3.0
37
27
21
15
VDDCA or VDDQ
VSEH(AC)
Differential Voltage
VSEH(AC)min
VDDCA/2 or VDDQ/2
CK_t or DQS_t
VSEL(AC)max
VSEL(AC)
VSSCA or VSSQ
Time
Note: While CA and DQ signal requirements are referenced to V REF, the single-ended
components of differential signals also have a requirement with respect to V DDQ/2 for
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Value
Symbol
VSEH(AC150)
Unit
Notes
Note 1
2, 3
(VDDCA/2) + 0.150
Note 1
2, 3
Note 1
(VDDQ/2) - 0.150
2, 3
Note 1
(VDDCA/2) - 0.150
2, 3
(VDDQ/2) + 0.135
Note 1
2, 3
(VDDCA/2) + 0.135
Note 1
2, 3
Note 1
(VDDQ/2) + 0.135
2, 3
Note 1
(VDDCA/2) + 0.135
2, 3
Min
Max
(VDDQ/2) + 0.150
VSEL(AC150)
VSEH(AC135)
VSEL(AC135)
1. These values are not defined; however, the single-ended signals CK and DQS[3:0] must
be within the respective limits (VIH(DC)max, VIL(DC)min) for single-ended signals, and must
comply with the specified limitations for overshoot and undershoot (see figure: Overshoot and Undershoot Definition).
2. For CK, use VSEH/VSEL(AC) of CA; for strobes (DQS[3:0]), use
VIH/VIL(AC) of DQ.
3. VIH(AC) and VIL(AC) for DQ are based on VREFDQ; VSEH(AC) and VSEL(AC) for CA are based on
VREFCA. If a reduced AC HIGH or AC LOW is used for a signal group, the reduced level
applies.
Notes:
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VDDCA, VDDQ
CK_c, DQS_c
CK_c, DQS_c
VIX
VIX
VDDCA/2,
VDDQ/2
VDDCA/2,
VDDQ/2
VIX
VIX
X
CK_t, DQS_t
CK_t, DQS_t
VSSCA, VSSQ
VSSCA, VSSQ
Table 81: Crosspoint Voltage for Differential Input Signals (CK, CK_c, DQS_t, DQS_c)
Parameter
Symbol
Min
Max
Unit
Notes
VIXCA(AC)
120
120
mV
1, 2
VIXDQ(AC)
120
120
mV
1, 2
Notes:
PDF: 09005aef85b4b06b
216b_16gb_2c0f_mobile_lpddr3.pdf Rev. B 09/14 EN
1. The typical value of VIX(AC) is expected to be about 0.5 VDD of the transmitting device,
and it is expected to track variations in VDD. VIX(AC) indicates the voltage at which differential input signals must cross.
2. For CK, VREF = VREFCA(DC). For DQS, VREF = VREFDQ(DC).
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From
To
Defined By
VIL,diff,max
VIH,diff,min
(VIH,diff,min - VIL,diff,maxTRdiff
VIH,diff,min
VIL,diff,max
(VIH,diff,min - VIL,diff,maxTFdiff
Note:
1. The differential signals (CK and DQS) must be linear between these thresholds.
Figure 73: Differential Input Slew Rate Definition for CK and DQS
TFdiff
TRdiff
VIH,diff,min
VIL,diff,max
Time
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Symbol
Value
Unit
VOH(AC)
VREF + 0.12
Notes
VOL(AC)
VREF - 0.12
VOH(DC)
0.9 VDDQ
VOL(DC)
0.1 VDDQ
DC output LOW measurement level (for I-V curve linearity); ODT enabled DQS_t
VOL(DC)ODT,enabled
Output leakage current (DQ, DM, DQS); DQ, DQS are disabled; 0V VOUT VDDQ
IOZ
5 (MIN)
MMPUPD
5 (MAX)
15 (MIN)
15 (MAX)
1. IOH = 0.1mA.
2. IOL = 0.1mA.
3. The minimum value is derived when using RTT,min and RON,max (30% uncalibrated, 15%
calibrated).
Notes:
Symbol
Value
Unit
Notes
VOH,diff(AC)
0.2 VDDQ
VOL,diff(AC)
0.2 VDDQ
1. IOH = 0.1mA.
2. IOL = 0.1mA.
Notes:
From
To
Defined by
VOL(AC)
VOH(AC)
[VOH(AC) - VOL(AC)TRSE
VOH(AC)
VOL(AC)
[VOH(AC) - VOL(AC)TFSE
Note:
PDF: 09005aef85b4b06b
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1. Output slew rate is verified by design and characterization and may not be subject to
production testing.
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TFSE
VOH(AC)
VREF
VOL(AC)
Time
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Symbol
Min
Max
Unit
SRQSE
1.5
4.0
V/ns
0.7
1.4
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From
To
Defined by
VOL,diff(AC)
VOH,diff(AC)
[VOH,diff(AC) - VOL,diff(AC)TRdiff
VOH,diff(AC)
VOL,diff(AC)
[VOH,diff(AC) - VOL,diff(AC)TFdiff
Note:
1. Output slew rate is verified by design and characterization and may not be subject to
production testing.
TRdiff
TFdiff
VOH,diff(AC)
VOL,diff(AC)
Time
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Symbol
Min
Max
Unit
SRQdiff
3.0
8.0
V/ns
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2133
1866
1600
1333
Unit
0.35
0.35
0.35
0.35
0.35
0.35
0.35
0.35
0.10
0.10
0.10
0.12
V-ns
0.10
0.10
0.10
0.12
V-ns
Notes:
Notes
1. VDD = VDDCA for CA[9:0], CK, CS_n, and CKE. VDD stands for VDDQ for DQ, DM, DQS, and
ODT.
2. VSS = VSSCA for CA[9:0], CK, CS_n, and CKE. VSS stands for VSSQ for DQ, DM, DQS, and
ODT.
3. Maximum peak amplitude values are referenced from actual VDD and VSS values.
4. Maximum area values are referenced from maximum operating VDD and VSS values.
Volts (V)
Overshoot area
VDD
Time (ns)
VSS
Undershoot area
Maximum amplitude
Notes:
PDF: 09005aef85b4b06b
216b_16gb_2c0f_mobile_lpddr3.pdf Rev. B 09/14 EN
1.
2.
3.
4.
VDD = VDDCA for CA[9:0], CK, CS_n, and CKE. VDD = VDDQ for DQ, DM, DQS, and ODT.
VSS = VSSCA for CA[9:0], CK, CS_n, and CKE. VSS = VSSQ for DQ, DM, DQS, and ODT.
Maximum peak amplitude values are referenced from actual VDD and VSS values.
Maximum area values are referenced from maximum operating VDD and VSS values.
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LPDDR3
VREF
0.5 VDDQ
50
VTT = 0.5 VDDQ
Output
CLOAD = 5pF
Note:
PDF: 09005aef85b4b06b
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1. All output timing parameter values (tDQSCK, tDQSQ, tHZ, tRPRE, etc.) are reported with
respect to this reference load. This reference load is also used to report slew rate.
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VOUT
ABS(IOUT)
IPU
RONPU
DQ
IOUT
RONPD
VOUT
IPD
VSSQ
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Mismatch between
pull-up and pull-down
VOUT
Min
Typ
Max
Unit
RON34PD
0.5 VDDQ
0.85
1.00
1.15
RZQ/7
RON34PU
0.5 VDDQ
0.85
1.00
1.15
RZQ/7
RON40PD
0.5 VDDQ
0.85
1.00
1.15
RZQ/6
RON40PU
0.5 VDDQ
0.85
1.00
1.15
RZQ/6
RON48PD
0.5 VDDQ
0.85
1.00
1.15
RZQ/5
RON48PU
0.5 VDDQ
0.85
1.00
1.15
RZQ/5
MMPUPD
15.00
15.00
Notes
Notes:
MMPUPD =
RONPU RONPD
100
RON,nom
For example, with MMPUPD (MAX) = 15% and RONPD = 0.85, RONPU must be less than 1.0.
Min
Max
Unit
0.5 VDDQ
0.5 VDDQ
RONPU
RTT
Notes:
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Parameter
Min
Max
Unit
0.75
%/C
dRONdT
dRONdV
0.20
%/mV
dRTTdT
0.75
%/C
dRTTdV
0.20
%/mV
VOUT
Min
Typ
Max
Unit
RON34PD
0.5 VDDQ
0.70
1.00
1.30
RZQ/7
RON34PU
0.5 VDDQ
0.70
1.00
1.30
RZQ/7
RON40PD
0.5 VDDQ
0.70
1.00
1.30
RZQ/6
RON40PU
0.5 VDDQ
0.70
1.00
1.30
RZQ/6
RON48PD
0.5 VDDQ
0.70
1.00
1.30
RZQ/5
RON48PU
0.5 VDDQ
0.70
1.00
1.30
RZQ/5
Notes:
Pull-Up
With Calibration
With Calibration
Voltage (V)
Min (mA)
Max (mA)
Min (mA)
Max (mA)
Min (mA)
Max (mA)
Min (mA)
Max (mA)
0.00
0.00
0.00
N/A
N/A
0.00
0.00
N/A
N/A
0.05
0.17
0.35
N/A
N/A
0.17
0.35
N/A
N/A
0.10
0.34
0.70
N/A
N/A
0.34
0.70
N/A
N/A
0.15
0.50
1.03
N/A
N/A
0.50
1.03
N/A
N/A
0.20
0.67
1.39
N/A
N/A
0.67
1.39
N/A
N/A
0.25
0.83
1.73
N/A
N/A
0.83
1.73
N/A
N/A
0.30
0.97
2.05
N/A
N/A
0.97
2.05
N/A
N/A
0.35
1.13
2.39
N/A
N/A
1.13
2.39
N/A
N/A
0.40
1.26
2.71
N/A
N/A
1.26
2.71
N/A
N/A
0.45
1.39
3.01
N/A
N/A
1.39
3.01
N/A
N/A
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Pull-Up
With Calibration
With Calibration
Voltage (V)
Min (mA)
Max (mA)
Min (mA)
Max (mA)
Min (mA)
Max (mA)
Min (mA)
Max (mA)
0.50
1.51
3.32
N/A
N/A
1.51
3.32
N/A
N/A
0.55
1.63
3.63
N/A
N/A
1.63
3.63
N/A
N/A
0.60
1.73
3.93
2.17
2.94
1.73
3.93
2.17
2.94
0.65
1.82
4.21
N/A
N/A
1.82
4.21
N/A
N/A
0.70
1.90
4.49
N/A
N/A
1.90
4.49
N/A
N/A
0.75
1.97
4.74
N/A
N/A
1.97
4.74
N/A
N/A
0.80
2.03
4.99
N/A
N/A
2.03
4.99
N/A
N/A
0.85
2.07
5.21
N/A
N/A
2.07
5.21
N/A
N/A
0.90
2.11
5.41
N/A
N/A
2.11
5.41
N/A
N/A
0.95
2.13
5.59
N/A
N/A
2.13
5.59
N/A
N/A
1.00
2.17
5.72
N/A
N/A
2.17
5.72
N/A
N/A
1.05
2.19
5.84
N/A
N/A
2.19
5.84
N/A
N/A
1.10
2.21
5.95
N/A
N/A
2.21
5.95
N/A
N/A
1.15
2.23
6.03
N/A
N/A
2.23
6.03
N/A
N/A
1.20
2.25
6.11
N/A
N/A
2.25
6.11
N/A
N/A
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PU (MAX)
mA
6
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
Voltage
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PU (MAX)
mA
6
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
Voltage
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ODT
VDDQ
To other
circuitry
IPU
VDDQ - VOUT
RTTPU
IOUT
DQ
VOUT
VSS
VOUT
Min (mA)
Max (mA)
RZQ/1
0.6
2.17
2.94
RZQ/2
0.6
4.34
5.88
RZQ/4
0.6
8.68
11.76
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Clock Specification
The specified clock jitter is a random jitter with Gaussian distribution. Input clocks violating minimum or maximum values may result in device malfunction.
Table 96: Definitions and Calculations
Symbol
tCK(avg)
Description
and
nCK
Calculation
Notes
tCKj /N
j=1
Where N = 200
tCH(avg)
tCH(avg) =
tCHj
/(N tCK(avg))
j=1
Where N = 200
tCL(avg)
tCL(avg) =
tCL
/(N tCK(avg))
j=1
Where N = 200
tJIT(per)
The single-period jitter defined as the largest detJIT(per) = min/max of tCK tCK(avg)
i
viation of any signal tCK from tCK(avg).
Where i = 1 to 200
tJIT(per),act
tJIT(per),
allowed
tJIT(cc)
tERR(nper)
i+n1
tERR(nper) =
tCK (n tCK(avg))
j
j=i
tERR(nper),act
tERR(nper),
allowed
tERR(nper),min
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Description
Calculation
tERR(nper),max
tJIT(duty)
Notes
2
=
MAX((tCH(abs),max tCH(avg),max),
(tCL(abs),max tCL(avg),max)) tCK(avg)
Notes:
tCK(abs), tCH(abs),
and tCL(abs)
These parameters are specified with their average values; however, the relationship between the average timing and the absolute instantaneous timing (defined in the following table) is applicable at all times.
Symbol
tCK(abs)
tCK(avg),min
Minimum
+
tCH(abs)
tCH(avg),min
+ tJIT(duty),min2/tCK(avg)min
tCK(avg)
tCL(abs)
tCL(avg),min
+ tJIT(duty),min2/tCK(avg)min
tCK(avg)
tJIT(per),min
Unit
ps1
Notes:
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tERR(tnPARAM),allowed,
t
t
t
t
t
CycleTimeDerating = max PARAM + ERR( nPARAM),act ERR( nPARAM),allowed tCK(avg) , 0
tnPARAM
Cycle time derating analysis should be conducted for each core timing parameter. The
amount of cycle time derating required is the maximum of the cycle time deratings determined for each individual core timing parameter.
Cycle-time derating analysis should be conducted for each core timing parameter.
When the device is operated with input clock jitter, tRPRE must be derated by the
tJIT(per),act,max of the input clock that exceeds tJIT(per),allowed,max. Output deratings are relative to the input clock:
tRPRE(min,derated) = 0.9 tJIT(per),act,max tJIT(per),allowed,max
tCK(avg)
For example, if the measured jitter into a LPDDR3-1600 device has tCK(avg) = 1250ps,
tJIT(per),act,min = 92ps, and tJIT(per),act,max = +134ps, then tRPRE,min,derated = 0.9
- (tJIT(per),act,max - tJIT(per),allowed,max)/tCK(avg) = 0.9 - (134 - 100)/1250 = 0.8728
tCK(avg).
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These parameters are measured from a specific clock edge to a data signal transition
(DMn or DQm, where: n = 0, 1, 2, or 3; and m = DQ[31:0]), and specified timings must be
met with respect to that clock edge. Therefore, they are not affected by tJIT(per).
tQSH, tQSL Parameters
These parameters are affected by duty cycle jitter, represented by tCH(abs)min and
tCL(abs)min. These parameters determine the absolute data-valid window at the device
pin. The absolute minimum data-valid window at the device pin = min [( tQSH(abs)min
tCK(avg)min - tDQSQmax - tQHSmax), (tQSL(abs)min tCK(avg)min - tDQSQmax tQHSmax)]. This minimum data valid window must be met at the target frequency regardless of clock jitter.
tRPST Parameter
tRPST
These parameters are measured from a data signal (DMn or DQm, where n = 0, 1, 2, 3;
and m = DQ[31:0]) transition edge to its respective data strobe signal crossing (DQSn_t,
DQSn_c: n = 0,1,2,3). The specification values are not affected by the amount of
tJIT(per) applied, because the setup and hold times are relative to the clock signal crossing that latches the command/address. Regardless of clock jitter values, these values
must be met.
tDSS, tDSH Parameters
These parameters are measured from a data strobe signal crossing (DQSx_t, DQSx_c) to
its clock signal crossing (CK_t/CK_c). The specification values are not affected by the
amount of tJIT(per)) applied, because the setup and hold times are relative to the clock
signal crossing that latches the command/address. Regardless of clock jitter values,
these values must be met.
tDQSS Parameter
tDQSS
is measured from the clock signal crossing (CK_t/CK_c) to the first latching data
strobe signal crossing (DQSx_t, DQSx_c). When the device is operated with input clock
jitter, this parameter must be derated by the actual tJIT(per),act of the input clock in excess of tJIT(per),allowed.
tDQSS(min,derated) = 0.75 - tJIT(per),act,min tJIT(per),allowed, min
tCK(avg)
tDQSS(max,derated) = 1.25 tJIT(per),act,max tJIT(per),allowed, max
tCK(avg)
For example, if the measured jitter into an LPDDR3-1600 device has tCK(avg) = 1250ps,
= -93ps, and tJIT(per),act,max = +134ps, then:
tJIT(per),act,min
tDQSS,(min,derated)
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Refresh Requirements
Table 98: Refresh Requirement Parameters (Per Density)
Parameter
Symbol
Number of banks
4Gb
6Gb
8Gb
16Gb
32Gb
Unit
TBD
tREFW
32
TBD
ms
tREFW
16
TBD
ms
tREFW
TBD
ms
8192
TBD
REFab
tREFI
3.9
TBD
REFpb
tREFIpb
0.4875
TBD
tRFCab
130
210
TBD
TBD
ns
tRFCpb
60
90
TBD
TBD
ns
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AC Timing
Table 99: AC Timing
Notes 13 apply to all parameters and conditions
Parameter
Data Rate
Symbol
Min/Max
1333
1600
1866
2133
Unit
667
800
933
1066
MHz
tCK(avg)
MIN
1.5
1.25
1.071
0.938
ns
tCH(avg)
tCL(avg)
tCK(abs)
tCH(abs)
tCL(abs)
Maximum frequency
Notes
Clock Timing
MAX
100
MIN
0.45
MAX
0.55
MIN
0.45
MAX
tJIT(per),
tJIT(cc),
al-
tCK(avg)
tCK(avg)
0.55
tCK(avg)
MIN
MIN
0.43
MAX
0.57
MIN
0.43
MAX
0.57
ns
tCK(avg)
tCK(avg)
MIN
80
70
-60
-50
MAX
80
70
60
50
allowed
MAX
160
140
120
100
tJIT(duty),
MIN
min((tCH(abs),min - tCH(avg),min),
(tCL(abs),min - tCL(avg),min)) tCK(avg)
lowed
allowed
MAX
ps
ps
ps
max((tCH(abs),max - tCH(avg),max),
- tCL(avg),max)) tCK(avg)
(tCL(abs),max
Cumulative errors across 2 cycles
tERR(2per),
MIN
allowed
MAX
118
103
88
74
tERR(3per),
MIN
140
122
-105
-87
allowed
MAX
140
122
105
87
tERR(4per),
MIN
155
136
-117
-97
allowed
MAX
155
136
117
97
tERR(5per),
MIN
168
147
-126
-105
allowed
MAX
168
147
126
105
tERR(6per),
MIN
177
155
-133
-111
allowed
MAX
177
155
133
111
tERR(7per),
MIN
186
163
-139
-116
allowed
MAX
186
163
139
116
tERR(8per),
MIN
193
169
-145
-121
allowed
MAX
193
169
145
121
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118
140
103
-88
-74
ps
ps
ps
ps
ps
ps
ps
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Data Rate
Symbol
Min/Max
tERR(9per),
MIN
allowed
MAX
200
175
150
125
tERR(10per),
MIN
205
180
-154
-128
allowed
MAX
205
180
154
128
tERR(11per),
MIN
210
184
-158
-132
allowed
MAX
210
184
158
132
tERR(12per),
MIN
215
188
-161
-134
allowed
MAX
215
188
161
134
tERR(nper),
MIN
1333
1600
1866
2133
Unit
200
175
-150
-125
ps
tERR(nper),allowed
tJIT(per),
allowed
MAX
tERR
MIN = (1 + 0.68ln(n))
allowed MIN
Notes
ps
ps
ps
ps
ZQ Calibration Parameters
tZQINIT
MIN
tZQCL
MIN
360
ns
tZQCS
MIN
90
ns
tZQRESET
MIN
ns
tDQSCK
MIN
2500
ps
READ
Parameters4
MAX
5500
tDQSCKDS
MAX
265
220
190
165
ps
tDQSCKDM
MAX
593
511
435
380
ps
tDQSCKDL
MAX
733
614
525
460
ps
tDQSQ
MAX
165
135
115
100
tQSH
MIN
tCH(abs)
- 0.05
tCK(avg)
tQSL
MIN
tCL(abs)
- 0.05
tCK(avg)
tQH
MIN
ps
READ preamble
tRPRE
MIN
0.9
tCK(avg)
8, 9
READ postamble
tRPST
MIN
0.3
tCK(avg)
8, 10
tLZ(DQS)
MIN
tDQSCK
(MIN) - 300
ps
(MIN) - 300
ps
(MAX) - 100
ps
ps
DQS-DQ skew
tLZ(DQ)
MIN
tDQSCK
tHZ(DQS)
MAX
tDQSCK
tHZ(DQ)
MAX
tDQSCK
ps
WRITE Parameters4
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Symbol
Min/Max
tDH
Data Rate
1333
1600
1866
2133
Unit
Notes
MIN
175
150
130
115
ps
tDS
MIN
175
150
130
115
ps
tDIPW
MIN
0.35
tCK(avg)
tDQSS
MIN
0.75
tCK(avg)
MAX
1.25
tDQSH
MIN
0.4
tCK(avg)
tDQSL
MIN
0.4
tCK(avg)
tDSS
MIN
0.2
tCK(avg)
tDSH
MIN
0.2
tCK(avg)
Write postamble
tWPST
MIN
0.4
tCK(avg)
Write preamble
tWPRE
MIN
0.8
tCK(avg)
tCKE
MIN
tCK(avg)
tISCKE
MIN
0.25
tCK(avg)
11
tIHCKE
MIN
0.25
tCK(avg)
12
tCPDED
tCK(avg)
MIN
Parameters4
tISCA
MIN
175
150
130
115
ps
13
tIHCA
MIN
175
150
130
115
ps
13
tISCS
MIN
290
270
230
205
ps
13
tIHCS
MIN
290
270
230
205
ps
13
tIPWCA
MIN
0.35
tCK(avg)
tIPWCS
MIN
0.7
tCK(avg)
MAX
100
ns
MHz)14, 15, 16
tCKb
MIN
18
tISCKEb
MIN
2.5
ns
tIHCKEb
MIN
2.5
ns
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Data Rate
Symbol
Min/Max
tISb
MIN
1150
ps
tIHb
MIN
1150
ps
tDQSCKb
MIN
ns
1333
1600
1866
2133
Unit
MAX
10
tDQSQb
MAX
1.2
ns
MODE REGISTER WRITE command period (MRW command to MRW command interval)
tMRW
MIN
10
tCK(avg)
tMRD
MIN
ns
tMRR
MIN
tCK(avg)
tMRRI
MIN
READ latency
RL
MIN
10
12
14
16
tCK(avg)
WL
MIN
tCK(avg)
WL
MIN
11
13
tCK(avg)
tRC
MIN
Notes
tRCD
(MIN)
ns
Core Parameters17
tRAS
tRAS
ns
tCKESR
MIN
ns
tXSR
MIN
ns
tXP
MIN
ns
CAS-to-CAS delay
tCCD
MIN
tCK(avg)
tRTP
MIN
ns
RAS-to-CAS delay
tRCD
MIN
ns
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Data Rate
Symbol
Min/Max
tRPpb
MIN
ns
tRPpab
MIN
ns
tRAS
MIN
ns
MAX
70
tWR
MIN
ns
tWTR
MIN
ns
tRRD
MIN
ns
tFAW
MIN
ns
tDPD
MIN
500
tODTon
MIN
1.75
ns
MAX
3.5
tODToff
MIN
1.75
tAODTon
MAX
tAODToff
MIN
tODTd
MAX
12
ns
tODTe
MAX
12
ns
tCAMRD
MIN
20
tCK(avg)
tCAENT
MIN
10
tCK(avg)
tCAEXT
MIN
10
tCK(avg)
tCACKEL
MIN
10
tCK(avg)
tCACKEH
MIN
10
tCK(avg)
1333
1600
1866
2133
Unit
Notes
ODT Parameters
MAX
ns
3.5
tDQSCK
- 300
ps
ps
CA Training Parameters
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Data Rate
Symbol
Min/Max
tADR
MAX
20
ns
tMRZ
MIN
ns
tCACD
MIN
RU(tADR/tCK) + 2
tCK(avg)
tWLDQSEN
MIN
25
ns
CA calibration command to
CA calibration command delay
1333
1600
1866
2133
Unit
Notes
tWLMRD
MAX
MIN
40
MAX
MIN
MAX
20
ns
tWLO
tWLH
MIN
205
175
150
135
ps
tWLS
MIN
205
175
150
135
ps
ns
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tDQSCK
MAX
tRCD
MIN
tRCD
tRC
MIN
tRC
tRAS
MIN
tRAS
tRP
MIN
tRP
tRRD
MIN
tRRD
5620
+ 1.875
+ 1.875
+ 1.875
+ 1.875
+ 1.875
ps
ns
ns
ns
ns
ns
1. Frequency values are for reference only. Clock cycle time (tCK) is used to determine device capabilities.
2. All AC timings assume an input slew rate of 2 V/ns.
3. Measured with 4 V/ns differential CK_t/CK_c slew rate and nominal VIX.
4. READ, WRITE, and input setup and hold values are referenced to VREF.
5. tDQSCKDS is the absolute value of the difference between any two tDQSCK measurements (in a byte lane) within a contiguous sequence of bursts in a 160ns rolling window.
tDQSCKDS is not tested and is guaranteed by design. Temperature drift in the system is
<10C/s. Values do not include clock jitter.
6. tDQSCKDM is the absolute value of the difference between any two tDQSCK measurements (in a byte lane) within a 1.6s rolling window. tDQSCKDM is not tested and is
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VTT + Y mV
VOH - X mV
VOH - 2x X mV
tLZ(DQS), tLZ(DQ)
actual wave
rm
fo
VTT
X
2x X
VTT + 2x Y mV
tHZ(DQS), tHZ(DQ)
VTT
Y
2x Y
VTT - Y mV
VOL + 2x X mV
VTT - 2x Y mV
VOL + X mV
T1 T2
Start driving point = 2 T1 - T2
VOL
T1 T2
End driving point = 2 T1 - T2
9. Measured from the point when DQS begins driving the signal, to the point when DQS
begins driving the first rising strobe edge.
10. Measured from the last falling strobe edge of DQS to the point when DQS finishes driving the signal.
11. CKE input setup time is measured from CKE reaching a HIGH/LOW voltage level to
CK crossing.
12. CKE input hold time is measured from CK crossing to CKE reaching a HIGH/LOW voltage
level.
13. Input setup/hold time for signal (CA[9:0], CS_n).
14. To ensure device operation before the device is configured, a number of AC boot timing
parameters are defined in this table. Boot parameter symbols have the letter b appended (for example, tCK during boot is tCKb).
15. Mobile LPDDR3 devices set some mode register default values upon receiving a RESET
(MRW) command, as specified in Mode Register Definition.
16. The output skew parameters are measured with default output impedance settings using the reference load.
17. The minimum tCK column applies only when tCK is greater than 6ns.
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1333
1600
(base)
100
75
(base)
62.5
47.5
(base)
125
100
80
65
Note:
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2133
Reference
1. AC/DC referenced for 2 V/ns CA slew rate and 4 V/ns differential CK slew rate.
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1333
1600
1866
2133
Reference
tISCS
(base)
215
195
tISCS
(base)
162.5
137.5
tIHCS
(base)
240
220
180
155
Note:
1. AC/DC referenced for 2 V/ns CS_n slew rate, and 4 V/ns differential CK slew rate.
4.0
tIS
tIH
38
25
3.0
7.0 V/ns
tIS
6.0 V/ns
tIH
tIS
tIH
tIH
4.0 V/ns
tIS
tIH
3.0 V/ns
tIS
tIH
38
25
38
25
38
25
38
25
25
17
25
17
25
17
25
17
38
29
13
13
25
17
25
17
12
2.0
1.5
Note:
5.0 V/ns
tIS
4.0
3.0
7.0 V/ns
6.0 V/ns
3.0 V/ns
tIS
tIH
tIS
tIH
tIS
tIH
tIS
tIH
34
25
34
25
34
25
34
25
34
25
23
17
23
17
23
17
23
17
34
29
11
13
23
17
23
17
12
1.5
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4.0 V/ns
tIH
2.0
Note:
5.0 V/ns
tIS
tIS
tIH
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tVAC
at 150mV (ps)
1333 Mb/s
tVAC
at 150mV (ps)
1600 Mb/s
tVAC
at 135mV (ps)
1866 Mb/s
tVAC
at 135mV (ps)
2133 Mb/s
Min
Max
Min
Max
Min
Max
Min
Max
>4.0
58
48
40
34
4.0
58
48
40
34
3.5
56
46
39
33
3.0
53
43
36
30
2.5
50
40
33
27
2.0
45
35
29
23
1.5
37
27
21
15
<1.5
37
27
21
15
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tIS
tIH
tIH
VDDCA
VIH(AC)min
tVAC
VREF to AC
region
VIH(DC)min
Typical
slew rate
VREF(DC)
Typical
slew rate
VIL(DC)max
VREF to AC
region
VIL(AC)max
tVAC
VSSCA
7)
75
VREF(DC) - VIL(AC)max
Setup slew rate
=
falling signal
7)
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VIH(AC)min - VREF(DC)
Setup slew rate
=
rising signal
75
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tIS
tIH
tIH
VDDCA
VIH(AC)min
VIH(DC)min
DC to VREF
region
Typical slew rate
VREF(DC)
Typical slew rate
DC to VREF
region
VIL(DC)max
VIL(AC)max
VSSCA
75
Hold slew rate VIH(DC)min - VREF(DC)
falling signal =
7)
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7)
Hold slew rate VREF(DC) - VIL(DC)max
rising signal =
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tIH
tIS
tIH
VDDCA
VIH(AC)min
tVAC
VREF to AC
region
Typical
line
VIH(DC)min
Tangent
line
VREF(DC)
Tangent
line
VIL(DC)max
Typical
line
VREF to AC
region
VIL(AC)max
TF
TR
tVAC
VSSCA
Setup slew rate tangent line [VREF(DC) - VIL(AC)]max]
falling signal =
7)
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tIS
tIH
tIH
VDDCA
VIH(AC)min
Typical
line
VIH(DC)min
DC to VREF
region
Tangent
line
VREF(DC)
Tangent
line
Typical line
DC to VREF
region
VIL(DC)max
VIL(AC)max
VSSCA
TR
Hold slew rate tangent line [VIH(DC)min - VREF(DC)]
falling signal =
TF
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TF
tangent line [VREF(DC) - VIL(DC)max]
Hold slew rate
=
rising signal
TR
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1333
1600
(base)
100
75
(base)
125
100
80
tDS
tDS
tDH
(base)
Note:
1866
2133
Reference
62.5
47.5
65
1. AC/DC referenced for 2 V/ns DQ, DM slew rate, and 4 V/ns differential DQS slew rate and
nominal VIX .
4.0
tIS
tIH
38
25
3.0
7.0 V/ns
tIS
tIH
6.0 V/ns
tIS
tIH
tIH
4.0 V/ns
tIS
tIH
3.0 V/ns
tIS
tIH
38
25
38
25
38
25
38
25
25
17
25
17
25
17
25
17
38
29
13
13
25
17
25
17
12
2.0
1.5
Note:
5.0 V/ns
tIS
4.0
3.0
7.0 V/ns
6.0 V/ns
3.0 V/ns
tIS
tIH
tIS
tIH
tIS
tIH
tIS
tIH
34
25
34
25
34
25
34
25
34
25
23
17
23
17
23
17
23
17
34
29
11
13
23
17
23
17
12
1.5
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4.0 V/ns
tIH
2.0
Note:
5.0 V/ns
tIS
tIS
tIH
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tVAC
at 150mV (ps)
1333 Mb/s
tVAC
at 150mV (ps)
1600 Mb/s
tVAC
at 135mV (ps)
1866 Mb/s
tVAC
at 135mV (ps)
2133 Mb/s
Min
Max
Min
Max
Min
Max
Min
Max
>4.0
58
48
40
34
4.0
58
48
40
34
3.5
56
46
39
33
3.0
53
43
36
30
2.5
50
40
33
27
2.0
45
35
29
23
1.5
37
27
21
15
<1.5
37
27
21
15
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tDS
tDH
tDH
VDDQ
VIH(AC)min
tVAC
VREF to AC
region
VIH(DC)min
Typical
slew rate
VREF(DC)
Typical
slew rate
VIL(DC)max
VREF to AC
region
VIL(AC)max
tVAC
VSSQ
TF
TR
VREF(DC) - VIL(AC)max
Setup slew rate
=
falling signal
TF
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VIH(AC)min - VREF(DC)
Setup slew rate
=
rising signal
TR
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DQS_c
DQS_t
tDS
tDS
tDH
tDH
VDDQ
VIH(AC)min
VIH(DC)min
DC to VREF
region
Typical
slew rate
VREF(DC)
Typical
slew rate
DC to VREF
region
VIL(DC)max
VIL(AC)max
VSSQ
TR
VIH(DC)min - VREF(DC)
Hold slew rate
falling signal =
TF
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TF
VREF(DC) - VIL(DC)max
Hold slew rate
=
rising signal
TR
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DQS_c
DQS_t
tDS
tDS
tDH
tDH
VDDQ
VIH(AC)min
tVAC
Typical
line
VREF to AC
region
VIH(DC)min
Tangent line
VREF(DC)
Tangent line
VIL(DC)max
Typical line
VREF to AC
region
VIL(AC)max
TR
TF
tVAC
VSSQ
Setup slew rate tangent line [VREF(DC) - VIL(AC)max]
falling signal =
TF
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DQS_c
DQS_t
tDS
tDS
tDH
tDH
VDDQ
VIH(AC)min
Nominal
line
VIH(DC)min
DC to VREF
region
Tangent
line
VREF(DC)
Tangent
line
Typical line
DC to VREF
region
VIL(DC)max
VIL(DC)max
VSSQ
TR
Hold slew rate
falling signal =
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TF
Hold slew rate
=
rising signal
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Revision History
Rev. B 09/14
Updated AC timing
Rev. A 06/14
Initial release
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