Adjustable Hysteresis CMOS Schmitt Triggers

Vipul Katyal, Randall L. Geiger and Degang J. Chen

Dept. of Electrical and Computer Engineering
Iowa State University
Ames, Iowa, USA
katyal@iastate.edu, rlgeiger@iastate.edu, djchen@iastate.edu
Abstract Adjustable hysteresis CMOS Schmitt trigger
design strategies are investigated and two new inverter based
designs are proposed. The sizing of the two feedback inverters
controls the two trip points of the structure independently. By the
addition of voltage controlled current sinking and/or sourcing
transistors, the hysteresis window can be easily moved without
changing its width. Moreover the new designs are immune to the
kick-back noise coming from the succeeding blocks.
KeywordsSchmitt Trigger, trip point, hysteresis, inverter

I.

INTRODUCTION

Schmitt triggers are used extensively in digital and analog

systems to filter out any noise present on a signal line and
produce a clean digital signal. These blocks find their way into
many instrumentation and test measurement systems. The
demand for implementation of controllable hysteresis Schmitt
triggers has increased in such systems. The traditional method
of implementing a Schmitt trigger is to use a resistive
regenerative (positive) feedback amplifier [1]. The basic idea
of a Schmitt trigger is to generate a bi-stable state which has a
switching threshold as a function of the direction of the input.
The main drawbacks of this implementation are mainly related
to op-amp design challenges, e.g. large die area, high DC gain
requirements, low offset requirements etc. Another
disadvantage of such an implementation is the high power
requirement which makes this structure unfavorable in many
analog and digital systems. Another approach for
implementation is to use standard CMOS inverters along with
positive feedback (e.g. latches) [2-4]. The basic idea proposed
in [2] is to provide an active alternate pull down path for the
output of the first inverter when the input is changing from
high to low. The alternate pull down path keeps pulling down
the output of the first inverter even beyond the quasi-static (or
the trip point) of the inverter. When the input is changing from
low to high, this alternate path is actually inactive and thus the
trip point will be determined primarily by only the input
inverter. This idea can be easily extended to a complementary
design where an alternate pull up path is also present [3]. For
hysteresis adjustment, the author in [4] introduced an additional
voltage controlled transistor in the feedback path. This
adjustment is actually non-linear with respect to the controlling
voltage.
In all of these designs one key performance determining
block has been neglected. This block is the output inverter
which is also present in the feedback path. The sizing of the
output inverter will also affect in the trip points of the Schmitt

978-1-4244-1684-4/08/$25.00 2008 IEEE

trigger. Another drawback of the present implementation

schemes is related to the kick-back noise coming from other
digital/analog blocks connected to the Schmitt triggers output.
To address this issue, the output inverter can be separated out
from feedback inverters. By doing this, the feedback node will
be internal to the Schmitt trigger and hence the design will be
more immune to the kick-back noise. Additional advantage of
such an approach is that the same inverter sizing for both pullup and pull-down feedback paths is not required. By using
different inverter sizing, the trip points of the Schmitt trigger
can easily by varied to compensate for power supply, process
and temperature variations. One can also introduce hysteresis
adjustable design as described in [4] into this new design
scheme. A different approach for adjusting the trip points of the
Schmitt trigger, without affecting the hysteresis width too
much, is to introduce voltage controlled current source/sink at
the output of the input inverter at a price of small power
consumption.
In section II, the basic operation of a traditional inverter
based Schmitt trigger will be discussed which will be followed
by new Schmitt trigger designs in section III. Simulation
comparison of these structures will be covered in section IV
and the conclusions will be summarized in section V.
II. TRADITIONAL INVERTER BASED SCHMITT TRIGGERS
A commonly used Schmitt trigger design is shown in the
Fig. 1 [2-3]. This structure has two inverters (INVI/P and
INVO/P) and two feedback transistors (NMOSFB and PMOSFB).
For analyzing this structure, first assume that no feedback
transistors are present. This case will be just a cascading of two
inverters and the O/P transition point (or quasi-static point,
VQS) will be primary defined by the INVI/P dimensions. Now
assume that VIN is high, VINT is low and VOUT is high and the
NMOSFB transistor is also present. The gate of NMOSFB
transistor is connected to the VOUT, which is high, hence this
transistor will be pulling the VINT node to the low voltage also.
This is basically generating a positive feedback in the system.
If VIN decreases from high to low, NMOSFB transistor will keep
on pulling the VINT node to the low voltage even after the input
crosses the VQS point. The NMOSFB transistor turns off only
when the VINT goes above the quasi-static point of the output
inverter causing VOUT to go low and at that time the system
starts to work as normal cascaded inverters. The transition or
the trip point occurs when the pole of the system crosses j
axis. At that transition point, the input inverters transistors are
in saturation, the output inverters NMOS and PMOS are in
saturation and triode, respectively, and the feedback NMOS

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Figure 1. Traditional inverter based Schmitt Trigger (Str. 1)

Figure 3. Proposed Schmitt Trigger design (Str. 2)

Figure 2. Hysteresis curve for VINT vs VIN

transistor is in triode region. One can formulate a set of three

non-linear equations for finding the High to Low trip point
(VHL), VINT and VOUT. Out of these three equations, one will
reflect the pole movement across j axis and the other two
would be KCL at the VINT and VOUT nodes. Similarly, if the
PMOSFB transistor is present in the system, it would introduce
another positive feedback and will affect the Low to High trip
point (VLH) of the system. Fig. 2 shows a typical hysteresis for
VINT vs. VIN. The VINT,High and VINT,Low voltages are the VINT
node voltages at VLH and VHL, respectively. The adjustment of
the trip points is possible by varying the sizing of the input
inverter transistors along with the sizing of the feedback
transistors [2-4]. Another possible trip point adjustment is by
changing the output inverter dimensions. This effect has been
neglected in the literature for such kind of positive feedback
Schmitt triggers. One issue with these structures is related to
the kick-back noise coming from the circuitry connected to the
output node of the Schmitt trigger. The output node is
connected to the feedback transistors and can easily affect the
performance of the overall structure in presence of the kickback noise.

Fig. 1 into three inverters (INVO/P, INVPFB and INVNFB) as

shown in the Fig. 3. If all three inverters have same transistor
dimensions as in traditional case, then the trip points will be
exactly the same as before. The splitting of the output inverter
has two advantages over the previous structure. The first
positive point of the new structure is freedom of independent
transistor sizing of the two feedback inverters. This
independent inverter sizing will result in nearly independent
control of the two trip points. The second positive point is
reduction in the kick-back noise as the output node is not in the
feedback path. But this new structure has a new design
challenge for the output inverter (INVO/P). The design
constraint will come from the VINT,High and VINT,Low. These
values will change when the feedback inverters dimensions
are changed. To ensure the proper operation of this new
Schmitt trigger, the quasi-static point (or the trip point) of the
inverter should be bounded by the maximum of the VINT,Low
and the minimum of the VINT,High. For a design where this is a
challenge, the output can be tapped from VP or VN followed by
2 cascaded inverters at an expense of longer propagation delay.
But still there is flexibility of adjusting the trip points
independently. Another modification to this new Schmitt
trigger design is to include the VOUT in the feedback path in
such a way that it doesnt introduce a direct path for kick-back
noise. One such method is shown in Fig. 4 where the feedback
inverters are modified to include two inputs (VINT and VOUT)
rather than one. These modified inverters (INV2NFB and
INV2PFB) are shown in Fig 5 and Fig. 6. These two input
inverters have same functional implementation as that of a
single input inverter. With this implementation scheme, the
VOUT is in the positive feedback loop and hence the VINT,High
and VINT,Low will track the sizing of the output inverter.
Therefore, the output inverter sizing will not hamper the
performance of the overall Schmitt trigger.

Based on the observations that the output inverter sizing

plays a role in determining the trip points along with the kickback noise problem, two new structures have been investigated
in the next section.

VDD
PMOSFB

NEW SCHMITT TRIGGER DESIGN

VIN

INVI/P

VINT

INVO/P

VSS

A new Schmitt trigger design is shown in the Fig. 3. The

first step in the new design is splitting the output inverter of

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2
3
1

NMOSFB

III.

INV2PFB

VP

VN

3
2

INV2NFB

Figure 4. Modified Proposed Schmitt Trigger design (Str. 3)

VOUT

TABLE I.

KEY VALUES USED FOR SIMULATIONS

Power Supply
Length (L) for all transistors
INVI/P (for all structures)
INVO/P (for Str. 2 and 3 only)
Feedback Inverters (for Str. 2
and the INVO/P of Str. 1)
INV2NFB of Str. 3 (feedback
inverter)

Figure 5. Two input inverter for NMOSFB (INV2NFB)

INV2PFB of Str. 3 (feedback

inverter)
Str. 1 and 2 Feedback
transistors
Str. 3 Feedback transistors
Simulation Temperature

Figure 6. Two input inverter for PMOSFB (INV2PFB)

Another possible modification to these structures is addition

of voltage controlled current sinking and/or sourcing transistors
at VINT node. The addition of such transistors will shift the
hysteresis window without changing the width of the hysteresis
much. Yet another modification to these new designs would
involve the trip point control as shown in [4]. Use of these
techniques can help in better control of the adjustment of the
trip points.
IV.

SIMULATION RESULTS

The traditional design, Fig. 1 (Str. 1), and the two proposed
designs, Fig. 3 (Str. 2) and Fig. 4 (Str. 3), are designed in
TSMC 0.18m process. Key values used for these structures
are listed in Table I. For generating the hysteresis curve, a
triangular input from rail to rail power supply with a frequency
of 50Hz is used. For comparison between these structures, all
transistor widths of the feedback inverters are sized 1m.
Different NMOSFB and PMOSFB sizes are used to achieve
similar trip points in all the three cases. For the traditional
design (Str. 1), the output inverter sizing of 1m will not be
used in an application as this inverter is also the output driving
inverter. But for studying the effects of the feedback inverter
sizing on the trip points, the nominal sizing of 1m will be
reasonable. For these transistors sizing scheme, the high to low
trip point (VHL) is approximately 0.49V (i.e. 24.5% w.r.t. VDD)
and the low to high trip point (VLH) is approximately 1.57V
(i.e. 78.5% w.r.t. VDD). Each feedback inverters transistor size
is varied from 1m to 20m one at a time while keeping the
others unchanged and VHL, VLH, VINT,Low and VINT,High are noted
down for all 3 designs. Tables II-VI summarizes these data.
The information stored in the trip points can be viewed by
looking at the change in the hysteresis width and its mid-point
value. From the traditional designs (Str. 1) data (Table II), the

VDD = 2V, VSS = 0V

0.4m
Width of NMOS: 2m
Width of PMOS: 8.3m
Width of NMOS: 4m
Width of PMOS: 17m
Width of NMOS: 1m
Width of PMOS: 1m
Width of MN1: 1m
Width of MN2: 1m
Width of MP: 1m
Width of MN: 1m
Width of MP1: 1m
Width of MP2: 1m
Width of NMOSFB: 1.8m
Width of PMOSFB: 5m
Width of NMOSFB: 3.7m
Width of PMOSFB: 16.6m
50C

hysteresis width changes only by around 8.8% w.r.t. VDD and

the hysteresis mid-point changes by 19.5% w.r.t. VDD implying
that by changing the output inverter sizing both VHL and VLH
track each other reasonably. This was actually expected as both
the feedback paths use same inverter. For the proposed design
(Str. 2), when only INVNFB is varied (Table III), the hysteresis
width changes by 9.6% w.r.t. VDD and the mid-point change is
5.6%, hence the INVNFB is affecting the VHL trip point
primarily and has little influence on the VLH trip point.
Structure 2 with INVPFB varying (Table IV), the hysteresis
width and mid-point values changes by 13.3% and 7.2% w.r.t.
VDD, respectively, which implies INVPFB primarily influences
VLH rather than VHL. For this proposed structure one design
challenge was noted for the output inverter sizing in the
previous section. This point is evident from the data of VINT,Low
and VINT,High in Tables III and IV. The maximum value of
VINT,Low is around 37% and the minimum value of VINT,High is
around 39% leaving a margin of only 2% to set the quasi-static
point (or the trip point) of the output inverter in that range. This
will be hard to achieve with the process and temperature
variations. The adjustable range of the trip points have to be
sacrificed for a better head room for the design of the output
inverter. When we go to the modified proposed design (Str. 3),
this worst difference between VINT,Low and VINT,High is around
50% (i.e. 1V) as shown by the data in Tables V and VI. This
large head room is achieved by introducing the output into the
feedback paths without adding any kick-back noise into the
system. For Str. 3 with INV2NFB varying (Table V), the
hysteresis width and mid-point values change by 10.6% and
5.3% and for the case where INV2PFB is varied (Table VI) these
values are 15.2% and 7.6%, respectively. In the modified
proposed structure, the simulation data also shows independent
control of the trip points by varying the respective inverter size
alone. Therefore, total hysteresis width change of 25% is
achievable along with 12.5% change in the mid-point of the
hysteresis. Typically these large controllable ranges will be
sufficient to compensate for any process or temperature
variations. Simulations also show that the output inverter sizing
has little impact on the trip points of the design of the Str. 3.

1940

The main advantage of adding VOUT into the feedback path by

utilizing 2 input inverter scheme is the increase in the
separation of the VINT,Low and VINT,High.
Other important performance characterization factors of a
Schmitt triggers trip points are with respect to temperature and
power supply. For these two cases all the transistors widths are
kept constant to the values given in Table I and only
temperature or the power supply was changed. Simulation data
for these two cases are shown in Tables VII and VIII. For these
set of simulations both traditional design (Str. 1) and proposed
design (Str. 2) have identical sizing, hence they have the same
results. For the temperature variation and the power supply
variation cases, all structures performed in a similar manner
with only small performance improvement of the Str. 3 over
the other two.
The two additional modifications mentioned in the previous
section, addition of voltage controlled current sinking and/or
sourcing transistor(s) at VINT node and the scheme mentioned
in [4], will also enhance the performance of the two proposed
structures without adding much to the die area.
V.

CONCLUSIONS

Two new Schmitt trigger designs were presented. As

opposed to the traditional implementation scheme, the new
design approach used two separate inverters for each positive
feedback paths. This modification resulted in near independent
trip point control by varying the sizing of the respective
feedback inverter in the first proposed design. In the second
proposed design, the feedback inverters were modified to
include two inputs, one from the internal node of the Schmitt
trigger and the other being the output node, which resulted in
independent control of the trip points by the sizing of the
respective two input inverters. Simulations for these structures
showed wide trip point control by varying feedback inverters
sizing, specifically by the latter modification utilizing two input
inverter scheme. The proposed structures also have added
advantage of reduced kick back noise. These structures can also
have current sourcing and/or sinking voltage controlled
transistors at the output of the input inverter, which can shift
the hysteresis window without changing its width. Splitting of
the inverters for separate feedback paths along with the use of
two input inverters are not limited to the present architecture,
but can be used in other Schmitt trigger designs making them
more favorable to different applications.
REFERENCES
[1]
[2]
[3]

[4]

A. S. Sedra and K. C. Smith, Microelectronic Circuits, 5th ed., Oxford:

New York, pp. 1188, 2004.
M. Steyaert and W. Sansen, Novel CMOS Schmitt Trigger, Electronic
Letters, vol. 22, issue 4, pp. 203-204, Feb. 1986.
J. M. Rabaey, A. Chandrakasan and B. Nikolic, Digital Integrated
Circuits: A Design Perspective, 2nd ed., Pearson Education: Upper
Saddle River N.J, pp364-367, 2003.
Z. Wang, CMOS Adustable Schmitt Triggers, IEEE Transcactions on
Instrumentation and Measurement, vol. 40, no. 3, pp. 601-605, June
1991.

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TABLE II.

TRIP POINT VARIATION VS. FEEDBACK INVERTER FOR STR. 1

INVOUT
(WN, WP) (m)
(1, 1)
(1, 5)
(1, 20)
(5, 1)
(20, 1)
TABLE III.

VHL

VLH

VINT,Low

VINT,High

24.80
21.76
19.41
27.71
30.05

78.30
78.30
78.30
78.30
78.30

20.87
23.94
24.50
18.93
17.02

78.70
78.90
79.19
78.90
78.90

TRIP POINT VARIATION VS. INV2PFB FOR STR. 3

TABLE VII.

(% w.r.t. VDD)
VHL

VLH

VINT,Low

VINT,High

24.80
24.80
24.80
24.80
24.80

78.30
74.26
71.19
82.72
86.44

20.87
21.04
20.91
21.05
21.64

78.70
81.53
83.42
76.76
74.46

HYSTERESIS VARIATION VS. TEMERATURE

(% w.r.t. VDD)

Str. 1 and Str. 2

Str. 3

Hyst. Width

Hyst. Mid-pt.

Hyst. Width

Hyst. Mid-pt.

58.89
56.02
53.84
52.62
52.16

45.18
48.26
51.38
54.27
56.97

58.76
54.92
53.49
53.07
53.26

45.79
48.32
51.55
54.57
57.40

TABLE VIII.

1.5
2
2.5

VINT,High
48.52
60.90
68.53
39.31

(% w.r.t. VDD)

INV2PFB
(WN, WP1, WP2)
(m)
(1, 1, 1)
(1, 5, 1)
(1, 20, 1)
(1, 1, 5)
(1, 1, 20)

VDD
(V)

(% w.r.t. VDD)
VLH
VINT,Low
78.31
31.28
72.91
31.26
69.02
30.88
82.86
29.31

VHL
24.46
24.46
24.46
25.01

TRIP POINT VARIATION VS. INV2NFB FOR STR. 3

TABLE VI.

-50
0
50
100
150

VINT,High
48.52
52.89
48.47
48.27

TRIP POINT VARIATION VS. INVPFB FOR STR. 2

INV2NFB
(WN1, WN2, WP)
(m)
(1, 1, 1)
(1, 5, 1)
(1, 20, 1)
(5, 1, 1)
(20, 1, 1)

Temp.
(oC)

(% w.r.t. VDD)
VLH
VINT,Low
78.31
31.28
77.54
37.24
78.31
25.04
78.31
21.79

VHL
24.46
20.32
28.16
30.71

INVPFB
(WN, WP) (m)
(1, 1)
(1, 5)
(1, 20)
(5, 1)
TABLE V.

VINT,High
48.52
60.90
68.43
33.38
27.04

TRIP POINT VARIATION VS. INVNFB FOR STR. 2

INVNFB
(WN, WP) (m)
(1, 1)
(1, 5)
(5, 1)
(20, 1)
TABLE IV.

(% w.r.t. VDD)
VLH
VINT,Low
78.31
31.28
72.91
40.96
69.02
54.10
84.33
25.03
92.71
21.86

VHL
24.46
19.70
15.40
28.16
30.71

HYSTERESIS VARIATION VS. POWER SUPPLY

(% w.r.t. VDD)

Str. 1 and Str. 2

Str. 3

Hyst. Width

Hyst. Mid-pt.

Hyst. Width

Hyst. Mid-pt.

63.54
53.84
49.80

47.50
51.38
54.34

48.42
53.49
59.62

49.24
51.55
54.73