Concept Map

KLU/ECE/2014-15/ODD/Teaching-Learning/FORM-2A(U.G.
-T)
ECE321 Digital MOS Circuits
Unit 1: Characteristics of MOS Transistors
KALASALINGAM UNIVERSITY
(Kalasalingam Academy of Research and Education)
Krishnankoil
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
Date:
1. UNIT DETAILS
COURSE CODE/NAME ECE321 Digital MOS Circuits
TOPIC (UNIT) TITLE Unit 1: Characteristics of MOS Transistors
The MOS Field Effect Transistor (MOSFET) is the fundamental building block of MOS and CMOS digital
integrated circuits. Compared to the bipolar junction transistor (BJT), the MOS transistor occupies a
relatively smaller silicon area, and its fabrication involves fewer processing steps. These technological
advantages, together with the relative simplicity of MOSFET operation, have helped make the MOS
transistor the most widely used switching device in LSI and VLSI circuits. In this unit, we will examine the
basic structure and the electrical behaviour of nMOS (n-channel MOS), as well as pMOS (p- channel MOS)
devices. The nMOS transistor is used as the primary switching device in virtually all digital circuit
applications, whereas the pMOS transistor is used mostly in conjunction with the nMOS device in CMOS
circuits. However, the basic operation principles of both nMOS and pMOS transistors are very similar to
DESCRIPTION each other.
This unit starts with a detailed investigation of the basic electrical and physical properties of Metal Oxide
Semiconductor (MOS) systems, upon which the MOSFET structure is based. We will consider the effects of
external bias conditions on charge distribution in the MOS system and on the conductance of free carriers. It
DETAILED COURSE TOPICS will be shown that, in field effect devices, the current flow is controlled by externally applied electric fields,
ECE Department, Kalasalingam University
Page 1 of 4
KLU/ECE/2014-15/ODD/Teaching-Learning/FORM-2A(U.G.-T)
and that the operation depends only on the majority carrier flow between two device terminals. Next, the
current-voltage characteristics of MOS transistors will be examined in detail, including physical limitations
imposed by small device geometries and various second-order effects observed in MOSFETs. Note that
these considerations will be particularly important for the overall performance of large-scale digital circuits
built by using small-geometry MOSFET devices.
Mathematics: 25%
CONTRIBUTION TO
PROFESSIONAL Engineering: 25%
COMPONENT Basic Sciences: 50%
Use mathematical methods and circuit analysis models in analysis of CMOS digital electronics
COURSE OUTCOMES FROM 1.
THIS UNIT circuits, including logic components and their interconnect
ASSESSMENT TOOLS FOR
THIS UNIT Short Answer , Long Answer, Closed Book Test

Page 2 of 4
2. CONCEPT MAP

Page 3 of 4
3. BOOKS THAT MAY BE REFERRED FOR THIS UNIT
Author(s)
Book Title
CMOS Digital Integrated Circuits - Sung-Mo Kang &

Yusuf Leblebici
Analysis & Design
Digital Integrated Circuits - A Design
Jan M Rabaey
Perspective
Publisher(s)
Edition/Print and
Year
Tata McGraw
Hill
2nd Edition, 2001
2001
PHI
Chapter(s)
# of copies in
Central
Dept.
library
library
1, 2, 3
10
4. WEBSITES, ONLINE MATERIALS, E-BOOKS THAT MAY REFERRED FOR THIS UNIT
Unit Topic
All topics
MOS transistor theory
VTC Parameters - DC Characteristics
URL (Address)
http://www.seas.upenn.edu/~ese570/
http://www.cse.wustl.edu/~vgruev/cse/463/index.htm
http://ocw.mit.edu/courses/electrical-engineering-and-computer-science/6-374-analysis-and-design-ofdigital-integrated-circuits-fall-2003/
Prepared By
Course Coordinator
Name: P. Sivakumar
Signature with date:
Verified By
Module Coordinator
Name: K. Jeyaprakash
FOR OFFICE USE ONLY
Comments (if any):

(Signature of Programme Coordinator with date)
(Signature of Head of the Department with date)

Page 4 of 4
Unit 2: SCALING IN MOSFETS
Krishnankoil
Date:
1. UNIT DETAILS
TOPIC (UNIT) TITLE Unit 2: SCALING IN MOSFETS
The design of high-density chips in MOS VLSI (Very Large Scale Integration) technology requires that the
packing density of MOSFETs used in the circuits is as high as possible and, consequently, that the sizes of
the transistors are as small as possible. The reduction of the size, i.e., the dimensions of MOSFETs, is
commonly referred to as scaling. It is expected that the operational characteristics of the MOS transistor will
change with the reduction of its dimensions. Also, some physical limitations eventually restrict the extent of
scaling that is practically achievable. In this unit, we will examine the constant voltage and constant field
scaling and scaling issues in interconnects, Latch up in CMOS and methods for preventing latchup. Later we
DESCRIPTION will discuss about digital MOSFET model, series connection of MOSFETs and body effect.
Constant voltage and constant field scaling, Digital MOSFET model, Series connection of MOSFETs, Body
DETAILED COURSE TOPICS effect, Scaling issues in interconnects, Latch up in CMOS and methods for preventing latchup.
Mathematics: 50%
CONTRIBUTION TO
PROFESSIONAL Engineering: 40%
COMPONENT Basic Sciences: 10%
COURSE OUTCOMES FROM
THIS UNIT 2.
Analyse various scaling in MOSFET and its issues in interconnects

Page 1 of 3
THIS UNIT Short Answer , Long Answer, Closed Book Test
2. CONCEPT MAP

Page 2 of 3
Author(s)
Book Title

Yusuf Leblebici
Analysis & Design
Digital Integrated Circuits - A Design
Jan M Rabaey
Perspective
Publisher(s)
Edition/Print and
Year
Tata McGraw
Hill
2nd Edition, 2001
2001
PHI
Chapter(s)
# of copies in
Central
Dept.
library
library
3, 4
10
Unit Topic
All topics
Latch in CMOS
Body effect
URL (Address)
http://ocw.mit.edu/courses/electrical-engineering-and-computer-science/6-374-analysis-and-design-ofdigital-integrated-circuits-fall-2003/
Prepared By
Course Coordinator
Name:
Verified By
Module Coordinator
Name:
FOR OFFICE USE ONLY
Comments (if any):


Page 3 of 3
ECE321 Digital MOS Circuits.
Unit 3: MOS INVERTERS
Krishnankoil
Date:
1. UNIT DETAILS
COURSE CODE/NAME ECE321 Digital MOS Circuits.
TOPIC (UNIT) TITLE Unit 3: MOS INVERTERS
In this unit, we focus on one single incarnation of the inverter gate, being the static CMOS inverter or the
CMOS inverter, in short. This is certainly the most popular at present, and therefore deserves our special
attention. We analyse the gate with respect to the different design metrics:
DESCRIPTION
DETAILED COURSE TOPICS
cost, expressed by the complexity and area
integrity and robustness, expressed by the static (or steady-state) behaviour
performance, determined by the dynamic (or transient) response
energy efficiency, set by the energy and power consumption.
Pseudo NMOS and CMOS inverters
Calculation of delay times, Power dissipation for CMOS inverter
Design of super buffer
Pass transistors and Transmission gates
CONTRIBUTION TO
PROFESSIONAL Mathematics: 50%
Page 1 of 4
COMPONENT Engineering: 50%
Understand the characteristics of CMOS inverters and the calculation of voltage levels, power
COURSE OUTCOMES FROM 3.
THIS UNIT dissipation and delays
THIS UNIT Short Answer, Long Answer, Assignment

Page 2 of 4
2. CONCEPT MAP

Page 3 of 4
Author(s)
Book Title

Yusuf Leblebici
Analysis & Design
Digital Integrated Circuit Design
Ken Martin
Publisher(s)
Edition/Print and
Year
Tata McGraw Hill
2nd Edition, 2001
Oxford Univ. Press
2003
Chapter(s)
# of copies in
Central
Dept.
library
library
5, 6, 7
4, 5
10
3
3
1
Unit Topic
All topics
Static Characteristics
Prepared By
Course Coordinator
Name:
URL (Address)
Verified By
Module Coordinator
Name:
Signature with date:.
FOR OFFICE USE ONLY

Comments (if any):

Page 4 of 4
Unit 4: PSEUDO NMOS
Krishnankoil
Date:
1. UNIT DETAILS
COURSE CODE/NAME ECE321 Digital MOS Circuits.
TOPIC (UNIT) TITLE Unit 4: PSEUDO NMOS
In high-density, high-performance digital implementations where reduction of circuit delay and silicon area
is a major objective, dynamic logic circuits offer several significant advantages over static logic circuits.
The operation of all dynamic logic gates depends on temporary (transient) storage of charge in parasitic
node capacitances, instead of relying on steady-state circuit behavior. In this unit, we will examine the
Dynamic CMOS circuits, Solutions for charge sharing, Method of Logical Effort for high speed CMOS
DESCRIPTION design. Later we will discuss about BiCMOS logic circuits, Simple gates using BiCMOS.
Dynamic CMOS circuits, Solutions for charge sharing - DOMINO Logic- NORA TSPC logic styles,
DETAILED COURSE TOPICS BiCMOS logic circuits
CONTRIBUTION TO
PROFESSIONAL
4.Classify the various CMOS logic style option and solutions for charge sharing problem
COURSE OUTCOMES FROM 5.Apply VLSI methodologies in the implementation of general system components like decoder, Flip flop at
THIS UNIT CMOS levels
ASSESSMENT TOOLS Short Answer, Long Answer, Assignment, Open book test
Page 1 of 3
Unit 4: PSEUDO NMOS
2. CONCEPT MAP

Page 2 of 3
Unit 4: PSEUDO NMOS
Author(s)
Book Title
CMOS Digital Integrated
Analysis & Design
Circuits
Digital Integrated Circuit Design
- Sung-Mo Kang &

Yusuf Leblebici
Ken Martin
Chapter(s)
# of copies in
Central
Dept.
library
library
Tata McGraw
Hill
2nd Edition, 2001
8, 9, 12
10
Oxford Univ.
Press
2003
7, 8, 9
Publisher(s)
Edition/Print and
Year
Unit Topic
Sequential Logic
All topics
Static Characteristics
Prepared By
Course Coordinator
Name:
URL (Address)
http://www.coe.montana.edu/ee/lameres/courses/eele414_fall11/
Verified By
Module Coordinator
Name:
Signature with date:.
FOR OFFICE USE ONLY
Comments (if any):

Page 3 of 3
Unit 5: CMOS CLOCKING STYLES
Krishnankoil
Date:
1. UNIT DETAILS
TOPIC (UNIT) TITLE Unit 5: CMOS CLOCKING STYLES
The need for low-power design is also becoming a major issue in high-performance digital systems, such as
microprocessors, digital signal processors (DSPs) and other applications. The common traits of highperformance chips are the high integration density and the high clock frequency. The power dissipation of
the chip, and thus, the temperature, increases with the increasing clock frequency. In this unit, we will
primarily concentrate on the circuit- or transistor-level design measures which can be applied to reduce the
power dissipation of digital integrated circuits.
The input/output (VO) circuits, clock generation, and distribution circuits are essential to VLSI chip design.
The design quality of these circuits is a critical factor that determines the reliability, signal integrity, and
DESCRIPTION inter chip communication speed of the chip in a systems environment.
Clock generation and distribution, High speed adders, subtractors and multipliers, CMOS Memory
DETAILED COURSE TOPICS structures, Low power design techniques, Input and Output circuits
CONTRIBUTION TO
PROFESSIONAL
Page 1 of 4
5.
Apply VLSI methodologies in the implementation of general system components like decoder, Flip
COURSE OUTCOMES FROM flop at CMOS levels
Explain low power design techniques and basic of adiabatic logic
THIS UNIT 6.
THIS UNIT Short Answer , Long Answer, Open book test, Assignment

Page 2 of 4
2. CONCEPT MAP

Page 3 of 4
Author(s)
Book Title
CMOS Digital Integrated
Analysis & Design
Microelectronics
Circuits
- Sung-Mo Kang &

Yusuf Leblebici
A, B
Publisher(s)
Edition/Print and
Year
Tata McGraw
Hill
2nd Edition, 2001
PHI
th
29 Print, 2009
Chapter(s)
# of copies in
Central
Dept.
library
library
8, 9, 12
4
10
---
3
3
Unit Topic
All topics
Memory, I/O circuits
Prepared By
Course Coordinator
Name:
URL (Address)
http://www.coe.montana.edu/ee/lameres/courses/eele414_fall11/
Verified By
Module Coordinator
Name:
FOR OFFICE USE ONLY
Comments (if any):

Page 4 of 4

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KLU/ECE/2014-15/ODD/Teaching-Learning/FORM-2A(U.G.

ECE Department, Kalasalingam University

ECE Department, Kalasalingam University

CMOS Digital Integrated Circuits - Sung-Mo Kang &

Comments (if any):

(Signature of Head of the Department with date)

ECE Department, Kalasalingam University

Analyse various scaling in MOSFET and its issues in interconnects

ECE Department, Kalasalingam University

ECE Department, Kalasalingam University

CMOS Digital Integrated Circuits - Sung-Mo Kang &

Comments (if any):

(Signature of Head of the Department with date)

ECE Department, Kalasalingam University

DETAILED COURSE TOPICS

cost, expressed by the complexity and area

integrity and robustness, expressed by the static (or steady-state) behaviour

performance, determined by the dynamic (or transient) response

energy efficiency, set by the energy and power consumption.

Pseudo NMOS and CMOS inverters

Calculation of delay times, Power dissipation for CMOS inverter

Design of super buffer

Pass transistors and Transmission gates

ECE Department, Kalasalingam University

ECE Department, Kalasalingam University

CMOS Digital Integrated Circuits - Sung-Mo Kang &

Tata McGraw Hill

2nd Edition, 2001

Oxford Univ. Press

FOR OFFICE USE ONLY

(Signature of Programme Coordinator with date)

(Signature of Head of the Department with date)

ECE Department, Kalasalingam University

ECE Department, Kalasalingam University

Digital Integrated Circuit Design

- Sung-Mo Kang &

Comments (if any):

(Signature of Programme Coordinator with date)

(Signature of Head of the Department with date)

ECE Department, Kalasalingam University

ECE Department, Kalasalingam University

ECE Department, Kalasalingam University

- Sung-Mo Kang &

Comments (if any):

(Signature of Programme Coordinator with date)

(Signature of Head of the Department with date)

ECE Department, Kalasalingam University

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