IBPS IT Officer Model Questions Computer MIcroprocessor and Assembly Language MCQ Question Bank

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Who is the brain of computer:

ALU
CPU
MU
None of these
Which technology using the microprocessor is fabricated on a single chip:

POS
MOS
ALU
ABM
MOS stands for:

Metal oxide semiconductor
Memory oxide semiconductor
Metal oxide select
None of these
In which form CPU provide output:

Computer signals
Digital signals
Metal signals
None of these
How many types of microprocessor comprises:

3
Which is the microprocessor comprises:

Register section
One or more ALU
Control unit
All of these
The register section is related to______ of the computer:

Processing
ALU
Main memory
None of these
What is the store by register:

data
operands
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memory
None of these
How many types of classification of processor based on register section:

1
10) In Microprocessor one of the operands holds a special register called:

Calculator
Dedicated
Accumulator
None of these
11) Accumulator based microprocessor example are:

Intel 8085
Motorola 6809
A and B
None of these
12) A set of register which contain are:

data
memory addresses
result
all of these
13) How many types are primarily register:

1
14) There are primarily two types of register:

general purpose register
dedicated register
A and B
none of these
15) Which register is a temporary storage location:
general purpose register
dedicated register
A and B
none of these
16) How many parts of dedicated register:

2
4
5
17) Name of typical dedicated register is:

PC
IR
SP
All of these
18) PC stands for:

Program counter
Points counter
Paragraph counter
Paint counter
19) IR stands for:

Intel register
In counter register
Index register
Instruction register 20) SP stands for:
Status pointer
Stack pointer
a and b
None of these
21) The act of acquiring an instruction is referred as the____ the instruction:

Fetching
Fetch cycle
Both a and b
None of these
22) How many bit of instruction on our simple computer consist of one____:
2-bit
6-bit
12-bit
None of these
23) How many parts of single address computer instruction :
24) Single address computer instruction has two parts:
The operation code

The operand
A and B
None of these
25) LA stands for:

Load accumulator
Least accumulator
Last accumulator
None of these
26) ED stands for:

Enable MRD
Enable MDR
Both a and b
None of these 27) LM stands for:
Least MAR
Load MAR
Least MRA
Load MRA
28) Causing a flag to became 0 is called:

Clearing a flag
Case a flag
Both a and b
None of these
29) Which are the flags of status register:

Over flow flag
Carry flag
Half carry flag
Zero flag
Interrupt flag
Negative flag
All of these
30) The carry is operand by:

C
31) The sign is operand by:

S
32) The zero is operand by:

Z
33) The overflow is operand by:
O
34) _____ is the condition:
CD
IR
Both a and b
None of these
35) ____ causes the address of the next microprocessor to be obtained from the memory:
CRJA
ROM
MAP
HLT
36) _________ Stores the instruction currently being executed:

Instruction register
Current register
Both a and b
None of these
37) In which register instruction is decoded prepared and ultimately executed:

Instruction register
Current register
Both a and b
None of these
38) The status register is also called the____:

Condition code register
Flag register
A and B
None of these
39) BCD stands for:

Binary coded decimal
Binary coded decoded
Both a & b
none of these
40) Which is used to store critical pieces of data during subroutines and interrupts:
Stack
Queue
Accumulator
Data register
41) The area of memory with addresses near zero are called:
High memory
Mid memory
Memory
Low memory
42) The point where control returns after a subprogram is completed is known as the :
Return address
Main Address
Program Address
Current Address
43) The subprogram finish the return instruction recovers the return address from the:
Queue
Stack
Program counter
Pointer
44) The processor uses the stack to keep track of where the items are stored on it this by
using the:
Stack pointer register

Queue pointer register
Both a & b
None of these
45) Which point to the ___ of the stack:

TOP
START
MID
None of these 46) Stack words on:
LILO
LIFO
FIFO
None of these
47) Which is the basic stack operation:

PUSH
POP
BOTH A and B
None of these 48) SP stand for:
Stack pointer
Stack pop
Stack push
None of these
49) How many bit stored by status register:

1 bit
4 bit
6 bit
8 bit
50) Which is the important part of a combinational logic block:

Index register
Barrel shifter
Both a & b
None of these
51) The structure of the stack is _______ type structure:

First in last out
Last in last out
Both a & b
None of these
52) The data in the stack is called:

Pushing data
Pushed
Pulling
None of these
53) The CU is designed by using which techniques:

HARDWIRED CONTROLS
MICROPROGRAMING
NANOPROGRAMING
ALL OF THESE
54) The 16 bit register is separated into groups of 4 bit where each groups is called:
BCD
Nibble
Half byte
None of these
55) A nibble can be represented in the from of:

Octal digit
Decimal
Hexadecimal
None of these
56) The left side of any binary number is called:

Least significant digit
Most significant digit
Medium significant digit
low significant digit
57) MSD stands for:

Least significant digit
Most significant digit
Medium significant digit
low significant digit
58) _____ a subsystem that transfer data between computer components inside a
computer or between computer:
Chip
Register
Processor
Bus
59) Which is called superhighway:

Processor
Multiplexer
Backbone bus
None of these
60) The external system bus architecture is created using from ______ architecture:
Pascal
Dennis Ritchie
Charles Babbage
Von Neumann
61) The network of wires or electronic path ways on mother board back side:
PCB
BUS
BOTH A and B
None of these
62) Which Bus connects CPU & level 2 cache:

Rear side bus
Front side bus
Memory side bus
None of these
63) Which bus carry addresses:

System bus
Address bus
Control bus
Data bus
64) A 16 bit address bus can generate___ addresses:

32767
25652
65536
none of these
65) The processor 80386/80486 and the Pentium processor uses _____ bits address bus:
16
32
36
64
66) CPU can read & write data by using :

Control bus
Data bus
Address bus
None of these
67) Which bus transfer singles from the CPU to external device and others that carry
singles from external device to the CPU:
Control bus
Data bus
Address bus
None of these
68) Which is not the control bus signal:

READ
WRITE
RESET
None of these
69) When memory read or I/O read are active data is to the processor :
Input
Output
Processor
None of these
70) When memory write or I/O read are active data is from the processor:
Input
Output
Processor
None of these
71) Using 12 binary digits how many unique house addresses would be possible:
8
2 =256
12
=4096
16
=65536
None of these 72) PROM stands for:
a. Programmable read-only memory 73) EPROM stands for:
a. Erasable Programmable read-only memory 74) Each memory location has:
Address
Contents
Both A and B
None of these
75) Which is the type of microcomputer memory:

Processor memory
Primary memory
Secondary memory
All of these
76) Secondary memory can store____:

Program store code
Compiler
Operating system
All of these
77) Secondary memory is also called____:

Auxiliary
Backup store
Both A and B
None of these
78) Customized ROMS are called:

Mask ROM
Flash ROM
EPROM
None of these
79) The ram which is created using bipolar transistors is called:

Dynamic RAM
Static RAM
Permanent RAM
DDR RAM
80) Which type of RAM needs regular referred:

Dynamic RAM
Static RAM
Permanent RAM
SD RAM
81) Which RAM is created using MOS transistors:
Dynamic RAM
Static RAM
Permanent RAM
SD RAM
82) Which latch is mostly used creating memory register:

SR-Latch
JK-Latch
D-Latch
T-Latch
83) Which statement is false about WR signal:

WR signal controls the input buffer
The bar over WR means that this is an active low signal
The bar over WR means that this is an active high signal
If WR is 0 then the input data reaches the latch input 84) Which technique is used for main
memory array design:
Linear decoding
Fully decoding
Both A and B
None of these
85) CS stands for:

Cable select
Chip select
Control select
Cable system
86) WE stands for:

Write enable
Wrote enable
Write envy
None of these
87) When CS _____ the chip is not selected at all hence D7 to D0 are driven to high
impedance state:
High
Low
Medium
Stand by
88) The capacity of this chip is 1KB they are organized in the form of 1024 words with 8
bit word The what is the site of address bus:
8 bit
10 bit
12 bit
16 bit
89) Which storage technique dose not decoding circuit:

Linear decoding
Fully decoding
Partially
None of these
90) In linear decoding address bus of 16-bit wide can connect only ____ of RAM.
16 KB
6KB
12KB
64KB
91) Which statement is wrong according to linear decoding : a. Address map is not
contiguous.
b.
Confects occur if two of the select lines become active at the same time
c. If all unused address lines are not used as chip selectors then these unused lines
become dont cares
d.
None of these
92) The problem of bus confect and sparse address distribution are eliminated by the
use of
______ address technique:

Fully decoding
Half decoding
Both a & b
None of these
93) A microprocessor retries instructions from :

Control memory
Cache memory
Main memory
Virtual memory
94) Which register is used to communicate with memory:

MAR
MDR
Both A and B
None of these 95) SAM stands for:
Simple architecture machine

Solved architecture machine
Both a & b
None of these
96) MAR stands for:

Memory address register
Memory address recode
Micro address register
None of these
97) MDR stands for:

Memory data register
Memory data recode
Micro data register
None of these
98) VAM stands for:

Valid memory address
Virtual memory address
Variable memory address
None of these
99) Which microprocessor to read an item from memory:

VAM
SAM
MOC
None of these
Which bus plays a crucial role in I/O:

System bus
Control bus
Address bus
Both A and B
Which register is connected to the memory by way of the address bus:

MAR
MDR
SAM
None of these
How many bit of MAR register:

8-bit
16-bit
32-bit
64-bit
MOC stands for:

Memory operation complex
Micro operation complex
Memory operation complete
None of these
Which are the READ operation can in simple steps:
Address
Data
Control
All of these
105) The upper red arrow show that CPU sends out the control signals____ and _____
indicate the data is read from the memory:
Memory request
Read
Both A and B
None of these
The information is transferred from the_____ and ____ specified register:

MDR
CPU
Both A and B
None of these
The information on the data bus is transferred to the ______register:

MOC
MDR
VAM
CPU
108) The lower red curvy arrow show that CPU places the address extracted from the
memory location on the_____:
Address bus
System bus
Control bus
Data bus
DMA stands for:

Direct memory access
Direct memory allocation
Data memory access
Data memory allocation
DMA stands for:
Dynamic memory access
Data memory access
Both B and C
CRT stands for:
Cathode ray tube

Compared ray tube
Command ray tube
None of these
The CPU sends out a ____ signal to indicate that valid data is available on the data bus:
Read
Write
Both A and B
None of these
The ____ place the data from a register onto the data bus:
CPU
ALU
Both A and B
None of these
The CPU removes the ___ signal to complete the memory write operation:
Read
Write
Both A and B
None of these
The value memvar must be transferred to the ___:

Computer
CPU
Both A and B
None of these
The microcomputer system by using the ____device interface:

Input
Output
Both A and B
None of these
How bit microprocessor inexpensive a separate interface is provided with I/O device:
2 bit
4 bit
8 bit
32 bit
118) How many ways of transferring data between the microprocessor and a physical I/O
device:
2
3
5
The standard I/O is also called:
Isolated I/O
Parallel I/O
both a and b
none of these
standard I/O uses which control pin on the micro processor:

IO/M
A___ on this pin indicates a memory operation:

Low
High
Medium
None of these
The external device is connected to a pin called the ______ pin on the processor chip.
Interrupt
Transfer
Both
None of these
123) The DMA controllers are special hardware embedded into the chip in modern
integrate processor that ____and_____ to the system;
Data transfer
arbitrate access
Both A and B
None of these
The CPU completes yields control of the bus to the DMA controller via:
DMA acknowledge signal
DMA integrated signal
DMA implicitly signal
None of these
The mode of DMA are:

Single transfer
Block transfer
Burst block transfer
Repeated single transfer
Repeatedblock transfer
Repeated Burst block transfer
All of these
EOC stands for:
a.
End of conversion
b.
Emphasize of conversion
c.
End of controller
d.
None of these
2.
IRR stands for:
a.
Interrupt request register
b.
Input request register
c.
Interrupt resolver register
d.
Input resolver register
3.
ISR stands for:
a.
Interrupt service register
b.
Input service register
c.
In-service register
d.
All of these
4.
PR stands for:
a.
Priority register
b.
Priority resolver
c.
Priority request
d.
None of these
5.
IMR stands for:
a.
Input mask register
b.
Input mask resolver
c.
Interrupt mask resolver
d.
Interrupt mask register
6.
INT stands for:
Input
b.
Interrupt
c.
Both a and b
d.
None of these
7.
INTA stands for:
a.
Interrupt acknowledge
b.
Interrupt access
c.
Interrupt address
d.
None of these
8.
CS stands for:
a.
Command select
b.
Chip select
c.
Chip series
d.
Command series
9.
RD stands for:
a.
Read
b.
Register
c.
Request
d.
Real
10.
ICW stands for:
a.
Interrupt command words
b.
Interrupt command write
c.
Initialization command words
d.
Initialization command write
11.
OCW stands for:
a.
Operational command words
b.
Operational conjunction words
c.
Operational control words
d.
Operational cost words
12.
DMA stands for:
a.
Direct memory allocation
b.
c.
Direct memory application
d.
Direct memory acknowledgment

13.
HLD stands for:
a.
High
b.
Hour
c.
Hold
d.
None of these
14.
HLDA stands for:
a.
High acknowledgment
b.
Hold acknowledgment
c.
High access
d.
Hold access
15.
HRQ stands for:
a.
Hold request
b.
Hold read
c.
Hold register
d.
Hold resolver
16.
AEN stands for:
a.
Address enable
b.
Address equivalent
c.
Acknowledgment enable
d.
Acknowledgment equivalent
17.
ADSTB stands for:
a.
Access strobe
b.
Access strobe
c.
Address store
d.
Address strobe
18.
MEMER and MEMW means:
a.
Memory read
b.
Memory write
c.
Both a and b
d.
None of these
19.
HRQ and HLDA means:
a.
Hold request
b.
Hold acknowledgment
c.
Both a and b
d.
None of these
20.
ADC stands for:
Analogue to analogue converters
Analogue to digital converters
Digital to digital converters
Digital to analogue converters
21.
DAC stands for:
Analogue to analogue converters
Analogue to digital converters
Digital to digital converters
Digital to analogue converters
22. Which is the commonly used programmable interface and particular used to provide
handshaking:
8251
8254
8259
8255
23.
8255
8254
Which is a programmable communication interface:
8251
8259
24.
8255
Which programmable timer is used to generate timing signal :
8254
8251
8259
25.
Which is widely used in interrupt controller with a number of microprocessor:
8251
8254
8255
8259
26.
Which are used DMA controllers with 8085/8086 microprocessor:
8237
8257
Both a and b
None of these
27.
Which provide a mechanism to establish a link between the microprocessor
and i/o device:
Input interface
Output interface
Both a and b
None of these
28.
In which the processor uses a protection of the memory address to represent
I/O ports:
Memory mapped I/O

I/O memory mapped
Both a and b
None of these
29.
The standard I /O is also called:
I/O mapped I/O
Isolated I/O
Both a and b
None of these
30. The processor of knowing the status of device and transferring the data with
matching speeds is called:
Handshaking
Peripheral
Ports
None of these
31.
8251
8254
Which is designed to automatically manage the handshake operation:
8255
8259
32.
Which mode is used for single handshake in 8255:
Mode 0
Mode 1
Mode 2
None of these
33.
Which mode is used for double handshake in 8255:
Mode 0
Mode 1
Mode 2
None of these
34.
Which mode is used for simple input or output without handshaking:
Mode 0
Mode 1
Mode 2
None of these
35.
Which are used for port B in 8255:
PC0-PC2
PC3-PC7
PC6-PC7
PC3-PC5
36.
Which are used for port A in 8255 mode 1:
PC0-PC2
PC3-PC7
PC6-PC7
PC3-PC5
37.
Which are used for handshake lines for port A in 8255 mode 2:
PC0-PC2
PC3-PC7
PC6-PC7
PC3-PC5
38.
AL&99H which operation is performed here:
Input
Output
Both a & b
None of these
39.
Input
34H&AX which operation is performed here:
Output
Progress
None of these
40.
Which chip used for AD&DA converters in 8086 processor:
8251
8255
8254
8259
41. The time taken by the ADC from the active edge of SOC pulse till the active edge of
EOC signal is called:
Conversion over
Conversion delay
Conversion signal
None of these
42.
Arrange the flowing step of the general algorithm for ADC interfacing:
Issuing start of conversion pulse to ADC.
Marking the end of the conversion processes by the.
Read digital data output of the ADC as equivalent
digital output.
Ensuring the stability of analogue input applied to
the ADC.
2,1,3,4
4,1,2,3
1,2,3,4
4,3,2,1
43.
Which chip is used for analogue to digital converter:
0809
0808
Both a & b
None of these
44.
2:4
3:8
4:16
Which multiplexer by ADC 0808/0809:
None of these
45.
Which chip is used for DAC:
AD7521
AD7522
AD7523
d.
AD7524
46.
Which converters convert binary number into their equivalent voltages:
a.
Analogue to analogue
b.
Analogue to digital
c.
Digital to digital
d.
Digital to analogue
47.
An external feedback resistor acts to control the:
Gain
Gate
Loss
Profit
48. Which used to generate accurate time delays and can be used for other timing
application such as a real time clock an event counter a digital one shot a square wave
generator and a complex wave form generator:
8251 programmable timer

49.
8254 programmable timer counter has two inputs signals:
CLK
Gate
Both a & b
None of these
50.
8254 programmable timer counter has:
1output signal
2output signal
3output signal
4output signal
51.
2
8254 can operate how many operating modes:
52.
8254 gate of a counter is to either:
Enable counting
Disable counting
Both
None of these
53.
8254 counters can count in the:
Binary
Decimal
Hexadecimal
A&B
54.
How many modes in 8254:
55.
Which is the state of gate signal for normal contains:
Low
High
Undefined
None of these
56.
time:
Which generate an interrupt to the microprocessor after a certain interval of
8251
8254
8255
8259
A central processing unit, fabricated on a single chip of semiconductor is called:
Microprocessor
RAM
ROM
None of these
Which is the architecture of microprocessor:
CISC
RISC
All of these
None of these
CISC stands for:

Complex Instruction System Computer
Complex Instruction Set Car
Complex Instruction Set Computer

None of these
RISC stands for:

Reduced Instruction Set Computer
Reduced Intergraded Set Computer
Resource Instruction Set Computer
Resource Instruction System Computer
Which is the components of computer:
System Bus
CPU
Memory Unit
All of these
System Bus Contains:
Address Bus
Data Bus
Control Bus
All of these
Microprocessor is the _____ of computer:
Hand
Heart
Brain
Leg
Microprocessor is fabricated on single chip using:
MOS
ALU
CPU
All of these
Which is the components of microprocessor:
Register unit
Arithmetic and logical unit
Timing and control unit

All of these
10. Which is an integral part of any microcomputer system and its primary purpose is to
hold program and data:
Memory unit
Register unit
A and B
None of these
11. How many group of memory unit:
Four
Three
Two
One
12. Which is the parts of memory unit:
Processor memory
Main memory
Secondary memory
All of these
13. MOS stand for:
Metal oxide semiconductor

Memory oxide semiconductor
A and B
None of these
14. Which system communicates with the outside word via the I/O devices interfaced to
it:
Microprocessor
Microcomputer
Digital computer
All of these
15. A computer which has the microprocessor as______ is called as a microcomputer:
CPU
ALU
RU
None of these
16. The organization of I/O devices create a difference between _____:
Digital computer
Micro computer
A and B
None of these
17. How many generation of microprocessor:
Four
Five
Six
Three
18. The___ was very successful in the calculator market at that time:
Motorola 6800 and 6809

Microprocessor 4004
Intel 8085
None of these
19. How are the successful microprocessor:
8004
5006
4004
All of these
20. How many microprocessor in the market during the same period:
8
3
21. PMOS stands for:

P-channel metal-oxide-semiconductor
P-channel memory oxide-semiconductor
Both A and B
None of these
22. Which provided the current:
Low-cost
Slow-cost
Low-Output
All the above
23. Second Generation_____?
1974-1976
1974-1978
1974-1972
None of these
24. The beginning of very efficient____ microprocessor in second generation:
4-bit
8-bit
16-bit
64-bit
25. Which are some of popular processor:
Motorola 6800 and 6809

Intel 8085
Zilog Z80
All the above
26. NMOS stands for:

N-channel metal-oxide-semiconductor
P-channel metal-oxide-semiconductor
N-channel memory-oxide-semiconductor
All the above
27. _____ Was more common year:
CRT
TTL
Both A and B
None of these
28. Which technology speed faster and higher density:
PMOS
NMOS
HMOS
All the above
29. What is the period of 3 generation:
1979-1981
1979-1980
1978-1979
1978-1980
30. Third generation microprocessor is dominated by____ microprocessor:
8 bit
4 bit
16 bit
64 bit
31. Intel used HMOS technology to recreate_____:
8084 A
8086 A
8085 A
8088 A
32. HMOS stands for:
High performance metal oxide semiconductor

High processor metal oxide semiconductor
Both A and b
None of these
33. What is the period of fourth generation:
1979-1980
1981-1995
1995-2000
1974-1980
34. The fourth generation of microprocessor came really as a soon boon to the_____:
Computing environment
Processing environment
Hot environment
All of these
35. How many bit microprocessor in the era marked beginning of fourth generation:
4 bit
8 bit
16 bit
32 bit
36. They were fabricated using a low power version of the HMOS technology called____:
HSMOS
HCMOS
HSSOM
None of these
37. Motorola introduced _____ processor:
2 bit-RISC
4 bit-RISC
8 bit-RISC
32 bit-RISC
38. Motorola introduced 32 bit RISC processor called______:
MC 88100
MC 81100
MC 80100
MC 81000
39. Period of fifth generation?
1974-1978
1979-1980
1981-1985
1995-till date
40. The growth of vacuum tube technology has been listed as follow:
1946-1957
1958-1964
1985-1999
None of these
41. The growth of transistor technology in_____:
1946-1957
1958-1964
1985-1999
None of these
42. How are the growth of SSI technology in_____:
1956 on words
1965 on words
1978 on words
1978 on words
43. The growth of medium scale integration in______:
Till 1971
Till 1970
Till 1972
Till 1969
44. The growth of SSI up to____:
100 device on a chip

45. The growth of LSI technology on_____:
1994-1995
1971-1977
1972-1978
None of these
46. Which is most commonly measured in terms of MIPS previously million instruction
per second:
Microprocessor
Performance of a microprocessor
Assembly line
None of these
47. The range of this rating for which microprocessor of_____:
VLSI
Motorola
Intel
Zilog
48. How can we make computers work faster?
The fetch-execute cycle and pipelining

The assembly
Both A and B
None of these
49. Who is the represents the fundamental process in the operation of the CPU:
The fetch-execute cycle and pipelining

The assembly
Both A and B
None of these
50. Which process information at a much faster rate than it can retrieve it from memory:
ALU
Processor
Microprocessor
CPU
51. _____ memory system which is discussed later can improve matters in this respect:
Data memory
Cache memory
Memory
None of these
52. The fetch-execute cycle is to use a system know as:
Assembly line
Pipelining
Cache
None of these
53. The time taken for all stages of the assembly line to become active is called the:
Flow through time

Clock period
Throughput
All of these
54. The clock period is denoted by:
Tp
T1+T2+T3-------+T n
Pt
None of these
55. Ti is the time taken for the ith stage and there are n stages in the:
Throughput
Assembly line
Both A and B
None of these
56. Who is the determined by the time taken by the stages the requires the most
processing time:
Clock period
Flow through
Throughput
None of these
57. The ____ of can assembly line to be I/t p:
Clock period
Pipelining
Throughput
Flow through
58. Which is the microprocessor launched by Motorola corporation introduced:
Mc6800
8080
IMP-8
RPS-8
59. How many bit MC6800 microprocessor:
4-bit
8-bit
16-bit
32-bit
60. Motorola has declined from having nearly __________ share of the microprocessor
market to much smaller share:
30%
40%
50%
60%
61. Which is the microprocessor launch by Fairchild company:
F-6
F-8
Both A and B
None of these
62. How many stages has fetch execute cycle:
3
4
63. Which is the worlds first microprocessor?
Intel 4004
Motorola 68020
Intel8008
None of these
64. MOSFET stands for?

Metal-oxide-semiconductor field effect transistor
Metal-oxide-semiconductor fan effort transistor
Both A and B
None of these
65. What is the main problem of Intel 4004 microprocessor:
Speed
Memory size
World width
All of these
66. The evolution of the 4 bit microprocessor ended when Intel released in:
4004
8008
40964
4040
67. How many bit microprocessor still survives in low-end application such as microwave
ovens and small control system:
4 bit
16 bit
32 bit
64 bit
68. Calculator are based on______ microprocessor:
4 bit
16 bit
32 bit
64 bit
69. BCD stands for:
Binary coded decimal

Based coded decimal
Both A and B
None of these
70. Intel 8008 microprocessor realizing in:
1971
1973
1999
1988
71. Intel 8008 microprocessors upgraded version is:
8080
4004
Both A and B
None of these
72. Intel 8008 microprocessor was introduced in:
1971
1973
1999
1988
73. MC6800 microprocessor was introduced by:
Motorola corporation
Fairchild
Both A and B
None of these
74. Which Microprocessor producer continue successfully to create newer and improved
version of the microprocessor:
Intel
Motorola
Both A and B
None of these
75. Motorola has declined how many % share of the microprocessor market to a much
smaller share:
50%
55%
48%
51%
76. Which year Intel corporation introduced an updated version of the 8080- the 8085:
1965
1976
1977
1985
77. In 1977 which corporation introduced an updated version of the 8080- the 8085:
Motorola
Intel
Rockwell
National
78. How many bit microprocessor developed by Intel:
4 bit
8 bit
32 bit
64 bit
79. Which is the main feature of 8085:
Internal clock generator

Internal system controller
Higher clock frequency
All of these
80. Which is 16 Bit microprocessor:
8088
8086
8085
All of these
81. How many speed of 8088,8085,8086 microprocessor:

2.5 Million instruction per second
82. Which year Intel family ensured:
1965
1978
1981
1999
83. Which corporation decided to use 8088 microprocessor in personal computer:
IBM
CRT
PMN
SPS
84. Which processor provided 1 MB memory:
16-bit 8086 and 8088

32-bit 8086 and 8088
64-bit 8086 and 8088
8-bit 8086 and 8088
85. Who was introduce the 80286 microprocessor updated on 8086,in 1983:
Intel
Motorola
Fairchild
None of these
86. Which is the microprocessor launched by Intel:
Z-8
8080
8000
None of these
87. Which is the microprocessor launched by national semiconductor:
IMP-4
IMP-8
IMP-6
IMP-7
88. Which is the microprocessor launched by Rockwell international:
RPS-4
RPS-6
RPS-8
All of these
89. Which is the microprocessor launched by Zilog:
Z-2
Z-4
Z-6
Z-8
90. CAD stands for:
Computer aided drafting

Compare aided drafting
Both A and B
None of these
91. GUI stands for:
Graphical user interface

Graph used Intel
Graphical use inter
None of these
92. VGA stands for:
Visual graph area

Visual graphics array
Visual graph accept
All of these
93. Pentium Pro Processor contains:
L1 Cache
L2 Cache
Both L1 & L2
None of these
94. L1 cache memory is places at ______
On Processor
On Mother Board
On Memory
All of these
95. L2 cache memory is places at ______
On Processor
On Mother Board
On Memory
All of these
96. Pentium Pro can address _____ of memory:
4 GB
128 GB
256 GB
512 GB
97. Which is the professional or Business version of Intel Processors:
Pentium II
Pentium Pro
Pentium MMX
Pentium Xeon
98. Pentium III processor is released in the form of:

Socket 370 Version
Slot 1 Version in Plastic Cartridge
Both a and b
None of these
99. What is the maximum clock speed of P III processors
1.0 GHz
1.1 GHz
1.2 GHz
1.3 GHz
Power PC microprocessor architecture is developed by:
Apple
IBM
Motorola
All of these
Which is not the main architectural feature of Power PC:

It is not based on RISC
Superscalar implementation
Both 32 & 64 Bit
Paged Memory management architecture
Alpha AXP is developed by:
DEC
IBM
Motorola
Intel
Which is not the main feature of DEC Alpha:

64 Bit RISC processor
Designed to replace 32 VAX(CISC)
Seven stage split integer/floating point pipeline
Variable Instruction length
Which is not the open-source OS:
Debian
BSD Unix
Gentoo & Red Hat Linux
Windows
ISA stands for:
Instruct set area

Instruction set architecture
Both a and b
None of these
RISC stands for:

Reduced Instruction set computer
Reduced Instruct set compare
Reduced instruction stands computer
All of these
DEC stands for:
Digital electronic computer
Digital electronic corporation

Digital equipment corporation
None of these
How many architectural paradigms in microprocessor:
2
3
Which are the architectural paradigms in microprocessor:
RISC
CISC
PISC
A and B
CISC stands for:

Complex instruction set computer
Camper instruct set of computer
Compared instruction set computer
None of these
PCs use____ based on this architecture:
CPU
ALU
MU
None of these
BIU STAND FOR:

Bus interface unit
Bess interface unit
A and B
None of these
EU STAND FOR:
Execution unit
Execute unit
Exchange unit
None of these
The register can be divided are:
Which are the part of architecture of 8086:
The bus interface unit
The execution unit
Both A and B
None of these
Which are the four categories of registers:
General- purpose register
Pointer or index registers
Segment registers
Other register
All of these
Eight of the register are known as:
General- purpose register
Pointer or index registers
Segment registers
Other register
The four index register can be used for:

Arithmetic operation
Multipulation operation
Subtraction operation
All of these
IP Stand for:
Instruction pointer
Instruction purpose
Instruction paints
None of these
CS Stand for:
Code segment
Coot segment
Cost segment
Counter segment
DS Stand for:
Data segment
Direct segment
Declare segment
Divide segment
Which are the segment:
CS: Code segment
DS: data segment
SS: Stack segment
ES:extra segment
All of these
The acculatator is 16 bit wide and is called:
AX
AH
AL
DL
The upper 8 bit are called______:
BH
BL
AH
CH
The lower 8 bit are called_______:
AL
CL
BL
DL
IP stand for:
Industry pointer
Instruction pointer
Index pointer
None of these
Which has great important in modular programming:
Stack segment
Queue segment
Array segment
All of these
Which register containing the 8086/8088 flag:
Status register
Stack register
Flag register
Stand register
Which flag are used to record specific characteristics of arithmetic and logical
instructions:
The stack
The stand
The status
The queue
How many bits the instruction pointer is wide:
16 bit
32 bit
64 bit
128 bit
How many type of addressing in memory:
Logical address
Physical address
Both A and B
None of these
The size of each segment in 8086 is:
64 kb
24 kb
50 kb
16kb
The physical address of memory is :
20 bit
16 bit
32 bit
64 bit
The _______ address of a memory is a 20 bit address for the 8086 microprocessor:
Physical
Logical
Both
None of these
To provide clarity in case of the status register_______ and __________ placeholders are
displayed:
Binary
Hexadecimal
Both
None of these
The pin configuration of 8086 is available in the________:
40 pin
50 pin
30 pin
20 pin
DIP stand for:
Deal inline package
Dual inline package
Direct inline package
Digital inline package
PA stand for:
Project address
Physical address
Pin address
Pointer address
SBA stand for:
Segment bus address
Segment bit address
Segment base address
Segment byte address
EA stand for:
Effective address
Electrical address
Effect address
None of these
BP stand for:
Bit pointer
Base pointer
Bus pointer
Byte pointer
DI stand for:
Destination index
Defect index
Definition index
Delete index
SI stand for:
Stand index
Source index
Segment index
Simple index
DS stand for:
Default segment
Defect segment
Delete segment
Definition segment
ALE stand for:
Address latch enable
Address light enable
Address lower enable
Address last enable
AD stand for:
Address data
Address delete
Address date
Address deal
NMI stand for:
Non mask able interrupt
Non mistake interrupt
Both
None of these
PC stand for:
program counter
project counter
protect counter
planning counter
AH stand for:
Accumulator high
Address high
Appropriate high
Application high
AL stand for:
Accumulator low
Address low
Appropriate low
Application low
Which are the categorized of flag:
Conditional flag
Control flag
Both a and b
None of these
Which are the general register:
AX: Accumulator
BX: Base
CX: Count
DX: Data
All of these
________ is the most important segment and it contains the actual assembly language
instruction to be executed by the microprocessor:
Data segment
Code segment
Stack segment
Extra segment
The offset of a particular segment varies from _________:
000H to FFFH
0000H to FFFFH
00H to FFH
00000H to FFFFFH
Which are the factor of cache memory:
Architecture of the microprocessor
Properties of the programs being executed
Size organization of the cache
All of these
________ is usually the first level of memory access by the microprocessor:
Cache memory
Data memory
Main memory
All of these
which is the small amount of high- speed memory used to work directly with the
microprocessor:
Cache
Case
Cost
Coos
The cache usually gets its data from the_________ whenever the instruction or data is
required by the CPU:
Main memory
Case memory
Cache memory
All of these
The amount of information which can be placed at one time in the cache memory is
called_________:
Circle size
Line size
Wide line size
None of these
How many type of cache memory:
Which is the type of cache memory:
Fully associative cache
Direct-mapped cache
Set-associative cache
All of these
Which memory is used to holds the address of the data stored in the cache :
Associative memory
Case memory
Ordinary memory
None of these
Direct mapping is a _________ to implement cache memory :
Cheaper way
Case way
Cache way
None of these
A fourth bit called the _________:
Direct bit
Cache bit
Valid bit
All of these
FIFO stand for:
First in first other
First in first out
First in first over
None of these
Microprocessor reference that are available in the cache are called______:
Cache hits
Cache line
Cache memory
All of these
Microprocessor reference that are not available in the cache are called_________:
Cache hits
Cache line
Cache misses
Cache memory
__________ is the most commonly used cache controller with a number of processor sets:
L211 controller
L210 controller
L214 controller
None of these
LFB stand for:
Line full buffers
Line fill buffers
Line fan buffers
None of these
LRB stand for:
Line read buffers
Line ready buffers
Line root buffers
Line right buffers
EB stand for:
Effect buffers
Effecting buffers
Effection buffers
None of these
EB stand for:
Effect buffers
Effecting buffers
Effection buffers
Eviction buffers
WB stand for:
Write buffers
Written buffers
Wrote buffers
None of these
WA stand for:
Write allocate
Wrote allocate
Way allocate
Word allocate
In case of direct- mapped cache lower order line address bits are used the access the
___________:
RAM
ROM
Directory
HDD
The index high order bits in the address known as_________:
tags
label
point
location
e.
The parity bits are used to check that a__________:
Two bit error
Single bit error
Multi bit error
None of these
Who works as cache on the variable:
Register
Memory
Pointer
Segment
Second level is a cache on the ________:
Main memory
RAM
Both
None of these
The memory system is said to be effective if the access time of the cache is close to the
effective access time of the_____:
ROM
RAM
HDD
Processor
Cache is usually the____________ of memory access by the microprocessor:
First level
Second level
Third level
Fourth level
The principal of working of the cache memory largely depends on which locality:
Spatial locality
Temporal locality
Sequentially
All of these
Who work as a cache for the page table:
TLB
TLP
LEB
WAB
Which formula is used to calculate the number of read stall cycles:
Reads* Read miss rate * Read miss penalty
Write* (Write miss rate * Write miss penalty)+write buffer stalls
Memory access * Cache miss rate * Cache miss penalty
None of these
Which formula is used to calculate the number of write stall cycles:
None of these
Which formula is used to calculate the number of memory stall cycles:

None of these
Which causes the microprocessor to immediately terminate its present activity:
RESET signal
INTERUPT signal
Both
None of these
Which are the cache controller ports:
64-bit AHB-Lite slave ports
64-bit AHB-Lite master ports
Both
None of these
Cache can be controlled __________:
16KB-2MB
17 KB-2MB
18 KB-2MB
19 KB-2MB
Which is responsible for all the outside world communication by the microprocessor:
BIU
PIU
TIU
LIU
e.
INTR: it implies the__________ signal:
INTRRUPT REQUEST
INTRRUPT RIGHT
INTRRUPT RONGH
INTRRUPT RESET

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Who is the brain of computer:

Which technology using the microprocessor is fabricated on a single chip:

MOS stands for:

Memory oxide semiconductor

Metal oxide select

In which form CPU provide output:

How many types of microprocessor comprises:

Which is the microprocessor comprises:

One or more ALU

The register section is related to______ of the computer:

What is the store by register:

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How many types of classification of processor based on register section:

10) In Microprocessor one of the operands holds a special register called:

11) Accumulator based microprocessor example are:

12) A set of register which contain are:

13) How many types are primarily register:

14) There are primarily two types of register:

15) Which register is a temporary storage location:

general purpose register

16) How many parts of dedicated register:

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17) Name of typical dedicated register is:

18) PC stands for:

19) IR stands for:

Instruction register 20) SP stands for:

21) The act of acquiring an instruction is referred as the____ the instruction:

23) How many parts of single address computer instruction :

24) Single address computer instruction has two parts:

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The operation code

25) LA stands for:

26) ED stands for:

None of these 27) LM stands for:

28) Causing a flag to became 0 is called:

29) Which are the flags of status register:

Half carry flag

30) The carry is operand by:

31) The sign is operand by:

32) The zero is operand by:

33) The overflow is operand by:

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36) _________ Stores the instruction currently being executed:

37) In which register instruction is decoded prepared and ultimately executed:

38) The status register is also called the____:

39) BCD stands for:

Binary coded decoded

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Stack pointer register

45) Which point to the ___ of the stack:

None of these 46) Stack words on:

47) Which is the basic stack operation:

None of these 48) SP stand for:

49) How many bit stored by status register:

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50) Which is the important part of a combinational logic block:

51) The structure of the stack is _______ type structure:

Last in last out

52) The data in the stack is called:

53) The CU is designed by using which techniques:

55) A nibble can be represented in the from of:

The information is transferred from the_ and specified register: