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  • IC Package Release - Version Description

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    Yeu Em
    154 Ansichten11 Seiten
    In integrated circuit design, waveform viewers are typically used in conjunction with a simulation. A waveform view allows an IC designer to see the signal transitions over time and the relation of those signals with other signals in an IC design, which is typically written in a hardware description language. Simulators can be used to interactively capture wave data for immediate viewing on a waveform viewer; however, for integrated circuit design the usage model is typically to save the output of simulation runs by running batch jobs and to view the waveforms off-line as a static database.[1]

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    Cadence14-15forWeb

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    In integrated circuit design, waveform viewers are typically used in conjunction with a simulation. A waveform view allows an IC designer to see the signal transitions over time and the relation of those signals with other signals in an IC design, which is typically written in a hardware description language. Simulators can be used to interactively capture wave data for immediate viewing on a waveform viewer; however, for integrated circuit design the usage model is typically to save the output of simulation runs by running batch jobs and to view the waveforms off-line as a static database.[1]

    Copyright:

    © All Rights Reserved
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    Markieren Sie unangemessene Inhalte
    154 Ansichten11 Seiten

    IC Package Release - Version Description

    Hochgeladen von

    Yeu Em
    In integrated circuit design, waveform viewers are typically used in conjunction with a simulation. A waveform view allows an IC designer to see the signal transitions over time and the relation of those signals with other signals in an IC design, which is typically written in a hardware description language. Simulators can be used to interactively capture wave data for immediate viewing on a waveform viewer; however, for integrated circuit design the usage model is typically to save the output of simulation runs by running batch jobs and to view the waveforms off-line as a static database.[1]

    Copyright:

    © All Rights Reserved
    Als PDF, TXT herunterladen oder online auf Scribd lesen
    Markieren Sie unangemessene Inhalte
    von 11

    Europractice Cadence

    2014-15 release
    IC Package
    release_version
    ASSURA 4.1
    ASSURA 4.1
    ASSURA 4.1
    CONFRML14.1
    CONFRML14.1
    CONFRML14.1
    CONFRML14.1
    CTOS 14.1
    EDI 14.1
    EDI 14.1
    EDI 14.1
    EDI 14.1
    EDI 14.1
    EDI 14.1
    EDI 14.1
    EDI 14.1
    ET 14.1
    ET 14.1
    ET 14.1
    ET 14.1
    ET 14.1
    ETS 13.1
    ETS 13.1
    ETS 13.1
    ETS 13.1
    ETS 13.1
    EXT 14.1
    EXT 14.1
    EXT 14.1
    EXT 14.1
    EXT 14.1

    Description
    Assura(TM) Design Rule Checker
    Assura(TM) Layout Vs. Schematic Verifier
    Assura(TM) Multiprocessor Option
    CCD Multi-Constraint Check Option
    Encounter (R) Conformal Constraint Designer - XL
    Encounter Conformal Low Power - GXL
    Encounter Conformal ECO Designer - GXL
    C-to-Silicon Compiler - L
    Encounter Digital Implementation System XL
    Encounter CPU Accelerator Option
    Encounter Mixed Signal GXL Option
    Encounter Giga Scale GXL Option
    Encounter Universal 20 GXL Option
    Encounter Clock Concurrent Optimization
    Encounter Advanced Node GXL Option
    Encounter Low Power GXL Option
    Encounter True Time ATPG Advanced
    Option to RC - DFT Architect Advanced
    Encounter Test LBIST Option
    Encounter Test Advanced MBIST Option
    Encounter Diagnostics Basic
    Encounter Library Characterizer - GXL
    Encounter Power System XL
    EPS Advanced Analysis GXL Option
    Encounter Timing System-XL
    ETS Advanced Analysis GXL Option
    Cadence QRC Advanced Modeling20 GXL Option
    Cadence QRC Extraction - XL
    Cadence QRC Advanced Modeling GXL Option
    Cadence QRC Advanced Analysis GXL Option
    Cadence QRCX Display Technology Option

    Europractice Cadence
    2014-15 release
    IC 6.1.6
    IC 6.1.6
    IC 6.1.6
    IC 6.1.6
    IC 6.1.6
    IC 6.1.6
    IC 6.1.6
    IC 6.1.6
    IC 6.1.6
    IC 6.1.6
    IC 6.1.6
    IC 6.1.6
    IC 6.1.6
    IC 6.1.6
    IC 6.1.6
    IC 6.1.6
    IC 6.1.6
    IC 6.1.6
    IC 6.1.6
    IC 6.1.6
    IC 6.1.6
    IC 6.1.6
    IC 6.1.6
    IC 6.1.6
    IC 6.1.6
    IC 6.1.6
    IC 6.1.6
    IC 6.1.6
    IC 6.1.6
    IC 6.1.6
    IC 6.1.6
    IC 6.1.6
    IC 6.1.6

    Virtuoso(R) Layout Suite - GXL


    Virtuoso(R) Analog Design Environment - GXL
    Virtuoso Implementation Aware Design Option
    Virtuoso(R) Power System XL
    Virtuoso EAD Advanced Electrical Analysis
    Virtuoso Layout Suite EAD
    Cadence(R) SKILL Development Environment
    Virtuoso(R) Layout Suite - GXL
    Virtuoso(R) EDIF 200 Reader
    Virtuoso(R) Layout Suite - GXL
    Virtuoso(R) Schematic Editor XL
    Virtuoso(R) Visualization & Analysis XL
    Dracula(R) Design Rule Checker
    Virtuoso(R) DFM Option
    Virtuoso SMG Runtime
    Virtuoso Behavioral Modeling Option
    Virtuoso(R) Analog Oasis Run-Time Option
    Diva(R) Layout Vs. Schematic Verifier
    Diva(R) Design Rule Checker
    Dracula(R) Parasitic Extractor
    Diva(R) Parasitic Extractor
    Virtuoso(R) Schematic VHDL Interface
    Virtuoso(R) Schematic Editor Verilog(R) Interface
    Virtuoso(R) EDIF 200 Writer
    Virtuoso(R) AMS Designer Environment
    Cadence(R) Design Framework II
    Virtuoso(R) Layout Migrate
    Cadence(R) OASIS for RFDE
    Virtuoso(R) Schematic Editor HSPICE Interface
    Dracula(R) Layout Vs. Schematic Verifier
    Cadence Framework Integration Runtime Option
    Cadence(R) Design Framework Integrator's Toolkit
    Virtuoso(R) Simulation Environment

    Europractice Cadence
    2014-15 release
    IC 6.1.6
    IC 6.1.6
    IC 6.1.6
    INCISIV 14.1
    INCISIV 14.1
    INCISIV 14.1
    INCISIV 14.1
    INCISIV 14.1
    INCISIV 14.1
    INCISIV 14.1
    INCISIV 14.1
    INCISIV 14.1
    INCISIV 14.1
    INCISIV 14.1
    INCISIV 14.1
    LIBERATE 13.1
    LIBERATE 13.1
    LIBERATE 13.1
    LIBERATE 13.1
    LIBERATE 13.1
    LIBERATE 13.1
    LIBERATE 13.1
    LIBERATE 13.1
    LIBERATE 13.1
    LIBERATE 13.1
    LIBERATE 13.1
    LIBERATE 13.1

    Virtuoso(R) Analog HSPICE Interface Option


    Virtuoso(R) Layout Suite - GXL
    Virtuoso EAD 3D Precision Solver
    Incisive Advanced Option
    Incisive Software Extensions
    Cadence(R) Export Model Packager
    Incisive Formal Verifier
    Incisive Low-Power Simulation Option
    AMS Designer with Flexible Analog Simulation
    Virtuoso AMS Designer Verification Option
    Digital Mixed Signal Option to IES
    Incisive Enterprise Simulator - XL
    Incisive Enterprise Verifier - XL
    Verifault(R)-XL simulator
    Incisive Enterprise Manager
    Virtuoso Liberate LV Client
    Virtuoso Liberate LV Server
    Virtuoso Liberate Client
    Virtuoso Variety Client
    Virtuoso Variety MX Server
    Virtuoso Liberate Server
    Virtuoso Variety Server
    Virtuoso Liberate AMS Server
    Virtuoso Liberate MX Client
    Virtuoso Variety MX Client
    Virtuoso Liberate MX Server
    Virtuoso Liberate AMS Client

    Europractice Cadence
    2014-15 release
    MMSIM 13.1
    MMSIM 13.1
    MMSIM 13.1
    MMSIM 13.1
    MMSIM 13.1
    MMSIM 13.1
    MVS 14.1
    MVS 14.1
    PVS 14.1
    PVS 14.1
    PVS 14.1
    PVS 14.1
    PVS 14.1
    PVS 14.1
    PVS 14.1
    PVS 14.1
    PVS 14.1
    PVS 14.1
    PVS 14.1
    PVS 14.1
    PVS 14.1
    PVS 14.1
    PVS 14.1
    PVS 14.1
    PVS 14.1
    PVS 14.1
    PVS 14.1
    RC 14.1
    RC 14.1
    RC 14.1
    RC 14.1

    Spectre Extensive Partitioned Simulator


    Virtuoso(R) Spectre Model Interface Option
    Virtuoso(R) RelXpert
    Virtuoso Multi-mode Simulation with AP Simulator
    Virtuoso Multi-mode Simulation with AP Simulator
    Virtuoso Multi-mode Simulation CPU Accelerator option
    Encounter DFM GXL Option
    Virtuoso LDE Analyzer Option
    Cadence(R) Physical Verification System Programmable Electrical Rules Checker
    Cadence Physical Verification System Advanced Metal Fill Option for PVS DRC XL (96210)
    PVS Design Analysis Option
    PVS Design Analysis Option
    Cadence(R) Physical Verification System Graphic LVS Debugger
    Cadence(R) Physical Verification System Layout vs. Schematic Checker XL
    Cadence(R) Physical Verification System Layout vs. Schematic Checker XL
    Cadence(R) Physical Verification System Design Rule Checker XL
    Cadence(R) Physical Verification System Design Rule Checker XL
    Virtuoso Integrated Physical Verification System Advanced Analysis Option for IPVS (96400)
    Cadence(R) Physical Verification System Advanced Device Parameter Extraction Option for PVS LVS XL (96220)
    Cadence(R) Physical Verification System Interactive Short Locator Option
    Virtuoso(R) Integrated Physical Verification System Option for Virtuoso Layout Suite (95300, 95310)
    Cadence(R) Physical Verification System Hierarchical DFM SignOff Option
    Cadence Physical Verification System Advanced Analysis Option for PVS DRC XL (96210)
    Cadence Physical Verification System Advanced Analysis Option for PVS DRC XL (96210)
    Cadence(R) Physical Verification System Constraint Validator
    Cadence(R) QuickView Layout and Mask Data Viewer
    Cadence QuickView Sign-Off Data Analysis Environment
    Encounter RTL Compiler - XL
    Encounter RTL Compiler CPU Accelerator Option
    Encounter RTL Compiler Low Power Option
    Encounter RTL Compiler Advanced Physical Option

    Europractice Cadence
    2014-15 release
    SSV 14.1
    SSV 14.1
    SSV 14.1
    SSV 14.1
    SSV 14.1
    SSV 14.1
    VIPCAT 11.3
    VIPCAT 11.3
    VIPCAT 11.3
    VIPCAT 11.3
    VIPCAT 11.3
    VIPCAT 11.3
    VIPCAT 11.3
    VIPCAT 11.3
    VIPCAT 11.3
    VIPCAT 11.3
    VIPCAT 11.3
    VIPCAT 11.3
    VIPCAT 11.3
    VIPCAT 11.3
    VIPCAT 11.3

    Voltus IC Power Integrity Solution - XL (VTS-XL)


    Tempus Timing Signoff Solution XL
    Voltus IC Power Integrity Solution Advanced Analysis GXL Option (VTS-AA)
    Tempus Timing Signoff Solution MP
    Tempus Timing Signoff Solution TSO
    Voltus IC Power Integrity Solution - MP (VTS-MP) (Acceleration Option to Voltus IC XL (VTS200))
    Memory Model Portfolio
    Memory Model for Flash PPN DDR
    VIP for USB 3.0 & OTG
    Memory Model for LRDIMM
    VIP for HDMI 1.4
    VIP for MR-IOV
    VIP for OCP 3.0
    VIP for PCI Express 3.0
    SOC Portfolio
    VIP for PCI Express 1.1 & 2.0 PureSuite - Initial Release
    VIP for SATA 6G
    VIP for MIPI SLIMbus
    Memory Model for Flash Toggle NAND 2
    Memory Model for Flash ONFi 3
    PureView

    Europractice Cadence
    2014-15 release
    Systems Package
    release_version
    ASI 16.6
    ASI 16.6
    ASI 16.6
    ASI 16.6
    ASIS 16.65
    ASIS 16.65
    ASIS 16.65
    INCISIV 14.1
    INCISIV 14.1
    INCISIV 14.1
    INCISIV 14.1
    INCISIV 14.1
    INCISIV 14.1
    INCISIV 14.1
    INCISIV 14.1
    INCISIV 14.1
    INCISIV 14.1
    INCISIV 14.1
    INCISIV 14.1
    SPB 16.6
    SPB 16.6
    SPB 16.6
    SPB 16.6
    SPB 16.6
    SPB 16.6
    SPB 16.6
    SPB 16.6
    SPB 16.6
    SPB 16.6
    SPB 16.6

    Description
    Allegro Sigrity Power Aware SI Option
    Allegro Sigrity System Serial Link Option
    Allegro Sigrity Package Assessment and Extraction Option
    Allegro Sigrity SI Base
    Allegro Sigrity Power Integrity Signoff and Optimization Option
    Allegro Sigrity PI Base
    Cadence IO-SSO Analysis Suite
    AMS Designer with Flexible Analog Simulation
    Virtuoso AMS Designer Verification Option
    Incisive Enterprise Simulator - XL
    Digital Mixed Signal Option to IES
    Incisive Advanced Option
    Verifault(R)-XL simulator
    Incisive Low-Power Simulation Option
    Incisive Enterprise Manager
    Cadence(R) Export Model Packager
    Incisive Software Extensions
    Incisive Enterprise Verifier - XL
    Incisive Formal Verifier
    Allegro(R) Design Authoring
    Allegro PCB Designer
    Allegro PCB High-Speed Option
    Allegro PCB Miniaturization Option
    Allegro(R) PCB Team Design Option
    Allegro PCB Routing Option
    Allegro PCB Design Planning Option
    Allegro(R) PCB Librarian
    Allegro(R) ASIC Prototyping with FPGA's
    Allegro Design Authoring Multi-Style Option
    Allegro(R) AMS Simulator

    Europractice Cadence
    2014-15 release
    SPB 16.6
    SPB 16.6
    SPB 16.6
    SPB 16.6
    SPB 16.6
    SPB 16.6
    SPB 16.6
    SPB 16.6
    VIPCAT 11.3
    VIPCAT 11.3
    VIPCAT 11.3
    VIPCAT 11.3
    VIPCAT 11.3
    VIPCAT 11.3
    VIPCAT 11.3
    VIPCAT 11.3
    VIPCAT 11.3
    VIPCAT 11.3
    VIPCAT 11.3
    VIPCAT 11.3
    VIPCAT 11.3
    VIPCAT 11.3
    VIPCAT 11.3

    Allegro(R) PCB Analog/RF Option


    Cadence SiP Layout - XL
    Cadence 3D Design Viewer
    Allegro PCB Global Route Environment Option - XL
    Allegro(R) Design Authoring Team Design Option
    Allegro(R) Physical Viewer
    Allegro Design Authoring High-Speed Option
    Cadence(R) SKILL Development Environment
    VIP for MR-IOV
    Memory Model for Flash PPN DDR
    VIP for USB 3.0 & OTG
    Memory Model for Flash ONFi 3
    Memory Model for Flash Toggle NAND 2
    VIP for MIPI SLIMbus
    VIP for SATA 6G
    VIP for PCI Express 1.1 & 2.0 PureSuite - Initial Release
    SOC Portfolio
    VIP for OCP 3.0
    VIP for HDMI 1.4
    Memory Model Portfolio
    Memory Model for LRDIMM
    VIP for PCI Express 3.0
    PureView

    Europractice Cadence
    2014-15 release
    TLM Package
    release_version
    CONFRML14.1
    CONFRML14.1
    CONFRML14.1
    CTOS 14.1
    INCISIV 14.1
    INCISIV 14.1
    INCISIV 14.1
    INCISIV 14.1
    INCISIV 14.1
    INCISIV 14.1
    INCISIV 14.1
    INCISIV 14.1
    INCISIV 14.1
    INCISIV 14.1
    INCISIV 14.1
    INCISIV 14.1
    INCISIV 14.1
    RC 14.1
    RC 14.1
    RC 14.1
    VIPCAT 11.3
    VIPCAT 11.3
    VIPCAT 11.3
    VIPCAT 11.3
    VIPCAT 11.3
    VIPCAT 11.3
    VIPCAT 11.3
    VIPCAT 11.3
    VIPCAT 11.3
    VIPCAT 11.3

    Description
    Encounter Conformal Low Power - GXL
    Encounter (R) Conformal Constraint Designer - XL
    CCD Multi-Constraint Check Option
    C-to-Silicon Compiler - L
    Virtuoso AMS Designer Verification Option
    Digital Mixed Signal Option to IES
    Incisive Advanced Option
    Verifault(R)-XL simulator
    Incisive Low-Power Simulation Option
    AMS Designer with Flexible Analog Simulation
    Incisive Enterprise Verifier - XL
    Incisive Enterprise Manager
    Cadence(R) Export Model Packager
    Incisive Software Extensions
    Cadence System Creator - L
    Incisive Formal Verifier
    Incisive Enterprise Simulator - XL
    Encounter RTL Compiler - XL
    Encounter RTL Compiler CPU Accelerator Option
    Encounter RTL Compiler Low Power Option
    VIP for PCI Express 3.0
    VIP for USB 3.0 & OTG
    Memory Model for Flash ONFi 3
    Memory Model for LRDIMM
    Memory Model Portfolio
    VIP for HDMI 1.4
    VIP for OCP 3.0
    SOC Portfolio
    VIP for PCI Express 1.1 & 2.0 PureSuite - Initial Release
    VIP for SATA 6G

    Europractice Cadence
    2014-15 release
    VIPCAT 11.3
    VIPCAT 11.3
    VIPCAT 11.3
    VIPCAT 11.3
    VIPCAT 11.3

    VIP for MIPI SLIMbus


    Memory Model for Flash Toggle NAND 2
    Memory Model for Flash PPN DDR
    VIP for MR-IOV
    PureView

    Europractice Cadence
    2014-15 release
    PCB Studio Package
    release_version
    ASI 16.6
    SPB 16.6
    SPB 16.6
    SPB 16.6
    SPB 16.6

    Description
    Allegro Sigrity SI Base
    Allegro(R) Design Entry CIS
    Allegro PCB Designer
    Allegro(R) AMS Simulator
    Allegro 2 FPGA System Planner Option

    Europractice Cadence
    2014-15 release
    Cynthesizer Optional Package
    release_version
    FORTE
    Cynthesizer Low Power
    FORTE
    Interface Generator
    Virtual Systems Platform Optional Package
    Release
    Description
    INCISIV 14.1
    Cadence System Creator - L
    3DIC Optional Package
    Release
    Description
    EDI 13.1
    Encounter Stacked Die GXL Option
    IC 6.1.6
    Virtuoso Stacked Die Option
    Virtuoso Advanced Node Optional Package
    Release
    Description
    ICADV 12.1
    Virtuoso Advanced Node Framework
    ICADV 12.1
    Virtuoso Implementation Aware Design Option
    ICADV 12.1
    Virtuoso Advanced Node Option for Layout
    EXT 14.1
    Advanced Node Modeling Option
    MVS 14.1
    Litho Physical Analyzer
    MVS 14.1
    Distributed Process for 8 CPUs
    SIP Optional Package
    Release
    SPB 16.6
    SPB 16.6
    SPB 16.6

    Description
    Cadence SiP Digital Architect - GXL
    Virtuoso SiP Architect XL
    Cadence Chip Integration Option

    Description

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