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TPS54340
SLVSBK0B OCTOBER 2012 REVISED MARCH 2014
3 Description
PACKAGE
BODY SIZE
TPS54340DDA
HSOIC (8)
4,89mm x 3,9mm
spacer
spacer
2 Applications
12 V, 24 V Industrial, Automotive
Communications Power Systems
and
4 Simplified Schematic
Figure 1. Efficiency vs Load Current
VIN
VIN
100
90
TPS54340
80
EN
SW
R1
COMP
VOUT = 3.3V
60
50
40
30
20
FB
R3
GND
Efficiency - %
VOUT
RT/CLK
VOUT = 5V
70
BOOT
VIN = 12V
fsw = 600 kHz
10
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
IO - Output Current - A
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS54340
SLVSBK0B OCTOBER 2012 REVISED MARCH 2014
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Simplified Schematic.............................................
Revision History.....................................................
Terminal Configuration and Functions................
Specifications.........................................................
1
1
1
1
2
3
4
7.1
7.2
7.3
7.4
7.5
7.6
7.7
4
4
4
4
5
6
6
5 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (February 2013) to Revision B
Page
Changed the Operating: nonswitching supply current TEST CONDITIONS From: FB = 0.83 V To: FB = 0.9 V ................. 5
Changed RT/CLK high threshold MAX value From: 1.7 V To: 2 V ....................................................................................... 5
Changed Figure 7 title From: HIGH FREQUENCY RANGE To: LOW FREQUENCY RANGE ............................................. 6
Changed Figure 8 title From: LOW FREQUENCY RANGE To: HIGH FREQUENCY RANGE ............................................. 7
Page
TPS54340
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SW
GND
COMP
FB
BOOT
VIN
EN
RT/CLK
Thermal
Pad
9
Terminal Functions
TERMINAL
NAME
NO.
I/O
DESCRIPTION
BOOT
A bootstrap capacitor is required between BOOT and SW. If the voltage on this capacitor is below the
minimum required to operate the high side MOSFET, the output is switched off until the capacitor is
refreshed.
VIN
EN
Enable terminal, with internal pull-up current source. Pull below 1.2 V to disable. Float to enable. Adjust the
input undervoltage lockout with two resistors. See the Enable and Adjusting Undervoltage Lockout section.
RT/CLK
Resistor Timing and External Clock. An internal amplifier holds this terminal at a fixed voltage when using an
external resistor to ground to set the switching frequency. If the terminal is pulled above the PLL upper
threshold, a mode change occurs and the terminal becomes a synchronization input. The internal amplifier is
disabled and the terminal is a high impedance clock input to the internal PLL. If clocking edges stop, the
internal amplifier is re-enabled and the operating mode returns to resistor frequency programming.
FB
COMP
Error amplifier output and input to the output switch current (PWM) comparator. Connect frequency
compensation components to this terminal.
GND
Ground
SW
The source of the internal high-side power MOSFET and switching node of the converter.
Thermal Pad
GND terminal must be electrically connected to the exposed pad on the printed circuit board for proper
operation.
TPS54340
SLVSBK0B OCTOBER 2012 REVISED MARCH 2014
www.ti.com
7 Specifications
7.1 Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
VIN
0.3
45
EN
0.3
8.4
BOOT
Input voltage
53
FB
0.3
COMP
0.3
RT/CLK
0.3
3.6
8
SW
SW, 10-ns Transient
BOOT-SW
Output voltage
UNIT
0.6
45
45
40
150
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
MIN
MAX
65
150
kV
500
(2)
(3)
UNIT
Electrostatic discharge (ESD) to measure device sensitivity and immunity to damage caused by assembly line electrostatic discharges
into the device.
Level listed above is the passing level per ANSI/ESDA/JEDEC JS-001. JEDEC document JEP155 states that 500V HBM allows safe
manufacturing with a standard ESD control process. terminals listed as 1000V may actually have higher performance.
Level listed above is the passing level per EIA-JEDEC JESD22-C101. JEDEC document JEP157 states that 250V CDM allows safe
manufacturing with a standard ESD control process. terminals listed as 250V may actually have higher performance.
MAX
UNIT
VIN
4.5
42
VO
Output voltage
0.8
41.1
IO
Output current
TJ
Junction Temperature
40
150
TPS54340
DDA (8 TERMINALS)
JA
42.0
JT
5.9
JB
23.4
JCtop
45.8
JCbot
3.6
JB
23.4
(1)
(2)
UNIT
C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
Power rating at a specific ambient temperature TA should be determined with a junction temperature of 150C. This is the point where
distortion starts to substantially increase. See power dissipation estimate in application section of this data sheet for more information.
TPS54340
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TEST CONDITIONS
MIN
TYP
MAX
UNIT
42
4.3
4.48
4.5
Rising
4.1
325
mV
1.3
3.5
FB = 0.9 V, TA = 25C
146
175
1.2
1.3
1.1
Hysteresis current
4.6
V
A
0.58
1.2
-1.8
2.2
3.4
-4.5
0.792
0.8
0.808
92
190
VOLTAGE REFERENCE
Voltage reference
HIGH-SIDE MOSFET
On-resistance
VIN = 12 V, BOOT-SW = 6 V
ERROR AMPLIFIER
Input current
Error amplifier transconductance (gM)
VFB = 0.8 V
50
nA
350
Mhos
77
Mhos
10,000
V/V
2500
kHz
30
12
A/V
CURRENT LIMIT
4.5
5.5
6.8
4.5
5.5
6.25
5.2
5.5
5.85
THERMAL SHUTDOWN
Thermal shutdown
Thermal shutdown hysteresis
176
12
Switching frequency
100
RT = 200 k
450
160
1.55
(1)
500
0.5
2500
kHz
550
kHz
2300
kHz
1.2
V
V
Open Loop current limit measured directly at the SW terminal and is independent of the inductor value and slope compensation.
TPS54340
SLVSBK0B OCTOBER 2012 REVISED MARCH 2014
www.ti.com
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIN = 12 V , TA = 25C
540
2.1
ms
Soft-Start Time
0.42
ms
VIN = 12 V, TA = 25C
135
ns
60
ns
15
ns
HIGH-SIDE MOSFET
Minimum controllable on time
CURRENT LIMIT
Current limit threshold delay
TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK TERMINAL)
Minimum CLK input pulse width
RT/CLK falling edge to SW rising edge
delay
55
ns
78
0.814
VFB - Voltage Referance ( V)
BOOT-SW = 3 V
BOOT-SW = 6 V
0.2
0.15
0.1
0.05
0
50
25
0
25
50
75
100
TJ Junction Temperature (C)
125
0.809
0.804
0.799
0.794
0.789
0.784
150
50
25
50
75
100
125
150
C026
VIN = 12 V
6.5
6.5
6.3
6.3
VIN = 12V
6.1
5.9
5.7
5.5
5.3
5.1
4.9
TJ = 40C
TJ = 25C
TJ = 150C
6.1
5.9
5.7
5.5
5.3
5.1
4.9
4.7
4.7
4.5
4.5
50
25
25
50
75
100
125
150
10
C027
15
20
25
30
VIN Input Voltage (V)
35
40
45
G004
VIN = 12V
VIN = 12 V
Figure 4. Switch Current Limit vs Junction Temperature
25
G001
TPS54340
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550
500
540
450
530
520
510
500
490
480
470
460
450
400
350
300
250
200
150
100
50
0
50
25
25
50
75
100
125
VIN = 12 V
150
200
300
400
500
600
700
800
900
RT/CLK - Resistance (k )
C029
1000
C030
RT = 200 k
2500
500
450
2000
400
1500
gm (A/V)
1000
300
500
250
50
100
150
RT/CLK Resistance (k)
200
200
50
25
50
75
100
125
150
C032
120
110
EN - Threshold (V)
100
90
80
70
60
50
40
30
20
25
VIN = 12 V
50
25
G007
VIN = 12V
gm (A/V)
350
25
50
75
100
125
150
1.3
1.29
1.28
1.27
1.26
1.25
1.24
1.23
1.22
1.21
1.2
1.19
1.18
1.17
1.16
1.15
50
25
VIN = 12 V
25
50
75
100
125
C033
150
C034
VIN = 12 V
TPS54340
SLVSBK0B OCTOBER 2012 REVISED MARCH 2014
www.ti.com
0.5
0.7
4.1
0.9
4.2
1.1
4.3
1.3
4.4
IEN (A)
IEN (A)
1.5
1.7
4.5
4.6
1.9
4.7
2.1
4.8
2.3
4.9
5
50
2.5
50
25
25
50
75
100
125
150
VIN = 5 V
150
G012
100
VFB Falling
VFB Rising
2.7
2.9
IEN - Hysteresis (A)
125
2.5
3.1
3.3
3.5
3.7
3.9
4.1
4.3
75
50
25
4.5
50
25
25
50
75
100
125
150
0.1
0.2
0.3
C037
0.4
VFB (V)
0.5
0.6
0.7
0.8
G013
VIN = 12V
VIN = 12 V
2.5
2.5
2
IVIN (A)
IVIN (A)
0
25
50
75
100
Tj Junction Temperature (C)
VIN = 12 V
1.5
1.5
0.5
0.5
0
50
25
25
50
75
100
125
150
10
20
30
40
C039
VIN = 12 V
50
60
C040
TJ = 25C
25
C036
TPS54340
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190
190
VIN Supply Current (A)
210
IVIN (A)
170
150
130
110
170
150
130
110
90
90
70
70
50
25
25
50
75
100
125
150
2.6
35
40
45
G018
4.5
BOOT-SW UVLO Falling
BOOT-SW UVLO Rising
4.4
2.4
4.3
Input Voltage (V)
15
20
25
30
VIN Input Voltage (V)
2.3
2.2
2.1
4.2
4.1
4
3.9
1.9
3.8
1.8
50
10
TJ = 25C
VIN = 12 V
2.5
C041
25
0
25
50
75
100
TJ Junction Temperature (C)
125
3.7
50
150
25
G018
0
25
50
75
100
Tj Junction Temperature (C)
125
150
G019
10
9
Soft-Start Time (ms)
8
7
6
5
4
3
2
1
0
2500
2300
VIN = 12 V
2100
1900
1700
1500
1300
1100
900
700
500
300
100
C045
TJ = 25C
TPS54340
SLVSBK0B OCTOBER 2012 REVISED MARCH 2014
www.ti.com
8 Detailed Description
8.1 Overview
The TPS54340 is a 42 V, 3.5 A, step-down (buck) regulator with an integrated high side n-channel MOSFET.
The device implements constant frequency, current mode control which reduces output capacitance and
simplifies external frequency compensation. The wide switching frequency range of 100 kHz to 2500 kHz allows
either efficiency or size optimization when selecting the output filter components. The switching frequency is
adjusted using a resistor to ground connected to the RT/CLK terminal. The device has an internal phase-locked
loop (PLL) connected to the RT/CLK terminal that will synchronize the power switch turn on to a falling edge of
an external clock signal.
The TPS54340 has a default input start-up voltage of approximately 4.3 V. The EN terminal can be used to
adjust the input voltage undervoltage lockout (UVLO) threshold with two external resistors. An internal pull up
current source enables operation when the EN terminal is floating. The operating current is 146 A under no load
condition (not switching). When the device is disabled, the supply current is 1 A.
The integrated 92m high side MOSFET supports high efficiency power supply designs capable of delivering 3.5
amperes of continuous current to a load. The gate drive bias voltage for the integrated high side MOSFET is
supplied by a bootstrap capacitor connected from the BOOT to SW terminals. The TPS54340 reduces the
external component count by integrating the bootstrap recharge diode. The BOOT terminal capacitor voltage is
monitored by a UVLO circuit which turns off the high side MOSFET when the BOOT to SW voltage falls below a
preset threshold. An automatic BOOT capacitor recharge circuit allows the TPS54340 to operate at high duty
cycles approaching 100%. Therefore, the maximum output voltage is near the minimum input supply voltage of
the application. The minimum output voltage is the internal 0.8 V feedback reference.
Output overvoltage transients are minimized by an Overvoltage Transient Protection (OVP) comparator. When
the OVP comparator is activated, the high side MOSFET is turned off and remains off until the output voltage is
less than 106% of the desired output voltage.
The TPS54340 includes an internal soft-start circuit that slows the output rise time during start-up to reduce inrush current and output voltage overshoot. Output overload conditions reset the soft-start timer. When the
overload condition is removed, the soft-start circuit controls the recovery from the fault output level to the nominal
regulation voltage. A frequency foldback circuit reduces the switching frequency during start-up and overcurrent
fault conditions to help maintain control of the inductor current.
10
TPS54340
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VIN
Thermal
Shutdown
UVLO
Enable
Comparator
OV
Shutdown
Shutdown
Logic
Enable
Threshold
Boot
Charge
Voltage
Reference
Boot
UVLO
Minimum
Clamp
Pulse
Skip
Error
Amplifier
Current
Sense
PWM
Comparator
FB
BOOT
Logic
Shutdown
Slope
Compensation
SW
COMP
Frequency
Foldback
Reference
DAC for
Soft- Start
Maximum
Clamp
Oscillator
with PLL
GND
POWERPAD
RT/ CLK
11
TPS54340
SLVSBK0B OCTOBER 2012 REVISED MARCH 2014
www.ti.com
12
TPS54340
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VI - Input Voltage - V
5.4
5.3
5.2
5.1
Dropout
Voltage
5
4.9
Dropout
Voltage
4.8
4.7
Start
4.6
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
Stop
0.4
0.45
0.5
Load Current - A
0.8 V
(1)
8.3.7 Enable and Adjusting Undervoltage Lockout
The TPS54340 is enabled when the VIN terminal voltage rises above 4.3 V and the EN terminal voltage exceeds
the enable threshold of 1.2 V. The TPS54340 is disabled when the VIN terminal voltage falls below 4 V or when
the EN terminal voltage is below 1.2 V. The EN terminal has an internal pull-up current source, I1, of 1.2 A that
enables operation of the TPS54340 when the EN terminal floats.
If an application requires a higher undervoltage lockout (UVLO) threshold, use the circuit shown in Figure 24 to
adjust the input voltage UVLO with two external resistors. When the EN terminal voltage exceeds 1.2 V, an
additional 3.4 A of hysteresis current, Ihys, is sourced out of the EN terminal. When the EN terminal is pulled
below 1.2 V, the 3.4 A Ihys current is removed. This addional current facilitates adjustable input voltage UVLO
hysteresis. Use Equation 2 to calculate RUVLO1 for the desired UVLO hysteresis voltage. Use Equation 3 to
calculate RUVLO2 for the desired VIN start voltage.
In applications designed to start at relatively low input voltages (e.g., 4.5 V) and withstand high input voltages
(e.g., 40 V), the EN terminal may experience a voltage greater than the absolute maximum voltage of 8.4 V
during the high input voltage condition. It is recommended to use a zener diode to clamp the terminal voltage
below the absolute maximum rating.
Submit Documentation Feedback
13
TPS54340
SLVSBK0B OCTOBER 2012 REVISED MARCH 2014
www.ti.com
TPS54340
i1
ihys
RUVLO1
EN
Optional
VEN
RUVLO2
- VSTOP
V
RUVLO1 = START
IHYS
RUVLO2 =
(2)
VENA
VSTART - VENA
+ I1
RUVLO1
(3)
14
101756
RT (kW)1.008
(6)
TPS54340
www.ti.com
CLPeak
tON
Figure 25. Current Limit Delay
To protect the converter in overload conditions at higher switching frequencies and input voltages, the TPS54340
implements a frequency foldback. The oscillator frequency is divided by 1, 2, 4, and 8 as the FB terminal voltage
falls from 0.8 V to 0 V. The TPS54340 uses a digital frequency foldback to enable synchronization to an external
clock during normal start-up and fault conditions. During short-circuit events, the inductor current can exceed the
peak current limit because of the high input voltage and the minimum controllable on time. When the output
voltage is forced low by the shorted load, the inductor current decreases slowly during the switch off time. The
frequency foldback effectively increases the off time by increasing the period of the switching cycle providing
more time for the inductor current to ramp down.
With a maximum frequency foldback ratio of 8, there is a maximum frequency at which the inductor current can
be controlled by frequency foldback protection. Equation 8 calculates the maximum switching frequency at which
the inductor current will remain under control when VOUT is forced to VOUT(SC). The selected operating frequency
should not exceed the calculated value.
Equation 7 calculates the maximum switching frequency limitation set by the minimum controllable on time and
the input to output step down ratio. Setting the switching frequency above this value will cause the regulator to
skip switching pulses to achieve the low duty cycle required at maximum input voltage.
fSW (max skip ) =
1
tON
I R + V
dc
OUT + Vd
O
VIN - IO RDS(on ) + Vd
(7)
15
TPS54340
SLVSBK0B OCTOBER 2012 REVISED MARCH 2014
www.ti.com
IO
Output current
ICL
Current limit
Rdc
inductor resistance
VIN
(8)
controllable on time
DIV
TPS54340
RT/CLK
RT/CLK
PLL
PLL
RT
Clock
Source
Hi-Z
Clock
Source
RT
16
TPS54340
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SW
SW
EXT
EXT
IL
IL
SW
EXT
IL
17
TPS54340
SLVSBK0B OCTOBER 2012 REVISED MARCH 2014
www.ti.com
VO
Power Stage
gmps 12 A/V
a
b
R1
RESR
RL
COMP
c
0.8 V
CO
R3
C2
RO
FB
COUT
gmea
350 mA/V
R2
C1
18
TPS54340
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Adc
VC
RESR
fp
RL
gmps
COUT
fz
Figure 31. Simple Small Signal Model and Frequency Response for Peak Current Mode Control
s
1 +
2p fZ
VOUT
= Adc
VC
s
1 +
2p fP
Adc = gmps RL
fP =
(9)
(10)
1
COUT RL 2p
(11)
1
fZ =
COUT RESR 2p
(12)
19
TPS54340
SLVSBK0B OCTOBER 2012 REVISED MARCH 2014
www.ti.com
R1
FB
gmea
Type 2A
COMP
Type 2B
Type 1
Vref
R2
RO
R3
CO
C2
C1
R3
C2
C1
Aol
A0
P1
Z1
P2
A1
BW
Figure 33. Frequency Response of the Type 2A and Type 2B Frequency Compensation
Aol(V/V)
gmea
gmea
=
2p BW (Hz)
Ro =
CO
(13)
(14)
s
1 +
2p fZ1
EA = A0
s
s
1 +
1 +
2p fP1
2p fP2
R2
R1 + R2
R2
Ro| | R3
R1 + R2
A0 = gmea Ro
A1 = gmea
P1 =
20
(15)
(16)
(17)
1
2p Ro C1
(18)
TPS54340
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P2 =
1
2p R3 C1
(19)
1
2p R3 | | RO (C2 + CO )
type 2a
(20)
1
P2 =
type 2b
2p R3 | | RO CO
P2 =
2p R O
(21)
1
type 1
(C2 + C O )
(22)
21
TPS54340
SLVSBK0B OCTOBER 2012 REVISED MARCH 2014
www.ti.com
VOPOS
+
VIN
Copos
+
Cin
VIN
Cboot
BOOT
GND
SW
Lo
Cd
R1
GND
Coneg
R2
TPS54340
VONEG
FB
EN
COMP
Rcomp
RT/CLK
RT
Czero
Cpole
22
TPS54340
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VIN
+
Cin
Cboot
Lo
Cd
VIN
BOOT
GND
SW
R1
+
GND
TPS54340
R2
FB
Co
VOUT
EN
COMP
Rcomp
RT/CLK
RT
Czero
Cpole
Figure 35. TPS54340 Inverting Power Supply from SLVA317 Application Note
23
TPS54340
SLVSBK0B OCTOBER 2012 REVISED MARCH 2014
www.ti.com
C4 0.1uF
U1
TPS54340DDA
VIN
6V to 42V
2
3
C1
C2
2.2uF
2.2uF
R1
365k
BOOT
SW
VIN
GND
EN
COMP
RT/CLK
PWRPD
GND
R2
86.6k
R3
162k
FB
C6
D1
8
100uF
B560C
R5
31.6k
7
6
5
GND
FB
R4
11.5k
C8
R6
10.2k
47pF
GND
FB
C5
5600pF
GND
GND
EXAMPLE VALUES
Output Voltage
3.3 V
VOUT = 4 %
3.5 A
Input Voltage
12 V nom. 6 V to 42 V
0.5% of VOUT
5.75 V
4.5 V
24
TPS54340
www.ti.com
Equation 7 and Equation 8 should be used to calculate the upper limit of the switching frequency for the
regulator. Choose the lower value result from the two equations. Switching frequencies higher than these values
results in pulse skipping or the lack of overcurrent protection during a short circuit.
The typical minimum on time, tonmin, is 135 ns for the TPS54340. For this example, the output voltage is 3.3 V
and the maximum input voltage is 42 V, which allows for a maximum switch frequency up to 712 kHz to avoid
pulse skipping from Equation 7. To ensure overcurrent runaway is not a concern during short circuits use
Equation 8 to determine the maximum switching frequency for frequency foldback protection. With a maximum
input voltage of 42 V, assuming a diode voltage of 0.7 V, inductor resistance of 21 m, switch resistance of 92
m, a current limit value of 4.7 A and short circuit output voltage of 0.1 V, the maximum switching frequency is
1260 kHz.
For this design, a lower switching frequency of 600 kHz is chosen to operate comfortably below the calculated
maximums. To determine the timing resistance for a given switching frequency, use Equation 5 or the curve in
Figure 7. The switching frequency is set by resistor R3 shown in Figure 36. For 600 kHz operation, the closest
standard value resistor is 162 k.
1
3.5 A x 21 mW + 3.3 V + 0.7 V
fSW(max skip) =
= 712 kHz
135ns
42 V - 3.5 A x 92 mW + 0.7 V
(23)
8
4.7 A x 21 mW + 0.1 V + 0.7 V
= 1260 kHz
135 ns
42 V - 4.7 A x 92 mW + 0.7 V
92417
RT (kW) =
= 163 kW
600 (kHz)0.991
fSW(shift) =
(24)
(25)
25
TPS54340
SLVSBK0B OCTOBER 2012 REVISED MARCH 2014
LO(min ) =
VIN(max ) - VOUT
IOUT KIND
www.ti.com
VOUT
42 V - 3.3 V
3.3 V
=
= 4.8 mH
VIN(max ) fSW
3.5 A x 0.3
42 V 600 kHz
(26)
spacer
IRIPPLE =
(27)
spacer
IL(rms ) =
(IOUT )
12
VIN(max ) LO fSW
(3.5 A )
(28)
spacer
IL(peak ) = IOUT +
IRIPPLE
0.905 A
= 3.5 A +
= 3.95 A
2
2
(29)
TPS54340
www.ti.com
Capacitance de-ratings for aging, temperature and dc bias increases this minimum value. For this example, 100
F ceramic capacitors with 5 m of ESR is used. The derated capacitance is 70 F, well above the minimum
required capacitance of 44.9 F.
Capacitors are generally rated for a maximum ripple current that can be filtered without degrading capacitor
reliability. Some capacitor data sheets specify the Root Mean Square (RMS) value of the maximum ripple
current. Equation 34 can be used to calculate the RMS ripple current that the output capacitor must support. For
this example, Equation 34 yields 261 mA.
2 DIOUT
2 1.75 A
=
= 44.9 mF
COUT >
fSW DVOUT 600 kHz x 0.13 V
(30)
OH
COUT > LO
OL
1
1
1
1
=
= 11.4 mF
COUT >
x
8 fSW VORIPPLE 8 x 600 kHz
16.5 mV
0.905 A
IRIPPLE
V
16.5 mV
= 18 mW
RESR < ORIPPLE =
IRIPPLE
0.905 A
ICOUT(rms) =
)=
12 VIN(max ) LO fSW
3.3 V
(42 V
(31)
(32)
(33)
- 3.3 V )
= 261 mA
(34)
(V
IN(max ) - VOUT
) I
OUT
VIN(max )
(42 V
Vf d
C j fSW (VIN + Vf d)
=
2
+
(35)
27
TPS54340
SLVSBK0B OCTOBER 2012 REVISED MARCH 2014
www.ti.com
VOUT
x
VIN(min )
(V
IN(min ) - VOUT
VIN(min )
) = 3.5 A
3.3 V
6V
(6 V
- 3.3 V )
6V
= 1.74 A
(36)
0.25
I
3.5 A 0.25
DVIN = OUT
=
= 331 mV
CIN fSW
4.4 mF 600 kHz
(37)
EIA Size
1210
1206
2220
2225
1812
1210
1210
1812
VOLTAGE
DIALECTRIC
100 V
COMMENTS
GRM32 series
50 V
100 V
GRM31 series
50 V
50 V
100 V
VJ X7R series
50 V
100 V
100 V
50 V
100 V
50 V
X7R
C series C4532
C series C3225
50 V
100 V
50 V
100 V
28
TPS54340
www.ti.com
VENA
1.2 V
=
= 87.8 kW
VSTART - VENA
5.75 V - 1.2 V
+ 1.2 mA
+ I1
365 kW
RUVLO1
(39)
(40)
9.2.2.9 Compensation
There are several methods to design compensation for DC-DC regulators. The method presented here is easy to
calculate and ignores the effects of the slope compensation that is internal to the device. Since the slope
compensation is ignored, the actual crossover frequency will be lower than the crossover frequency used in the
calculations. This method assumes the crossover frequency is between the modulator pole and the ESR zero
and the ESR zero is at least 10 times greater the modulator pole.
To get started, the modulator pole, p(mod), and the ESR zero, z1 must be calculated using Equation 41 and
Equation 42. For COUT, use a derated value of 70 F. Use equations Equation 43 and Equation 44 to estimate a
starting point for the crossover frequency, co. For the example design, p(mod) is 2411 Hz and z(mod) is 455 kHz.
Equation 42 is the geometric mean of the modulator pole and the ESR zero and Equation 44 is the mean of
modulator pole and the switching frequency. Equation 43 yields 33.1 kHz and Equation 44 gives 26.9 kHz. Use
the lower value of Equation 43 or Equation 44 for an initial crossover frequency. For this example, the target co
is 26.9 kHz.
Next, the compensation components are calculated. A resistor in series with a capacitor is used to create a
compensating zero. A capacitor in parallel to these two components forms the compensating pole.
IOUT(max )
3.5 A
fP(mod) =
=
= 2411 Hz
2 p VOUT COUT 2 p 3.3 V 70 mF
(41)
f Z(mod) =
1
2 p RESR COUT
fco =
fp(mod) x f z(mod) =
fco =
fp(mod) x
fSW
2
1
= 455 kHz
2 p 5 mW 70 mF
2411 Hz x
600 kHz
2
(42)
= 33.1 kHz
(43)
= 26.9 kHz
(44)
29
TPS54340
SLVSBK0B OCTOBER 2012 REVISED MARCH 2014
www.ti.com
To determine the compensation resistor, R4, use Equation 45. Assume the power stage transconductance,
gmps, is 12 A/V. The output voltage, VO, reference voltage, VREF, and amplifier transconductance, gmea, are 5
V, 0.8 V and 350 A/V, respectively. R4 is calculated to be 11.6 k and a standard value of 11.5 k is selected.
Use Equation 46 to set the compensation zero to the modulator pole frequency. Equation 46 yields 5740 pF for
compensating capacitor C5. 5600 pF is used for this design.
VOUT
2 p fco COUT
3.3 V
2 p 26.9 kHz 70 mF
R4 =
x
=
x
= 11.6 kW
gmps
12 A / V
0.8 V x 350 mA / V
VREF x gmea
(45)
C5 =
1
1
=
= 5740 pF
2 p R4 x fp(mod)
2 p 11.5 kW x 2411 Hz
(46)
A compensation pole can be implemented if desired by adding capacitor C8 in parallel with the series
combination of R4 and C5. Use the larger value calculated from Equation 47 and Equation 48 for C8 to set the
compensation pole. The selected value of C8 is 47 pF for this design example.
C
x RESR
70 mF x 5 mW
=
= 30.4 pF
C8 = OUT
R4
11.5 kW
(47)
1
1
=
= 46.1 pF
C8 =
R4 x f sw x p
11.5 kW x 600 kHz x p
(48)
9.2.2.10 Discontinuous Conduction Mode and Eco-mode Boundary
With an input voltage of 12 V, the power supply enters discontinuous conduction mode when the output current
is less than 342 mA. The power supply enters Eco-mode when the output current is lower than 31.4 mA. The
input current draw is 237 A with no load.
9.2.2.11 Power Dissipation
The following formulas show how to estimate the TPS54340 power dissipation under continuous conduction
mode (CCM) operation. These equations should not be used if the device is operating in discontinuous
conduction mode (DCM).
The power dissipation of the IC includes conduction loss (PCOND), switching loss (PSW), gate drive loss (PGD) and
supply current (PQ). Example calculations are shown with the 12 V typical input voltage of the design example.
V
3.3 V
2
PCOND = (IOUT ) RDS(on ) OUT = 3.5 A 2 92 mW
= 0.31 W
12 V
VIN
(49)
spacer
PSW = VIN fSW IOUT trise = 12 V 600 kHz 3.5 A 4.9 ns = 0.123 W
(50)
spacer
PGD = VIN QG fSW = 12 V 3nC 600 kHz = 0.022 W
(51)
spacer
PQ = VIN IQ = 12 V 146 mA = 0.0018 W
(52)
Where:
IOUT
sw
trise is the SW terminal voltage rise time and can be estimated by trise = VIN x 0.16ns/V + 3.0ns.
QG
30
TPS54340
www.ti.com
IQ
Therefore,
PTOT = PCOND + PSW + PGD + PQ = 0.31 W + 0.123 W + 0.022 W + 0.0018 W = 0.457 W
(53)
(54)
(55)
Where:
Ptot
TA
TJ
RTH
10 V/div
1 A/div
C4: IOUT
VIN
C3
20 mV/div
100 mV/div
C4
VOUT
Time = 4 ms/div
Figure 38. Line Transient (8 V to 40 V)
5 V/div
5 V/div
C1: VIN
-3.3 V offset
C1: VIN
C3: EN
C3
C2: VOUT
2 V/div
C1
2 V/div
2 V/div
2 V/div
C1
C2
C3: EN
C3
C2: VOUT
C2
Time = 2 ms/div
Figure 39. Start-up With VIN
Time = 2 ms/div
Figure 40. Start-up With EN
31
TPS54340
SLVSBK0B OCTOBER 2012 REVISED MARCH 2014
500 mA/div
C4: IL
10 mV/div
20 mV/div
10 V/div
C1
1 A/div
10 V/div
C1: SW
www.ti.com
C2
C4
C1: SW
C1
C4: IL
C4
C2
Time = 2 ms/div
Time = 2 ms/div
IOUT = 3.5 A
IOUT = 100 mA
10 V/div
C1: SW
C1
C1: SW
C1
1 A/div
C4: IL
C4: IL
C4
C2
200 mV/div
20 mV/div
200 mA/div
10 V/div
C2
C4
Time = 2 ms/div
Time = 2 ms/div
No Load
IOUT = 3.5 A
Figure 44. Input Ripple CCM
C1: SW
2 V/div
C1: SW
C1
200 mA/div
C4: IL
C4
20 mV/div
50 mV/div
500 mA/div
10 V/div
C3
C4
C4: IL
C3
Time = 2 ms/div
IOUT = 100 mA
VIN = 12V
VIN = 5.5 V
VOUT = 5 V
Figure 45. Input Ripple DCM
32
Time = 20 ms/div
No Load
EN Floating
TPS54340
SLVSBK0B OCTOBER 2012 REVISED MARCH 2014
2 V/div
2 V/div
www.ti.com
VIN
VIN
VOUT
VOUT
Time = 40 ms/div
EN Floating
IOUT = 100 mA
IOUT = 1 A
100
100
90
90
80
80
70
70
Efficiency - %
Efficiency - %
60
50
40
30
20
60
50
40
30
20
6Vin
12Vin
24Vin
10
36Vin
42Vin
0.5
1.0
1.5
2.5
2.0
3.0
6Vin
12Vin
24Vin
10
0
0.001
3.5
VOUT = 3.3 V
36Vin
42Vin
0.1
0.01
IO - Output Current - A
IO - Output Current - A
sw = 600 kHz
VOUT = 3.3 V
sw = 600 kHz
100
100
90
90
80
80
70
70
Efficiency - %
Efficiency - %
Time = 40 ms/div
EN Floating
60
50
40
30
20
60
50
40
30
20
6Vin
12Vin
24Vin
10
36Vin
42Vin
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
6Vin
12Vin
24Vin
10
4.0
0
0.001
0.01
IO - Output Current - A
VOUT = 5 V
36Vin
42Vin
0.1
IO - Output Current - A
sw = 600 kHz
VOUT = 5 V
sw = 600 kHz
33
TPS54340
SLVSBK0B OCTOBER 2012 REVISED MARCH 2014
www.ti.com
180
60
1
0.8
20
60
Gain
0
-60
-20
-40
-120
-60
-180
10
100
VIN = 12 V
1000
10000
100000
120
Phase - degree
Gain - dB
Phase
40
0.6
0.4
0.2
0
-0.2
0.4
-0.6
-0.8
-1
0
1000000
0.5
1.0
1.5
2.0
2.5
3.0
3.5
IO - Output Current - A
Frequency - Hz
VOUT = 3.3 V
IOUT = 3.5 A
VIN = 12 V
VOUT = 3.3 V
sw = 600 kHz
0.3
0.2
0.1
-0.1
0.2
-0.3
5
10
15
20
25
30
35
40
45
VOUT = 3.3 V
IOUT = 3.5 A
sw = 600 kHz
34
TPS54340
www.ti.com
11 Layout
11.1 Layout Guidelines
Layout is a critical portion of good power supply design. There are several signal paths that conduct fast
changing currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise
or degrade performance
To reduce parasitic effects, the VIN terminal should be bypassed to ground with a low ESR ceramic bypass
capacitor with X5R or X7R dielectric.
Care should be taken to minimize the loop area formed by the bypass capacitor connections, the VIN
terminal, and the anode of the catch diode.
The GND terminal should be tied directly to the power pad under the IC and the PowerPAD.
The PowerPAD should be connected to internal PCB ground planes using multiple vias directly under the
IC.
The SW terminal should be routed to the cathode of the catch diode and to the output inductor.
Since the SW connection is the switching node, the catch diode and output inductor should be located close
to the SW terminals, and the area of the PCB conductor minimized to prevent excessive capacitive coupling.
For operation at full rated load, the top side ground area must provide adequate heat dissipating area.
The RT/CLK terminal is sensitive to noise so the RT resistor should be located as close as possible to the IC
and routed with minimal lengths of trace.
The additional external components can be placed approximately as shown.
It may be possible to obtain acceptable performance with alternate PCB layouts, however this layout has
been shown to produce good results and is meant as a guideline.
Output
Capacitor
Topside
Ground
Area
Output
Inductor
Input
Bypass
Capacitor
BOOT
Vin
UVLO
Adjust
Resistors
Catch
Diode
SW
VIN
GND
EN
COMP
RT/CLK
FB
Frequency
Set Resistor
Compensation
Network
Resistor
Divider
Thermal VIA
Signal VIA
35
TPS54340
SLVSBK0B OCTOBER 2012 REVISED MARCH 2014
www.ti.com
12.3 Glossary
SLYZ022 TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
36
www.ti.com
31-Oct-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Eco Plan
Lead/Ball Finish
(2)
(6)
(3)
Op Temp (C)
Device Marking
(4/5)
TPS54340DDA
ACTIVE SO PowerPAD
DDA
75
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
54340
TPS54340DDAR
ACTIVE SO PowerPAD
DDA
2500
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
54340
(1)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
www.ti.com
31-Oct-2013
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TPS54340 :
Automotive: TPS54340-Q1
NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 2
13-May-2013
Device
TPS54340DDAR
DDA
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2500
330.0
12.8
Pack Materials-Page 1
6.4
B0
(mm)
K0
(mm)
P1
(mm)
5.2
2.1
8.0
W
Pin1
(mm) Quadrant
12.0
Q1
13-May-2013
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS54340DDAR
SO PowerPAD
DDA
2500
366.0
364.0
50.0
Pack Materials-Page 2
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