Avr Alp

Embedded Systems and Software
Lecture 5-7: AVR Assembly Language

Programming
Inside an ASDL Modem/Router
Embedded Systems and Software, 55:036. The University of Iowa, 2012
Lecture 5-7, Slide 1
AVR, ATmega88PA, ATtiny45, etc.

We will not cover all of the AVR instructions
Will not cover all of the AVR assembler directives and
features
Relevant Atmel documentation are under Resources on
class website
A quick review of the AVR memory map is useful, since
some instructions are specific to certain memory
Review Number Notation
The AVR documentation and assembler use several notations for numbers, and we will
follow these in the lecture notes.
By default, numbers are decimal. Thus 10 means ten, decimal.

Hexadecimal numbers are written as 0xAB, or 0xaB, or 0xAb. The leading character is
a zero. Sometimes hexadecimal number are written as $AB.
Binary numbers are written as 0b10101011. The leading character is a zero.
Octal numbers begin with 0 (zero)l. For example: 0253
Upper nibble
Lower nibble
ATmega88 Memory Map
This is where the

program is placed.
Program variables
Here one can place bootloader code,

which is a small program that can have
the controller reprogram itself. For
example, to download new firmware.
ATmega88 Memory Map

Some instructions are specific to certain memory areas
Use SBR and CBR to set and clear bits in
general purpose registers
Use SBI and CBI to set and clear bits in I/O registers
(PORTS, timers, etc.)
In some cases I/O register lie outside of 063 I/O space,
and one has to use LDS and STS instructions, e.g., TMSK0
on the ATmega88
ATmega88 Memory Map

Some instructions are specific to certain memory areas
Use LDI, MOV, instruction for general
purpose registers
Use IN, OUT, instructions for in I/O registers

(PORTS, timers, etc.)
In some cases I/O register lie outside of the 063 I/O
space, and one has to use LDS and STS instructions,
e.g. TMSK0 on ATmega88
LDI Load Immediate

Loads an 8-bit constant directly to register 16 to 31.
DEC Decrement
Subtracts one -1- from the contents of register Rd and places the result in the destination
register Rd.
The C Flag in SREG is not affected by the operation, thus allowing the DEC instruction to be
used on a loop counter in multiple- precision computations.
When operating on unsigned values, only BREQ and BRNE branches can be expected to
perform consistently. When operating on twos complement values, all signed branches are
available.
INC Increment
Adds one -1- to the contents of register Rd and places the result in the destination register
Rd.
The C Flag in SREG is not affected by the operation, thus allowing the INC instruction to be
used on a loop counter in multiple- precision computations.
When operating on unsigned numbers, only BREQ and BRNE branches can be expected to
perform consistently. When operating on twos complement values, all signed branches are
available.
CLR Clear Register

Clears a register. This instruction performs an Exclusive OR between a register and itself.
This will clear all bits in the register.
CPSE Compare Skip if Equal

This instruction performs a compare between two registers Rd and Rr, and skips the next
instruction if Rd = Rr.
CPI Compare with Immediate

This instruction performs a compare between register Rd and a constant. The register is not
changed. All conditional branches can be used after this instruction.
CP Compare
This instruction performs a compare between two registers Rd and Rr. None of the registers
are changed. All conditional branches can be used after this instruction.
TST Test for Zero or Minus

Tests if a register is zero or negative. Performs a logical AND between a register and itself.
The register will remain unchanged.
BRNE Branch if Not Equal

Conditional relative branch. Tests the Zero Flag (Z) and branches relatively to PC if Z is
cleared. If the instruction is executed immediately after any of the instructions CP, CPI, SUB
or SUBI, the branch will occur if and only if the unsigned or signed binary number
represented in Rd was not equal to the unsigned or signed binary number represented in Rr.
This instruction branches relatively to PC in either direction (PC - 63 destination PC +
64). The parameter k is the offset from PC and is represented in twos complement form.
(Equivalent to instruction BRBC 1,k)
IN - Load an I/O Location to Register

Loads data from the I/O Space (Ports, Timers, Configuration Registers etc.) into register Rd
in the Register File.
OUT Store Register to I/O Location

Stores data from register Rr in the Register File to I/O Space (Ports, Timers, Configuration
Registers etc.).
CBI Clear Bit in I/O Register
Not the same as clearing bits in registers (CBR)
Clears a specified bit in an I/O Register. This instruction operates on the lower 32 I/O
Registers addresses 0-31.
SBI Set Bit in I/O Register
Not the same as setting bits in registers (CBR)
Sets a specified bit in an I/O Register. This instruction operates on the lower 32 I/O Registers
addresses 0-31.
SBIC Skip if Bit in I/O Register is Cleared

This instruction tests a single bit in an I/O Register and skips the next instruction if the bit is
cleared. This instruction operates on the lower 32 I/O Registers addresses 0-31.
SBIS Skip if Bit in I/O Register is Set

This instruction tests a single bit in an I/O Register and skips the next instruction if the bit is
set. This instruction operates on the lower 32 I/O Registers addresses 0-31.
MOV Copy Register

This instruction makes a copy of one register into another. The source register Rr is left
unchanged, while the destination register Rd is loaded with a copy of Rr.
SBR Set Bits in Register
Not the same as setting bits in I/O (SBI)
Sets specified bits in register Rd. Performs the logical ORI between the contents of register
Rd and a constant mask K and places the result in the destination register Rd.
CBR Clear Bits in Register
Not the same as clearing bits in I/O (CBI)
Clears the specified bits in register Rd. Performs the logical AND between the contents of
register Rd and the complement of the constant mask K. The result will be placed in register
Rd.
PUSH and POP Save and Restore on Stack

The PUSH instruction stores the contents of register Rr on the STACK. The Stack Pointer is
post-decremented by 1 after the PUSH.
The POP instruction loads register Rd with a byte from the STACK. The Stack Pointer is preincremented by 1 before the POP. This instruction is not available in all devices. Refer to the
device specific instruction set summary.
A PUSH should have a matching POP or the
stack will be corrupted
Stack Pointer or SP
SP on ATtiny45
The stack is implemented in SRAM, and SP always points to the top of the stack and decrements with a
push instruction.
Thus, to utilize the stack using the push and pop instructions, one must initialize SP properly.
On AVRs, SP is initialized to the end of SRAM (see diagram above)
Other AVR documentation suggest that at reset, SP is initialized to 0x00, which is where the 32 general
purpose registers startsee the AVR memory map, so programmer has to initialize SP.
; Point the stack to end of SRAM.
ldi
r23,LOW(RAMEND)
; Load LSB of last SRAM address in r23
out
spl,r23
ldi
r23,HIGH(RAMEND) ; Load MSB of last SRAM address in r23
out
sph,r23
Initializing Stack Pointer or SP
RAMEND is defined in m88padef.inc
.include "m88padef.inc"
SP is located
in I/O space so
we use in and
out instructions
; Point the stack to end of SRAM.

ldi
r23,LOW(RAMEND)
; Load LSB of last SRAM address in r23
out
spl,r23
ldi
r23,HIGH(RAMEND) ; Load MSB of last SRAM address in r23
out
sph,r23
LOW and HIGH are Assembler

operators that extract LSB and
MSB from RAMEND.
RJMP Relative Jump

Relative jump to an address within PC - 2K +1 and PC + 2K (words). For AVR
microcontrollers with Program memory not exceeding 4K words (8K bytes) this instruction
can address the entire memory from every address location. See also JMP.
RCALL Relative Call to Subroutine

Relative call to an address within PC - 2K + 1 and PC + 2K (words). The return address (the
instruction after the RCALL) is stored onto the Stack. See also CALL. For AVR
microcontrollers with Program memory not exceeding 4K words (8K bytes) this instruction
can address the entire memory from every address location. The Stack Pointer uses a postdecrement scheme during RCALL.
RET Return from Subroutine

Returns from subroutine. The return address is loaded from the STACK. The Stack Pointer
uses a pre-increment scheme during RET.
EOR Exclusive OR
Performs the bitwise logical EOR between the contents of register Rd and register Rr and
places the result in the destination register Rd.
Example: Assume R18 holds 0xB8 and R19 holds 0x58. Then, after the instruction
EOR R18, R19, register R19 will hold the value 0xE0:
0xB8
0b1011 1000
0x58
0b0101 1000
Bitwise Exclusive OR
0b1110 0000
= 0xE0
OR Logical OR
Performs the logical OR between the contents of register Rd and register Rr and places the
result in the destination register Rd. of register Rd and register Rr and places the result in
the destination register Rd.
OR R18, R19, register R19 will hold the value 0xF8:
0xB8
0b1011 1000
0x58
0b0101 1000
Bitwise Exclusive OR
0b1111 1000
= 0xF8
AND Logical AND

Performs the bitwise logical AND between the contents of register Rd and register Rr and
places the result in the destination register Rd.
AND R18, R19, register R19 will hold the value 0x18:
0xB8
0b1011 1000
0x58
0b0101 1000
Bitwise AND
0b0001 1000
= 0x18
ADD Add without Carry

Adds two registers without the C Flag and places the result in the destination register Rd.
ADIW Add Immediate to Word
Not available on all AVRs, but is on ATmega88PA
Adds an immediate value (0 - 63) to a register pair and places the result in the register pair.
This instruction operates on the upper four register pairs, and is well suited for operations on
the pointer registers. This instruction is not available in all devices. Refer to the device
specific instruction set summary
Example
msg: .DB "Hello "
ldi
ldi
lpm
r30,LOW(2*msg)
r31,2*HIGH(msg)
; Load Z register low

; Load Z register high
; r0 <-- load byte
zl,1
; Increment Z pointer
adiw
SUB Subtract without Carry

Subtracts two registers and places the result in the destination register Rd.
SUB R18, R19, register R19 will hold the value 0x60:
0xB8
0b1011 1000
0x58
0b0101 1000
0xB8-0x58
0b0110 0000
= 0x60
SUB Subtract without Carry
SUB R18, R19, register R19 will hold the value 0xA0:
0x58
0b0101 1000
0xB8
0b1011 1000
2s complement of 0xB8
Add 2s complement of 0xB8 to 0x58
0b0100 1000
0b1010 0000
= 0xA0
ADC Add with Carry

Adds two registers and the contents of the C Flag and places the result in the destination
register Rd.
Example: add two 16-bit numbers
May set C flag in SREG
SBC Subtract with Carry

Subtracts two registers and subtracts with the C Flag and places the result in the destination
register Rd.
Instruction enables multi-byte arithmetic on AVR 8-bit architecture
RETI Return from Interrupt

Returns from interrupt. The return address is loaded from the STACK and the Global
Interrupt Flag is set.
Note that the Status Register is not automatically stored when entering an interrupt routine,
and it is not restored when returning from an interrupt routine. This must be handled by the
application program. The Stack Pointer uses a pre-increment scheme during RETI.
LSL Logical Shift Left

Shifts all bits in Rd one place to the left. Bit 0 is cleared. Bit 7 is loaded into the C Flag of the
SREG. This operation effectively multiplies signed and unsigned values by two.
The carry (c) bit is located in SREG
LSR Logical Shift Right

Shifts all bits in Rd one place to the right. Bit 7 is cleared. Bit 0 is loaded into the C Flag of
the SREG. This operation effectively divides an unsigned value by two. The C Flag can be
used to round the result.
ASR Arithmetic Shift Right

Shifts all bits in Rd one place to the right. Bit 7 is held constant. Bit 0 is loaded into the C
Flag of the SREG. This operation effectively divides a signed value by two without changing
its sign. The Carry Flag can be used to round the result.
ROL Rotate Left trough Carry

Shifts all bits in Rd one place to the left. The C Flag is shifted into bit 0 of Rd. Bit 7 is shifted
into the C Flag.
This operation, combined with LSL, effectively multiplies multi-byte signed and unsigned
values by two.
The carry (c) bit is

located in SREG
Before ROL: 0xB8
After ROL:0x71
ROR Rotate Right through Carry

Shifts all bits in Rd one place to the right. The C Flag is shifted into bit 7 of Rd. Bit 0 is shifted
into the C Flag.
This operation, combined with ASR, effectively divides multi-byte signed values by two.
Combined with LSR it effectively divides multibyte unsigned values by two. The Carry Flag
can be used to round the result.
The carry (c) bit is

located in SREG
Before ROR: 0xB8
After ROR:0xDC
I/O address
Sign Bit
Bit Copy Storage
SRAM Address
Half Carry Flag
Negative Flag
2s Complement
Overflow Flag
Carry Flag
Zero Flag
SEC Set Carry Flag in SREG
CLC Clear Carry Flag in SREG
SEH Set Half Carry Flag
CLH Clear Half Carry Flag
SEI Set Global Interrupt Flag
CLI Clear Global Interrupt Flag
SEN Set Negative Flag in SREG
CLN Clear Negative Flag
SES Set Signed Flag
CLS Clear Signed Flag
SET Set T Flag
CLT Clear T Flag
SEV Set Overflow Flag
CLV Clear Overflow Flag
SEZ Set Zero Flag
CLZ Clear Zero Flag
NEG Twos Complement

Replaces the contents of register Rd with its twos complement; the value $80 is left
unchanged.
Example: Assume R18 holds the value 0x71. Then, after the instruction
neg r18
R18 will hold 0x8F. How? Recall to get 2s complement, invert bits and add 1
0x71
0b0111 0001
Bits inverted
0b1000 1110
Add 1
+0b0000 0001
2s Complement
0b1000 0001
=0x8F
SWAP Swap Nibbles

Swaps high and low nibbles in a register.
Before swap r1
After swap r1
We will use swap instruction when working with LCDs later in this class.
SLEEP
This instruction sets the circuit in sleep mode defined by the MCU Control Register.
Question: Why sleep?

Answer: In sleep modes, the clocks (are) running slower/stopped, other peripherals may be
powered down save power
Question: How will MCU wake up?
Answer: One can configure the controller so that Timers, WDT, and external interrupts and
pin changes wake it up from a sleep.
Waking up from Sleep
One can configure the microcontroller so that it wakes up when there is a high-low or lowhigh (i.e., pin change) on some of the pins.
One can configure the microcontroller so that it wakes up when WDT times out
LPM Load Program Memory

Loads one byte pointed to by the Z-register into the destination register Rd. If Rd is not
specified, the it is implied to be R0.
These constant are located in Program (Flash)

memory and not SRAM
Example: In the snippet below, for LPM a destination register is not supplied, so R0 is
implied
msg: .DB "Hello "
ldi
ldi
lpm
r30,LOW(2*msg)
r31,2*HIGH(msg)

; r0 <-- load byte
zl,1
; Increment Z pointer
adiw
Example: In the snippet below, the LPM Rd,Z+ variant is used
displayC:
ldi
r30,LOW(2*msg)
ldi
r31,2*HIGH(msg)
L20:
lpm
r2,Z+
tst
r2
breq done
rjmp L20
done:
ret

; r2 <-- first byte
; Reached end of message ?
; Yes => quit
For Further information on the LPM instruction, please see the Atmel
Application Note AVR108: Setup and Use of the LPM Instruction on the
companys website.
The AVR Assembler

We will be using AVRASM2 assembler that comes with
AVR studio
The Assembler performs the conversion from English
mnemonics to opcodes that are programmed into the
microcontroller
C compilers generate assembly language mnemonics
that are then assembled by an assembler
Much confusion arises when one does not have a
conceptual understanding of the different assembly
phases
The assemblers text substitution allows one to use symbols rather than numbers
.equ
.equ
PORTB
DDRB
= 0x18
= 0x17
.include "tn45def.inc"
.cseg
sbi
DDRB,1
loop:
sbi
cbi
rjmp
PORTB,1
PORTB,1
loop
Phase 1: text substitution

000000
sbi
0x17,1
loop:
These are program addresses
000001
000002
000003
000004
sbi
cbi
cbi
rjmp
0x17,1
0x18,2
0x18,1
0x01
Phase 2: machine instructions,
The assemblers text substitution allows one to use symbols rather than numbers
.cseg
sbi
sbi
sbi
DDRB,1
loop:
sbi
cbi
rjmp
sbi
000000
000001
sbi
cbi
cbi
rjmp
PORTB,1
PORTB,1
loop
0x17,1
loop:
000001
000002
000003
000004
DDRB,1
DDRB,2
loop:
sbi
cbi
rjmp
PORTB,1
PORTB,1
loop
000000
.cseg
0x17,1
0x18,2
0x18,1
0x01
sbi 0x17,1
sbi 0x17,2
loop:
000002
000003
000004
000005
sbi
cbi
cbi
rjmp
0x17,1
0x18,2
0x18,1
0x02
Assembler Directives
Assembler directives instruct the assembler what to do
The directives are not translated directly into opcodes.
Instead, they are used to adjust the location of the program in memory, define
macros, initialize memory and so on.
.cseg
sbi
DDRB,1
loop:
sbi
cbi
rjmp
This does not generate opcodes.

Rather it direct the assembler to
include replace this line with the
contents of tn45def.inc
PORTB,1
PORTB,1
loop
We have seen this directive

several times thus far
.BYTE Reserve bytes to a variable
ASM Directive
The BYTE directive reserves memory resources in the SRAM. In order to be able to refer to
the reserved location, the BYTE directive should be preceded by a label. The directive takes
one parameter, which is the number of bytes to reserve.
The directive can only be used within a Data Segment. Note that a parameter must be given.
The allocated bytes are not initialized.
.CSEG Code Segment
ASM Directive
The CSEG directive defines the start of a Code Segment. An Assembler file can consist
of several Code Segments, which are concatenated into one Code Segment when
assembled. The BYTE directive can not be used within a Code Segment.
The default segment type is Code. The Code Segments have their own location counter
which is a word counter.
.DSEG Data Segment
ASM Directive
The DSEG directive defines the start of a Data Segment. An Assembler file can consist of
several Data Segments, which are concatenated into one Data Segment when assembled. A
Data Segment will normally only consist of BYTE directives (and labels).
The ORG directive (later) can be used to place the variables at specific locations in the
SRAM. The directive does not take any parameters.
.ESEG EEPROM Segment
ASM Directive
The ESEG directive defines the start of an EEPROM Segment. An Assembler file can consist
of several EEPROM Segments, which are concatenated into one EEPROM Segment when
assembled. The BYTE directive can not be used within an EEPROM Segment.
The EEPROM Segments have their own location counter which is a byte counter. The ORG
directive (later) can be used to place constants at specific locations in the EEPROM memory.
.DB - Define constant byte(s) in program memory or EEPROM
ASM Directive
The DB directive reserves memory resources in the program memory or the EEPROM
memory. In order to be able to refer to the reserved locations, the DB directive should be
preceded by a label.
The expression list is a sequence of expressions, delimited by commas. Each expression
must evaluate to a number between -128 and 255. If the expression evaluates to a negative
number, the 8 bits two's complement of the number will be placed in the program memory or
EEPROM memory location.
.DW - Define constant word(s) in program memory or EEPROM
ASM Directive
The DW directive reserves memory resources in the program memory or EEPROM memory.
In order to be able to refer to the reserved locations, the DW directive should be preceded by
a label.
The expression list is a sequence of expressions, delimited by commas. Each expression
must evaluate to a number between -32768 and 65535. If the expression evaluates to a
negative number, the 16 bits two's complement of the number will be placed in the program
memory location.
.DEF - Set a symbolic name on a register
ASM Directive
The DEF directive allows the registers to be referred to through symbols. A defined symbol
can be used in the rest of the program to refer to the register it is assigned to. A register can
have several symbolic names attached to it. A symbol can be redefined later in the program.
A symbol can be redefined later in the program.
.EQU - Set a symbol equal to an expression
ASM Directive
The EQU directive assigns a value to a label. This label can then be used in later
expressions.
A label assigned to a value by the EQU directive is a constant and can not be changed or
redefined.
.SET - Set a symbol equal to an expression
ASM Directive
The SET directive assigns a value to a label. This label can then be used in later
expressions.
A label assigned to a value by the SET directive can be changed later in the program.
.DEVICE Define which device to assemble for
ASM Directive
The DEVICE directive allows the user to tell the Assembler which device the code is to be
executed on. If this directive is used, a warning is issued if an instruction not supported by
the specified device occurs in the code. If the size of the Code Segment or EEPROM
Segment is larger than supported by the specified device, a warning is issued.
.INCLUDE Include another file
ASM Directive
The INCLUDE directive tells the Assembler to start reading from a specified file. The
Assembler then assembles the specified file until end of file (EOF) or an EXIT directive is
encountered. An included file may itself contain INCLUDE directives.
Contents of iodefs.asm
Include this in another AM program, and one can use symbols such as sreg
rather than 0x3f:
.EXIT - Exit this file
ASM Directive
The EXIT directive tells the Assembler to stop assembling the file. Normally, the Assembler
runs until end of file (EOF). If an EXIT directive appears in an included file, the Assembler
continues from the line following the INCLUDE directive in the file containing the INCLUDE
directive.
.ORG - Set program origin
ASM Directive
The ORG directive sets the location counter to an absolute value. The value to set is
given as a parameter.
If an ORG directive is given within a Data Segment, then it is the SRAM location counter
which is set, if the directive is given within a Code Segment, then it is the Program memory
counter which is set and if the directive is given within an EEPROM Segment, then it is the
EEPROM location counter which is set.
.ORG - Set program origin
ASM Directive
.MACRO Begin macro
ASM Directive
.ENDMACRO Ends macro

.LISTMAC Show how macros is expanded
.LISTMAC
.MACRO SUBI16
subi @1,low(@0)
sbci @2,high(@0)
.ENDMACRO
;
;
;
;
Start macro definition

Subtract low byte
Subtract high byte
End macro definition
.CSEG
SUBI16 0x1234,r16,r17
; Sub.0x1234 from r17:r16

Text substitution/macro expansion
subi r16 , low ( 0x1234 )

sbci r17 , high ( 0x1234 )
Generate opcodes
Assembler Functions
This returns the low byte
ldi r19,low(0x07F3)
ldi r20,high(0x07F3)
This returns the high byte
Text substitution & apply functions
ldi r19,0xF3
ldi r20,0x07
Generate opcodes
Assembler Functions
LOW and HIGH are often used, others less frequently, and we will not cover these
in this course
Assembler Operators
Assembler function and operators are related to assembler directives
The functions and operators are not translated directly into opcodes.
Instead, they are used to do calculations on the assembly language source file
.EQU c1 = 0b11011010
.equ c2 = 0b10101010
This is the Assembler

bit-wise exclusive or
(XOR) operator.
ldi r18,c1^c2
Text substitution & apply functions
ldi r18,0x70
Generate opcodes
Some Assembler Operators

Multiplication
Division

Addition
Subtraction

Shift left
Shift right

Bitwise AND
Bitwise OR

Logical AND
Logical OR

Logical NOT
Bitwise NOT

Not Equal
Equal

Less Than
Greater Than
Assembler Preprocessor
The AVRASM2 preprocessor is modeled after the C preprocessor, with some exceptions
(see AVRASM2 documentation).
#define
#if
#pragma
Operators:
#elif
#ifdef
#undef
# (stringification
#else
#ifndef
#warning
## (concatenation)
#endif
#include
# (empty directive)
#error
#message
.EQU c1 = 0b11011010
.equ c2 = 0b10101010
#define DEBUG
#ifdef DEBUG
ldi r18,low(c1|c2)
rcall delay
#else
ldi r18,low(c1^c2)
#endif
As with the C preprocessor, the AVRASM2

preprocessor allows conditional processing.
For example, one can build a special debug version as
shown in the snippet.
Assembler Preprocessor
The AVRASM2 preprocessor is modeled after the C preprocessor, with some exceptions
(see AVRASM2 documentation).
#define
#if
#pragma
Operators:
#elif
#ifdef
#undef
# (stringification
#else
#ifndef
#warning
## (concatenation)
#endif
#include
# (empty directive)
#error
#message
.EQU c1 = 0b11011010
.equ c2 = 0b10101010
#define DEBUG
#ifdef DEBUG
ldi r18,low(c1|c2)
rcall delay
#else
ldi r18,low(c1^c2)
#endif
As with the C preprocessor, the AVRASM2

preprocessor allows conditional processing.
For example, one can build a special debug version as
shown in the snippet.
Microcontroller Configuration/Fuses
AVR ATtiny45 8-Pin Microcontroller
Except for GND and VCC all other pins can perform at least 4 functions
PB5 can be hardware RESET or an ADC input
PB3 & PB4 can be ADC inputs or where crystal for external oscillator
goes
How does one configure controller for the external environment?
Microcontroller Configuration/Fuses
The Configuration Fuses (Configuration Bits) are the settings
that configure a microcontroller for the external environment
it is expecting to find
Typical settings include
Oscillator Type, REST pin usage

Code Protection
Brown-Out and Watchdog Timer usage
Low Voltage Programming
Different microcontrollers, and members within a device

family has its own fuses
Programming fuses in Studio 5.0 and AVRISP mkII
Enables use of WDT
This chooses if the clock is divided

by 8 or not, start-up time,

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Embedded Systems and Software

Lecture 5-7: AVR Assembly Language

Inside an ASDL Modem/Router

Embedded Systems and Software, 55:036. The University of Iowa, 2012

Lecture 5-7, Slide 1

AVR, ATmega88PA, ATtiny45, etc.

Embedded Systems and Software, 55:036. The University of Iowa, 2012

Lecture 5-7, Slide 2

Review Number Notation

By default, numbers are decimal. Thus 10 means ten, decimal.

Embedded Systems and Software, 55:036. The University of Iowa, 2012

Lecture 5-7, Slide 3

ATmega88 Memory Map

This is where the

Here one can place bootloader code,

Lecture 5-7, Slide 4

ATmega88 Memory Map

Embedded Systems and Software, 55:036. The University of Iowa, 2012

Lecture 5-7, Slide 5

ATmega88 Memory Map

Use IN, OUT, instructions for in I/O registers

Lecture 5-7, Slide 6

LDI Load Immediate

Embedded Systems and Software, 55:036. The University of Iowa, 2012

Lecture 5-7, Slide 7

Embedded Systems and Software, 55:036. The University of Iowa, 2012

Lecture 5-7, Slide 8

Embedded Systems and Software, 55:036. The University of Iowa, 2012

Lecture 5-7, Slide 9

CLR Clear Register

Embedded Systems and Software, 55:036. The University of Iowa, 2012

Lecture 5-7, Slide 10

CPSE Compare Skip if Equal

Embedded Systems and Software, 55:036. The University of Iowa, 2012

Lecture 5-7, Slide 11

CPI Compare with Immediate

Embedded Systems and Software, 55:036. The University of Iowa, 2012

Lecture 5-7, Slide 12

Embedded Systems and Software, 55:036. The University of Iowa, 2012

Lecture 5-7, Slide 13

TST Test for Zero or Minus

Embedded Systems and Software, 55:036. The University of Iowa, 2012

Lecture 5-7, Slide 14

BRNE Branch if Not Equal

Embedded Systems and Software, 55:036. The University of Iowa, 2012

Lecture 5-7, Slide 15

IN - Load an I/O Location to Register

Embedded Systems and Software, 55:036. The University of Iowa, 2012

Lecture 5-7, Slide 16

OUT Store Register to I/O Location

Embedded Systems and Software, 55:036. The University of Iowa, 2012

Lecture 5-7, Slide 17

CBI Clear Bit in I/O Register

Not the same as clearing bits in registers (CBR)

SBI Set Bit in I/O Register

Not the same as setting bits in registers (CBR)

Embedded Systems and Software, 55:036. The University of Iowa, 2012

Lecture 5-7, Slide 18

SBIC Skip if Bit in I/O Register is Cleared

SBIS Skip if Bit in I/O Register is Set

Embedded Systems and Software, 55:036. The University of Iowa, 2012

Lecture 5-7, Slide 19

MOV Copy Register