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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 60, NO. 3, MARCH 2013

Fully CMOS-Compatible 1T1R Integration

of Vertical Nanopillar GAA Transistor and
Oxide-Based RRAM Cell for High-Density
Nonvolatile Memory Application
Z. Fang, X. P. Wang, X. Li, Z. X. Chen, A. Kamath, G. Q. Lo, and D. L. Kwong

AbstractA fully CMOS-compatible vertical nanopillar gateall-around transistor integrated with a transition-oxide-based resistive random access memory cell to realize 4F 2 footprint has
been demonstrated and systematically characterized. The nanopillar transistor exhibits excellent transfer characteristics with diameter scaled down to a few tens of nanometer. Three types of
resistive switching behavior have been observed in the fabricated
one-transistor one-resistor cell, namely, preforming ultralowcurrent switching, unipolar switching, and bipolar switching after forming process. A reset current of only 200 pA has been
observed in the preforming ultralow-current switching, while for
the unipolar and bipolar switching modes after forming process,
good memory performance and operation parameter uniformity
are demonstrated. Furthermore, reset current is found to decrease
with reducing nanopillar transistor design diameter, which is
beneficial for circuit power consumption consideration.
Index TermsGate-all-around structure, high density 1T1R
integration, low power switching, resistive random access memory
(RRAM), vertical nanopillar transistor.

I. I NTRODUCTION

INCE LATE 1990s, resistive random access memory

(RRAM) has attracted considerable attention for the potential of being the next-generation nonvolatile memory [1][5].
Compared to conventional charge-trapping nonvolatile memory, RRAM devices exhibit lower operation voltage and higher
access speed; they also have advantages of low power consumption, superior data retention, high-density capacity, and CMOS
compatibility [6][8]. Various transition metal oxides have been
explored for resistive switching application [9][14], among
which HfOx has shown outstanding device performance and is
thus used as the memory switching layer in this work [15][17].

Manuscript received October 26, 2012; revised December 26, 2012; accepted
January 11, 2013. Date of publication February 4, 2013; date of current version
February 20, 2013. This work was supported by the Agency for Science,
Technology and Research SERC Future Data Center Technologies Thematic
Strategic Research Programme (NVM Based on Integration of PCRAM and
RRAM Cells With Ultra Scaled Vertical Si Nanowire Devices) under Grant
1121720016. The review of this paper was arranged by Editor K. Roy.
The authors are with the Institute of Microelectronics, ASTAR (Agency for
Science, Technology and Research), Singapore 117685 (e-mail: fangz@ime.
a-star.edu.sg; wangxin@ime.a-star.edu.sg; lix@ime.a-star.edu.sg; chenzx@
ime.a-star.edu.sg;
kamathar@ime.a-star.edu.sg;
logq@ime.a-star.edu.sg;
kwongdl@ime.a-star.edu.sg).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TED.2013.2240389

In order to realize high-density memory arrays, crosstalk between adjacent cells shall be avoided by adapting one-selectiondevice one-resistor or similar structures. An RRAM cell in
one-transistor one-resistor (1T1R) configuration has been implemented with a planar transistor, as reported previously [15],
[18]. However, the minimum cell size for planar 1T1R structure
is 6F 2 , where F stands for the minimum feature size. In 2010,
an RRAM cell integrated with a 3-D vertical bipolar junction
transistor (BJT) was demonstrated to have 4F 2 footprint [19].
It was the first attempt to use a transistor as the selective device
with 4F 2 density, whereas BJT has high leakage current and
may also increase process complexity if implemented along
with a CMOS logic circuit. As such, a more direct method to
achieve 4F 2 density is to integrate an RRAM cell with a vertical
nanopillar gate-all-around (GAA) transistor, of which the cell
size is 4F 2 [20]. A vertical nanopillar GAA transistor takes
unique advantages of nanowire GAA architecture, which has
been demonstrated with feasibility being an option for technology nodes 15 nm and beyond with sub-10-nm-channel-length
devices through both simulations and experiments [21], [22].
In this paper, we demonstrate the integration of a vertical
nanopillar GAA transistor with a transition-oxide-based RRAM
cell to achieve 4F 2 footprint and systematically investigate
1T1R architecture in nanometer scale for high-density nonvolatile memory application.
II. FABRICATION P ROCESS
Device fabrication is performed on standard 8-in CMOS platform; the architecture of the 1T1R memory cell is schematically
shown in Fig. 1. The RRAM cell forms directly on top of the Si
nanopillar without occupying any extra planar space. A brief
fabrication process flow is presented in Fig. 1. The vertical
nanopillar transistor, with amorphous Si (-Si) as the gate and
thermal oxide as the gate dielectric, is formed in Fig. 1(a)(g).
A detailed process flow of similar vertical transistors can be
found in [20]. After the formation of the transistor, a second
nitride spacer is formed on the pillar sidewall to prevent short
circuit to it as well as the transistor gate. Then, a resistive
switching layer of 3-nm HfOx and a top electrode with thin Ni
of 5 nm covered by TiN are deposited with PVD. After memory cell patterning and etch, the 1T1R configuration is ready.
The fabrication process is completed with premetal dielectric
(PMD) oxide deposition, contact formation, and metallization.

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Fig. 1. Fabrication process flow of the vertical nanopillar 1T1R memory cell. (a) Si nanopillar formation with nitride hard mask etching, trimming with oxidation
for a smaller diameter, and source implantation doping. (b) Plasma-enhanced chemical vapor deposition isolation oxide. (c) Gate oxide growth and -Si gate
deposition and implantation. (d) HDP isolation oxide deposition and etch back to expose Si nanopillar. (e) Excess gate -Si removal and As drain implantation.
(f) Spacer formation and oxide strip, followed by -Si gate patterning. (g) HDP oxide deposition and CMP to expose and remove hard mask. (h) RRAM memory
cell deposition and patterning after second nitride spacer formed on nanopillar tip sidewall. (i) PMD oxide deposition for passivation. (j) Metallization with Al
metal pad.

Fig. 2. SEM images of (upper part) single device and (lower part) 4 4
array during major steps of fabrication process. (a) Si nanopillar formation
with nitride hard mask on top. (b) -Si gate pad formed after thermally grown
gate oxide. (c) Nanopillar transistor drain exposed for memory cell integration.
(d) Oxide-based RRAM cell deposited and patterned after isolation spacer
formation. (e) Metallization and patterning.

Other than the 1T1R single device, a small array of 4 4

is also demonstrated. Fig. 2(a)(e) shows the SEM images of
the single device and small array during the major steps of the
fabrication process.
High-resolution cross-sectional TEM is used to confirm the
formation of the 1T1R structure, as shown in Fig. 3. The -Si
gate has been indicated in the figure, and the RRAM cell
consisting of n+ -Si/HfOx /Ni/TiN is also separately indicated
on the right of this figure. A thin layer of SiO2 might form
between n+ -Si and HfOx due to the oxidation of the pillar tip.
A relatively large diameter nanopillar of 80 nm is used here for
the ease of TEM sample preparation.
III. R ESULTS AND D ISCUSSION
For the first time, a nanoscale integration of a vertical
nanopillar GAA transistor and oxide-based RRAM has been
demonstrated. The fabricated 1T1R memory device exhibits
three modes of resistive switching operations, namely, preforming ultralow-current switching, unipolar switching, and bipolar

Fig. 3. High-resolution cross-sectional TEM image of 1T1R configuration

with nanopillar diameter of 80 nm; oxide-based RRAM stack is shown on the
right of this figure.

switching. The control transistor performance and different

resistive switching characteristics are presented in the following
section.
A. Transistor Characteristics
Fig. 4 shows the scaling trend of saturation current with
nanopillar diameter; it is seen from this figure that, when pillar
diameter scales down to 37 nm, the saturation current is only
25 A. All saturation current values are collected at a gate
voltage of 1.5 V.
Fig. 5 shows the Id Vg characteristics of the nanopillar
transistor without RRAM cell integration, which exhibits a
threshold voltage of 0.57 V, a drain-induced barrier lowering (DIBL) of 27 mV/V, and a subthreshold swing of only
66 mV/decade at 300 K.
Id Vd transfer characteristics of the transistor with electrically cutoff RRAM cell integration are shown in Fig. 6. It
is seen that both IV curves are similar, suggesting minimal
impact of functionality of the vertical transistor with subsequent
RRAM cell integration.

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Fig. 4. Saturation drive current (Idsat ) for vertical nanopillar control transistor with pillar diameter from 180 down to 40 nm, which is the size of
the bottom electrode for RRAM cell after integration. Drain current values are
collected under same gate voltage of 1.5 V for all transistors.

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 60, NO. 3, MARCH 2013

Fig. 7. Typical preforming ultralow-current switching IV characteristics.

Reset current of below 200 pA is observed for 100 dc consecutive cycles.

Fig. 5. Excellent Id Vg characteristics of the control transistor without

RRAM integration; subthreshold swing of 66 mV/decade and DIBL of
27 mV/V have been extracted from measurement.

Fig. 8. (a) Resistance distribution of 100 consecutive dc cycles in preforming

ultralow-current resistive switching; memory window of larger than ten times
is maintained. (b) Room temperature retention over a few thousand seconds
without obvious degradation and projection to ten years.

Fig. 6. Output Id Vd characteristics of control transistor and 1T1R with

electrically broken RRAM cell. Similar curves suggest minimum impact on
transistors performance with the RRAM cell incorporation.

B. Ultralow-Current Switching
Usually, in RRAM devices, a forming process is necessary
to initialize the resistive switching [6]. However, in the 1T1R
device fabricated in this work, a preforming resistive switching
with ultralow current is observed, as seen in Fig. 7. An external
20-nA current compliance is set to prevent unexpected current
jump during voltage sweeping. A reset current of only below
200 pA is observed for more than 100 dc switching cycles.
Fig. 8(a) plots the on/off resistive distribution of 100 dc
cycles from ultralow-current switching with a resistance ratio
window of larger than ten times. Room temperature retention is

also plotted in Fig. 8(b) with a read voltage of 2 V showing no

obvious degradation after a few thousand seconds.
Such low-current bipolar switching is possibly due to oxygen
ion movement in the HfOx layer. Without high-voltage forming
process, a thin layer of SiO2 exists between the nanopillar
transistor tip and HfOx switching layer, which limits the current
levels. When positive voltage is applied on the transistor drain
(Ni/TiN electrode), negatively charged oxygen ions in HfOx
tend to be attracted toward the Ni layer, which results in a more
oxygen-deficient oxide and higher conductance of the stack. On
the other hand, for reset process, reverse movement of oxygen
ions recovers the resistance of the memory cell. In addition,
in Fig. 7, an asymmetric IV curve is observed. This may be
due to electrons encountering a lower barrier when transferring
from n+ -Si to traps in HfOx with positive bias than when
transferring in the opposite direction with negative bias.

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Fig. 9. Plot of forming voltage versus nanopillar design CD. An increasing

forming voltage with decreasing pillar design CD or, equivalently, device area
can be seen.
Fig. 11. Statistical switching parameters of 200 dc switching cycles of unipolar mode. (a) Set/reset voltage distribution with average values of 2.38 V/0.78 V
and standard deviations of 0.27 V/0.30 V, respectively. (b) Reset current of 200
cycles with median value of only 38.8 A. (c) O N-/OFF-resistance distribution
with a memory window of around 103 times over 200 cycles.

Fig. 10. Typical resistive switching IV characteristics of unipolar switching in n+ -Si/HfOx /Ni/TiN stack. Inset shows the IV fitting for ON / OFF
states. External current compliance of 10 A is used to prevent device breakdown, and reset current is below 100 A for most switching cycles.

Fig. 12. Plot of reset current in unipolar switching versus nanopillar transistor
diameter, showing a decreasing trend of current amplitude with decreasing
design diameter. In this box chart plot, upper and lower whiskers indicate
90% and 10% percentage distributions, respectively, upper and lower parts of
rectangular box indicate 75% and 25% percentage distributions, respectively,
and the middle line indicates 50% percentage distribution.

C. Unipolar Switching
In addition to preforming ultralow-current switching, the
1T1R cell in this work also shows unipolar and bipolar switching behaviors after proper forming process around 56 V at
positive direction. Fig. 9 summarizes the forming voltage distribution of devices versus nanopillar transistor design CD. An
increasing forming voltage with decreasing pillar design CD
or, equivalently, device area can be seen here; this is consistent
with literatures [23]. It should be noted here that the nanopillar
design CD is different from the actual pillar diameter. Since
techniques like photoresist trimming and pillar oxidation are
implemented to reduce pillar size, the actual nanopillar diameter is much smaller than its design CD [20].
A typical unipolar switching curve of the memory device is
shown in Fig. 10. A system current compliance of 10 A is
used to prevent the device from permanent breakdown. The
inset of this figure shows the IV fitting of ON / OFF states
separately. Both states give a nearly linear relationship between

Fig. 13. Bipolar resistive switching IV characteristics of 100 dc cycles

from 1T1R configuration after forming process. Inset shows the linear IV
fitting for both ON and OFF states. Device set in positive bias with current
limited by nanopillar transistor while reset in negative direction without current
compliance.

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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 60, NO. 3, MARCH 2013

Fig. 14. Statistical bipolar resistive switching data of 100 dc cycles from ten devices. (a) ON-/OFF-resistance distribution of all devices gives a memory window
of 102 times over 100 cycles. (b) Switching voltage plot for all ten devices with average value of 2.50 V/ 1.08 V and standard deviation of 0.37 V/0.32 V for
set/reset transition, respectively. In the box chart plot in this figure, upper and lower whiskers indicate 90% and 10% percentage distributions, respectively, upper
and lower parts of rectangular box indicate 75% and 25% percentage distributions, respectively, and the middle line indicates 50% percentage distribution.

voltage and current, indicating ohmic conduction behavior.

However, it is inappropriate to draw such conclusion for OFF
state, as conduction mechanism in OFF state may be complicated [24]. Unipolar switching behavior of memory stack
n+ -Si/HfOx /Ni/TiN is very similar to what has been reported
by Tran et al. [25]. It is commonly accepted that the origin of
unipolar switching is the formation and thermal dissolution of
conduction filament in the NiO layer; in this case, the NiO layer
formed at the HfOx /Ni interface.
The statistical switching parameter is also summarized from
200 dc switching cycles of unipolar mode in Fig. 11. Tight
distribution of Vset and Vreset is achieved with average values
of 0.78 and 2.38 V and standard deviations of 0.30 and
0.27 V, respectively. Below 100 A, reset current is also observed with a median value of 38.8 A, as shown in Fig. 11(b).
An ON-/OFF-resistance window of 1000 (or 103 ) is maintained
after 200 cycles without obvious degradation, particularly for
ON -resistance which is nearly a constant value.
It is observed in Fig. 4 that nanopillar transistor saturation
current scales with pillar diameter, while a similar trend is
observed here on 1T1R integration. Fig. 12 plots RRAM reset
current versus nanopillar design CD; it is seen that reset current
decreases as nanopillar transistor design CD decreases. In this
figure, compliance used for all unipolar switching testing is
10 A, while reset current has a decreasing trend with shrinking
pillar diameter. It suggests that the saturation drive current of
the transistor also helps to limit the damage during set process
other than system compliance, since this saturation current
is roughly the maximum current that can pass through the
transistor as well as the RRAM cell.
D. Bipolar Switching
Voltage-bias-polarity-dependent bipolar switching is also observed in the fabricated memory cells. Fig. 13 plots the typical bipolar switching IV characteristics of 100 dc cycles.
Set process occurs at positive bias with nanopillar-transistorlimited current without system current compliance, while reset
occurs at the negative-bias side without any current compliance.
IV fitting of the switching curve is also shown in the inset

Fig. 15. Reset current statistic in bipolar mode versus different nanopillar
transistor design CDs. A similar decreasing trend versus transistor diameter
can be seen as in unipolar switching mode.

of this figure. Both ON- and OFF-state IV fittings show

slopes close to one. This is similar to that of unipolar switching; however, the current conduction mechanism in OFF state
needs to be confirmed with more detailed study on memory
cells [24].
To get statistical resistive switching data, 100 dc cycles are
measured and summarized from ten devices. Fig. 14(a) shows
the ON-/OFF-resistance distribution of ten devices; similarly,
very tight distribution of ON-resistance is observed, and around
102 -times resistance window is maintained for all ten devices.
Switching voltage is summarized in Fig. 14(b), for 100 data
points from each of the ten devices; it gives average voltages of
2.50 V/ 1.08 V and standard deviations of 0.37 V/0.32 V
for set/reset voltage only, respectively.
Similar to unipolar switching mode, reset current in bipolar
mode is also found to reduce with shrinking design CD of the
nanopillar transistor, as shown in Fig. 15. Median reset current
value reduces from more than 200 A in large devices with
a design CD of 295 nm to only about 30 A in the smallest
device. With further device scaling, this value is expected to
lower further, which is beneficial for high-density memory
integration as power consumption has become one of the most
important issues in todays IC chips.

FANG et al.: INTEGRATION OF VERTICAL NANOPILLAR GAA TRANSISTOR AND RRAM CELL

IV. C ONCLUSION
In this paper, 1T1R architecture involving vertical GAA
nanopillar transistors has been systematically investigated.
TiN/Ni/HfO2 /n+ -Si stack used for RRAM cells shows excellent NVM properties, including preforming ultralow-current
switching as well as normal unipolar and bipolar switching
behaviors after electrical forming. It is found that the reset
current in both unipolar and bipolar switching modes decreases
with shrinking nanopillar diameter, which is good for device
scaling. Moreover, the demonstrated results suggest that this
vertical integration architecture would be a more direct and
flexible test vehicle to verify scalability and functionality for
novel RRAM cells with a dimension close to that of real
application.
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Authors photographs and biographies not available at the time of

publication.