Sie sind auf Seite 1von 61

LABORATORY MANUAL

DEPARTMENT OF
ELECTRICAL & COMPUTER ENGINEERING

UNIVERSITY OF CENTRAL FLORIDA

EEL 4515

DIGITAL COMMUNICATIONS

Revised
August 2004

TABLE OF CONTENTS

Instructions........................................................................................................................................iv
Troubleshooting Hints ......................................................................................................................vi
Student Information .........................................................................................................................vii
Title Page Format........................................................................................................................... viii
Attendance Record............................................................................................................................ix
Lab 1 ..................................................................................................................................................1
Pulse Width Modulation (PWM) ...................................................................................................1
1.1 Objective ..............................................................................................................................1
1.2 Theory ..................................................................................................................................1
1.3 Simulation ............................................................................................................................3
1.4 Hardware Experiment: PWM ..............................................................................................4
Lab 2 ..................................................................................................................................................9
Pulse code modulation ...................................................................................................................9
2.1 Objective ..............................................................................................................................9
2.2 Theory ..................................................................................................................................9
2.3 Simulation ..........................................................................................................................10
2.4 Implementation ..................................................................................................................13
2.5 Hardware Procedure...........................................................................................................17
2.6 Questions............................................................................................................................18
Lab 3 ................................................................................................................................................19
Delta Modulation .........................................................................................................................19
3.1 Objective ............................................................................................................................19
3.2 Theory ................................................................................................................................19
3.3 Simulation ..........................................................................................................................20
3.4 Hardware Experiment ........................................................................................................22
3.5 Questions............................................................................................................................24
Lab 4 ................................................................................................................................................25
Frequency Shift Keying ...............................................................................................................25
4.1 Objective ............................................................................................................................25
4.2 Theory ................................................................................................................................25
4.3 Simulation ..........................................................................................................................27
4.4 FSK modem design............................................................................................................29
4.6 Questions............................................................................................................................31
Lab 5 ................................................................................................................................................33
Binary Phase Shift Keying...........................................................................................................33
5.1 Objective ............................................................................................................................33
5.2 Theory ................................................................................................................................33
5.3 Simulation procedure .........................................................................................................37
5.4 Hardware Experiment ........................................................................................................38
5.5 Questions............................................................................................................................40
Lab 6 ................................................................................................................................................41
Introduction to System View Tool for Communication Simulation............................................41
Digital Communications

ii

EEL-4515

6.1 Objective ............................................................................................................................41


6.2 Welcome to Systemview: ..................................................................................................41
6.3 Salient features:..................................................................................................................41
6.4 Installation procedure: .......................................................................................................41
6.5 Overview:...........................................................................................................................42
6.6 User Interface:....................................................................................................................42
6.7. Building circuits in Systemview: ......................................................................................44
6.7 Lab Assignments:...............................................................................................................51

Digital Communications

iii

EEL-4515

INSTRUCTIONS
LAB TITLE:

Lab Section:
SCHEDULE:

Room:
Lab Instructor:
Office:
Office Hours
Email:
Telephone
Please pay attention to the following:
Lab Sessions
Please, arrive at the lab at least 5 minutes before official starting time.
When a la session has to be cancelled or rescheduled, a notification will be posted outside the Lab
prior to that session.
Lab sessions are divided in two categories: Pre-la Sessions and Experiment Sessions. Each student
is permitted to miss a maximum of 2 experiment sessions, that he/she can make up, provided
he/she has adequate reasons for his/her absence. However, if a student intends not to attend a
particular lab session, prior notice should be given to the instructor. After the end of the regular
lab sessions a special make-up Experiment Session will be scheduled if needed. Note, however,
that there wont be any make-up Pre-lab Sessions. In the exceptional case, where there is a
possibility to make up an Experiment Session by attending a different lab section, you must first
contact tour lab instructor, in order to get his permission and for him to make the arrangement.
Lab Reports
Lab reports consist of the answered questions or solved problems pertaining to the pre-lab of an
experiment and the corresponding portion relevant to the actual experiment. The reports are
always due on the date of the next experiment lab session, hence every other week. The due date
for the last lab report to be turned in will be announced. You can turn your reports in either right
before the start of a session or you can ask the secretaries in room ENGR 407 CEBA I to put
them into my mailbox. No late lab reports will be accepted.
Lab reports have to be legible, detailed and presentable, so typing them is strongly encouraged.
Sharing among same group members of data, tables, graphs and figures to be included in lab
reports is encouraged, but contents must be individually prepared.
When you prepare a lab report, pay attention to the following points:
Do not write your Social Security Number on the cover page. However, make sure the title and the
number of the experiment are correct.
Avoid attaching copied pages from books or lab manuals to your lab report. Instead integrate any
such material during the time you compile the lab report.

Digital Communications

iv

EEL-4515

Any reported experimental data should be always accompanied by the corresponding units of
measurement.
Manually produced graphs should be neatly prepared. Construct the axes with a ruler and do not
omit putting the variable names and corresponding units of measurement.
Answer to the questions inside the lab report in detail. Make sufficient comments concerning your
observations during the experiment. Also, put emphasis on conclusions that might be drawn from
the comparison of theoretical results and experimental ones.
Before you come to the lab for an experiment
Before you attend an Experiment Session make sure you have familiarized yourself with the
material related to the experiment. The needed theoretical background can be found in your
textbook and the pre-lab notes. Also, take some time and read through the steps of the experiment.
It is very important that you have completed all the work mentioned in your pre-lab notes, which
will involve some simulations, computations, e.t.c. Systematic failure in doing this will definitely
result in reduction of your lab grade.
Grading Policy
The grade for each individual experiment will be points out of a total of 20.
The way a pre-lab/lab report will be graded depends on how much
complete your lab report is
detailed your answers are
accurate your results are
neat and presentable your lab report is
Its in the lab instructors discretion to allocate points regarding these factors.
Failing to attend a Pre-lab Session will result in a 2 points reduction from the corresponding total
lab grade.
Failing to attend an Experiment Session, without eventually making it up, results to 0(zero) credits
for the experiment portion of the la, even if the student has turned in a lab report.
At the end of the semester for each student attending the lab all the grades of the experiments will
be averaged and this will constitute the final lab grade, which will e forwarded to the
corresponding instructor of the class, it is in the course instructors discretion to curve any lab
grades, if he/she feels that it is necessary.

Digital Communications

EEL-4515

Troubleshooting Hints
Be sure that the power is turned on.
Be sure that the ground connections are common.
Be sure that the circuit you built is identical to that the diagram. (Do a node-by-node check).
Be sure that the supply voltages are correct.

Be sure that the equipment is set up correctly and you are measuring the correct parameter.
If steps 1 through 5 are correct, then you probably have used a component with the wrong value or
one that doesnt work. It is also possible that the equipment does not work (although this is not
probable) or the protoboard you are using may have some unwanted paths between nodes. To find
your problem you must trace through the voltages in your circuit node by node and compare the
signal you have to the signal you expect to have. Then if they are different use your engineering
judgment to decide what is causing the difference or ask your lab assistant.

Digital Communications

vi

EEL-4515

STUDENT INFORMATION
Please, provide the information requested in the empty fields of the table below and hand in. It
will be kept confidential by your Lab Instructor.

Student Name

Social Security Number


(confidential)

Emergency Phone Number


(confidential)

Email

Name of Class Instructor

Lab Section

Digital Communications

vii

EEL-4515

Title Page Format

Eel 4515
Digital Communication Lab
Experiment:
Experiment Title:
Lab Section#:
Date:

Your Name

Lab Partners

University of Central Florida

Department of Electrical Engineering

Digital Communications

viii

EEL-4515

Attendance Record
Lab Section:
Experiment & Session Type:
Date:
Please, print your name and sign at the corresponding spaces
Station
NAME
NAME
NAME

Signature
Signature
Signature

Station
NAME
NAME
NAME

Signature
Signature
Signature

Station
NAME
NAME
NAME

Signature
Signature
Signature

Station
NAME
NAME
NAME

Signature
Signature
Signature

Station
NAME
NAME

Signature
Signature

NAME

Signature

Digital Communications

ix

EEL-4515

LAB 1

PULSE WIDTH MODULATION (PWM)


1.1 Objective
The objective of this lab is to be familiarized with Pulse Width Modulation (PWM). Students are
expected to write Matlab programs to simulate the modulation process for the PWM. In the
hardware experiment part you will design the PWM modulator.

1.2 Theory
To transmit a signal f(t) that is band-limited to fm Hz, it is only necessary to transmit the
information about its sample values at (2fm)-1 second interval (recall Nyquist Theory). It is
possible to represent each sample by a pulse. Certain parameters of the pulse (such as amplitude,
width or position) can be varied depending on the value of the sample. In other words, one of the
parameters of the pulse vary in proportion to f(t). Thus, a series of modulation schemes are
evolved. Consider Figure 1.1 where three types of modulation scheme are illustrated.

Figure 1.1: An illustration of PAM, PWM, and PPM


Figure 1.1 (a) shows the Pulse Amplitude Modulation (PAM) scheme, where the amplitude of the
pulse is the proportional to the amplitude of the signal f(t) at the sampling points.
Figure 1.1 (b) shows the Pulse Width Modulation (PWM) scheme. PWM uses constant amplitude
pulses whose width is proportional to the value of the f(t) at the sampling instants.

Digital Communications

EEL-4515

Figure 1.1 (c) shows the Pulse Position Modulation (PPM) scheme, where the amplitude and
width of the pulse are constant but the pulse position varies in proportion to the value of f(t).
PWM
As it was mentioned in the above, Pulse Width Modulation (PWM) encodes a signal into periodic
pulses of equal amplitude but varying width. The width of a pulse at a given point in time is
proportional to the amplitude of the message signal at the time. For example, a large value of the
message signal corresponds to a wide pulse, and a small value of the message yields a narrow
pulse. The width of the pulse can be describe in terms of its duty cycle, which is defined as:
d=

tw
100 %
td

Where, tw = width of the pulse


td = period of the pulse.
Here, td is constant and tw varies.

td
tw

Figure 1.2: Definition of duty cycle


In PWM, there is a linear relationship between the duty cycle (d) and amplitude of message signal
(Vin). This relationship can be written as following
d Vin

d = M d Vin
Where, Md is the modulation index.
To implement the PWM, the message signal is compared with sawtooth carrier. When the
message signal is greater than the carrier, the comparator output becomes high and vice versa; the
highs and lows can be represented by +1 or 1 respectively. The comparator output is the pulse
width modulated signal.

Digital Communications

EEL-4515

Message
Signal f(t)

Output

Carrier
Figure 1.3: Basic Structure for PWM implementation

PWM Applications
PWM is used to deliver variable dc power supply. The comparator input controls the level of the
supply. This variable power supply may be used in motor control, digital light dimmer circuits,
digital controllers etc.

1.3 Simulation
We will use the Matlab tool to do this simulation. The main idea of this simulation is to write
Matlab codes, which will produce Pulse Width Modulated signals (e.g., see Figure 1.4).

Simulation Procedure:
Construct a time array from 0 to 10 sec with 0.01 intervals. Name it T.
Find the size of the array T. Use length function. Name the size N.
Construct signal array x. Signal is a sinewave with unity amplitude and unity angular frequency.
Construct carrier array saw. Carrier is a sawtooth signal with 1.2 amplitude and angular
frequency 5. Use sawtooth function to generate the carrier.
Compare the signal and carrier for each time interval (for each element of array T). When the
signal is greater than the carrier set output y high (say 1), low (say 1) otherwise. Construct a
loop with N iterations to perform this.
In step (4) take the amplitude of the carrier to be 0.8 and redo the simulation. What happens?
Why?
In step (4) take the frequency of the carrier to be equal to 0.5, 1, 10 keeping the same carrier
amplitude at 1.2 and redo the simulation. What happens? Why?
Plot signal vs time, carrier vs time and output vs time for each of the above cases. Use subplot
function to plot saw-t over x-t and y-t below in a same template.
Submit a report and the soft copy of your codes.

Digital Communications

EEL-4515

1.5
carrier

1
0.5
0

signal

-0.5
-1
-1.5
0

10

10

1.5
modulated signal

1
0.5
0
-0.5
-1
-1.5

Figure 1.4: Message signal, Saw-tooth Carrier and PWM modulated signal. These are the outputs
of Matlab simulation. Your simulation output may look like this figure.

1.4 Hardware Experiment: PWM


To implement the PWM modulation we will use the circuit setup shown in the Figure 1.7. Upper
half of the circuit generates a sawtooth (or triangular) carrier signal. The lower half of the circuit is
basically a comparator.
The circuit shown in Figure 1.6 generates a PWM signal by comparing the level of the message
signal (Vin) to the level of the Sawtooth of period td at the input of the comparator. If the Sawtooth
voltage is larger than the message, the output of the comparator saturates at -Vcc (0V) otherwise the
comparator will saturate at +Vcc (5V). The output of the comparator is the PWM signal. Note that
the input is biased such that for 0 dc the voltage at the comparator is 2.5V.
Let us conduct some analysis on the two basic building blocks of the Pulse Width Modulator
(PWM) circuit.

Digital Communications

EEL-4515

Oscillator (Sawtooth generator) Analysis:


Using superposition in pin 3 of the saw-tooth generator circuit in Figure 1.7. Let us denote the
voltage at this node by V. Assume Vcc + =5 V and Vcc- = 0 V.
+

Vcc V Vout V V
+

=0
R1
R3
R2
Vcc + Vout

+
V = Rt

R
R
3
1
R1 R2 R3
where, Rt =
R1 R2 + R2 R3 + R3 R1
Vu or Vupper-limit is defined by the voltage that will cause the amplifier to switch from its positive
output swing to its negative. That means Vu will cause the output to be Vcc (5 V in our case).

V + V (= Vcc )

Vu = Rt cc + out

R3

R1
Vl or Vlower lim it is defined by the voltage that will cause the Op-amp output to switch from its
negative output swing to its positive. At this point the output will -Vcc (0 V in our case).

Vcc +

Vl = Rt

R
1
Substituting values for the resistors:
Vu = 2.72V
Vl = 2.272V

Vswing = ( 2.727 2.272) = 0.4545V


The period of oscillation is really found by observing the time constant of the capacitor ( R5 C 1 ).
The capacitor will charge exponentially at e t / R5C1 . Note that the charging and discharging times
are the same.
Assuming that the oscillation is in its highest voltage Vu and knowing that Vu will decrease until
reaches VL at which point it will start to rise again producing oscillation.
Solving for t:
V u e t / R5C1 = Vl

Digital Communications

EEL-4515

V
t = R5C1ln u
Vl
Substituting Vu / VL from their respective values shown above,
Vu 1 + R1
=
VL
R3
The period of the output oscillation is given by
1 + R1

T = 2t = 2 R5C1 ln
R
3

Comparator Analysis:
+

Using superposition theorem and assuming Vcc = 5V and Vcc- = 0 V the voltage at pin 2 of the
comparator (designated as Vs) is equal to
RR
RR
Vs = Vin [ 7 8 + R6 R8 + R7 R8 ] + Vcc + [ 6 8 + R6 R8 + R7 R8 ]
R6 R7
R6 R7
Substituting resistor values and Vcc=5V
Vs = Vin(0.0909) + 2.2727
Note that the input to the comparator is biased such that for an input of Vin = 0V, voltage at pin 2
of the comparator, Vs = 2.2727 V (equal to VL for the oscillator). Likewise, for an input of Vin =
5V, Vs = 2.2727 V (equal to Vu for the oscillator).
For a dc input, the corresponding PWM signal will be as shown in the Figure 1.5 below:

Output
2.72 V
Vin DC
2.5 V

2.27 V
Reference
Figure 1.5: The PWM signal for a dc input.

Experimental Procedure:
Build the circuit shown in Figure 1.7. Sketch the triangular wave going into the comparator with
its maximum and minimum values. Check for a duty cycle of 0% at an input dc level of zero Volts

Digital Communications

EEL-4515

and for d=100% when Vin=5V. The input-biasing network consisting of R6, R7 and R8 is very
sensitive to small variations in the resistor values.
To measure modulation index Md, apply dc input (Vin = Vdc) and measure modulated output.
Compute Md, using the ratio of duty cycle d to input Vdc.
Vdc

Compute Md, using the ratio of d to Vdc

1
2.5
4.0
Connect the output of the circuit to the spectrum analyzer and sketch the spectrum for reach of the
input voltages in step 1 above.
Remove DC input. Apply a 100Hz, 3V peak-to-peak sine wave offset, and 2.5V dc to the input of
the PWM. Observe the scope waveform. Can you find Md, using the observed waveform? Show
how.
Build the circuit shown in figure 1.7. Use filter box (Kron-Hite filter) setting the switch in the
back to max flat. Use as low pass filter. Apply PWM modulated signal to the input (Vin(t)) of
the filter. Set cutoff frequency to 150 Hz. Sketch the output of the filter, Vo (t).
Use the PWM signal to make digital dimmer. Just put an LED at the output of the comparator as
shown in the Figure 1.6. Give a variable dc supply at the input of the comparator. As you change
the input of the comparator the brightness of the LED changes. In real application load may be
digital dimmer or dc motor, and Vin is the actuating signal.

Vin

PWM
generator
as shown
in Figure
1.7

LED

1K

Figure 1.6: Circuit arrangement for Digital Dimmer.

1.5 Calculations and Questions:


For a dc input of 2.5 V, sketch the spectrum for the PWM modulated signal. How would the
spectrum change for a dc input of

Digital Communications

EEL-4515

i) 0 < Vin < 2.5?


ii) 2.5 < Vin <5?
(Hint: PWM signal is square wave with varying duty cycle.)

+5

+5

R1 20k

R4

1k

R3

R2
20k

C1
.01 uf

100k
+5
3 +
8 1
4
2

Square
wave

R5
100k

Triangular
Wave

+5
+5
R7 20k
R6
vin
(0-5V) 100k

2
R8 20k

+5 R9

3 +

8
4

1k
Output

LM393N

Figure 1.7: Circuit diagram for PWM

Digital Communications

EEL-4515

LAB 2

PULSE CODE MODULATION


2.1 Objective
The objective of this lab is to be familiarized with Pulse Code Modulation. Students are expected
to write Matlab code, that will help them to understand the fundamentals of PCM. They will also
observe the modulation and demodulation process of PCM using a pre-built hardware board.

2.2 Theory
Pulse Code Modulation (PCM) is a method of converting an analog signal into a digital signal
(A/D conversion). Analog signal is characterized by the fact that its amplitude can take on any
value over a continuous range. This means that it can take on an infinite number of values. But,
digital signal amplitude can take only finite number of values.
In PCM an analog signal is first sampled at a rate higher than the Nyquist rate, and then the
samples are quantized. It is assumed that the analog signal is distributed on an interval denoted by
[-xmax, xmax], and the number of quantization levels is large. The quantization levels can be equal
(uniform PCM) or unequal (Non-uniform PCM). In this lab we will only consider the uniform
PCM. Topics on non-uniform PCM may be found in the following reference.
B. P. Lathi, Modern Digital and Analog Communication Systems 3rd edition, pages 267-271,
Oxford University Press, 1998

Uniform PCM
In uniform PCM the interval [-xmax, xmax] of length 2xmax is divided into N equal subintervals, each
of length = 2xmax/N. If N is a power of 2 or N=2v, then v bits are required for representation of
each level.
As we discussed, after quantization, the quantized levels are encoded using v bits for each
quantized level. The encoding scheme that is usually employed is natural binary coding (NBC),
meaning that the lowest level is mapped into a sequence of all 0s and the highest level is mapped
into a sequence of all 1s. All the other levels are mapped in increasing order of the quantized
value.
Figure 2.1 shows an example with an analog signal which amplitude lies in the range of [-xmax,
xmax]. The number of levels to which the signal is quantized is 8. In this case each sample requires
3 bits to represent digitally.

Digital Communications

EEL-4515

Encoded
Output
Xmax

- Xmax

Quantized
samples

111
110
101
100
011
010
001
000

Quantized Signal
Samp led every T second

Input Signal, x(t )

2Xmax/N

2T

3T

4T

5T

2T

3T

4T

5T

Figure 2.1: Quantization of a sampled analog signal.

The message is periodically sampled and digitally encoded in PCM. Since the signal is digitally
encoded, only certain discrete voltage levels can be represented and there will be some error in
encoding a random analog signal. This error is known as the quantization error. The ratio of the
signal power to quantization error power is generally termed as SQNR (Signal to Quantization
Noise Ratio).

2.3 Simulation
In this simulation we will quantize a sinewave signal (message) and encode it to binary bits. We
will reconstruct the sinewave from binary bits. We will also calculate the SQNR for the 8-level
and 16-level quantization.
For the simulation, generate a sinusoidal signal with amplitude 1, and =1. Using a uniform PCM
scheme, quantize it once to 8 levels and once to 16 levels. Plot the original signal and the
quantized signals on the same axis. Compare the resulting SQNRs in the two cases.
We arbitrarily choose the duration of the signal to be 10s. The resulting SQNRs are 18.90 dB for
the 8-level PCM and 25.13 dB for 16-level PCM, compare these values with the results that you
get from your simulation. The plots are shown in figure 2.2.

Digital Communications

10

EEL-4515

8 level quantized signal


0.8

signal

16 level quantized signal

0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
0

10

t
Figure 2.2: A sinusoidal signal before and after quantization. You can compare this figure with
your simulation results. A zoomed potion of this figure is given in the following Figure 2.2 (a).

Figure 2.2(a): The portion of the Figure 2.2 is zoomed here for clarity.

Digital Communications

11

EEL-4515

Matlab functions that may be needed for this lab:


Length, abs, max,

round, log10, dec2bin, plot, grid, title, X label, Y label, Subplot, Figure

Simulation procedure:
The following procedure only gives you an idea of how the PCM modulation and de-modulation
are performed. Actual implementation may vary.
1. Construct a time array from 0 to 10 sec with 0.1 intervals. Name it t.
2. Find the size of the array t. Use length function. Name the size m.
3. Construct signal array a. Signal is a sinewave with unity amplitude and angular frequency.
4. Assign the number of quantization level n equal to 8.
5. Calculate, amax = max (abs (a)). See figure 2.3(a).
6. Calculate the following as shown in figure 2.3.
b = a + amax
c = (n-1) (b/(2amax))
d = round(c)
a_quan = 2 amax.d/(n-1) amax

a_error = a-a_quan
7. Calculate
m

S = a 2 (i )
i =1
m

N=

a _ error

(i )

i =1

8. Calculate Signal to noise ratio,


SQNR=10 log 10(S/N)
9. Calculate binary coding to corresponding quantized value using dec2 bin function.
10. Repeat 4-9 with quantization level n=16.
11. Plot the input signal and quantized signal as in Figure 2.2. Use black solid line for signal, red
solid line for 8 levels quantized and blue solid line for 16 level quantized signals. Use figure
function for multiple figures (you have to plot another figure in step 12.
12. Plot your variables a, b, c, d, a_quant and a_error for quantization level 8. Show your plots
exactly as shown in the Figure 2.3 in a single template. Use subplot function for that.
13. Compare the two quantized signals. Which is more close to input signal?
14. Tabulate few sample binary codes for both cases.
15. Reconstruct the original sinewave from the binary codes (both) using the Matlab function
bin2dec. How is it different from the original signal?

Digital Communications

12

EEL-4515

0.5

1.5

0.5

-0.5
-1
0

a- quant

7
6
5
4
3
2
1
0
0

4 t

4 t

10

0
0

10

7
6
5
d 4
3
2
1
0
0

0.5

0.5

-0.5

- 0.5

-1
0

4 t

10

-1
0

10

10

10

a- error

4 t

Figure 2.3: Steps of quantization in simulation

2.4 Implementation
Synchronization
When the encoded bits are transmitted, how does the receiver know when the bit sequence starts
and when it ends?
For this type of encoding it is possible that some synchronization bits are transmitted periodically.
The receiver can synchronize itself using these synchronizing bits. Additionally, some guard bits
are needed to separate adjacent codes. The total number of bits necessary to transmit to be able to
decode a signal is therefore much larger than the number of bits containing information. The prebuilt board Module 296f will be used for this lab. This board implements PCM with two 0s as
the guard bits, the four information bits, and two more guard 0s as followed by eight 1 as
synchronization bits (Figure 2.8).
The Figure 2.4 shows the complete PCM system. In the transmitter the input message signal f(t) is
sampled, quantized, and encoded to binary bits. The serial bit stream represents the PCM output.
At the receiver the PCM bit stream is decoded. After D/A conversion the message signal is
reconstructed. Reconstructed signal represents the original message signal with some quantization
error.

Digital Communications

13

EEL-4515

Sampler

Quantizer

Encoder

Parallel/Serial

Signal
f(t)

PCM
output

Transmitter
Decoder
PCM in

D/A Converter

f(t)
Analog Out

Receiver
Figure 2.4: PCM system: Transmitter & Receiver

Encoding
The module 296f encodes a signal by comparing the input signal level to an 8 or 16-step ramp.
Each step ramp represents the current state of the binary counter. To encode PCM, the ramp must
repeat itself at least at Nyquist frequency, which is higher than the frequency of the message. The
message signal and ramp are inputs to a comparator, which has two output states high, and low.
When the ramp signal exceeds the message signal, the comparator output swings low and the
counter value is latched and is held until the ramp repeats.

Decoding
When the data bits are separated from the bit streams (removing the synchronization and guard
bits), they are sent to a D/A converter, where each bit is given the appropriate weight in voltage,
and the voltage due to each bit is summed.

Modulator
As shown in the Figure 2.5, the clock frequency f1 feeds to the clk line of the 4-bit counter and
also the shift-left control line of the 8-bit register. The clock f1 simultaneously increases the
counter and shifts left the 8-bit register.

Digital Communications

14

EEL-4515

f2 = f1/ 16

Clock

f1 b it frequency
Ramp
Output

4-bit Counter

clk

shift
left

D/A
Latch (4-bit)

load

f(t)

load

Shift Register (4-bit)


1

PCM Out (Serially)


Figure 2.5: PCM Modulator
The comparator has f(t)/k (where k is an attenuation constant) and a ramp signal as the + and
inputs respectively. The output of the comparator drives the load line of the 4-bit latch. The
comparator output is high until the ramp input becomes higher than f(t)/k. at that point, the last
input to the latch stays for the rest of cycle until counter is reset to 0000.
Synchronously with the counter reset the f2 clock signal goes high loading the output of the latch
to the 8-bit register. Note that only the four counter bits are loaded from the latch, the other four
are grounded and therefore loaded as 0.
At this point the cycle starts again. The counter starts counting and the 8-bit register starts shifting
out serially the 8 bits loaded in it. Note that every time a bit is shifted out serially, another bit is
taken as input in the rightmost bit of the registers from the serial input. In our cases this input is
connected to a logic 1 and are the synchronization bits. An example is given in the Figure 2.6 (a)
& (b).
Data in

Serial in 1

PCM serial out


(a)

Digital Communications

15

EEL-4515

Three Clock Pulse Later

Serial in 1
1
0
0
into demodulator

PCM serial out


(b)

Figure 2.6(a) & (b): Status of the shift register as it shifts the bits.

Demodulator
The synchronization circuit found in Figure 2.7 recognizes the eight 1 used to synchronize and
with the last 1 turns the clock on (same frequency as f1). The 8-bit register on the demodulator
will load serially the next eight bits coming from the modulator.
The same clock runs a 3-bit counter with its carry line connected to a load control line of latch.
The latch will load the 4 counter bits on the 8-bit register when the counter is reset to 0000. Note
that it takes nine clock pulses to reset instead of eight. In order to avoid an extra bit to be shifted-in
three outputs from the counter are NAND together and tied to the clock. This avoids the 8 bit
register to shift in another bit when the counter output is 111.

PCM
Input
z

Sync
Circuit

Shift Register
serial input
Parallel Out

Clock

Latch

x
y

R/2

R/4

/9

R/8

Counter

/8
y

D/A
Converter

Analog

Figure 2.7: PCM Demodulator

Digital Communications

16

EEL-4515

2.5 Hardware Procedure


Encoding
Plug module 296f into the power supply (wooden adaptors are available).
Set the clock control to slow and the 3 bit /4 bit switch to 4 bit.
Set the oscilloscope to dc and display the ramp output signal on the scope. The state of the
counter is displayed on the LEDs, and you should see all the binary numbers between 0000 and
1111 (0 and 15, decimal) displayed while you see the voltage step up on the scope. The voltage
level displayed on the scope is an analog equivalent of the counter value, determined by the
internal A/D converter.
To see the full ramp at once, set the clock control to fast. What are the voltage limits of the ramp
at the ramp output?
Return the clock control to slow.
Set the analog input to the following DC values and record the binary number indicated as shown
on LED display.
Dc Input (V)
-4
-3
-2
-1
0
1
2
3
4

Number latched

Table 2.1: Record the number latched for different dc inputs.

Decoding
Set the clock control to fast. Apply a 4V peak, 0.2Hz sinusoid to the analogue input.
Set both scope inputs to dc. Display the PCM output along with the analogue input on the
scope.
Draw one full period of the PCM out, identifying the sync bits, guard bits, and the information
bits.

Digital Communications

17

EEL-4515

PCM
Output

Word 1

Word 2

0 0 0 1 1 1 0 0 1 11 1 1 1 1 1 0 0 0 1 1 1 0 0 1 1 1 1 1 1 1 1

Guard Band
Information

Sync Pulses

Figure 2.8: PCM Output: What it should look like.


Change the input signal to a 2.5V peak, 500Hz sine wave.
Connect PCM output to the PCM input and make all grounds common.
Display the analogue input together with analogue output on the scope, where analogue
output is the demodulated message. Is the input signal accurately reproduced? Explain any
differences.
Press the inhibit sync button on the decoder clock. What happens? Is synchronization necessary
for PCM?

2.6 Questions
Consider again the output signal from step (6) of the decoding portion in section 2.4. What could
you do to improve the demodulated signal? What would that cost be? Use bandwidth, data storage,
cost or any other relevant factor as your basis.
Hint: Think about the quantization and its effect.

Digital Communications

18

EEL-4515

LAB 3

DELTA MODULATION
3.1 Objective
Introduction of basic concepts of Delta Modulation (DM) system with simulation and hardware
implementation.

3.2 Theory
With Delta Modulation (DM) a train of fixed width pulses is transmitted, whose polarity indicates
whether the demodulator output should rise or fall at each pulse. The output is caused to rise or
fall by a fixed step height at each pulse. A block diagram of DM system is given in Figure 3.1.

Figure 3.1: Delta modulation system. Upper block is for encoder and lower block is for decoder.
The modulating message signal m(t) is applied to the non-inverting input of a high gain
differential amplifier. The input analog signal m(t) is compared with the loop estimated signal
mr(t) to generate the error signal e(t). Then, this error signal is fed into a two level quantizer. The
quantized error signal is multiplied by the sampling function p(t) to generate the output s(t). The
signal s(t) is integrated and amplified to generate the loop estimate mr(t).

Digital Communications

19

EEL-4515

In this implementation, the sampling function is a train of narrow pulses with unit amplitude (most
practical implementations also). The multiplier becomes a switch and the sampling function
becomes the switch enable input. The output s(t) is a sequence of pulses with amplitude +A or
A. It is very important to note that the DM process samples the quantized error function and not
the input signal itself and for narrow sampling pulses the estimated signal mr(t) is a stepwise
approximation of m(t).
The DM process is a process of analog to digital conversion. Quantization error is present at the
output. Two types of quantization noise are present in delta modulation, granular nose and slope
overload nose.
Granular noise is due to the use of finite quantization steps to reconstruct (approximate) the input
signal. It is similar to the quantization noise observed in pulse code modulation (PCM) systems.
Slope overload noise occurs whenever the slope of the input signal exceeds the DM maximum
slope or the input signal changes between samples, by an amount greater than the step size of the
DM.
DM approximate a waveform by a linear staircase function, the waveform must change slowly
relative to the sampling rate. This requirement implies that waveform must be oversampled, i.e., at
least five times the Nyquist rate.
"Oversampling" means that the signal is sampled faster than is necessary. In the case of Delta
Modulation this means that the sampling rate will be much higher than the minimum rate of twice
the bandwidth. Delta Modulation requires "oversampling" in order to obtain an accurate prediction
of the next input. Since each encoded sample contains a relatively small amount of information
Delta Modulation systems require higher sampling rates than PCM systems.

3.3 Simulation
The simulation in this lab includes the modulation (encoding) and demodulation (decoding) steps.
Students are expected to be famiriazed with a simple Delta Modulation system as a whole.

Procedure:
1. Construct a time array from 0 to 1/25 second with ts=1/fs interval (sample frequency fs=2000).
Name it 'tn'.
2. Set the step size 1/15. Name it 'StepSize'.
3. Construct a signal 'm' which is a sine wave with 0.5 amplitude
and frequency of 50, time is 'tn'. Th esignal m is our modulating message signal.
4. Call function Delta modulation encoder 's=DM_Encod(m, StepSize)'

Digital Communications

20

EEL-4515

With input signal 'm' and step size "StepSize' as the parameter to the function. 's' is the output. The
following steps describe the procedure to write this function.
4.1 Use 'length' to find the size of te signal m, name it 'xlen'.
4.2 Set accumulation at start is zero.
4.3 Compare input signal(s) with accumulation (i) from beginning to end.
When signal is greater than accumulation, encoder out s(i)=+1, next accumulation (i+1) equals
accumulation (i) plus step size.
When signal less than accumulation,, encoder out s(i)=-1, next accumulation(i+1) equals
accumulation(i) minus step size.
5. Call function Delta modulation decoder '[Si]=DM_Decod(StepSize,s)'
With input signal 's' and step size "StepSize'. Output 'Si'.
5.1 use 'length' find size of signal (s), name it 'xlen'
5.2 set accumulation at start is zero.
5.3 compare input signal s(i) with zero from beginning to end.
When s(i) is greater than 0, next accumulation(i+1)
equals accumulation(i) plus step size.
Else, next accumulation (i+1) equals accumulation (i) minus step size.
5.4 Set output 'Si' equal equals accumulation (2:i+1)
6. Call function low pass filter 'So=LowPassFilter(100, 4*50/fs, Si);'
Input signal 'Si', Output 'So'.
This function program is given in following.
function So=LowPassFilter(fod, cf, Si)
%lowpass filter
%So=LowPassFilter(100, .1, Si);
%
%fod: filter order.
%cf: cut-off frequency.
%So: output.
b=fir1(fod,cf);
size(b)
So = conv2(Si,b,'same');
7. Plot the signal of input 'm', Decoder output 'Si' and Lowpassfilter output 'So' vs time. Use
'subplot' function plot them in same template.
8. By change the (1) fs to 500, 1000, rerun program. What happen? Why?
9. By change the (2) step size to 1/20, 1/40 rerun program. What happen? Why?
10. Submit a report and the soft copy of your codes.

Digital Communications

21

EEL-4515

Fig 3.2. Top sinewave signal is given as the input to the modulator. Next signal is the decoder
output. Th elast signal is the low pass filter. So it is faithful reproduction of the original message
signal.

3.4 Hardware Experiment


For the hardware experiment we will focus on the encoding as well as estimation process of the
Delta Modulation (DM).
The circuit for DM modulation is given in Figure 3.3. Which consists of an LM741 operate
amplifier, CD4013 dual D flip flop and CD4016 bilateral switch. The LM 741 is operated open
loop as a comparator between the input signal m(t) and the feed back signal mr(t) . The function of
the CD4013 is to hold the value of the quantized error signal constant (+ or Vcc) during the
sampling period. Both the flip-flop and the bilateral switch are enabled by same clock pulse.
Propagation delay in the flip-flop may be considered negligible in comparison with the pulse
width. A dc integrator is used in the feed back loop.

Procedure
Assemble the DM circuit as given in Figure 3.3.
Set the signal generator to generate a square wave with amplitude =10 volt (p-p) with 5V dc and
frequency=10kHz.

Digital Communications

22

EEL-4515

Note: Clock input should be within 0 to +Vdd. The CD 4013 IC will burn with negative voltage.
Generate a 200 Hz, 1.0 Vpp sine wave with 0.5 V dc offset with the other signal generator. Same
precaution applies here as written in the previous step.
Connect the output of the square wave generator to the clock input of the DM circuit. Connect the
sine wave to the message input of the DM circuit.
Check the waveforms at the output of the flip-flop and the sampler. Compare the output of the
integrator mr(t) with the input waveform m(t) by superimposing both signals. Plot all waveforms
and measure the step size. Explain your observations. Vary the following parameters and observe
the changes in the reconstructed signal mr(t). Record the waveforms for each case.
Vary the message frequency between 50 Hz and 1KHz.
Vary the message amplitude between 0 and 2Vpp.
Vary the sampling frequency between 400Hz and 100KHz.
Submit a report.

Figure 3.3: Delta Modulation circuit.

Digital Communications

23

EEL-4515

3.5 Questions
Delta modulation is special case of Differential PCM where each sample is represented by just 1 bit
explain.
(Hint: See the sections 6.3 and 6.4 of your text:
B. P. Lathi, Modern Digital and Analog Communication Systems 3rd edition, pages 267-271, Oxford
University Press, 1998)

Digital Communications

24

EEL-4515

LAB 4

FREQUENCY SHIFT KEYING


4.1 Objective
The objective of this lab is to introduce the concepts of Frequency Shift Keying (FSK) modulation
technique through simulation. Students apply the concepts of FSK to design a modem, which uses
this modulation scheme.

4.2 Theory
4.2.1 FSK: Modulation:
In Frequency Shift Keying (FSK), the instantaneous frequency of the carrier signal is switched
between two (or more) values in response to the digital code (e.g. PCM code).
In binary FSK, the binary digital information is modulated to two different frequencies, say f1 and
f2 =f1 +f.
Thus binary 0 can be expressed by a sinusoidal signal with frequency f1.
u1 =cos2 f1t
And, binary 1 can be expressed a sinusoidal signal with frequency f2.
u2=cos2 f2 t
where, f2 = f1 + f

Digital Communications

25

EEL-4515

1.5
Tb = 1

0.5

0.5

1.5

2.5

3.5

3.5

Digital signal
1.5

f2

f1

f2

f1

0.5

-0.5

-1.5

0.5

1.5

2.5

FSK modulated signal

Figure 4.1: Digital signal and its corresponding FSK modulated signal. Notice that binary 1 is
represented by a sinusoidal signal with frequency f1 and binary 0 by signal with frequency f2.
Let us assume that the FSK modulated signal is delayed in the transmission through the channel.
The channel also introduces random noise in the received signal. We may assume the random
noise to be Gausian White Noise.
Consequently the received signal is,
r(t) = cos(2 fit+) + GWN
; i=1, 2
where, = phase delay during transmission.
GWN = Gausian White Noise added to the signal during transmission.

4.2.2 Detection/Demodulation:
Demodulation of the binary FSK signal can be done by the non-coherent detection method as
shown in the Figure 4.2.

Digital Communications

26

EEL-4515

U1=cos2f1t
X
V1=sin2f1t

()dt

sample at t=T
r1c

r1s

X
Received signal
r(t)

()dt

Detector

Output decision

U2=cos2f2t
r2c

X
V2=sin2f2t

()dt
0

r2s

()dt
0

Figure 4.2: FSK detection/ demodulation process


The r1 and r2 is defined by the following equations
r1 = r12c + r12s
r2 = r22c + r22s

The detector decides the received signal by comparing r1 and r2. To be precise if r1> r2 then the
detector decides that the received signal is of frequency f1 (which corresponds to binary 0 at
input) and vice versa.

4.3 Simulation
We will use Matlab to do the simulation. We will use the system described in section 4.2 for this
simulation. In the simulation, a single bit (either logic 0 or 1) is modulated, channel
impairments are added to the modulated signal, and, finally the received signal is non-coherently
detected and verified whether detection decision is right or wrong.

Simulation Procedure:
1. Define,
Tb =1
f1=1000/Tb
f2=f1+1/Tb

Digital Communications

27

EEL-4515

phi=pi/4
N=5000

% delay during transmission.


% Number of samples from t= 0 to t=Tb.

2. Construct time array t from t=0 to t=Tb with 5000 elements.


3. Define,
u1 = cos2f1t
u2 = cos 2f2 t
v1 = sin 2f1 t
v2 = sin 2f2 t
4.Assume that u1 is transmitted. So received signal is given by
r(t) = cos(2f1t + )
After demodulation we will verify that u1 was transmitted (binary 0). This proves the validity of
decision making in detection process.
5. Calculate r1c(k), r2c(k) and r2s(k) as following;
N

r1c = r (k ).u1 (k )
K =1
N

r1s = r (k ).v1 (k )
K =1
N

r2 c = r (k ).u 2 (k )
K =1

r2 s = r (k ).v 2 (k )
K =1

6. Calculate
r1 = sqrt( r1c2 +r1s2)
r2 = sqrt( r2c2 +r2s2)
7. Compare r1 and r2. if r1> r2, output y=0. Otherwise, output y=1.
Since we transmitted the modulated signal u1 so we should get y=0.
8. Repeat 4 to 7 assuming u2 was transmitted.
9. Repeat 4 to 7 assuming u1 was transmitted but an additive gaussian white noise is added in
received signal. So,
Digital Communications

28

EEL-4515

r(t) = cos(2f1t +) +GWN(1, 1, 1)


You may use gwn function for gaussion noise.

4.4 FSK modem design


Frequency shift keying (FSK) modulation is introduced in this experiment. It is a commonly used
method for transmitting digital data over telephone lines. For FSK, a modulator- demodulator
(modem) is needed to translate digital 1s and 0s into their respective frequencies. For modems
operating at 1200 bps over commercial telephone channels, the transmit frequencies are 1200 and
2200 Hz.
In this experiment a modem with 1200 bps data rate with mark (correspond to binary 1) and
space (correspond to binary 0) frequencies of 1200 Hz and 2200 Hz will be designed.
In this experiment we will use XR-2206 monolithic function generator, and XR-2211 phaselocked loop ICs. General and preliminary descriptions for these ICs are given below. These
descriptions are taken from the respective data sheets.
XR-2206
The XR-2206 is a monolithic function generator integrated circuit capable of producing high
quality sine, square, triangle, ramp, and pulse waveforms of high-stability and accuracy. The
output waveforms can be both amplitude and frequency modulated by an external voltage.
Frequency of operation can be selected externally over a range of 0.01Hz to more than 1MHz.
The circuit is ideally suited for communications, instrumentation, and function generator
applications requiring sinusoidal tone, AM, FM, or FSK generation. It has a typical drift
specification of 20ppm/C. The oscillator frequency can be linearly swept over a 2000:1 frequency
range with an external control voltage, while maintaining low distortion.
XR-2211
The XR-2211 is a monolithic phase-locked loop (PLL) system especially designed for data
communications applications. It is particularly suited for FSK modem applications. It operates
over a wide supply voltage range of 4.5 to 20V and a wide frequency range of 0.01Hz to 300kHz.
It can accommodate analog signals between 10mV and 3V, and can interface with conventional
DTL, TTL, and ECL logic families.
The circuit consists of a basic PLL for tracking an input signal within the pass band, a quadrature
phase detector, which provides carrier detection, and an FSK voltage comparator, which provides
FSK demodulation. External components are used to independently set center frequency,
bandwidth, and output delay. An internal voltage reference proportional to the power supply is
provided at an output pin.

Digital Communications

29

EEL-4515

For further detail, students are strongly encouraged to see the data sheets of these ICs in the
following web pages before they start designing the modem.
http://www.exar.com/products/xr2211.pdf
http://www.exar.com/products/xr2206.pdf

4.4.1 Modulator
Frequency of oscillation, f0 : The XR-2206 can be operated with two separate timing resistors, R1
and R2, connected to pins 7 and 8 respectively. When pin 9 is open circuited or connected to logic
1 only R1 is active. Similarly, when the voltage level at pin 9 is logic 0 only R2 is activated.
Therefore, the output frequency can be generated between two frequency f1 and f2, and
f1=/R1C0 and f2=1/R2C0, let C0=0.022 F
for a mark frequency, f1 of 1200 Hz
R1=1/(1200*0.022E-6)=37.8 Select R1=39 K
For a space frequency, f2, of 2200 Hz
R2=1/(2200*0.022E-6)=20.7 Select R2=20 K
Output amplitude, for a sinewave output, is approximately 60mv per per K of R3. Since the XR2211 requires an input smaller than 3Vrms a value of 50 K for R3 will be chosen (experimentally,
a value of 25 K give the desired results).
Output dc level. The dc levels at in pin 2 are approximately the same as the DC bias at pin 3. It is
set for Vc/2.
In applications where minimal distortion is unnecessary, pins 15 and 16 may be left open and a
200 resistor is then connected between pins 13 and 14.

4.4.2 Demodulator
The tracking range(+/- f) is the range of frequencies over which the phase-locked loop can retain
locked with a swept input signal. This range is determined by the formula
f=(R0/R4)*f0
f should be made equal to, or slightly less than, the difference between the mark and space
frequencies.
The capture range (+/-fc) is the range of frequencies over which the phase-locked loop can acquire
lock. It is always less than the tracking range. The capture range is limited by C2, which in
conjunction with R4, forms the loop filter time constant. In most applications, fc=(80%-90%)f.

Digital Communications

30

EEL-4515

The loop damping factor () determines the amount of over shoot, undershoot, or ringing present
in the phase locked loop response to a step change in frequency. It is determined with:
=(1/4)*sqrt(C1/C2). For most modem applications =0.5.

4.4.3 Calculations:
The XR-2211 can be used for any FSK decoding application by the choice of five key circuit
components R0, R4, C1, C2, and CF. For a given set of FSK mark and space frequencies, f1 and f2,
these key circuit components parameters should be calculated as follows.
Calculate the PLL center frequency, f0:
f0=(f1+f2)/2=(1200+2200)/2=1700Hz
Calculate R0 from the VCOs center frequency design equation:
let C1=0.027 F
f0=1/R0C1
R0=(1/C1)*f0=1/(1/0.027E-6)*1700=21.8 Select, R0=22 K
Calculate R4 to give a f equal to the mark-space deviation:
R4 = R0*f0/(f1-f2) = 22000*(1700/(2200-1200))=39 K
Calculate C2 to set loop damping. From the design equation and the recommended of :
C2=C1/4=0.027E-6/4=6.75 nF select C2=6.8nF
Calculate data filter capacitance, CF, from the data filter time constant equation:
TF = RFCF where TF = 0.3/ baud rate, and RF=100K
CF=0.3/(baud rate)RF=0.3/(1200*100E3)=2.5nF select CF=2.4nF
4.5 Experimental Procedure
Build the modem according to the Figure 4.3 given.
Observe and draw the input, FSK, and output waveforms.
Explain the operation and performance of the modem. Was it necessary to make any adjustments
for frequency tuning?

4.6 Questions
Calculate R0, R4, C1, C2, and CF for a 75 baud FSK demodulator with mark/space frequencies of
1110/1170 Hz.
Hint: Use the same procedure as shown in section 4.4.3.

Digital Communications

31

EEL-4515

FSK output
GND
10uF

5.1K
R3
5.1K

16

15

14

XR-2206

200

13

+12V
1uF
C0

R1

12

11

10

GND
1uF

R2
f2

Modulator

FSK in
12V
1KHz

V+

0.1uF

14

13

12

11
10

XR-2211

5
51K

Data Out

Input

f1

39nF
12K
51K
3.9nF
0.1uF

1.2M

255K
1nF

Demodulator
Figure 4.3: Circuit diagrams for FSK modem. Modulator and Demodulator

Digital Communications

32

EEL-4515

LAB 5

BINARY PHASE SHIFT KEYING


5.1 Objective
Understand the principles of Binary Phase Shift Keying (BPSK) digital modulation scheme, its
error performance through simulation and hardware implementation of BPSK modulation.

5.2 Theory
PSK was developed during the early days in the deep-space program; PSK is now widely used in
both military and commercial communications systems. The general analytic expression for PSK
is

si (t ) =

2E
cos[2f c t + i (t )]
Tb

where, 0 t Tb , i = 1,....., M . Note that fc is the frequency of the carrier, Tb is the symbol
duration, E is symbol energy, and i(t) has M discrete values. Typically we choose
i (t ) =

2i
M

for i = 1,....., M

For binary PSK (BPSK) M is 2. In BPSK modulation the data shifts the phase of the waveform
si(t) to one of the two states, either zero or . The signals waveform can be represented in terms of
a basis function 1(t), as follows.
s1 (t ) = Eb 1 (t )
s 2 (t ) = Eb 1 (t )

where, 1 (t ) =

2
cos(2f c t )
Tb

The signal waveform can also be represented as vectors or phasors in a polar plot; the vector
length corresponds the signal amplitude, and the vector direction corresponds to the signal
direction.
In the BPSK case, a binary one and zero can be represented by the two vectors S1 and S2
respectively as shown in Figure 5.1.

Digital Communications

33

EEL-4515

M=2

s2

s1

1(t)

Figure 5.1: BPSK vectors


The vectors shown in Figure 5.1 are collinear and of opposing direction. Signal sets that can be
depicted with such opposing vectors are called antipodal signal sets.
There are several ways to demodulate or detect such BPSK symbols. The receiver may perform a
differentially coherent detection process, in which the phase of each bit is compared to the phase
of the preceding bit. Better performance can be obtained with fully coherent PSK, but that requires
an absolute phase reference at each end, and no phase variations in the propagation path.
The received signal from the channel is given by
r(t)=si(t)+n(t)
where, si is either s1 or s2 , and n(t) is the noise signal.
The noise analysis of communication system is customarily based on an idealized form of noise
called Additive Gaussian White Noise (AWGN) signal n(t). The probability distribution of n(t) is
given by
P (n) =

n2
exp
2
2
2

The noise n(t) contains all frequency component from - to +. The power spectral density of
such a noise is shown in Figure 5.2. N0 is the single-sided noise power spectral density (Watts /
Hertz). N = Noise Power over the bandwidth B.
Noise Power Spectral Density
Watts/Hz

N=N0 B
N

Frequency (Hz)

Figure 5.2: Noise Spectral Density

Digital Communications

34

EEL-4515

Figure 5.3: BPSK receiver


In Figure 5.3, we show the block diagram of a BPSK receiver. If there is no noise in the channel
i.e. n(t) = 0, then for r (t ) = s1 (t ) , x1 = + Eb , and for r (t ) = s 2 (t ) , x1 = Eb . The corresponding
signal constellation diagram is shown Fig 4.
Decision
Boundary

- Eb

1/2

1/2

- Eb

Figure 5.4: Constellation diagram

Figure 5.5: Probability distribution of the received BPSK signal.

Digital Communications

35

EEL-4515

The probability distribution of the received signal is shown Figure 5.5. It has been assumed that
the BPSK signals are transmitted through an Additive White Gaussian Noise (AWGN). The
f(x1/0) curve is the probability distribution of the signal point if only s1 is transmitted. The f(x1/1)
curve is the probability distribution of the signal point if only s2 is transmitted.
The decision boundary of a BPSK receiver affected by AWGN is the point X1=0 (see Figure 5.5).
If the received signal lies on the left of the decision boundary, we will decide that a symbol s1 was
transmitted and vice versa.
For the binary decision making depicted in Figure 5.5, there are two ways an error can occur. An
error will occur when s1 was transmitted, and channel noise results in the received output signal
r(t) being less then the decision boundary. The probability of such occurrence can found
integrating the shaded in the Figure 5.6.

Figure 5.6:Calculating the probability of error


The probability of error given that a binary zero is transmitted and binary one is detected can
be written by the following mathematical expression.
x + E 2

1
b
dx1
P (1 | 0) = f ( x1 | 0)dx1 =
exp 1
2
2

0
0

Let, z =

(x +
1

Eb

Then
P (1 | 0) =

Eb /

z2
exp dz =
2
2

Eb

=
(
)
f
z
dz
Q

Eb /

For P(1|0) = P(0|1) and P(1)=P(0)=0.5. The probability of an error in a binary digit is
Digital Communications

36

EEL-4515

Eb

Pe = P (1 | 0) P (0) + P (0 | 1) P (1) = P (1 | 0)[P (0) + P (1)] = P (1 | 0) = Q


The standard deviation of the probability distribution of the coordinate x1 on the signal space
diagram is

N0
2

For a given signal-to-noise ratio SNR

Eb
= 10
N0

Eb / N 0 ( dB )
10

= 10

SNR
10

5.3 Simulation procedure


In the simulation of this lab, we will generate number of BPSK signal and will be added to
AWGN and will be detected. The probability of error will be calculated from number of wrong
detection. The simulation procedure is given below.
1. Construct an array with number of simulation for different SNR. Name it 'NN'.
NN=[1000, 2000, 3000, 5000, 8000, 20000, 20000, 40000,100000,500000,900000];
2. Change signal to noise ratio (SRN) from 0 to 10 dB with 1 interval. Name it dB.
3. Generate random binary stream (1,0) with length N=NN(dB+1). Use Matlab function
rand(1,N). Name it 'a'.
4. Modulate binary stream 'a' to Antipodal signal stream (1, -1). Name it 's'. the code segment
as below.
s=a*2-1;

% modulate to Antipodal (1, -1)

5. According to

Eb
= 10
N0

Eb / N 0 ( dB )
10

= 10

SNR
10

and =

N0
2

for Eb=1, we get

= 1
2 * 10

SNR

Digital Communications

10

37

EEL-4515

Use randn(1,N)*, generate normally distributed with mean 0 and variance white noise.
Name it 'awgn'
6. Add signal 's' and noise 'awgn' together get received signal. Name it 'r'.
7. Detect 'r' larger than zero with 'a' equal zero. Count the number of such case (error case).
Name it 'ErrorNo'
8. Divide ErrorNo with binary stream length N, get simulated error rate. Name it 'ErrorRS'.
9. Plot 'ErrorRS' vs SNR(dB) with 'ErrorRS' in log scale use matlab 'semilogy' function.
10. From
Eb
Pe = P (1 | 0) P (0) + P (0 | 1) P (1) = P (1 | 0)[P (0) + P (1)] = P (1 | 0) = Q

1
and =
, we get with Eb=1, the probability of error
SNR
/
10
2 10

Pe = Q 2 10 SNR / 10

Use matlab function 'erfc' to caculate the Analytical error rate for SNR from 0 to 10 dB with
interval of 0.1. Name it 'ErrorRA'.
11. Plot 'ErrorRA' vs SRN(dB) with 'ErrorRA' in log scale use Matlab 'semilogy' function.
12. Submit a report with
Plots and graphs you obtained,
Calculations, and
Matlab codes.

5.4 Hardware Experiment


In the hardware experiment we will build a BPSK modulator. We will generate binary data stream
and convert it to a BPSK modulated waveform.
Build the BPSK modulation circuit shown in Figure 5.7.

Digital Communications

38

EEL-4515

Carrier

351

PSK
Modulated
Output

351
-

2N4392
+

1K

0.0022uF

R=11K

R
R
Data
Source

Figure 5.7: BPSK modulator


The 351 in the Figure 5.7 is a wideband operational amplifier. The pin-out for an LF351N is given
below.

Input (-)

LF351N

V+ (12V)
Output

Input (+ )
V- (-12V)

The 2N4392 in Figure 5.7 is a NMOS transistor. The pin-out is given below. Note that this is the
bottom view of the transistor.

Gate

Drain

Source

The data source in Figure 5.7 generates a bit-stream. In this case the bit-stream is a square wave
with around 16KHz. Apply a sinewave (5V p-p) as a carrier in your modulator with a frequency of
7-8 times the frequency of the data-stream. A carrier with 120KHz will work in this case.
Plot the carrier, data-stream and BPSK modulated signal.

Digital Communications

39

EEL-4515

5.5 Questions
How BPSK modulated signal can be detected? Show the demodulation process for BPSK symbols
through block diagrams for the case of
Coherent detection, and
Non-coherent detection.

Digital Communications

40

EEL-4515

LAB 6

INTRODUCTION TO SYSTEM VIEW TOOL FOR


COMMUNICATION SIMULATION
6.1 Objective
In this lab we will be familiar with a new tool, which is found to be very useful in analyzing
communication systems. Learning the tool might be useful for the students, who wish to be in the
communication area in future.

6.2 Welcome to Systemview:


Systemview is a comprehensive dynamic systems analysis environment for the design and
simulation of engineering and scientific systems.
Systemview allows the user to build circuits pertaining to analog or digital signal processing, or to
design filters, control systems, communication systems etc.

6.3 Salient features:

No codes or scripts to learn.


User-friendly.
Visual interface-drag and drop tokens etc.,
Convenient alternative to actually implementing the circuit in hardware.

6.4 Installation procedure:

Insert Systemview CD into drive and click Setup.exe


Follow the instructions and re-boot after install.
The CD is a Student Edition and is a limited-save yet fully functional version of the
professional edition, only systems having less than or equal to 10 tokens can be saved to
the hard disk.
Minimum requirements: Microsoft Windows 9x/2000/NT
Pentium 166 MHz or higher
64MB-128MB SDRAM
100MB minimum hard disk space.

Digital Communications

41

EEL-4515

6.5 Overview:

Systemview provides the means for building a visually oriented, dynamic system
simulation model.
Systemview uses symbolic tokens to represent processes, and a time base to represent
system sampling characteristics.
Complete systems can be designed by selecting tokens from the various token libraries and
connecting them together in the design area.
The user can control parameters like frequency, time, sampling rate etc.

6.6 User Interface:

To start Systemview simply click on the icon on the desktop, or in the Start bar.
The system window appears when Systemview is started.
The system window consists of a menu bar, a toolbar, horizontal and vertical scroll bars,
the design area, a message area (bottom left hand corner), and the token libraries to the left
of the screen. It is shown below.

Digital Communications

42

EEL-4515

Systemview also contains an analysis window, which can be invoked by clicking the
appropriate icon. It is possible to switch between the design window and analysis window.
The analysis window is used to view the input and output waveforms. It is shown below.

Digital Communications

43

EEL-4515

6.7. Building circuits in Systemview:


A) Inputs:

The components for building circuits in Systemview are called tokens and can be selected
from the token reservoir.
For any circuit, it is essential to have an input. Different types of inputs can be selected
using the source token.
The source token can be dragged-dropped into the design area.
Now that a source token has been employed, one can define the type of input by simply
double-clicking the source token.
The inputs discussed here are sinusoid, pulse train and PN-sequence.

Digital Communications

44

EEL-4515

A sinusoid input can be found under the Periodic signals group.


Clicking the sinusoid token will identify the source token as a sinusoid input.
The parameters of the sinusoid can be defined by clicking the Parameters button.
It is possible to specify the amplitude, frequency and phase of the sinusoid.
The pulse train input can also be found under the Periodic signals group.
Clicking the pulse train icon makes the source a pulse-train input.
The parameters that can be specified for the pulse-train are amplitude, frequency, phase,
offset, and pulse-width. It is also possible specify a square wave pulse train by clicking the
square wave button.
The PN-sequence input can be found under the group Noise/PN and the parameters that
can be specified for this input are amplitude, symbol rate, number of levels, offset, and
phase.

Digital Communications

45

EEL-4515

B) Outputs

The output of any circuit, in Systemview, is specified by the means of a sink token.
Various types of sinks can be specified by selecting the sink token.
The sinks discussed here are the Systemview sink and the Analysis sink.
To specify the sink, drag-drop the sink token onto the design area and then double-click it.
The Systemview sink can be found under the Graphic group.
Once the Systemview sink button is selected, a window is displayed in the design area,
which will display the output waveform when the input is applied to the circuit.
The Analysis sink can be found under the Analysis group, and does not display the output
waveform in the design area. (Serves to reduce clutter in the design area).
In order to view the output of the analysis sink, it is necessary to switch to the analysis
window. See the following Figure.

Sinks have no parameters.

Digital Communications

46

EEL-4515

C) Intermediate components:

The components discussed covered under this heading are as follows:


1. Multiplier token
2. Adder token.
3. Delay token.
4. Exclusive-OR token.

The multiplier token can be selected from the token reservoir. It is used to multiply two
signals in the time domain, and has no parameters that need be specified.
The adder token is similar to the multiplier token in all respects except that it adds two
signals instead of multiplying them.
The Delay token can be specified as follows:

i. Select an operator token into the design area, and double-click it.
ii. Click on the delays group and select the delay token.
iii. Specify the parameters for the delay token.

Digital Communications

47

EEL-4515

To specify an Exclusive-OR token (modulo-2 adder) click the optional libraries button,
and drag a logic token onto the design area.
Select the Ex-OR gate token under the Gates/Buffers group.
Specify the threshold and the true-false output voltage parameters.

D) Connecting and disconnecting tokens:

To connect two components (two tokens), click the connection button.


Click the source token, then the target token and the two tokens are connected
automatically.

Digital Communications

48

EEL-4515

To disconnect two or more tokens click the disconnect button and then click the source
and target tokens. The connection between the two tokens will disappear.

E) Running the circuit, viewing the outputs and saving the system as a file:

First click the system time icon, and set the start time=0 and number of samples=128.
Next close the system time window and click the run button.
If Systemview sinks are present the output waveforms are visible in their respective
sink windows.
If Analysis sinks have been specified go to the Analysis window, and view the
waveforms there.

Digital Communications

49

EEL-4515

Return to the Systems window by clicking the appropriate button.


To save the system as a file, click the File menu and then click Save.
Save the system with a .svu extension.

Note: Only those tokens required for the lab assignments have been discussed under the
Building circuits section. For explanation regarding other tokens please refer the
help-file that comes with the software

Digital Communications

50

EEL-4515

6.7 Lab Assignments:


A) Amplitude modulation:

m(t)

m(t)*cos(wt)

Cos(wt) (carrier)
Total token count: 6
1.
2.
3.
4.

1 Source token: Sinusoid (sine wave, amplitude=10V, freq.= 1Hz)


1 Multiplier token.
1 Source token: Sinusoid (cosine wave, amplitude=1V, freq.=10Hz)
3 Systemview sink tokens (graphic) showing the sine wave, cosine wave and AM-DSBSC
wave.

B) Amplitude modulation with carrier:


Total token count: 10
1. Create the circuit shown in part A. (6 tokens)
2. Add to the output m(t)cos(wt), another carrier of amplitude A volts (Use A=20V) and
frequency 10Hz. (4 tokens in all, 1 adder, 1 source token and 2 Systemview sinks to show
the output of the adder as well as the 20V carrier signal).
3. Thus, the signal is now: [A+m(t)]cos(wt)
4. Check the signals in the analysis window.

C) Scrambler-Descrambler:
Total token count: 8
Create the scrambler-descrambler circuit shown below:

Digital Communications

51

EEL-4515

1.
2.
3.
4.
5.
6.
7.

PN sequence (input), amplitude=1V number of levels=2.


Systemview sink showing PN sequence.
EX-OR gate (modulo-2 adder) at scrambler. (True/False output=+/- 1 V, threshold=0)
1 delay token-Delay of 2 (Use time delay) for scrambler.
Systemview sink showing scrambled output.
EX-OR gate and delay of 2 for de-scrambler (2 tokens).
Systemview sink showing descrambled output.

For the assignments:

Create 3 different files.

Digital Communications

52

EEL-4515