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About me
MASc (2012) and BASc (2009) from UBC
2 years of work experience at different
companies Bcom, PMC, and Intrinsyc.
Area of interest system validation and test
+ formal methods for debug + physical
design.
I am new in embedded software design
A firmware guy but mostly on the hardware
side.
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Leveraging Linux: Code Coverage for PostSilicon Validation --- Mehdi Karimibiuki
Outline
Motivation
Why post-silicon validation?
Why post-silicon coverage?
Outline
Motivation
Why post-silicon validation?
Why post-silicon coverage?
Miron Abramovici, Paul Bradley, Kumar Dwarakanath, Peter Levin, Gerard Memmi, and Dave Miller.
2006. A reconfigurable design-for-debug infrastructure for SoCs. In Proceedings of the 43rd annual
Design Automation Conference (DAC '06). ACM, New York, NY, USA, 7-12.
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Disadvantages:
-- Difficult to model complex electrical behaviors and offchip interactions requires very good understanding of
the behavior of the chip for different functional modes
(some tools from Cadence/Synopsys/AtopTech)
3 million gates takes about 8 hours to simulate timing.
--
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Slow
10
Simulation is SLOW.
Consider Linux boot that takes 1 minute on actual
hardwareit takes 1900 years in simulation!
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11
responses
# of spins
12
Outline
Motivation
Why post-silicon validation?
Why post-silicon coverage?
13
14
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15
Did I do enough?????
(And if not, am I making progress? What areas
need more verification? )
How can I get a feeling about the effectiveness
of my validation schemeon the chip
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17
Outline
Motivation
Why post-silicon validation needed?
Why post-silicon coverage?
18
IBM POWER7
Adir, A.; Nahir, A.; Shurek, G.; Ziv, A.; Meissner, C.; Schumann, J.; , "Leveraging presilicon verification resources for the post-silicon validation of the IBM POWER7
processor," Design Automation Conference (DAC), 2011 48th ACM/EDAC/IEEE , vol.,
no., pp.569-574, 5-9 June 2011
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Outline
Motivation
Why post-silicon validation needed?
Why post-silicon coverage?
20
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Outline
Motivation
Why post-silicon validation needed?
Why post-silicon coverage?
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25
26
Outline
Motivation
Why post-silicon validation needed?
Why post-silicon coverage?
27
Case Study
We pick an industrial-size SoC that is
synthesizable to FPGA.
Instrument code coverage in 9 blocks
Measure post-silicon coverage
Also compare with pre-silicon simulation
results
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SoC Platform
Built from Aeroflex Gaisler open-source IP
Features:
Leon3 processor
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IEEE-754 FPU
SPARC V8 reference MMU
Multiway D- and I-caches
Its a notebook-on-chip
DDR2 SDRAM controller/interface
DVI Display Controller
10/100/1000 Ethernet MAC
PS2 Keyboard and Mouse
Compact Flash Interface
Can be fabricated to 0.18um ASIC technology.
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LOGAN
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JTAG
GRMON
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31
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96.10%
88.70%
92.70%
94.40%
90.20%
40.30%
92.90%
89.20%
86.00%
0.00%
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10.00% 20.00% 30.00% 40.00% 50.00% 60.00% 70.00% 80.00% 90.00% 100.00%
33
iu3
mmu
57.60%
svgactrl
mmutlb
88.60%
90.20%
uart
mul32
41.20%
40.30%
90.50%
92.90%
92.80%
89.20%
mmutw
div32
90.00%
86.00%
i2cmst
0.00%
92.70%
92.30%
94.40%
10.00% 20.00% 30.00% 40.00% 50.00% 60.00% 70.00% 80.00% 90.00% 100.00%
pre-silicon stmt
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34
iu3
85.90%
mmu
90.50%
svgactrl
mmutlb
81.00%
72.50%
uart
mul32
35.70%
mmutw
94.70%
73.30%
div32
i2cmst
0.00%
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81.80%
10.00% 20.00% 30.00% 40.00% 50.00% 60.00% 70.00% 80.00% 90.00% 100.00%
Leveraging Linux: Code Coverage for
Post-Silicon Validation --- Mehdi
Karimibiuki
35
iu3
95.00%
63.20%
mmu
85.90%
32.20%
svgactrl
90.50%
74.60%
mmutlb
81.00%
68.30%
uart
72.50%
39.10%
mul32
35.70%
78.90%
mmutw
80.00%
div32
73.30%
86.40%
i2cmst
0.00%
81.80%
10.00%
20.00%
30.00%
40.00%
pre-silicon branch
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94.70%
50.00%
60.00%
70.00%
80.00%
90.00%
100.00%
post-silicon branch
36
Post-Silicon
95.00%
96.10%
iu3
85.90%
88.70%
mmu
90.50%
92.70%
svgactrl
81.00%
mmutlb
94.40%
72.50%
uart
90.20%
35.70%
40.30%
mul32
94.70%
92.90%
mmutw
73.30%
div32
89.20%
81.80%
86.00%
i2cmst
0.00%
10.00%
20.00%
30.00%
40.00%
50.00%
post-silicon branch
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60.00%
70.00%
80.00%
90.00%
100.00%
post-silicon stmt
37
Outline
Motivation
Why post-silicon validation needed?
Why post-silicon coverage?
38
Conclusions
Demonstrated a practical and an effective
technique to measure coverage for postsilicon validation effectiveness.
Measured and compared pre- and post-silicon
code coverage on a realistic SoC.
Results show Linux boot is a very good test to
run in post-silicon, but the results also show
that Linux boot is not a sufficient test to claim
our chip is working completely fine.
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Conference Paper
M. Karimibiuki, K. Balston, A.J. Hu, and A. Ivanov. "Postsilicon code coverage evaluation with reduced area
overhead for functional verification of SoC". In IEEE
International High Level Design Validation and Test
Workshop (HLDVT), pages 92 97, Nov. 2011.
Journal Paper
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Future Work
Explore monitoring for other code coverage metrics
Expression and condition
41
End.
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Outline
Motivation
Why post-silicon validation needed?
Why post-silicon coverage?
44
45
140.0%
120.0%
100.0%
80.0%
65.0%
60.0%
60.0%
61.4%
38.4%
40.0%
31.0%
21.9%
21.7%
20.0%
9.6%
0.0%
i2cmst
div32
mmutw
mul32
uart
mmutlb svgactrl
mmu
iu3
overhead
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22.0%
20.0%
18.6%
18.0%
16.0%
14.0%
12.9%
12.0%
10.0%
8.0%
6.0%
4.0%
6.3%
5.6%
4.5%
3.5%
4.2%
1.2%
2.0%
0.0%
i2cmst
div32
mmutw
mul32
uart
mmutlb svgactrl
mmu
iu3
overhead
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Outline
Motivation
Why post-silicon validation needed?
Why post-silicon coverage?
48
Agrawals method
Code coverage is a classic concept in software
testing
We use a classic technique devised by Agrawal for
control flow graphs. (Reference: Hiralal Agrawal. Dominators, super
49
Agrawals method
begin
module example
4
end
begin
4
end
Leveraging Linux: Code Coverage for
Validation --- Mehdi
CFG Post-SiliconKarimibiuki
Pre-dominator tree
51
begin
3
1
4
end
Post-dominator tree
CFG
Leveraging Linux: Code Coverage for
Post-Silicon Validation --- Mehdi
Karimibiuki
52
module example
always @ (posedge
clk)
begin
if(s1) then
s2;
else
s3;
endif;
s4;
endmodule;
begin
3
2
4
end
CFG
Post-dominator
tree
Pre-dominator
tree
1, 4
Superblock dominator
Basic block dominator
leaves
graph
Leveraging
Code Coverage
for
SoLinux:
far...50%
overhead
graph
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module example
always @ (posedge
clk)
begin
if(s1) then
s2;
else
s3;
endif;
s4;
endmodule;
begin
4
end
CFG
1, 4
Superblock dominator
graph
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Outline
Motivation
Why post-silicon validation needed?
Why post-silicon coverage?
55
140.00%
120.00%
100.00%
80.00%
65.00%
60.00%
60.00%
52.50%
45.60%
40.00%
20.00%
63.00%
61.40%
31.00%
21.70%
20.30%
45.50%
38.40%
32.90%
21.90%
21.40%
17.10%
9.60%
6.70%
0.00%
i2cmst
div32
mmutw
mul32
overhead
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uart
mmutlb
svgactrl
mmu
iu3
reduced overhead
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18.60%
15.80%
15.00%
12.90%
12.10%
10.00%
5.00%
4.10%
3.50%
6.30%6.30%
5.60%
4.50%
4.50%
4.20%
4.00%
3.30%
1.20%1.20%
0.00%
i2cmst
div32
mmutw
mul32
overhead
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uart
mmutlb
svgactrl
mmu
iu3
reduced overhead
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Agrawals Algorithm
(POPL 1994)
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tree
All nodes are minimally connected
N nodes and n-1 edges
No more than one edge to a node
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Linearly ordered
a linearly ordered or totally ordered group is
an ordered group G such that the order
relation "" is total. This means that the
following statements hold for all a, b, c G:
if a b and b a then a = b (antisymmetry)
if a b and b c then a c (transitivity)
a b or b a (totality)
the order relation is translation invariant: if a
b then a + c b + c and c + a c + b.
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