02-3-Sequential Logic Synthesis With VHDL

19-Feb-11
Outline
Sequential Logic Synthesis

with VHDL
Review of sequential statements

Latches and Flipflop (FF)
Registers
Counters
State Machines
Refs: Chapters 6 8 of the book of Pedroni
Sequential statements
These statements can appear inside a process
description :
variable assignments
if-then-else
case
loop
infinite loop
while loop
for loop
assertion and report
signal assignments
function and procedure calls
Processes
A process is a region of VHDL code that
executes SEQUENTIALLY
Exists inside the architecture
Multiple processes execute with each
other concurrently
3
Process Statement
[process_label:]
PROCESS [(signal_name {,signal_name})
]
[VARIABLE declarations]
BEGIN
[WAIT statement]
[Simple Signal Assignment
Statements]
[Variable Assignment Statements]
[IF Statements]
[CASE Statements]
[LOOP Statements]
END PROCESS [process_label];
IF statement
sensitivity list : determines

when process becomes
active. Any signal in list
thats value changes triggers
process.
Variables : may or
may NOT represent
physical wires in a
circuit.
here there be dragons!

Venture carefully. Check
results of synthesis.
IF expression THEN
statement;
{statement;}
ELSIF expression
THEN
statement;
{statement;}
ELSE
statement;
{statement;}
END IF;
-- 2to1 multiplexer example

IF Sel = 0 THEN
f <= x1;
ELSE
f <= x2;
END IF;
19-Feb-11
LOOP Statements
CASE Statement
CASE expression IS
-- example 2to1mux
WHEN constant_value =>
CASE Sel IS
statement;
WHEN 0 =>
f <= x1;
{statement;}
WHEN OTHERS =>
WHEN constant_value => f <= x2;
END CASE;
statement;
{statement;}
WHEN OTHERS =>
statement;
{statement;}
END CASE;
[loop_label:]
FOR variable_name IN range LOOP
statement;
{statement;}
END LOOP [loop_label];
Describing Combinational Logic

using a PROCESS Statement
PROCESS( Sel, x1, x2 )
BEGIN
IF Sel = 0 THEN
f <= x1;
ELSE
f <= x2;
END IF;
END PROCESS;
All inputs to combinational

logic appear in sensitivity list.
All outputs from

combinational logic assigned
a value on EVERY activation
(i.e., for any combination of
inputs).
[loop_label:]
WHILE boolean_expression LOOP
statement;
{statement;}
END LOOP [loop_label];
Statement Ordering
Statements are evaluated in order they
appear within process, but
SIGNAL data objects are not assigned values
until the end of the process. Only last
statement that assigns a value to a given
signal updates that signal.
If f <= x1; were moved
Example:
Using a VARIABLE in a PROCESS

VARIABLE does not represent wires -- more flexible.
(Unlike SIGNAL values) VARIABLE values are updated
immediately before evaluating the next statement.
-- example : count bits, INCORRECT version.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY numbits IS
PORT( X : IN STD_LOGIC_VECTOR(1 TO 3);
Count : BUFFER INTEGER RANGE 0 TO 3 );
END numbits;
ARCHITECTURE Behavior OF numbits IS
BEGIN
PROCESS(X) -- count the number of bits in X with value 1
BEGIN
Count <= 0;
FOR i IN 1 to 3 LOOP
IF X(i) = 1 THEN
Count <= Count + 1;
END IF;
END LOOP;
END PROCESS;
END Behavior;
BAD!
11
after IF statement, then

f would always be equal to
x1.
PROCESS(Sel, x1, x2)

BEGIN
f <= x1;
IF Sel = 1 THEN
f <= x2;
END IF;
END PROCESS;
10
Using a VARIABLE in a PROCESS

Correct version: use Tmp VARIABLE to
accumulate number of bits set.
-- example : count bits, GOOD version.
LIBRARY ieee;
ENTITY numbits IS
PORT( X : IN STD_LOGIC_VECTOR(1 TO 3);
Count : BUFFER INTEGER RANGE 0 TO 3 );
END numbits;
ARCHITECTURE Behavior OF numbits IS
BEGIN
PROCESS(X) -- count the number of bits in X with
value 1
VARIABLE Tmp : INTEGER;
Note: VARIABLE
BEGIN
Tmp := 0;
FOR i IN 1 to 3 LOOP
IF X(i) = 1 THEN
Tmp := Tmp + 1;
END IF;
END LOOP;
Count <= Tmp;
END PROCESS;
END Behavior;
assignment operator is :=
12
19-Feb-11
Introduction
Digital Logic
Sequential Logic Circuit
(1) Combinational Logic Circuit, (2) Sequential Logic Circuit
Combinational Logic Circuit
Y=f(X)
Latches, Flip-flops
RAM, etc.
X: the finite set of input symbols

Y: the finite set of output symbols
f: a Boolean function for the output

13
Multivibrators
14
Latches
1.Bistable Multivibrator: latches and flip-flops
The S-R (Set-Reset) Latch
Has two stable states
A type of bistable multivibrator

Store one bit
2.Monostable Multivibrator: one-shot

Has one stable state
3.Astable Multivibrator: clock

Has no stable state
Q : 1 or 0
Latch /
flip-flop Q
Oneshot
Clock
Two versions of SET-RESET (S-R) latches.

15
16
Input Output
Comments
S R Q Q
0 0 1 1 Not allowed
Set
0 1 1 0
Reset
1 0 0 1
1 1 Q Q No change
The 74xx279 quad S-R latch.

17
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19-Feb-11
The SR Latch
More on SR Latches
SR Latch
Basic Storage
Element
S
0
0
1
1
Q
Q
NAND-based SR Latch
R Q(t+1)
0 Q(t)
1
0
0
1
1
??
Pair of inverters provides stable storage.

To enable stored value to be changed, use crosscoupled NOR gates.
equivalent to inverter pair when both inputs are low
SR latch is key building block for flip flops.
when S=1, R=0 latch is set

when S=0, R=1 latch is reset
when S=0, R=0 latch retains value
when S=1, R=1 latch state is undefined
S Q
R Q
R
0
1
0
1
q <= p;
qbar <= pbar;
end sr_df;
Behavioral Implementation
Q
Q
0
1
1
Qbar
Qbar
1
0
1
entity sr_bhv is
port( s, r in bit;
q, qbar out bit);
end sr_bhv;
State
Hold
Reset
Set
Illegal
S
0
0
1
1
architecture sr_bhv of sr_bhv is

begin
flipflop : process (s,r)
variable test bit;
begin
test := s OR r;
if (test = '1') then
q <= s;
qbar <= r;
end if;
end process flipflop;
R
0
1
0
1
Q
Q
0
1
1
Qbar
Qbar
1
0
1
State
Hold
Reset
Set
Illegal
test = 0
Q
test = 1
end sr_bhv;
22
Implementing D Flip Flops
D Latch
Alternative Implementation
D Q
C Q
D Q
C
Q
S Q
C
R Q
Q
C
Q
Q
The D latch stores the value on the D input when the enable
input is asserted.
no forbidden input combinations
but input should be stable when the control input drops
if not, outputs may become metastable
Alternative implementation uses transmission gates.

TGs enable either input or feedback path
in CMOS, this uses 10 transistors vs. 18
TG
TG
20
Example: SR Latch
D Latch
inputs are active high

forbidden input condition is C=S=R=1
change S, R inputs when C=0
19
21
S Q
C
R Q
SR latch with control input changes state only when

control input is high.
architecture sr_df of sr_df is

signal p, pbar bit;
begin
p <= not(s) nand pbar after 1 ns;
pbar <= not(r) nand p after 2 ns;
inputs are active low (negative logic inputs)

when both inputs are low, both outputs high
when inputs rise together, outputs can become metastable
Ex: SR Latch
S
0
0
1
1
SR Latch with Control Input

S
SR latch most often implemented with NAND gates.
Dataflow Implementation
entity sr_df is
port( s, r in bit;
q, qbar out bit);
end sr_df;
S R Q(t+1)
0 0 ??
01
1
10
0
1 1 Q(t)
23
When clock rises, value in D-latch propagates

to SR-latch and outputs.
New value determined by D input at time clock
rises.
Flip flop setup and hold time conditions
designed to prevent metastability in latches.
Propagation delay determined primarily by SR24
latch delay.
19-Feb-11
Types of Latches and Flip Flops
SR Master-Slave Flip Flop

S
R
S Q
C
R Q
Standard Graphic Symbols
S Q
C
R Q
Q
Q
Latches
The SR master-slave flip flop uses two SR latches with

complementary enables.
First stage follows all changes while clock is high, but
second stage only sees value after the clock drops.
not the same as a negative edge-triggered flip flop
S
C
R
S
C
R
J
C
K
J
C
K
Master-Slave Flip Flops

D
>C
>C
J
>C
K
J
>C
K
Edge-Triggered Flip Flops
Characteristic Tables
J K Q(t+1)
0 0 Q(t)
0 1
0
1 0
1
1 1 Q(t)
D Q(t+1)
0
1
0
1
T Q(t+1)
0
1
Q(t)
Q(t)
Forbidden input combination causes metastability.

Recommended usage: change S, R only when C=0.25
26
Loops
A loop repeatedly executes the sequential statements
contained within the loop structure
for loop
Entry point
Iteration
Terminal test
for identifier in starting value to stopping value loop
VHDL statements
end loop
27
28
While loop
Ex 7-9) Write a VHDL
program that reads a
set of 7-input bits, then
counts the number of
bits that are 1 and
send the count to an
output port.
Sol)
7
Bit
counter
entity OnesCount is
port (A: in std_logic_vector(0 to 6);
X: out natural range 0 to 7);
end entity OnesCount;
architecture MyCount of OnesCount is
begin
process(A)
variable V1: natural range 0 to 7;
begin
V1:=0;
for i in 0 to Alength-1 loop
if(A(i)=1) then
V1:= V1 + 1;
end if;
end loop;
X<=V1;
end process;
end architecture MyCount;
A for loop stops after a fix number of iterations

A while loop continues to loop until a condition is met
Structure
Entry point
Terminal test
Exit point
while Boolean expression loop
VHDL statements
end loop
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19-Feb-11
Shift registers
Multiple bit Registers

library ieee;
use ieee.std_logic_1164.all;
entity reg is
generic (n : natural := 4);
port (D : in std_logic_vector(n-1 downto 0);
Clock, Reset : in std_logic;
Q : out std_logic_vector(n-1 downto
0));
end entity reg;
architecture behavioural of reg is
begin
p0: process (Clock, Reset,D) is
begin
if (Reset = '0') then
Q <= (others => '0');
elsif rising_edge(Clock) then

Q <= D;
end if;
end process p0;
end architecture behavioural;
Shift registers are the second most important sequential

circuit building block.
Applications of shift registers:
Others : used in vector index here.
Serial-to-parallel converters
Parallel-to-serial converters
Delay
Counters
Classifications of shift registers

Serial-in vs. parallel-in
Serial-out vs. parallel-out
Unidirection vs. bidirectional
31
Universal shift register = parallel-in, parallel-out,

bidirectional.
32
Shift registers VHDL code

serial-in, parallel-out
Serial-in shift registers
library ieee;
architecture rtl of sipo is
begin
entity sipo is
p0: process (CLK,SIN) is
generic(N : natural := 8);
variable REG : std_logic_vector(N-1 downto 0);
port(SIN: in std_logic;
begin
Q : out std_logic_vector(n-1 downto 0); if rising_edge(CLK) then
CLK : in std_logic);
REG := REG(N-2 downto 0) & SIN;
end entity sipo;
Q <= REG;
end if;
end process p0;
end architecture rtl;
Define a dummy variable REG

(a) SISO
(b) SIPO
33

serial-in, parallel-out
34

serial-in, parallel-out(2)
library ieee;
begin
entity sipo is
port(SIN: in std_logic;
begin
Q : out std_logic_vector(n-1 downto 0); if rising_edge(CLK) then
end entity sipo;
end if;
Q <= REG;
end process p0;
library ieee;
begin
entity sipo is
p0: process (CLK,Q,SIN) is
begin
port(SIN : in std_logic;
if rising_edge(clk) then
Q : inout std_logic_vector(N-1 downto 0);
Q <= Q(N-2 downto 0)&SIN;
end if;
end entity sipo;
end process p0;
(1) VHDL style is preferred to (2)

Define a dummy variable REG
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19-Feb-11

serial-in, serial-out
library ieee;
entity siso is
port(CLK,SIN : in std_logic;
SOUT : out std_logic);
end entity siso;

serial-in, serial-out(2)
architecture rtl of siso is

begin
begin
if rising_edge(CLK) then
SOUT <= REG(N-1);
end if;
end process p0;
library ieee;
entity siso is
port(SIN,CLK : in std_logic;
SOUT : out std_logic);
end entity siso;
architecture rtl of siso is

signal Q:STD_LOGIC_VECTOR(N-1 downto 0);
begin
p0: process (CLK,SIN,Q) is
begin
Q <= Q(N-2 downto 0)&SIN;
end if;
SOUT<=Q(N-1);
end process p0;
37
Universal shift register

in VHDL
Universal Shift register
library ieee;
entity usr is
generic(n : natural := 8);
port(a : in std_logic_vector(n-1 downto 0);
lin, rin : in std_logic;
s : in std_logic_vector(1 downto 0);
clk, reset : in std_logic;
q : out std_logic_vector(n-1 downto 0));
end entity usr;
S1 S0 control signals:
Hold
Shift right
Shift left
Parallel load
38
00
01
10
11
architecture rtl of usr is

begin
p0: process(clk, reset) is
variable reg : std_logic_vector(n-1 downto 0);
39
Sequential Statements
Implied Registers
begin
if (reset = '0') then

reg := (others => '0');
elsif rising_edge(clk) then
case s is
when "11" =>
reg := a;
when "10" =>
reg := reg(n-2 downto 0) & lin;
when "01" =>
reg := rin & reg(n-1 downto 1);
when others =>
null;
end case;
end if;
q <= reg;
end process p0;
40
Implied Registers
Positive edge triggered D-FF with asynchronous reset
Process (d,clock,reset)
In
begin
if (reset = 0) then
q <= 0;
elsif( clockevent and clock=1) then
q <= d;
end if;
end process;
Registers
hardware, this becomes

D
SET
Qn+1
Clock
CLR
Reset
A clockevent is a 0 to 1 or 1 to 0 transition on the clock line.
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19-Feb-11
Implied Registers
Implied Registers
We can easily extend this to a register block by using a
std_logic_vector datatype instead of a std_logic datatype.
How does this produce a register?

1. If reset = 0, q is set to 0 (asynchronous reset)
2. If clock line makes a transition from 0 to 1
D
Clockevent and clock = 1
D
Clock
then q is assigned to d
But, we have not defined an output for
1. Reset = 1,
Reset
2. A non Clockevent , or
3. ClockEvent and Clock = 0
SET
CLR
Qn+1
So, VHDL assumes we want to retain the current value of q

for these conditions and synthesizes a D-FF for us.
.
In hardware, this
Signal ns,ps:std_logic_vector(7 downto 0);
..
Process (ns,clock,reset)
R
ns
begin
E
if (reset = 0) then
G
ps <= 00000000;
ps <= ns;
end if;
reset
end process;
becomes
ps
43
Implied Registers
44
Clock edges:
Use of wait-until to represent a Flip Flop
We can also define a S0 (reset state) and use it to reset the

register.
.
Signal ns,ps:std_logic_vector(7 downto 0);
Constant S0:std_logic_vector(7 downto 0) := 00000000;
..
Process (ns,clock,reset)
begin
if (reset = 0) then
ps <= s0; --- use reset state
ps <= ns;
end if;
end process;
The two statements are the same :

wait until CLK = 1; --edge triggered
wait until CLKevent and CLK = 1;--edge trig.
wait has to be put inside a process;

the process with wait-until has no
sensitivity list because it is automatically
implied in wait-until.
Wait should be the first statement in a process.
45
Rising edge and falling edge functions

The std_logic_1164 package defines the functions
rising_edge and falling_edge to detect rising and
falling edges of signals.
One of these functions can be used in place of (clks
event and clk = 1) expression.
Example:
ARCHITECTURE a OF dff_logic IS
BEGIN
PROCESS(clk)
BEGIN
IF rising_edge(clk) THEN
q <= d ;
END IF;
END PROCESS ;
END a;
Counters
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19-Feb-11
Counters and pattern

generators
Up/down counters are FSMs
Up/down counters: generate a sequence

of gradually increasing or decreasing
counting patterns according to the clock
and inputs. (E.g. digital clock, 1,2,3,4..)
Pattern generators: generate any patterns
of finite states. Use state diagrams to
design. (E.g. traffic light,red,green, yellow..)
Asyn.clock -more delay among outputs, less

logic
the output of one state register is the clock of
another state register.
Syn. clock -less delay among outputs, more
logic
all clock inputs of state registers (flip-lops) are
connected.
Examples here are all Moore machines

(output depends on state registers.)
4-bit Asynchronous clock down counter (Moore)
Asynchronous clock counter

design
Easier to design
More delay at outputs
library IEEE; -- moore asyn. Clock counter with asyn. reset, synthesized ok
use IEEE.std_logic_1164.all;
entity asyn_counter is
port (
CLK: in STD_LOGIC;
RESET: in STD_LOGIC;
COUNT: inout STD_LOGIC_VECTOR(3 downto 0));
end asyn_counter;
-- Since count is an IO bus connected outside, it must have type inout

or buffer
Architecture asyn_counter_arch of asyn_counter is

begin
process (CLK, COUNT, RESET)
begin
if RESET='1' then COUNT <= "0000";
else
if rising_edge(CLK) then COUNT(0) <= not COUNT(0);
end if;
if rising_edge(COUNT(0)) then COUNT(1) <= not COUNT(1);
end if;
end if;
end if;
end if;
end process ;
end asyn_counter_arch;
CLK: in STD_LOGIC; --from language assistant of Xilinx-fundation

COUNT: inout STD_LOGIC_VECTOR(3 downto 0);
1 process (CLK, COUNT, RESET)

2 begin
3 if RESET='1' then COUNT <= "0000";
4 else
5 if rising_edge(CLK) then COUNT(0) <= not COUNT(0);
6 end if;
7 if rising_edge(COUNT(0)) then COUNT(1) <= not COUNT(1);
8 end if;
10 end if;
12 end if;
13 end if;
14 end process;
Exercise on 4-bit Asyn. Clock Counter
Plot count, and check delay

Draw the schematic for the port declaration.
Plot count, calculate delay from first clock to Q(3)
Count(0)
clock
Count(1)
Count(2)
Count(3)
D(3)
D(0)
D(1)
D(2)
1FF
FF
FF
FF
Q(0) ck
Q(2) ck
Q(3)
ck
Q(1) ck
reset
clock
Q(0)
t= time delay at one FF
19-Feb-11
Synchronous clock counter

design
More difficult to design
Less delay at outputs (more precise)
A counter with load, reset, dir.

(E,g a clock that can be preset)
Load: for setting output to some value
DIR: for up/down control
CE: count or not count control
reset
Load
16-bit
din (data in)
DIR
CE
16-bit
count output
clock
-4-bit syn. Clock counter with count enable, asyn. reset and syn. load
--CLK: in STD_LOGIC; --from language assistant of Xilinx-fundation
-RESET: in STD_LOGIC;
-CE, LOAD, DIR: in STD_LOGIC;
-DIN: in INTEGER range 0 to 15;
-COUNT: inout INTEGER range 0 to 15;
1 process (CLK, RESET) begin
if RESET='1' then COUNT <= 0;

3 elsif CLK='1' and CLK'event then
4
if LOAD='1' then COUNT <= DIN;
5
else if CE='1' then
6
if DIR='1' then
7
COUNT <= COUNT + 1;
8
else
9
COUNT <= COUNT - 1;
10
end if;
11
end if;
12
end if;
13 end if;
14 end process;
Exercise for 4-bit Syn. Clock

counter
Draw the overall schematic diagram
describing the port declaration.
Plot all signals including count
--4-bit syn.clock counter with asyn reset ,from language assistant of X-fundation,
synthesized ok
library IEEE; --4-bit syn. counter with count enable, asyn. reset and syn. load, synthesized
ok
entity syn_counter is
port (
CLK: in STD_LOGIC;
CE, LOAD, DIR: in STD_LOGIC;
DIN: in INTEGER range 0 to 15;
COUNT: inout INTEGER range 0 to 15);
end syn_counter; --Since count is an IO bus connected outside, it must have type inout or
buffer
Architecture syn_counter_arch of syn_counter is
begin process (CLK, RESET) begin
if RESET='1' then COUNT <= 0;
elsif CLK='1' and CLK'event then
if LOAD='1' then COUNT <= DIN;
else if CE='1' then
if DIR='1' then
COUNT <= COUNT + 1;
else
COUNT <= COUNT - 1;
end if;
end if;
end if;
end if;
8-bit counter with three-state buffer

library ieee;
use ieee.std_logic_unsigned.all; -- for + or with overloading
entity counter is port (
clk, load, oe, enable: in std_logic;
data
: in std_logic_vector(7 downto 0);
cnt_out
: buffer std_logic_vector(7 downto 0));
end counter;
architecture cnt8 of counter is
signal cnt: std_logic_vector(7 downto 0);
begin
process ( clk)
begin
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19-Feb-11
VHDL Counters
if load = 1 then
cnt <= data;
elsif enable = 1 then
cnt <= cnt+1;
end if;
end if;
end process;
LIBRARY ieee;
ENTITY cnt IS
PORT(clk: IN STD_LOGIC;
reset: IN STD_LOGIC;
z: OUT STD_LOGIC_VECTOR(2 downto 0));
END cnt;
ARCHITECTURE behavior OF cnt IS
Type state_type is (A,B,C,D,E,F);
SIGNAL state: state_type;
BEGIN
Declare possible states
PROCESS(reset,clk)
(A-F is six states)
BEGIN
if (reset=1) then
state <= A;
z <=000;
Asynchronous reset to 000
elsif (clk'event and (clk=1)) then
case state is
when A=> state <= B; z <= "011";
when B=> state <= C; z <= 100";
when C=> state <= D; z <= "101";
Heres the counter
when D=> state <= E; z <= 010";
when E=> state <= F; z <= 001";
when F=> state <= A; z <= "000";
END CASE;
end if;
end process;
END behavior;
000
011 A 001
B
F
100C
E
010
D
101
-- three-state buffers
three_state: process(oe,cnt)
begin
if oe = 0 then
cnt_out <= (others => Z);
else
cnt_out <= cnt;
end if;
end process three_state;
end counter;
62
Common Errors
library ieee;
use ieee.std_logic_unsigned.all;
entity term-count is port
clock, reset, oe : in bit;
--Errors: (i) missing ( (ii) - not acceptable in the identifier
data
: out std_logic_vector(7 downto 0);
equals, cnt_out
: out std_logic;);
-- Error: ; before ) not acceptable.
end term-count;
architecture a of term-count
-- Error : is missing
begin
process (cnt, data)
begin
if data = cnt
equals = 1;
--Error then missing, use <= instead of =
end if;
end process;
Counter example : after correction

library ieee;
use ieee.std_logic_unsigned.all;
entity term_count is port (
clock, reset, oe
: in bit;
data
: out std_logic_vector(7 downto 0);
equals, cnt_out
: out std_logic);
end term_count;
architecture a of term_count is
begin
process (cnt, data)
begin
if data = cnt then
equals <= 1;
else
equals <= 0;
end if;
end process;
Common Errors
counter: process (clk)

--Error: replace clk with clock.
begin
if reset = 1 then
cnt <=0000;
--Error width of cnt is 8.
elseif (clockevent and clock=1)
--Error: replace elseif with elsif , add then
cnt <= cnt + 1;
--Operation + not defined for std_logic_vector
end if;
end process;
cnt_out <= (others <= Z) when oe=0 else cnt;
--Error: The second <= should be =>
end a;
Counter example: after correction

counter: process (clock)
begin
if reset = 1 then
cnt <=00000000;
elsif (clockevent and clock=1) then
cnt <= cnt + 1;
end if;
end process;
cnt_out <= (others => Z) when oe=0 else cnt;
end a;
11
19-Feb-11
Counter example: after correction

counter: process (clock)
begin
if reset = 1 then
cnt <=00000000;
elsif (clockevent and clock=1) then
cnt <= cnt + 1;
end if;
end process;
cnt_out <= (others => Z) when oe=0 else cnt;
end a;
Binary Counter Simulation
Binary Counter in VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use
IEEE.STD_LOGIC_UNSIGNED.ALL;
entity cnt4 is
Port ( CLK : in std_logic;
RST : in std_logic;
Q : out std_logic_vector(3 downto
0));
end for
cnt4;std_logic_vector is
+
defined in unsigned.all
package
Dummy variable, QQ
architecture Behavioral of cnt4 is

begin
process(CLK,RST)
variable QQ: std_logic_vector(3 downto
0);
begin
if RST='1' then
QQ:=(others=>'0');
else
QQ:=QQ+"0001";
end if;
end if;
Q<=QQ;
end process;
end Behavioral;
Binary Counter in VHDL(2)

library IEEE;
use
entity cnt4 is
RST : in std_logic;
0));
end cnt4;
Integer is supported in VHDL

Integer Range should be
specified.

begin
process(CLK,RST)
variable QQ: integer range 0 to 9;
begin
if RST='1' then
QQ:=0;
else
QQ:=QQ+1;
end if;
end if;
Q<=conv_std_logic_vector(QQ,4);
end process;
end Behavioral;
Conversion function is called.
Decimal Counter in VHDL

library IEEE;
use
entity cnt4 is
RST : in std_logic;
0));
end cnt4;

begin
process(CLK,RST)
variable QQ: std_logic_vector(3 downto
0);
begin
if RST='1' then
QQ:=(others=>'0');
elsif QQ="1001" then
QQ:=(others=>'0');
else
QQ:=QQ+"0001";
end if;
end if;
Q<=QQ;
end process;
end Behavioral;
Decimal Counter in VHDL(2)

library IEEE;
use
entity cnt4 is
RST : in std_logic;
0));
end cnt4;

begin
process(CLK,RST)
begin
if RST='1' then
QQ:=0;
elsif QQ=9 then
QQ:=0;
else
QQ:=QQ+1;
end if;
end if;
end process;
end Behavioral;
12
19-Feb-11
Decimal Counter in VHDL(3)

library IEEE;
use
entity cnt4 is
RST : in std_logic;
0));
end cnt4;

begin
process(CLK,RST)
begin
if RST='1' then
QQ:=0;
else
QQ:=QQ+1;
if QQ=9 (or =10 which one ???)
then
QQ:=0;
end if;
end if;
end if;
end process;
end Behavioral;
Sequential Logic Block Design

VHDL model 74LS190

VHDL model 74LS190
Datasheet of 74LS190 (course web site)
The 74x190 is asynchronously presettable BCD decimal counters. Presetting
the counter to the number on preset data inputs (AD) is accomplished through a
low asynchronous parallel load (LOAD) input. Counting occurs when LOAD is
high, count enable (CTEN) is low, and the down/up (D/U) input is either high for
down counting or low for up counting. The counter is decremented or incremented
synchronously with the low-to-high transition of the clock.
When an overflow or underflow of the counter occurs, the MAX/MIN output,
which is low during counting, goes high and remains high for one clock cycle. This
output can be used for look-ahead carry in high-speed cascading. The MAX/MIN
output also initiates the ripple clock (RCO) output, which normally is high, goes
low, and remains low for the low-level portion of the clock pulse. These counters
can be cascaded using RCO. If a decade counter is preset to an illegal state or
assumes an illegal state when power is applied, it returns to the normal sequence in
one or two counts, as shown in the state diagrams.

VHDL model 74LS190
PIN
Asynchronous reset
Asynchronous LOAD
Clock Enables: CTEN,
D/U
CLK
CTEN
UP/DOWN
LOAD
Synchronous
Binary Counter
counter
output
Output signals: RCO,

MAX/MIN
Schematic diagram of
74LS190

VHDL model 74LS190
architecture Behavioral of IC74LS190
is
signal QQ:unsigned(3 downto 0);
begin
process(RST,PIN,CTEN,LOAD,DOWN
_UP,CLK,QQ)
begin
if RST='1' then
QQ<=(others=>'0');
elsif LOAD='0' then
QQ<=unsigned(PIN);
elsif (CLK'event and CLK='1') then
if (CTEN='0') then
CLOCK Enable
RCO
Max/Min

VHDL
model 74LS190
if DOWN_UP='1' then
if QQ="1001" then
QQ<="0000";
else
QQ<=QQ+1;
end if;
Asynchronous
RESET and LOAD
Output
combinational
function block
Decimal Up Counting
else
if QQ="0000" then
QQ<="1001";
else
QQ<=QQ-1;
end if;
end if;
end if;
end if;
end process;
Q<=std_logic_vector(QQ);
Decimal Down Counting
13
19-Feb-11

VHDL model 74LS190
rco_max_min_pro: process(CLK,QQ,CTEN,DOWN_UP)
begin
RCO<='1';
if (CLK='0' and CTEN='0' and DOWN_UP='0' and QQ="0000") then
RCO<='0';
elsif (CLK='0' and CTEN='0' and DOWN_UP='1' and QQ="1001") then
RCO<='0';
end if;
MAX_MIN<='0';
if (CTEN='0' and DOWN_UP='0' and QQ="0000") then
MAX_MIN<='1';
elsif (CTEN='0' and DOWN_UP='1' and QQ="1001") then
MAX_MIN<='1';
Output enable signals
end if;
and output combinational logic
end process;
end behavioral;
Pattern generators
Irregular pattern counter examples: traffic
light, memory read/write patterns.
The control unit of a computer is a pattern
generator.
Or the whole digital computer is a pattern
generator counting according to the clock
and inputs (keyboard, memory, disk etc.)
State concepts
Answer the following questions:
How many states can a 4-bit counter have?
How many bits for the state registers
(using binary encoding) are required if you
need
Pattern generators (finite state

machines)
Pattern any pattern you desire.
E.g. CPU,
Memory controller etc.
Binary and one-hot encoding for

state machine design.
Binary encoding:
using N flip-flops to represent 2N states.
Use less flip-flops but more combinational logics
One-hot encoding:
Using N flip-flops for N states.
Use more flip-lops but less combination logic.
Xilinx default is one-hot. choose at XILINX

foundation_project_ manager synthesis
options.
Pattern generator design steps

Step 1. Identify the states
Step 2. Connect the states with certain
conditions.
4 states?
9 states?
21 states?
Repeat the above question if you use onehot encoding.
14
19-Feb-11
(liga0_nr) Example to generate traffic light

patterns R
State type (enumeration type)
You may declare your state types using:

1 architecture
2 type traffic_state_type is (s0, s1,s2,s3);
3 signal L_state: traffic_state_type;
4 begin...
process
So you dont have to worry about how many
FFs you need , the VHDL compiler will decide
for you.
State diagram notations

Each circle is a state; each arc is a transition after
a rising clock edge
E.g. if it is at state s0 the next state (after a

rising clock) will be at s1 etc.
The arc can be labeled to show state
switch conditions. If unlabeled, it is
unconditional.
L_stateA = s0
R
s1
s2
R
Y
Y
G
out_light(0) red
out_light(1) yellow
out_light(2) green
_nr stands for no reset, only the input

clock
red(s0) -> red-yellow(s1) -> green(s2) ->
yellow(s3) ->s1red(s0):s24 states s3
L_stateA = s0
R
R
Y
Y
G
Design flow
Process1(p1): -- clocked sequential
process
define state transitions
Process2(p2) : -- combinational process

from states to output (--> lights)
s3
Y
1 Architecture lightA of traffic is

2 type traffic_state_type is (s0, s1,s2,s3);
Liga0_nr.vhd
3 signal L_stateA: traffic_state_type;
4
out_light signal: std_logic_vector(2 downto0);

5 p1:Process
-- exec. Once when clock rises
6 begin
-- sequential process
7 wait until clock=1;
8 case L_stateA is
9
when s0 => L_stateA <= s1;
10 when s1 => L_stateA<= s2;
13 end case
14 end process --to be continued , see next
page
15 -- convert L_statesA to out_light

16 p2:process(L_stateA) -- combin.
process
17 begin case (L_stateA) is
18
when s0 => out_light <= 100;
19
20
20
22
end case
23 end process
24 end light1
R
RY
G
Y
15
19-Feb-11
library IEEE; -- Traffic light "liga0_nr.vhd full listing" ,

-- synthesized ok, but may have problem in
simulation .
entity traffic is
port (out_light :out std_logic_vector( 2 downto 0);

-- out_light uses type out because no feedback
requirement
clock: in std_logic);
end traffic;----------------------------------------------- Architecture lightA of traffic is
type traffic_state_type is (s0, s1,s2,s3);
signal L_stateA: traffic_state_type;
begin
----------------------continue next page----------------------
p1:process
-- exec. Once when clock rises
begin wait until clock=1; --s sequential process
case L_stateA is
when s0 => L_stateA <= s1;
when s1 => L_stateA<= s2;
end case;
end process; --to be continued , see next page
---- convert L_statesA to out_light
p2:process(L_stateA) -- combin. process
begin case (L_stateA) is
when s0 => out_light <="100";
end case;
end process;
end lightA;
Exercise on the traffic light

program
Programming hints:
In practice, lig0_nr.vhd does not have a
reset/set for sequential flip-flops, I.e.
(L_stateA).
Warning: In Xilinx-Foundation, the timing
simulator may not know how to initialize
L_stateA, hence does not know how to
begin the simulation.
So we have to modify the program.
Draw the signal feedback block diagram of

liga0_nr.vhd.
Why is it classified as a Moore machine?
Write the programs :
Liga1_sr:Add synchronous reset to to lightA.
Liga2_ar:Add asynchronous reset to lightA.
Advanced example with inputs,

see the labels of the arcs
This is your dream: If you press the button on
the light post, the light will become green at the
next state. (syn. or asyn input?)
Based on lightA, we modify case statements
L_stateA =
reset
s1
s0
InB=1
InB=0
R
R
Y
s2
inB=1
s3
InB=1
inB=0
Liga1_sr.vhd
Add synchronous reset
programming
Y
G
InB=0
16
19-Feb-11
--example 1: liga1_sr syn. reset based on lightA.vhd

library IEEE; -- ok for foundation1.5
entity traffic is
requirement
inB: in std_logic ;----------*********
end traffic;-----------------------------------------------Architecture lightA of traffic is
begin
--- inside liga1_sr.vhd --------------- convert L_statesA to out_light

begin
case (L_stateA) is
end case;
end process;
end lightA;
--- end of program
--example 2, liga2_ar.vhd, with asyn reset

-- use "if" for clock sensing instead of wait-until
-- clocked process with asyn input
library IEEE; -- Traffic light "lightA" ,-- synthesized ok.
entity traffic is
requirement
inB: in std_logic ;----------*********
end traffic;
Architecture lightA of traffic is
begin
---- inside liga1.vhd------p1:process -- wait-until-clock type process;

--exec.once when clock rises;the sensitivity list is empty
--it implies only the clock will trigger the process
--inb is only an syn. reset governed by clock.
begin wait until clock='1'; --edged-clock triggering point
if inB='1' -- syn. reset
Syn reset
then L_stateA <=s2;
else case L_stateA is
when s0 => L_stateA<=s1;
end case;
end if; end process; --to be continued , see next
Liga2_ar.vhd
Add asynchronous reset
programming
---- inside liga2_ar .vhd--------p1:process(inB , clock) sens. list has 2

elements
begin --asyn reset; situated before sensing
clock
Asyn. reset
if (inB ='1')
then L_stateA<= s2;
elsif( clock='1' and clock'event) then
case L_stateA is
end case; end if;end process; --to be
continued , see next page
17
19-Feb-11
---- inside liga2_ar.vhd ------------ convert L_statesA to out_light

begin case (L_stateA) is
end case;
end process;
end lightA;
----end of program
Liga3_ar.vhd
Based on liga2_ar.vhd combine
two processes (p1+p2) into one.
Further exercises
Liga3_ar.vhd: Rewrite liga2_ar using only
one process; combine the two processes.
--example 3: lig3a_ar.vhd 00-10-28 foundation 1.5 ok;

--same as lig2a_ar.vhd but combined into 1 process
-- inb force it goes to state s2, asyn. input
library IEEE;
entity traffic is
port ( inb: in bit;
out_light :out bit_vector( 2 downto 0);
requirement
clock: in bit);
end traffic;-----------------------------------------------Architecture lightA of traffic is
begin
-------- continue next page ---------------
------ inside liga3_ar.vhd --------------P1:process(clock,inB) -- combined process

Begin --exec. Once when clock rises
if inB='1' then L_stateA <= s2;
else
if clock'event and clock='1' then --s sequential
process
case L_stateA is --replace 8 of lightA from here
when s0 => out_light <="100"; L_stateA <= s1;
when others=> null;
end case ;
end if;
end if;
end process; end lightA; -- end of progam.
18

02-3-Sequential Logic Synthesis With VHDL

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19-Feb-11

Sequential Logic Synthesis

Review of sequential statements

Refs: Chapters 6 8 of the book of Pedroni

sensitivity list : determines

here there be dragons!

-- 2to1 multiplexer example

Describing Combinational Logic

All inputs to combinational

All outputs from

Using a VARIABLE in a PROCESS

after IF statement, then

PROCESS(Sel, x1, x2)

Using a VARIABLE in a PROCESS

Sequential Logic Circuit

(1) Combinational Logic Circuit, (2) Sequential Logic Circuit

Combinational Logic Circuit

X: the finite set of input symbols

f: a Boolean function for the output

1.Bistable Multivibrator: latches and flip-flops

The S-R (Set-Reset) Latch

Has two stable states

A type of bistable multivibrator

2.Monostable Multivibrator: one-shot

3.Astable Multivibrator: clock

Two versions of SET-RESET (S-R) latches.

The 74xx279 quad S-R latch.

Pair of inverters provides stable storage.

SR latch is key building block for flip flops.

when S=1, R=0 latch is set

architecture sr_bhv of sr_bhv is

Implementing D Flip Flops

Alternative implementation uses transmission gates.

inputs are active high

SR latch with control input changes state only when

architecture sr_df of sr_df is

inputs are active low (negative logic inputs)

SR Latch with Control Input

SR latch most often implemented with NAND gates.

When clock rises, value in D-latch propagates

Types of Latches and Flip Flops

SR Master-Slave Flip Flop

Standard Graphic Symbols

The SR master-slave flip flop uses two SR latches with

not the same as a negative edge-triggered flip flop

Master-Slave Flip Flops

Edge-Triggered Flip Flops

Forbidden input combination causes metastability.

A for loop stops after a fix number of iterations

Multiple bit Registers

elsif rising_edge(Clock) then

Shift registers are the second most important sequential

Others : used in vector index here.

Classifications of shift registers

Universal shift register = parallel-in, parallel-out,

Shift registers VHDL code

Serial-in shift registers

Define a dummy variable REG

Shift registers VHDL code

Shift registers VHDL code

(1) VHDL style is preferred to (2)

Shift registers VHDL code

Shift registers VHDL code

architecture rtl of siso is