IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSI: REGULAR PAPERS, VOL. 55, NO.

5, JUNE 2008

1197

A Precision High-Voltage Current Sensing Circuit

Tuli Dake and Erhan zalevli, Member, IEEE

AbstractThis paper presents a precision current sensor featuring a high voltage, high gain ( 140dB), and low input offset
( 1 mV) current sense amplifier. This amplifier does not require
offset trimming even for low offset applications. It is a single stage
amplifier that has a common gate pMOS differential input pair,
which makes it inherently stable. This amplifier topology allows
for a wide input common-mode range, thus increasing the versatility of current sensing circuit.
Index TermsAmplifier, CMOS, common, current, gain, gate,
high, offset, sense, voltage.

I. INTRODUCTION
IGH-PRECISION current sensing circuits are essential
part of the systems in battery-powered portable and automotive applications. Switch-mode dcdc converters commonly
utilize these circuits for monitoring, energy saving, protection,
and/or achieving fast transient response [1][3]. The accuracy
of the sensed current in multiphase converters has a strong impact on the system performance. Similarly, the accurate current
sensing information is exploited for sensor applications, motor
drivers, and automotive applications [4], [5]. The sensing circuit
in motor drivers is generally used to monitor the motor phase
current in high-performance motor drives. Therefore, the design
of a high precision current sensing circuit can readily improve
the performance of these system applications.
Depending upon the application, it becomes critical for the
current sensing design to have the ability to sense the inductor
current accurately and/or without loss [6]. While the accuracy
can be easily achieved by sensing the current by using a series
resistor, this design approach suffers from the power loss across
the resistor. The voltage drop across the resistor degrades the
power efficiency of the supply since the current can be in the
range of Amperes. Alternatively, the on-resistance of the series
field-effect transistor (FET) can be utilized to sense the conducted current [7]. However, the variation in the process, temperature, and supply also causes a large variation in the on-resistance, and this poses an inherent limit to the accuracy of the
current sensing with this approach. Another common method
is to filter the voltage across the inductor to sense the inductor
current [8]. The accuracy with this technique is dependent on
the tolerance of the filter time constant [9][11], and therefore
preferred for custom discrete designs.
As the physical size and cost of the systems become more critical for the electronic equipments, integrated current sensing circuits serve as a better option for current sensing applications. In

Manuscript received June 28, 2007. This paper was recommended by Associate Editor T. B. Tarim.
The authors are with Mixed-Signal Automotive Design Group, Texas
Instruments Incorporated, Dallas, TX 75243 USA (e-mail: e-ozalevli@ti.com;
l-dake1@ti.com).
Digital Object Identifier 10.1109/TCSI.2008.916452

Fig. 1. Current sensing circuit used to sense the load current through an inducand I
are the load and sense current, respectively. I
tive motor I
is converted to voltage, V
, which is then converted to digital data by an
analog-to-digital converter (ADC) to be used for signal processing. The digital
signal processor (DSP) controls the switching frequency of the driver. SA is the
sense amplifier. The supply voltage of the driver, V , is 12 V higher than the
supply voltage of the main-FET and sense-FET V .

that respect, sense-FET technique provides an integrated, lossless, and accurate design solution for current sensing [12][14].
In this method, a fraction of the load current is sensed by using
a scaled transistor (sense-FET) in parallel to the power transistor (main-FET) [15], [16]. To successfully achieve this, the
and drainsource voltage
of the
gatesource voltage
and
of the sensemain-FET need to be matched with
FET. In a number of current sensing applications, an amplifier
across the main-FET and sense-FET to
is required to force
be equal, as illustrated in Fig. 1. This amplifier is what we typically call as the sense/error-amplifier. The precision and versatility of the current sensor revolve around this amplifier. To minimize the error in the sensed current, the sense-amplifier needs
to have a very high gain. For low to min-range input supply voltages, it has been shown that this can be achieved by incorporating a two-stage amplifier [14], [17], [18]. However, the stability issues and the limited bandwidth of the two-stage amplifiers result in reduced speed and increased design complexity.
The accuracy of the sensed current is also dependent on the
input common-mode range of the sense-amplifier. This amplifier typically should be able to go from one rail to very close to
the opposite rail to maintain the accuracy across the large input
common-mode range.
In this paper, we propose a precision high-voltage current
sensing circuit based on the sense-FET technique to alleviate
these design issues for high-voltage applications. The proposed
design incorporates a single-stage amplifier to obtain a better
speed, gain, and stability performances and to achieve a large

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSI: REGULAR PAPERS, VOL. 55, NO. 5, JUNE 2008

Fig. 2. Circuit schematics. IN and IN are the negative and positive input terminals, respectively. M , M , M , and M are the n-FET and p-FET low
and high-voltage transistors, respectively. V and V are the low-voltage and high-voltage supply-rails. (a) The conventional cascode sense-amplifier. (b) Adopted
sense-amplifier topology consist of two nested-amplifiers A and A . (c) Adopted topology for A .

input common-mode range. In Section II, we describe the design and implementation of the proposed current sensing circuit.
After that we analyze the effect of the offset and amplifier gain
on the accuracy. Subsequently, we present the measurement and
simulation results of this circuit.
II. CIRCUIT DESCRIPTION
The current sensing scheme is illustrated in Fig. 1. This paper
will focus on a high side sensing topology; however, the same
reasoning applies for low side topologies too. The sense-amplifier forces the source voltages of main-FET and sense-FET to
be equal by modulating the gate of the pFET. As a result, a fraction of the load current, namely the sense-current is generated by
the sense-FET. This current is then converted to a sense-voltage,
, using a resistor to be used for digital signal processing.
The processed information is fed back to the system by the processor to control the switching frequency of the driver. The circuit shown in this figure is designed for high-voltage applications and therefore DMOS transistors, which can easily handle
high voltages, are utilized for main-FET and sense-FET.
The conventional cascode current-mirror topology commonly used as a sense-amplifier is illustrated in Fig. 2(a). This
amplifier is a single-stage differential amplifier with pMOS
common-gate differential pairs, and designed for high voltage
and
, are
applications. The high voltage transistors,
and
, by
used to protect the low voltage devices,
utilizing them as cascode transistors. The cascode transistors
, where
is
increase the output resistance by
is the output resistance of the
the transconductance and
high voltage transistor. In this circuit, the bias currents through
, and the sources of the
the amplifier legs are set by
low-voltage pFET transistors are used as the input terminals,
, on the left
INn and INp. The diode connected transistor,
branch is used to mirror the INn voltage to the gate of the
transistor on the right branch. As a result, the gate voltage of the
transistor on the right side becomes
, where
is set by
. Therefore,
of the amplifier is set by the
,
, and the generated small signal
transconductance of

current becomes
addition, the output resistance,

. In
, of this amplifier becomes

(1)
and
are the output resistance of low-voltage
where
and
are the
nMOS and pMOS transistors, and
transconductance of high-voltage nMOS and pMOS transisand
are the output resistance of
tors. Similarly,
high-voltage nMOS and pMOS transistors. The above equation
. By using
can be approximated as
these expressions, the gain of this amplifier can be written as
(2)
Also, this conventional amplifier has very low input impedance,
which is approximately equal to
. The input commonas its lower limit
mode of the sense-amplifier is
represents
and the supply voltage as its upper limit, where
the threshold of an FET, and
is the overdrive voltage and
.
equal to
The performance of the conventional amplifier is improved
by utilizing the nested-amplifiers in the proposed sense-amplifier, shown in Fig. 2(b). This proposed circuit is based on [19]
and similar to the gain boost concept used in [20], [21]. The
and
, are the main feature
nested-amplifiers, namely
of the proposed design. The suggested architecture of the
for high voltage applications is depicted in Fig. 2(c).
incorporates a cascoding technique proposed in [22]. Similar
, its low-voltage version with nFET input pairs is used
to
, since it does not have to withstand high voltages.
for
incorporates a source follower to generate the cascode gate
. This technique enables
to operate with
voltage for
lower input common-mode voltages since extra diode drop for
cascode voltage generation as in the conventional circuit is not
needed anymore.
Advantages of the suggested topology over the conventional
amplifier are the increased accuracy and most importantly increased gain. The dc gain of the proposed design is increased

DAKE AND ZALEVLI: A PRECISION HIGH-VOLTAGE CURRENT SENSING CIRCUIT

by the dc gains of
and
. The output resistance of this
regulated cascode current mirror, shown in Fig. 2(b), is

(3)

1199

represents the difference in the

of the
where
sense-FET and main-FET due to overall system offset, and
represents the
mismatch of the sense-FET and
main-FET over temperature. From (5) & (6), the sense current
output can be written as

Similarly, the above expression can be simplified as

, where
is the open loop gain of
the nested-amplifiers. Therefore, the gain of the proposed senseamplifier becomes
(7)
(4)
From the above equation, it is clear that the adopted topology
increases the gain by without the concomitant stability issues
and the need of another stage.
This adopted sense-amplifier topology offers low input
impedance, increased gain, and large input common-mode
range. Similar to the conventional amplifier, the proposed
and the input
sense amplifier has input impedance of
as
common-mode of the sense-amplifier is
its lower limit and the supply voltage as its upper limit. In
Section III, we analyze the effect of the offset and gain errors
on the performance of the sense-amplifier, and show the advantages of the proposed architecture.

to achieve very
As illustrated in Fig. 1,
small voltage drop across the main-FET and sense-FET for this
high-voltage application. Therefore, we can easily assume that
and
, and based on this we can approximate the
first part of the above equation as
(8)
However,
if the minimum
plified as

will be different from 1, especially

is only tens of mV. Hence,
can be sim-

(9)
III. ERROR ANALYSIS
The main source of error in current sensing is caused by the
threshold mismatch between the main-FET and sense-FET. This
error becomes more of a concern for high-voltage applications
since it is very problematic to match high voltage transistors. In
this application, this problem is circumvented by trimming the
mismatch of sense-FET and main-FET
room temperature
to achieve an accurate ratio, , for current sensing. This trim is
performed while the amplifier is running. However, this alone is
not sufficient and we will show that extra design steps need to
be taken to account for other error sources.
of main-FET being
In applications where the minimum
tracked is small, e.g., 50 mV, achieving even a 2% sensing pre, which is the
difference of
cision requires overall
main-FET and sense-FET, to be less than 1 mV. Assuming the
threshold mismatch of main-FET and sense-FET is trimmed;
is mainly determined by the input offset and dc-gain of
the sense amplifier.
The proposed sense-amplifier presented in this paper achieves
a dc-gain of more than 100 dB, thus the input offset of the amplifier
become the primary concern. The quantitative analysis is given
mismatch,
here to show the contributions of the mismatch,
and finite amplifier gain to the total sensed current error.
and are the input load and sense output current, respectively, shown in Fig. 1. These currents can be expressed as

(5)
(6)

Therefore, the sense current error/offset due to

becomes

(10)
In the above equation,
consists of three main components;
mismatch of
transistors
, an offset
which are
mismatch between
transistors
,
caused by the
and sense current offset due to finite gain of the amplifier.
does not include
mismatch between the
However,
main-FET and sense-FET.
The system error contributed by the finite gain of the sense
, where
is the
amplifier is given by
open loop gain of the sense amplifier and is the source voltage
of the sense-FET. Therefore, the total error in the sense current
based on (10) can be written as
(11)
From the above equation, if
is as low as 50 mV, achieving
for
will require
an accuracy of
mV. This can only be accomplished if the
and
errors are minimized and the finite gain error is virtually
zero.
To get a virtually zero finite gain error offset, a high sense-amis 12 V, even an 80
plifier gain is required. For example, if
. TheredB gain will result in minimum of 1.2 mV of
fore, around 100 dB is required to achieve the desired objective.
Single stage gain of greater than 120 dB can easily be obtained
based on the regulated cascoded current mirror circuit, shown
in Fig. 2(b). The total gain of this amplifier is basically the addition of cascoded amplifier gain (typically 60 dB80 dB) and

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSI: REGULAR PAPERS, VOL. 55, NO. 5, JUNE 2008

TABLE I
NUMERICAL ILLUSTRATION OF OFFSET CAUSED BY V

MISMATCH

the nested amplifier gain (typically 40 dB60 dB). This is equivalent to having a two stage amplifier gain without introducing
additional poles in the frequency range of interest.
mismatch, which is part of
, can be mitThe
igated by adopting a CMOS matching technique or by using
. In this application, these transistors are
pnp transistors for
sized reasonable large in addition to adopting a common-centroid layout technique for matching.
can actually domThe sensed current error caused by
. Therefore, even a small
inate the error generated by
can cause an input offset, and consequently a sense current error. In the proposed sense-amplifier, the nested-amplimismatch. This
fiers virtually eliminate any offset due to
to be approximately zero.
is achieved by forcing
error is usually overlooked in most applications, but it
can be a significant source of error. This error is associated with
the channel length modulation and causes a mismatch between
the source voltages of sense-FET and main-FET. The source
voltage of the sense amplifier can be expressed as

Fig. 3. Measured load current to sense current ratio over temperature and load
current.

(12)
Table I uses the above equation to numerically illustrate the
effect of lambda ( ) on the offset of input pair (
transistors) shown in Fig. 2(a). In this table, it is assumed that there
mismatch,
is equal in both legs, and
is equal.
is no
The
offset is calculated by generating a mismatch between
values of two legs. The cascoded
transistors in
the
mismatch when subjected
Fig. 2(a) will generate 108.8 mV
mismatch. In high voltage applications, such a
to a 12 V
high drainsource voltage should be expected across
since
the output of the amplifier has to be very low for small sense
currents while the input common-mode can be very high.
mismatch on the input differFrom the table, a 100 mV
ential pair will cause a 1.21 mV input-offset. This tells us using a
conventional cascoded topology, shown in Fig. 2(a), will not be
mismatch of the cascoded transufficient especially if the
sistors is significant (e.g., 12 V used in table), which is expected
in most high-voltage sense amplifier applications.
IV. RESULTS AND COMPARISON
In this section, we present the experimental results and worstcase corner simulations of the proposed circuit. This circuit is
fabricated in 0.35- m BICMOS DMOS (BCD) process and designed to have a ratio, , of 40. The offset measurements are performed indirectly by measuring the variation of the sense-current with temperature and load current. The load current is swept

Fig. 4. Effect of V mismatch on offset, demonstrated here by sweeping load

current and plotting current ratio.

from 4.5 mA to 34.5 mA, and the ratio of the sense and load current is measured for temperatures of 40 C, 25 C, and 95 C,
as shown Fig. 3.
The mismatch between main-FET and sense-FET is trimmed
at room temperature to obtain a current sense ratio of 40, as illustrated in Fig. 3. This ratio is chosen based on the load current.
For a fixed load current, the upper limit of the ratio is determined
by the leakage current in the circuit. The gain of the sense amplifier stays more than 100 dB across the temperature. Also, in
the closed loop system, the offset of the amplifier is the only parameter that has significant temperature dependence. Therefore,
based on the variation of the sense current with temperature and
load current, the total variation in the ratio can be measured.
ratio has a variation of less
The plot shows that
is
than 2% between 5 mA30 mA. It is measured that when
variation
around 50 mV and there is 5-mA of load current,
stays less than 1 mV across the temperature and load current.
The worst-case corner simulations of the sense amplifier are
performed to verify the measurement results and to compare the
performance of the proposed sense amplifier with that of the
conventional sense amplifier. Fig. 4 shows the effect of

DAKE AND ZALEVLI: A PRECISION HIGH-VOLTAGE CURRENT SENSING CIRCUIT

1201

TABLE II
CIRCUIT PARAMETERS

by about two orders of magnitude, while maintaining singlestage response. It was shown that the proposed sense amplifier topology has the advantage of operating with small voltage
mismatch that
headroom and significantly mitigates any
might contribute to the system offset.
ACKNOWLEDGMENT
Fig. 5. Gain and phase plots for input common-mode voltage of 2.5 and 40 V.

The authors thank J. Pitz and J. Devore, Mixed Signal Automotive Design, Texas Instruments Incorporated, Dallas, TX, for
their insightful contributions.
REFERENCES

Fig. 6. Microphotograph of the die that contains the presented circuit.

on the overall system offset. This is achieved by sweeping the

load current and computing the corresponding current ratio. No
mismatch is generated and both topologies are designed to
in (11) is the main
have comparable gains. Therefore,
factor causing the variation in the ratio. We see that the adopted
topology has a much better current ratio flatness, which directly
translates into a much smaller offset value.
Fig. 5 shows the worst-case corner simulations of the sense
amplifier. This plot illustrates the gain and phase responses for
input common-mode of 2.5 and 40 V. The maximum gain of
around 140 dB is obtained for input common-mode of 40 V.
However, this gain decreases down to 120 dB for input commonmode of 2.5 V. The phase margin of the amplifier is shown to be
around 80 and its unity-gain bandwidth is around 2 MHz. The
zero observed in the plots is due to the nulling resistor, shown
in Fig. 2(b). The nondominant pole starts coming into play at
much higher frequencies due to the high gain-bandwidth of the
topology. Finally, the die photo of the fabricated chip is shown
in Fig. 6 and the circuit parameters are listed in Table II.
V. CONCLUSION
In this paper, we presented a precision current sensing technique with a sense-amplifier topology that incorporates the gain
boost concept. This topology was shown to increase the gain

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Tuli Dake received the B.Sc. degree in electrical and

electronics engineering from Kwame Nkrumah University of Science and Technology (KNUST), Kumasi, Ghana, and the M.S. degree from Texas A&M
University, College Station, in 2000.
He is currently a Design Engineer with the Mixed
Signal Automotive group, Texas Instruments Incorporated, Dallas, TX, and has two U.S. patents in the
area of power management. His research interests include mixed-signal circuits, power management, and
sensor interfaces for automotive applications.

Erhan zalevli (S04M06) received the B.Sc.

degree in electrical and electronics engineering from
Bilkent University, Ankara, Turkey, in 2001, the
M.Sc. degree in electrical and computer engineering
from the University of Arizona, Tucson, in 2003,
and the Ph.D. degree in electrical and computer engineering from the Georgia Institute of Technology,
Atlanta, in 2006.
He is currently a Design Engineer with Mixed
Signal Automotive group, Texas Instruments Incorporated, Dallas, TX. His research interests include
mixed-mode multichip VLSI systems for bio-inspired and neuromorphic
applications, tunable floating-gate CMOS resistors and their applications, and
data converters for embedded systems.