RESUME

Objective:
To offer the organization best of my abilities and skills to bring in an adaptable improvement
within the organization culture and looking for a challenging career.
Educational Qualification:
Post Graduation:
Branch of M.Tech: VLSI Design & Embedded system.
College :
R.V College of Engineering, Bangalore.
Course
M.Tech

Semester
Till 2nd

University
Visvesvaraya Technological University,
Belgaum.

% Marks
71

Under Graduation:
Bachelor of Engineering (Telecommunication) in Bangalore Institute of Technology with
aggregate of 60.04%
Diploma in Electronics and Communication in Mahatma Gandhi Polytechnic with aggregate of
64%
GATE Score:
Examination
GATE

Examination
Paper

Year Of Passing

Percentile Score

Gate Score

EC

2010

90.94

397

Internship: GE Healthcare India Pvt Ltd, JFWTC, ITPL Road, Bangalore.

Working for GE Healthcare since August 2011 as Trainee, Currently working on Porting Real
Time Linux Kernel to ARM Core for Interfacing Data Acquisition in Patient Monitors.
The aim of this project is to Port the Real time Embedded Linux Kernel to ARM Core for
interfacing Data Acquisition unit to Patient monitor, the project overcomes the problem of
handling exception and interrupt latency in ARM Processor.
Work Experience: Worked as Technical Support Engineer for INTEL for a period of 9
months, were I used to trouble shoot the problems raised in Intel Motherboard and Intel
Processor. During the term I was able to put down many papers for rectifying methodology for
the problems came up with Intel Motherboard and Intel Processor.
Skills and Technical Expertise:
C, Embedded C, Linux Kernel Development.

Verilog and VHDL Coding using the tools Cadence (Analog and Digital) and Xilinx.
Real Time Operating System development.
Transistor (CMOS) level Digital circuit design.

Publications in International and National Journals:

Presented and published a paper on Synthesis and optimization of Combinational
circuits using Reversible Logics in a National Conference, Bangalore 2012.
Presented and Published a paper on Low Power Design of Combinational Logic
Circuits in International Conference, Udaipur 2012
Is Image Steganography Natural? In the year 2008, BIT College Bangalore
4:1 and 8:1 Multiplexers using Reversible Logic in the year 2012, RV College ,
Bangalore
Co-Curricular Activities:
Vocational training (Advanced Diploma in Embedded System Software Engineering)
for the duration of six month after the completion of degree at Indian Service Machine,
Bangalore. Authorized by AICTE-CEP, Govt. of India.

Participated Project Presentation contest organized in a technical fest by Bangalore

Institute of Technology Karnataka, during Engineering.

Participated in National Level Paper Presentation Contest held at RV College of

Engineering.

Technical Project:
1) Title: Simulation and Synthesis of Digital Circuits using Reversible Logics.
Institute: RV College of Engineering.
Description: As per the recent trend, the number of transistors per chip is increasing. As the
device density increases, the power dissipation in the circuit also increases. This fuels the need
for low power VLSI chips. Another factor that fuels the need for low power chips is the
increased market demand for portable consumer electronics powered by batteries. E.g. Mobile
handset. Also power dissipation has a direct impact on packaging cost of the chip and cooling
cost of the system. Hence circuits with less power dissipation are being is required. This has been
designed here using reversible gates.
In this project 2 new designs are developed on and proved how Transistor cost and Gate cost
improves using Reversible Logic.
2) Title: Modified Booth Wallace Algorithm using HDL.
Institute: Rastriya Vidyalaya College Of Engineering.

Description: In this project fast multiplication is been developed using the Booth Wallace
Algorithm. It not only operates the unsigned multiplication but also supports signed
multiplication. XILINX ISE v 10.2 for programming. Considered Verilog as our primary
language, for test bench waveforms Xilinx is used to write our own test benches. The code is
dumped into the hardware (FPGA Kit) and checked with the result.
The main aim of this project is to reduce the delay while doing the normal multiplication and
power optimization.
3) Currently working project:
Title: Design of Low Power Sequential Circuits using Reversible Logic.
Institute: RV College Of Engineering.
Description: The main intension of this project is to reduce the transistor count used in normal
circuits which in turn reduces the chip area and reduces the power consumption. Comparison of
different design is brought out t show the power optimization. This particular project is
developed using the tool Cadence.
4) Title: Image Compression and Satellite Image Classification using Haar-Wavelet
Transformation.
Institute: Bangalore Institute of Technology.
Description: In this project digital images were compressed and satellite images were classified,
the images were given as the input to the computer where the code was being executed and the
compressed and classified images were obtained after execution. MATLAB coding was used as
the tool to develop this project.
The main intension of this project is to compress a digital image and classify the satellite image;
information in the picture is encoded as matrix, if this information is so big it requires a large
storage of memory system, we can transfer the main information to the user so that they can
understand what the picture is like. This project is worked on the 4 band namely Red, Green,
blue and Infrared band image got from Quick Bird satellite which was launched into orbit using
PSLV INSAT 4A.
Extra-Curricular Activities:

Was the student head for the Techno-Cultural Fest and National Level Conference held at
RV College Of Engineering in the year 2011.

Participated in many drawing competitions and inter school cultural events, got placed
first class in higher level drawing.

Awards and achievements:

Awarded with Best Student of the Year during diploma for the year 2004.

Awarded with First Class certificate in drawing from Karnataka Secondary Education,
Bangalore during the year 2001.

Hobbies:
Photography and Drawing.
Personal Details:
Name
Date of Birth
Sex
Nationality
Marital status
Place of Birth

: PRAVEEN G
: 8th March 1985
: Male
: Indian
: Single
: Bangalore

Declaration:
I here by declare that above information is true to the best of my knowledge.
Place:
Date :

Praveen G