Arithmetic 2015

UEEA4653: Computer Architecture
Arithmetic for Computers
UUEA4653 May 2015
Major Goals
Introduce 2's complement numbers and their addition & subtraction

Explain the construction of a 32-bit arithmetic logic unit (ALU)
Show algorithms and implementations of multiplication and division
Copyright Dr. Lai An Chow
Base, Representation and Value
Numbers can be represented in any base
Human: decimal (base 10); Computer: binary (base 2)
The value of the ith digit d is d x Basei
10012 = (1 x 23) + ( 0 x 22 ) + ( 0 x 21 ) + ( 1 x 20 )
10
= 910
Bits are numbered 0, 1, 2, 3 from right to the left in a word

A MIPS word can represent 232 different 32-bit patterns (values)
31 30 29 28
...
...
most significant bit (MSb)
3 2 1 0
least significant bit (LSb)
Value of the 32-bit binary numbers =
(b31 x 231) + (b30 x 230) + + (b1 x 21) + (b0 x 20)

Hexadecimal Representation
Why hexadecimal?
To avoid reading and writing long binary numbers
Hexadecimal (base 16) numbers are commonly used
Conversion to hexadecimal
Since base 16 is a power of 2, we can simply convert by replacing
each group of four bits by a single hexadecimal digit, and vice versa
Example of hexadecimal-to-binary conversion:
0hex - 9hex
for 00002 - 10012
ahex - fhex
for
10102 11112
i.e. 0000 1010 0000 0101 0000 1100 0000 01102

= 0
a
0
5
0
c
0
6hex
= 0x0a050c06
# 0x to indicate it is a hexadecimal
= 16810291810
2's Complement Representation
All computers use 2's complement representation for signed numbers

Bit 31 is called the sign bit: (0 for non-negative, 1 for negative)
The positive half uses the same representation as before

The negative half uses conversion illustrated below:
0000 0000 0000 0000 0000 0000 0000 0110 2 = 610
i)
Invert bits to get 1s complement
1111 1111 1111 1111 1111 1111 1111 1001 2 = -710
ii) Add 1 to get 2s complement
1111 1111 1111 1111 1111 1111 1111 1010 2 = -610

Largest integer represented by a MIPS word:
0111 1111 1111 1111 1111 1111 1111 1111 2 = (231 1)10 = 2,147,483,64710
Smallest integer represented by a MIPS word:
1000 0000 0000 0000 0000 0000 0000 0000 2 = -23110 = -2,147,483,64810
Immediate part for lw, sw & addi are represented in 2s complement

Signed and Unsigned Numbers
Signed numbers
negative or non-negative integers, e.g. int in C/C++
Unsigned numbers
non-negative integers, e.g. unsigned int in C/C++
Operations for unsigned numbers
Comparison:
Arithmetic:
sltu (set on less than unsigned), sltiu

addu, subu (add/subtract unsigned)
Treat values of all registers as non-negative
addiu (add unsigned immediate)
The 16-bit immediate is treated as unsigned
(range: 0 > (216 1) = 65535)
addi (add signed immediate); range: -32768 -> +32767
Load:
lbu (load byte unsigned), lhu (load half unsigned)
Signed vs. Unsigned Comparison
$s0 1111 1111 1111 1111 1111 1111 1111 11112

$s1 0000 0000 0000 0000 0000 0000 0000 00012
What are the values in registers $t0 and $t1 in the examples below?
slt $t0, $s0, $s1

# signed comparison
$s0 = -110, $s1 = 110, $t0 = 1
sltu $t1, $s0, $s1 # unsigned comparison
$s0 = 429496729510, $s1 = 110, $t1 = 0
Sign Extension
Why sign extension?

e.g. lb $t0, 0($s0) # load a 8-bit signed number to 32-bit register
Bits 0~7 of $t0 will contain the byte value stored at 0($s0)
If the byte is a negative number, what happens to bits 8~24 of $t0?
Conversion of n-bit binary signed numbers into m-bit numbers (m > n)
Done by filling the leftmost bits (n-th ~ (m-1)-th) with the sign bit
For example:
2 (16 bits -> 32 bits):
0000 0000 0000 0010 -> 0000 0000 0000 0000 0000 0000 0000 0010
-2 (16 bits -> 32 bits):
If the immediate in the addi instruction = 1111 1111 1111 1110,

the sign is extended as shown above before the ALU starts addition
For unsigned addition operation addiu, sign is not extended and
65534 (why this value?) is used in the addition
1111 1111 1111 1110 -> 1111 1111 1111 1111 1111 1111 1111 1110
Addition and Subtraction
Addition
Digits are added bit by bit from right to left, with carries
passed to the next digit to the left
Subtraction
Subtraction uses addition

The appropriate operand is negated before being added to the
other operand
Overflow
The result is too large to fit into a word
Examples
10
Addition (7 + 6 = 13):
0000 0000 0000 0000 0000 0000 0000 0111 2

0000 0000 0000 0000 0000 0000 0000 0110 2
=
=
710
610
0000 0000 0000 0000 0000 0000 0000 1101 2
1310
0000 0000 0000 0000 0000 0000 0000 0111 2

1111 1111 1111 1111 1111 1111 1111 1010 2
=
=
710
-610
= 1 0000 0000 0000 0000 0000 0000 0000 0001 2
110
Subtraction (7 - 6 = 1):
Examples
11
Addition (1073741824 + 1073741824 = 2147483648):
0100 0000 0000 0000 0000 0000 0000 0000 2

0100 0000 0000 0000 0000 0000 0000 0000 2
= 107374182410
= 107374182410
1000 0000 0000 0000 0000 0000 0000 0000 2
214748364810
if considering MSb a sign bit

but, it means -214748364810
Detecting Overflow
12
Addition (X + Y)
Subtraction (X - Y)
No overflow occurs when:

X and Y are of different signs
No overflow occurs when:

X and Y are of the same sign
Overflow occurs when:

X and Y are of the same sign
But, X + Y is represented in a
different sign
Overflow occurs when:

X and Y are of different signs
But, X - Y is represented in a
different sign from X
Overflow condition
Operation
Sign Bit of X
Sign Bit of Y
Sign Bit of Result
X+Y
X+Y
XY
XY
Effects of Overflow
13
MIPS detects overflow with an exception (also called an interrupt)

Exceptions occur when unscheduled events disrupt program execution
Some instructions are designed to cause exceptions on overflow
e.g. add, addi and sub cause exceptions on overflow
But, addu, addiu and subu do not cause exception on overflow;
programmers are responsible for using them correctly
When an overflow exception occurs
Control jumps to a predefined address (code) to handle the
exception
The interrupted address is saved to EPC for possible resumption
EPC = exception program counter; a special register
MIPS software return to the offending instruction via jump register
14
2. Arithmetic Logic Unit
Constructing an Arithmetic Logic Unit
15
The arithmetic logic unit (ALU) of a computer is the hardware
component that performs:

Arithmetic operations (like addition and subtraction)
Logical operations (like AND and OR)
Processor
Control Unit
ALU
Registers
& Cache
Universal Representation
16
Knowing what is exactly inside a 32-bits ALU, from now on we will use
the universal symbol for a complete ALU as follows:
ALU operation
a
Zero
Result
Overflow
ALU
b
ALU Control lines

000
001
010
110
111
Operation
AND
OR
ADD
SUB
SLT
CarryOu t
Constructing an Arithmetic Logic Unit (contd)
17
Since a word in MIPS is 32 bits wide, we need a 32-bit ALU

Ideally, can build a 32-bit ALU by connecting 32 1-bit ALUs together
1-bit logical unit for AND and OR:
Operation
a
0
Result
b
A multiplexor selects the appropriate result depending on the

operation specified
1-Bit Full Adder
18
An adder must have
Two inputs (bits) for the operands

A single-bit output for the sum
Also, must be a second output to pass on the carry, called carry-out
Carry-out becomes the carry-in to the neighbouring adder
1-bit full adder is also called a (3, 2) adder (3 inputs and 2 outputs)
CarryIn
(1)
(1)
(0)
(carries)
0
1
1
1
0
1
1
0_____
1 (1)1 (1)0 (0)1
a
Sum
b
CarryOut
Truth Table and Logic Equations for 1-Bit Adder
19
Truth table:
a
0
0
0
0
1
1
1
1
Inputs
b
CarryIn
0
0
1
1
0
0
1
1
Outputs
CarryOut SumOut
0
1
0
1
0
1
0
1
0
0
0
1
0
1
1
1
Comments
0+0
0+0
0+1
0+1
1+0
1+0
1+1
1+1
0
1
1
0
1
0
0
1
+
+
+
+
+
+
+
+
0=
1=
0=
1=
0=
1=
0=
1=
002
012
012
102
012
102
102
112
Logic equations:
CarryOut (b CarryIn) (a CarryIn) (a b) (a b CarryIn)

(b CarryIn) (a CarryIn) (a b)
SumOut (a b CarryIn) ( a b CarryIn) ( a b CarryIn)

(a b CarryIn)
Hardware Implementation of 1-Bit Adder
20
CarryOut (b CarryIn) (a CarryIn) (a b) (a b CarryIn)
(b CarryIn) (a CarryIn) (a b)
C arryIn
C arryOut
SumOut bit: (It is left as an exercise)
1-Bit ALU (AND, OR, and Addition)
21
3 in 1 building block
Use the Operation bits to decide what to carry out

Operation = 0, do AND
Operation
Operation = 1, do OR
CarryIn
Operation = 2, do addition
a
0
1
Result
2
b
CarryOut
32-Bit ALU
22
Ripple carry organization of a
CarryIn
32-bit ALU constructed from 32

1-bit ALUs:
a0
CarryIn
Result0
ALU0
b0
A single carry out of the least

significant bit (Result0) could
ripple all the way through the
adders, causing a carry out
of the most significant bit
(Result31)
Operation
CarryOut
a1
CarryIn
Result1
ALU1
b1
CarryOut
a2
There exist more efficient

implementations (based on
the carry lookahead idea
to be explained later)
CarryIn
Result2
ALU2
b2
CarryOut
a31
CarryIn
Result31
ALU31
b31
Subtraction
23
Subtraction is the same as adding the negated operand

By doing so, an adder can be used for both addition and subtraction
A 2:1 multiplexor is used to choose between
an operand (for addition) and

its negative version (for subtraction)
Shortcut for negating a 2's complement number:
Invert each bit (to get the 1's complement representation)

Obtain the 2s complement by setting the ALU0s carry bit to 1
1-Bit ALU (AND, OR, Addition, and Subtraction)
24
Binvert: the selector input of a multiplexor to choose between addition
and subtraction
Binvert
Operation
CarryIn
0
1
Result
CarryOut
To form a 32-bit ALU, connect 32 of these 1-bit ALUs

Set CarryIn input of the least significant bit (ALU0) to 1 for subtraction
Tailoring the ALU for MIPS
25
The 32-bit ALU being designed so far can perform add, sub, and, or
operations which constitute a large portion of MIPS instruction set
Two instructions not yet supported are: slt and beq

When we need to compare Rs to Rt
By definition of slt, if Rs < Rt
LSb of the output is set to 1

Otherwise, it is set to 0
How to implement it?
The comparison above is equivalent to testing if (Rs Rt) < 0
If (Rs Rt) is smaller than 0
MSb of the subtraction (Rs Rt) equals to 1 (means negative)
Otherwise, MSb of the subtraction equals to 0
Notice that the outcome of MSb is similar to the result of slt
We can copy the MSb of the subtraction to the LSb of slts output
slt can be done using two types of 1-bit ALUs in next slide
Tailoring the ALU for MIPS (contd)
Binvert
Operation
CarryIn
26
Binvert
Operation
CarryIn
0
1
1
Result
b
Result
b
2
Less
3
Set
Less
3
Overflow
detection
Overflow
CarryOut
1-bit ALU for the MSB
1-bit ALU for bits 0 to 30
32-Bit ALU with (add, sub, AND, OR, slt)

The set signal is the MSb
of the result of the

subtraction, A B
It is passed to LSB
Result0 will equal to this
set signal when operation
= 3 (which means slt
instruction is being
executed)
B in v e r t
C a rry In
a0
b0
C a rry In
ALU0
Le ss
C a rry O u t
a1
b1
0
C a rry In
ALU1
Le ss
C a rry O u t
a2
b2
0
C a rry In
ALU2
Le ss
C a rry O u t
27
O p e r a t io n
R e s u l t0
R e s u l t1
R e s u l t2
C a rry In
a31
b31
0
C a rry In
ALU 31
Le ss
R e s u l t3 1
S et
O v e r f lo w
32-Bit ALU with (add, sub, AND, OR, slt)

Finally, this adds a zero
Bnegate
detector
For addition and
AND/OR operations
both Bnegate and
CarryIn are 0 and for
subtract, they are both
1 so we combine them
into a single line
28
Operation
a0
b0
CarryIn
ALU0
Less
CarryOut
Result0
a1
b1
0
CarryIn
ALU1
Less
CarryOut
Result1
a2
b2
0
CarryIn
ALU2
Less
CarryOut
Result2
a31
b31
0
CarryIn
ALU31
Less
Zero
Result31
Set
Overflow
Put All Together
29
ALU operation
Bnegate
a0
b0
CarryIn
ALU0
Less
CarryOut
Result0
a1
b1
0
CarryIn
ALU1
Less
CarryOut
Result1
a2
b2
0
CarryIn
ALU2
Less
CarryOut
Result2
ALU operation
a
ALU
Zero
Result
Overflow
Zero
Result
b
CarryOu t
a31
b31
0
CarryIn
ALU31
Less
Result31
Set
Overflow
Comparing Two Unsigned Numbers
30
We can subtract as usual, but use the CarryOut31 to tell the result
If A < B
Example: A = 0111, B = 1000

A B = A + B = 0111 + 1000 (0111+1)
= 0 1111
If A > B
Example: A = 0111, B = 0110
A B = A + B = 0111 + 1010 (1001+1)
= 1 0001
If A = B
Example: A = 0111, B = 0111
A B = A + B = 0111 + 1001 (1000+1)
= 1 0000
If CarryOut31 is 0 then A < B, otherwise A >= B; slt is achieved
10
Carry Lookahead
31
Using the ripple carry adder, the carry has to propagate from the LSb
to the MSb in a sequential manner, passing through all the 32 1-bit

adders one at a time. SLOW for time-critical hardware!
Key idea behind fast carry schemes without the ripple effect:
CarryIn2 (b1 CarryIn1) (a1 CarryIn1) (a1 b1)

CarryIn1 (b0 CarryIn0) (a0 CarryIn0) (a0 b0)
Substituting the latter into the former, we have:
CarryIn2 (a1 a0 b0) (a1 a0 CarryIn0) (a1 b0 CarryIn0)

(b1 a0 b0) (b1 a0 CarryIn0) (b1 b0 CarryIn0)
(a1 b1)
All other CarryIn bits can also be expressed using CarryIn0
32
3. Multiplication
Multiplication
33
Multiplication is much more complicated than addition and subtraction

Paper-and-pencil example (100010 x 100110):
Multiplicand
Multiplier
Product
1000
1001
1000
0000
0000
1000
1001000
Observation:
Suppose we limit ourselves to using only digits 0 and 1

If we ignore the sign bits (i.e., unsigned numbers), multiplying an
N-bit multiplicand with an M-bit multiplier gives a product that is
at most N+M bits long
11
Signed Multiplication
34
If the multiplicand or multiplier is negative, we first negate it to get a
positive number
Use any one of the above methods to compute the product of two
positive numbers
The product should be negated if the original signs of the operands
disagree
Booths algorithm: a more efficient and elegant algorithm for the
multiplication of signed numbers
Motivation behind Booth Algorithm
35
Lets consider multiplying 00102 and 01102
Multiplicand
Multiplier
Product
x
+
+
+
+
=
Convention
0010
0110
0000
0010
0010
0000
0001100
+
+
+
=
Booth
0010
0110
0000
0010
0000
0010
0001100
shift
subtract
shift
add
Keys
Shifts are much faster than adds
Algorithm looks at two bits of multiplier at a time from right to left
Take action only when the two-bit pair is either 01 or 10
Avoiding unnecessary additions to speed up the calculation
Example to Explain the Math
36
Multiplier = 00111100
i.e. b1 = 2, b2 = 5
M x 00111100 = 22 *M + 23 *M + 24 *M + 25 *M
= 22 * (20 + 21 + 22 + 23) *M
= 22 * (24 - 1) *M
= (26 - 22) *M
Running the Booths algorithm by scanning multiplier from right to left
Iteration 0, pattern = 00
12
Booths Algorithm
37
To find out why, do the math:

Consider a series of ones in the multiplier (from bit b1 to bit b2)
M: multiplicand; multiplying M with this series of ones results in
Prod = (2b1)* M + (2b1+1)* M + + (2b2)* M
= (2b2+12b1)* M
Number of additions, (b2-b1), in revised algorithm is reduced to one
addition and one subtraction in Booths algorithm
Detailed algorithm:
We look at 2 bits at a time (current bit and previous one):
00: middle of a string of 0s; no arithmetic operation
01: end of a string of 1s; add M to the left half of product
10: start of a string of 1s; subtract M from the left half of product
11: middle of a string of 1s- no arithmetic operations
Previous bit is set to 0 for the first iteration to form a two-bit pattern
Multiply in MIPS
38
Separate pair of 32-bit registers to contain 64-bit product, Hi and Lo

mult (multiply) and multu (multiply unsigned)
mult $s2, $s3

multu $s2, $s3
# Hi, Lo = $s2 x $s3

# Hi, Lo = $s2 x $s3
Both MIPS multiply instructions ignore overflow

No overflow if Hi is 0 for multu or the replicated sign of Lo
for mult
Fetch the integer 32-bit product
mflo (move from lo)

mflo $s1
# $s1 = Lo
mfhi (move from hi)
mfhi $s1
# $s1 = Hi
mfhi can transfer Hi to a general-purpose register to test for
overflow
39
4. Division
13
Division
40
Division is the reciprocal operation of multiplication

Paper-and-pencil example (1001010ten / 1000ten):
Divisor
1000
1001
1001010
-1000000
0001010
0001010
0001010
-1000
10
Quotient
Dividend
Remainder
Dividend = Quotient x Divisor + Remainder
Example
41
Paper-and-pencil example (00001112 / 00102):

0011
Divisor
0010
00000111
Quotient
Dividend
00001110
-0010
00011100
-0010
00111000
-0010
00011000
00110000
-0010
0001
Remainder
Division Hardware
32-bit ALU
42
Divisor
32 bits
Two registers:
Divisor register: 32 bits

Remainder register: 64 bits
(right half also used for storing quotient)
32-bit ALU
Remainder
Shift right
Shift left
Write
Control
test
64 bits
Operations:
32-bit divisor is always subtracted from the left half of remainder register
The result is written back to the left half of the remainder register
The right half of the remainder register is initialized with the dividend
Left shift remainder register by one before starting
The new order of the operations in the loop is that the remainder register
will be shifted left one time to many
Thus, final correction step: must right shift back only the
remainder in the left half of the remainder register
14
Division Algorithm Improved Version
43
Start
1. Shift the Remainder register left 1 bit
2. Subtract the Divisor register from the

left half of the Remainder register and
place the result in the left half of the
Remainder register
Remainder >
0
Test Remainder
3a. Shift the Remainder register to the

left, setting the new rightmost bit to 1
Remainder < 0
3b. Restore the original value by adding

the Divisor register to the left half of the
Remainder register and place the sum
in the left half of the Remainder register.
Also shift the Remainder register to the
left, setting the new rightmost bit to 0
32nd repetition?
No: < 32 repetitions
Yes: 32 repetitions
Done. Shift left half of Remainder right 1 bit
Example
44
Division of a 4-bit unsigned number (0111) by another one (0011)

Iteration
Divisor (D)
Remainder (R)
0011
0000 0111
0000 1110
1101 1110
0000 1110
0001 1100
1110 1100
0001 1100
0011 1000
0000 1000
0001 0001
1110 0001
0001 0001
0010 0010
0001 0010
0
1
2
3
4
extra
Remainder
correction
Remark
Initial state
R = R << 1
Left(R) = Left(R) D
Undo
R = R << 1, R0 = 0
Left(R) = Left(R) D
Undo
R = R << 1, R0 = 0
Left(R) = Left(R) D
R = R << 1, R0 = 1
Left(R) = Left(R) D
Undo
R = R << 1, R0 = 0
Left(R) = Left(R) >> 1
Quotient
Signed Division
45
Similar to signed multiplication, the signs of the divisor and dividend
are checked to determine whether the results (quotient and

remainder) should be negated.
Two rules to follow:
If the signs of the divisor and dividend are different, then the
quotient should be negated.
If the remainder is nonzero, then its sign should be the same as
that of the dividend.
Example:
Dividend
+7
-7
+7
-7
Divisor
+2
+2
-2
-2
Quotient Remainder
+3
+1
-3
-1
-3
+1
+3
-1
15
Divide in MIPS
46
div ('divide')
divu ('divide unsigned')
Examples:
div
divu
$s1, $s2
$s1, $s2
# Lo = $s1 / $s2; Hi = $s1 mod $s2

# Lo = $s1 / $s2; Hi = $s1 mod $s2
MIPS Instructions for Floating-Point Operations
47
MIPS supports IEEE 754 single-precision and double-precision formats

Addition:
add.s ('addition, single'), add.d ('addition, double')
Subtraction:
sub.s ('subtraction, single'), sub.d ('subtraction, double')
Multiplication:
mul.s ('multiplication, single'), mul.d ('multiplication, double')
Division:
div.s ('division, single'), div.d ('division, double')
Comparison:
c.x.s ('comparison, single'), c.x.d ('comparison, double')

where x may be eq, neq, lt, le, gt, ge
Branch:
bclt ('branch, true'), bclf ('branch, false')
Key Concepts to Remember
48
2's complement representation for signed numbers

A 32-bit ALU can be built by connecting 32 1-bit ALUs together
Subtraction makes use of addition
SLT makes use of subtraction
A multiplexor is used in an ALU to select appropriate result
Carry lookahead adders better than ripple carry adders
Multiplication: through a series of addition and shift operations
Division: through a series of subtraction and shift operations
Make sure you understand how the hardware algorithms work
Overflow (a type of exception)

A result of addition or subtraction
Detected by checking the signs of the operands and result
16

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UEEA4653: Computer Architecture

Arithmetic for Computers

UUEA4653 May 2015

Introduce 2's complement numbers and their addition & subtraction

Copyright Dr. Lai An Chow

Arithmetic for Computers

Base, Representation and Value

Numbers can be represented in any base

Human: decimal (base 10); Computer: binary (base 2)

The value of the ith digit d is d x Basei

Bits are numbered 0, 1, 2, 3 from right to the left in a word

most significant bit (MSb)

least significant bit (LSb)

Value of the 32-bit binary numbers =

(b31 x 231) + (b30 x 230) + + (b1 x 21) + (b0 x 20)

Arithmetic for Computers

i.e. 0000 1010 0000 0101 0000 1100 0000 01102

Copyright Dr. Lai An Chow

Arithmetic for Computers

2's Complement Representation

All computers use 2's complement representation for signed numbers

The positive half uses the same representation as before

Invert bits to get 1s complement

1111 1111 1111 1111 1111 1111 1111 1001 2 = -710

ii) Add 1 to get 2s complement

1111 1111 1111 1111 1111 1111 1111 1010 2 = -610

Smallest integer represented by a MIPS word:

Immediate part for lw, sw & addi are represented in 2s complement

Arithmetic for Computers

Signed and Unsigned Numbers

negative or non-negative integers, e.g. int in C/C++

non-negative integers, e.g. unsigned int in C/C++

Operations for unsigned numbers

sltu (set on less than unsigned), sltiu

Copyright Dr. Lai An Chow

Arithmetic for Computers

Signed vs. Unsigned Comparison

$s0 1111 1111 1111 1111 1111 1111 1111 11112

slt $t0, $s0, $s1

Copyright Dr. Lai An Chow

Arithmetic for Computers

Why sign extension?

-2 (16 bits -> 32 bits):

If the immediate in the addi instruction = 1111 1111 1111 1110,

Copyright Dr. Lai An Chow

Arithmetic for Computers

Addition and Subtraction

Subtraction uses addition

The result is too large to fit into a word

Copyright Dr. Lai An Chow

Arithmetic for Computers

0000 0000 0000 0000 0000 0000 0000 0111 2

0000 0000 0000 0000 0000 0000 0000 1101 2

0000 0000 0000 0000 0000 0000 0000 0111 2

= 1 0000 0000 0000 0000 0000 0000 0000 0001 2

Copyright Dr. Lai An Chow

Arithmetic for Computers

Addition (1073741824 + 1073741824 = 2147483648):

0100 0000 0000 0000 0000 0000 0000 0000 2

1000 0000 0000 0000 0000 0000 0000 0000 2

if considering MSb a sign bit

Copyright Dr. Lai An Chow

Arithmetic for Computers