Beruflich Dokumente
Kultur Dokumente
Week 1
Spring 2014
EECS 170C
Vin
R1 = 1 k
C2 = 1 pF
Vout
ideal
op-amp
R2
Av =
=1
R1
f 3dB
Spring 2014
EECS 170C
1
=
= 159 MHz
2 C2 R2
Prof. M. Green / U.C.
Irvine
Specifications:
Av = 2
Vin
R1
C2
Vout
ideal
op-amp
R2
Av =
=2
R1
1
f 3dB =
= 500 10 6
2 C 2 R2
Spring 2014
EECS 170C
Set C2 = 1 pF
R2 = 318
R1 = 159
R1
C2
Vout
f3dB
Spring 2014
EECS 170C
f
Prof. M. Green / U.C.
Irvine
Vin
R1
C2
Vout
C1
R3
H ( s) =
R2
1
VG
Vin
Vout
Vin
Vout
Spring 2014
EECS 170C
Analog
representation:
Digital
representation:
a3 a2 a1 a0
16
possible digits Dynamic Range = 16
Spring 2014
EECS 170C
Continuoustime signaling:
Discrete-time
signaling:
Spring 2014
EECS 170C
Passive Components
Power dissipation in a resistor:
PD = I V = I 2 R 0
VS2
Power supplied by VS: PS =
RS + RL
Power dissipated in RL:
2
#
&
RL
1
PL = %VS
(
RS + RL ' RL
$
PL
RL
=
<1
Power gain:
PS RS + RL
10
Active Components
A component that is not passive is said to be active.
PL
rin2
RL
2
=A
PS
RS + rin R + r
L
out
A2
rin
RL
Power amplification is possible with active devices -- thats why we need transistors.
Spring 2014
EECS 170C
11
Spring 2014
EECS 170C
12
Spring 2014
EECS 170C
13
Circuit Realization:
Discrete vs. Monolithic
Spring 2014
EECS 170C
14
Example of Matching
Design an amplifier with an accurate gain of +10:
Assume Av can take values between 10,000 and 50,000.
V+ = Vin
V = Vout
Vout
1
=
1
1
Vin
+
Av 1 + R1 R2
R2
R1 + R2
Vout = Av (V+ V )
Very small
depends only
on resistor ratio
Let R1 = 9k , R2 = 1k:
Av = 10,000 Vout /Vin = 9.990
Av = 50,000 Vout /Vin = 9.998
Spring 2014
EECS 170C
15
Manufacturability of ICs
1. Die Size
X
X
Spring 2014
EECS 170C
16
2. Power Dissipation
Power dissipated in the IC is converted to heat, raising the temperature of the
die & package.
Elevated die temperature can degrade circuit performance or even
permanently damage the silicon.
To accelerate heat removal, a heat sink may need to be used, requiring more
space.
17
3. Robust Design
IC must operate properly in the presence of variations in:
Processing in fabrication technology
Individual component values can vary 15% or more
Voltage supply
Supply voltages can vary 10%
Temperature
Circuit should operate to spec at 0--70 C ambient
temperature
Spring 2014
EECS 170C
PVT
18
Use of Approximation
KCL at Vout:
F IES eVX
VT
$ (V V )
1 IES &e in out
%
KCL at VX:
(2 F ) eVX
VT
1 +
VT
'
1) = 0
(
1
VX VCC = 0
R
Spring 2014
EECS 170C
Prof.
Prof.
M. Green
M. Green
/ U.C.
Univ. of California,
Irvine
Irvine
19
My Research
1. High-speed frequency divider:
Spring 2014
EECS 170C
20
&W #
$ !
% L "D
&W #
$ !
% L "D
&W #
$ !
% L "C
&W #
$ !
% L "L
&W #
$ !
% L "L
&W #
$ !
% L "C
&W #
$ !
% L "D
&W #
$ !
% L "D
&W #
$ !
% L "L
&W #
$ !
% L "C
&W #
$ !
% L "L
&W #
$ !
% L "C
Spring 2014
EECS 170C
21
Designed at Broadcom
using 0.13 m CMOS process;
shunt-peaking was used.
Spring 2014 EECS 170C
22
Normally
the
equalizer
and
CDR
are
designed
and
implemented
as
separate
blocks.
Common
elements
in
each
of
the
two
blocks
can
be
iden?ed
and
combined...
Spring 2014
EECS 170C
23
Circuit Details
L
R
AN
L
R
OUTN
OUTP
AP
BP
V0
BN CP
V1
CN DP
V3
V2
L1
L1
Input Data
a0
a1
+
- -
Summer
DN
R1
L2
R1
R2
L2
R2
a2
a3
2mA
4mA
Slicer
FB path
DFF1
DFF2
DFF3
DFF4
DFF5
V-I
Rp
Cp
C2
VCO
Alexander PD
Recovered clock
Retimer
Spring 2014
EECS 170C
Retimed Data
24
Measurement Setup
Cable
Anritsu MP1763B
Pattern Generator
1.8V
Anritsu 69137B
Synthesized Signal
Generator
INDATA_P
DFE &
CDR
INDATA_N
RF Clock
OUT_CLK_N
OUTDATA_P
Trigger
Clock
OUTDATA_N
OUT_CLK_P
V_UP
V_DOWN
HP 83480A
Oscilloscope
Test
setup
Test
board
Spring 2014
EECS 170C
25
Recovered
clock
RJ
=
1.83
ps
rms
3.6
m
cable
Cable
output
eye
diagram.
Spring 2014
EECS 170C
Recovered
clock
RJ
=
2.15
ps
rms
Prof. M. Green / U.C.
Irvine
D-FF
Din1
Q
D-FF
A
B
Select
Latch
A
B
Select
D-FF
re?mer
10 GHz
Din2
Q
D-FF
Din3
Q
D-FF
Latch
20 GHz
40 GHz
A
B
Select
Latch
D-FF
20
GHz
10
GHz
10 GHz
20 GHz
40 GHz
PLL
10
GHz
Spring 2014
EECS 170C
27
Dout
Spring 2014
EECS 170C
28
40 Gb/s
output
40 Gb/s
output
40Gb/s
Distributed
buffer
625 MHz
Reference
clock
20 GHz clock
output
Push-push
differential
VCO
40Gb/s MUX
and retimer
Clock
buffers
PLL
20Gb/s inputs
20 Gb/s
inputs
Spring 2014
EECS 170C
29
40Gb/s
MUX
output
(Dieren?al)
with
450
mV
dieren?al
peak-to-peak
ver?cal
eye
opening
and
1.14
ps
rms
jiXer
Spring 2014
EECS 170C
30