Beruflich Dokumente
Kultur Dokumente
Proceedings
of 2013 University
International Conference
Fuzzy
Theory and ItsTaipei,
Application
National
Taiwan
of Scienceonand
Technology,
Taiwan, Dec. 6-8, 2013
National Taiwan University of Science and Technology, Taipei, Taiwan, Dec. 6-8, 2013
Prabhavathi P
M.Tech Student
Department of Electronics and Communication
BNM Institute of Technology, Bangalore, India
Associate Professor
Department of Electronics and Communication
BNM Institute of Technology, Bangalore, India
e-mail: manubn88@gmail.com
e-mail: prabha@bnmit.org
I. INTRODUCTION TO AMBA
The Advanced Microcontroller Bus Architecture
(AMBA) interconnect protocol is developed by ARM
and it is the de facto industry-standard on-chip interconnect specification that serves as a framework for SoC
designs, effectively providing the digital glue that
binds IP process together. It is also the backbone of
ARMs design reuse strategy. AMBA specifies a hierarchy of bus types, tailored to differing priorities found
across the interconnect structure of SoC designs.
A. AMBA Buses
Three distinct buses are defined within the AMBA
specifications [1]. Advanced High-performance Bus
(AHB), Advanced System Bus (ASB), Advanced Peripheral Bus (APB).
Figure 1 shows, Microprocessors, DMA controllers,
memory controllers and other higher performance blocks
are suited for connection to the AHB/ASB. Lower performance blocks such as UARTs, General Purpose Input/Output (GPIO) and Timers are suited for connection
to the APB.
The AMBA specification has been derived to satisfy four
key requirements. 1) To facilitate the right-first-time
development of embedded microcontroller products with
one or more CPUs or signal processors. 2) To be technology independent and ensure that highly reusable peripheral and system macro cell can be migrated across a
diverse range of IC processes and be appropriate for
full-custom, standard cell and gate array technologies. 3)
To encourage modular system design to improve
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IV. IMPLEMENTATION
The implementation technique involves modeling the
following:
1) Arbiter
2) Decoder
3) APB Bridge
4) Reset controller
5) Remap and pause controller
A. Arbiter
The AMBA bus specification is a multi-master bus
standard. As a result, a bus arbiter is needed to ensure
that only one bus master has access to the bus at any
particular point in time. Each bus master can request the
bus, the arbiter decides which has the highest priority and
issues a grant signal accordingly. Every system must
have a default bus master which is granted use of the bus
during reset, or when no other bus master requires the
bus. The ASB arbitration is controlled by the AREQ,
AGNT, BLOK and BWAIT signals. When an ASB
master requires use of the bus, it sets its AREQ output
line HIGH. This is sampled by the arbiter, on the falling
edge of BCLK, and the AGNT outputs change according
to the arbitration priority scheme used by the system. The
BLOK and BWAIT signals are used to extend the
granted period to allow masters to finish transfers before
bus master handover begins. If BLOK is set HIGH by the
current master, and a higher priority master requests the
bus, handover will not start until BLOK is set LOW,
showing that the locked transfer has finished.
The following arbitration priorities (from highest to
lowest) are implemented in the default system: Test interface controller (highest), Bus master 1, Bus master 2,
ARM processor (lowest).
B. Decoder
The decoder performs three functions, it generates the
slave select signals (DSELx) for each of the bus slaves,
indicating that a read or write access to that slave is
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ARBITER
GRANTS
DEFAULT
MASTER
ARBITER
REQUESTS
WRITE
POWER
ON RESET
READ
Fig. 11. ChipScope Pro analysis with active high power on reset
Table 1. Area report
Instance
Cells
Bridge
234
Cell Area
Net Area
Wireload
2141
<none> (D)
PERIPHERAL
SELECTED
234
Leakage
Power (nW)
5591.030
Total
Power
(nW)
37808.
347
Dynamic
Power
(nW)
32217.318
APB BRIDGE
RESET
CONTROLLER
REMAP
ADDRES
PAUSE
ADDRESS
DECODER
REMAP AND
PAUSE
GRANT
ARBITER
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VII. CONCLUSIONS
This paper presents modeling and simulation results of
AMBA ASB APB Bridge. From the simulation results
we can conclude that upto four masters can be connected
over the ASB with a priority based arbitration scheme
and these masters can communicate with the peripherals
over the APB Bridge. In a way the APB Bridge provides
a direct translation of the ASB masters to the peripherals
connected to the APB.
VIII. REFERENCES
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
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