Novel Class of Energy-Efficient Very High-Speed

Conditional PushPull Pulsed Latches

AIM:
The main aim of the project is to design Novel Class of Energy-Efficient Very
High-Speed Conditional PushPull Pulsed Latches.

(ABSTRACT)
In this paper, a new class of pulsed latches is presented and experimentally
assessed in 65-nm CMOS. Its conditional pushpull pulsed latch topology is based
on a pushpull final stage driven by two split paths with a conditional pulse
generator. Two circuit implementations of the concept are discussed, with their
main difference being in the pulse generator, which can be either shared (CSP3L)
or not (CP3L).Measurements show that the proposed topology is very fast,as it
outperforms the well-known transmission gate pulsed latch (TGPL) by 1.52;
hence the proposed pulsed latch has the highest performance ever reported. The
proposed pulsed latch is also shown to significantly improve the energy efficiency
compared to the state of the art. Indeed, improvement in ED3 product (energy
delay3) over TGPL was found for designs targeting minimum ED3. For designs
targeting minimum ED,improvement was found in ED product. This comes at the
cost of a 1.151.35 cell area penalty, which translates into an overall area
increase well below 1% in typical systems.Measurements on 256 replicas confirm
that the above benefits are kept in the presence of variations. Accordingly, the
proposed class of pulsed latches goes beyond the current state of the art and is well
suited for VLSI systems that require both high performance and energy efficiency .
Proposed Architecture:

Advantage:
Pushpull final stage and split paths in the first stage enable a significant reduction
in path and parasitic effort. proposed topologies are fastest ever reported. More
importantly, the energy efficiency of the proposed pulsed latches enables a
significant improvement beyond the state of the artFinally, the CP3L and CSP3L
were shown to be equivalent in terms of energy and performance, hence both
topologies are equally worth considering when designing highly energyefficient
systems..
BLOCK DIAGRAM:

General scheme of the proposed class of pulsed latches

TOOLS: hspice_vA-2008.03, t-spice

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