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Code Coverage Tutorial

Table Of Contents
Code Coverage Tutorial .................................................................................................................. 1
Introduction .................................................................................................................................. 1
Loading Sample Design............................................................................................................... 1
Code Coverage Setup ................................................................................................................. 2
Checking Results ......................................................................................................................... 3
Conclusion ................................................................................................................................... 5

Code Coverage Tutorial

Introduction
With the growing complexity of today's designs, testing the validity of HDL designs becomes
increasingly difficult. Designers have to answer the question of whether or not the design was
fully tested, which basically means if all statements were executed. Designers usually have to
take a calculated risk and decide when their designs are fully tested and all "dangerous corners"
are checked. Unfortunately, there is still a degree of uncertainty in this statement that leaves the
risk that some areas in a design that are left unchecked can still cause problems. When time-tomarket becomes crucial to a project there is absolutely no room for doubt on this issue. Utilizing
the new Code and Branch Coverage feature in Active-HDL Aldec helps engineers to remove the
uncertainty of the design testing.
Code Coverage is a debugging tool that allows users to check how satisfactory the source code
has been developed. Code Coverage checks if all VHDL or Verilog statements from a testbench
are executed during the simulation.
Branch Coverage is a part of the Code Coverage engine. It examines branches of the IF or CASE
statement and checks how many times a true or false condition was met by each branch during
the simulation. Designers see clearly if their source code is fully covered by their testbenches,
which allows to make sure if all VHDL or Verilog statements were executed.

Loading Sample Design

In this tutorial we will use the freq_meter sample design that is shipped with the Active-HDL
software. The design you have just opened has to be compiled, before you advance to the
simulation phase.
1. In the first step, run Active-HDL and open the Workspace/Design Explorer (File | Open
Workspace/Design Explorer) to load the freq_meter workspace it is located in the
Samples/VHDL_Designs folder. Before Code Coverage can be used, the design should be
compiled and the top-level unit should be selected. In our design, we will compile all files and
select top-level unit as it is illustrated in Figure 1. To do so, choose the menu command Design |
Compile All and then point to the testbench (stimulusfromfile) top-level unit.

Code Coverage Tutorial

Figure 1. Setting testbench (stimulusfromfile) as top-level.

Code Coverage Setup

2. When this operation is completed you need to enable the generation of Code Coverage data.
To do so, go to the Design menu and choose Settings.
3. In the Design Settings window, switch to the Code Coverage/Profiler tab:

Figure 2. The Design Settings window.

4. Select the Coverage radio button that enables the generation of Code Coverage data. In the
Output directory field, you will see the path to the folder where the results.ccl will be created. If

Code Coverage Tutorial

required, you can specify another location by pressing the browsing button (...). During the
simulation, the simulator will write the Code Coverage data to this folder.
5. After you have specified Code Coverage settings, you can close the Design Settings window
and run the simulation (Simulation | Initialize Simulation, then Run (Alt+F5)). Code Coverage
data is gathered during the simulation, however, the file specified in the Output directory field is
created when you choose End Simulation from the Simulation menu.
When the Collect data per instance checkbox is selected, the coverage data will be collected
separately for each instantiated object. The Code Coverage Viewer displays this information in a
separate tab - Instances. By default, this option is not set and Code Coverage collects the data
on a per-unit basis.
The Collect data for all units checkbox determines whether the coverage data should be limited
to objects residing in the current working library or extended to objects from external system
libraries as well.

Checking Results
When simulation is complete, you can then invoke the Code Coverage Viewer from the Tools
menu and view the results generated by Code Coverage.
6. Selecting Code Coverage brings up the Code Coverage Viewer window. In this window,
choose Open (Ctrl+O) from the File menu or click the Open File icon. This window allows you to
find and point to the file containing the Code Coverage data that will be displayed in the Code
Coverage Viewer window.

Figure 3. Loading the Code Coverage data.

Double-click the results.ccl file or select it and press Open. The Code Coverage data is loaded
into the Code Coverage Viewer window as it is presented in Figure 4.

Code Coverage Tutorial

Figure 4. The Code Coverage Viewer window.

The Source Code window displays the following columns:

Line
Displays the line numbers of the source code.

Count
Displays an execution count for each line of the HDL code. If a number of lines has been
collapsed with - sign, the Count Column displays the total for all collapsed lines. If a line
contains more than one executable statement, the count number is followed by an
asterisk. Moving the mouse pointer over that line displays a tooltip with execution counts
for each statement

BC
Displays Branch Coverage data for the IF or CASE construct.
When the source code contains the IF construct then the BC column displays the number
of conditions that evaluated to True (e.g. 3t) and the number of conditions that evaluated
to False (e.g. 4f) during the simulation. True (t) means that the condition in the selected if
branch was met and this branch was executed. False (f) means that the condition in the if
branch was not met and the elsif or else branches were executed instead. The total
number of executions is displayed in the Count column.
When the source code contains the CASE construct then the BC column displays the
number of when branches that covered all explicitly listed choices and the total number of
branches within the construct.

By selecting the Details tab in the right pane, you can see details in the form of graphical charts
describing the Code Coverage results of your project.

Code Coverage Tutorial

Figure 5. The Details tab of the Code Coverage Viewer window.

The upper part presents the results generated by the Code Coverage engine. The Results for
selected item chart shows the number of executed statements for the selected instance in green
and the number of statements that were not executed within this instance in red.
The lower part presents the results generated by the Branch Coverage engine. The Branch
Coverage for selected item chart shows the number of executed branches for the selected
instance in green and the number of branches that were not executed in red.

Conclusion
Code/Branch Coverage is a very powerful debugging tool that provides designers an efficient
analysis of the currently used testbench. This tool can decrease the time required for verification
and optimize the development process by showing users if they still need to develop their tests
and which part of the design needs to be tested.
Thank you for using Active-HDL!