Beruflich Dokumente
Kultur Dokumente
NameoftheFaculty:B.BHARATHI
LectureDuration:50Min.
LessonPlan
Lectur
TopicsasperJNTU
Suggested
Topicstobecovered
PageNo
eNo.
syllabus
Book
UNITI:NUMBERSYSTEMS&CODES,BOOLEANALGEBRA&SWITHCHINGFUNCTIONS
Introduction
1
2
3,4
5
6,7
8
ComplementRepresnetation
BinaryArithmetic
IntroductiontoPhilosophyofNumber
systems
1'scomplement&2'scomplement
Addition,subration,multiplication,divis
ionofbinarynumbers
excesscodes,Binarycodes
ErrorcorrectingCodes,Detecting
T1,T2
T1
T1,T2
9
10
11
BinaryCodes
ErrorCodes
HammingCodes
FundamentalPostulates
BasicTheorems
SwitchingFuctions
12
CanonicalForms
TypesofConanicalForms
T1,T2
13
StandardForms
TypesofStandardForms
T1,T2
14
Algebraicsimplification
DigitalLogicGates
T1,T2
15,15
DifferentTypeofGates
Basicgates,Notgate
T1,T2
17
DifferentTypeofGates
PropertiesofXORgates,
T1,T2
Std.Deviation,Variance,Deviation,Range
DifferentPostulatesofBoolean
PropertiesandTheoremsofBoolean
DifferenttypesofSwitchingFuctions
usedinGates
T1,T2
T1,T2
T1.
T1
T1,T2
T1,T2
18
DifferentTypeofGates
UniversalGates,Realisation
T1,T2,R1
UNITII:MINIMIZATIONOFSWITCHINGFUCTIONS,COMBINATIONALLOGICDESIGN
19
20,21
Mapping
PrimeImplicants
22,23
Don'tCareCombinations
2425
26
27
28
29,30
31,32
33,34
35
36,37
MinimalForms
MethodsofMapMethods
DifferenttypesofPrimeImplicants,
SimpleProblems
MappingandDon'tcare
evaluation,problems
SOP&POSForms
PropertiesandRulesofTubular
methods
Tabularmethod
ImplicantChart,Simplification Properties,Rules,SimpleProblemson
charts
Rules
DesignofLogicgates
ConvectionalLogicGates
Coders
Encoders&DecodersDesign
Plexers
Multiplexers,Demultiplexers
ModularDesign
MUXrealisation,ParityBitGenerators
Converters
Realizations
CodeConverters
HaxardFreeRealisations
T1,T2,R1
T1,T2
T1,T2,R1
T1,T2,R1
T1,T2,R1
T1,T2,R1
T1,T2
T1,T2,R1
T2,R1,R2
T1,T2,R1
T1,T2,R2
T1,T2,R2
UNITIII:SEQUENTIALMACHINESFUNDAMENTALS
38
39,40
41,42
43
Introduction
Fundamentals
Flipflops
Flipflops
remarks
T1
T1,T2
T1,T2,R2
T1,T2
BB
BB
BB
BB
44
45
Conversions
Timing consideration
T2,R1,R2
T2,R1
UNITIV:SEQUENTIALCIRCUITDESIGNANDANALYSIS
46
47,48
49
Classification
FlipFlops
TruthTables(FF)
50,51
SequentialCircuitDesign
52,53
ShiftCounters
Sequentialcircuits(Synchronous
,Asynchoronous,Pulsemode,Level
mode)
Basics,Types,TruthTables
T1,T2,R1
Triggering&ExcitationTables
T1,T2,R2
DesignofCircuitDesign,Sequentail
Detector
SerialBinaryAdder,ShiftCounters
T1,
T2,R2
T1,T2
DesignofaModuloNRing
T1,T2,R2
Design
UNITV:SEQUENTIALCIRCUITSANDALGORITHMICSTATEMACHINES
54
55
FiniteStateMachine
Capabilities&Limitaions
L1
56
Mealy&MooreModels
DesignCapabilities
L2
57
SpecifiedSequentialMachines
Minimization
PartitionTechniques
MethodsofPartition
mergermethods
ChartsinMergerMethods
L6,L7
ASM
BasicFeatures,simpleexamples
L1,L2
63
systemdesign
datapath&controlsubsystems
L3
64
ControlImplimentations
SimpleExamples
L4
65
WeighingMachine
examplesProblems
L5
66
BinaryMultipler
examplesProblems
L6
58,59
60
61,62
L3,L4
L5
TEXTBOOKS:
1T1:DIGITALDESIGNMorrisMano,3rdEdition,PHI
2T2.SwithchingTheoryandLogicDesignGodsey.
REFERENCES:
1R1:FundamentalsofLogicDesignAAnandKumar,2008.
R2:DigitalLogicApplicationsandDesignJohnMYarbrough,2006,ThomsnPublications.