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XILINX Aerospace solutions Olivier Olivier MEHAIGNERIE MEHAIGNERIE / / SILICA SILICA Joel Joel LE LE

XILINX Aerospace solutions

OlivierOlivier MEHAIGNERIEMEHAIGNERIE // SILICASILICA JoelJoel LELE MAUFFMAUFF // XILINXXILINX

December 2008

MEHAIGNERIE / / SILICA SILICA Joel Joel LE LE MAUFF MAUFF / / XILINX XILINX December

Xilinx Confidential

MEHAIGNERIE / / SILICA SILICA Joel Joel LE LE MAUFF MAUFF / / XILINX XILINX December
OUTLINE OUTLINE • • Xilinx Xilinx introduction introduction • Products overview • Aerospace & Defense

OUTLINEOUTLINE

XilinxXilinx introductionintroduction

Products overview

Aerospace & Defense introduction

Avionics solutions

Products offering

Atmospheric Environement Testing & Results

RTCA DO-254 / EUROCAE ED-80

Space solutions

Product offering

Space Environment Testing & Results

Mitigations techniques

XTMR architecture & TMRtool

Summary

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2

Xilinx Confidential

techniques – XTMR architecture & TMRtool • Summary 2008-12-02_Xilinx-CNES CCT FPGA-JLM 2 Xilinx Confidential

XilinxXilinx FactsFacts

Worldwide leader in programmable solutions

Founded in 1984

$1.8B in revenues in FY ’08

~3,500 employees worldwide

20,000+ customers worldwide

Pioneer of the fabless semiconductor model

Inventor of the FPGA

First to 180nm, 150nm, 130nm, 90nm and 65nm

of the FPGA – First to 180nm, 150nm, 130nm, 90nm and 65nm – Currently ship over

Currently ship over 98% of high-end 65nm production FPGAs in the world

50% PLD market segment share

Larger than all competitors combined

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Xilinx Confidential

market segment share – Larger than all competitors combined 2008-12-02_Xilinx-CNES CCT FPGA-JLM 3 Xilinx Confidential

InnovationInnovation atat XilinxXilinx

1,325 Patents XilinxXilinx PatentPatent HallHall
1,325 Patents
XilinxXilinx PatentPatent HallHall

Industry’s first 65-nm FPGAs with

30% higher performance *

35% lower dynamic power *

65-nm ExpressFabric technology

2 nd Generation Triple-oxide technology

Embedded PCIe and GbE interfaces

Enhanced Sparse Chevron packaging

Columnar architecture (ASMBL)

ChipSync™

IP immersion

Differential clock tree

Optional FIFO logic

XtremeDSP slice

Tri-Mode hard Ethernet MAC

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Xilinx Confidential

Tri-Mode hard Ethernet MAC 2008-12-02_Xilinx-CNES CCT FPGA-JLM 4 Xilinx Confidential * Compared to 90nm Virtex-4 FPGAs

* Compared to 90nm Virtex-4 FPGAs

DigitalDigital ConvergenceConvergence DrivesDrives DemandDemand

Voice Video Data Xilinx Confidential
Voice
Video
Data
Xilinx Confidential

The Core Infrastructure ( VirtexVirtex )

• Performance & capability are premium

• Power & cost constrained

• Longer time-in-market

The Expanding Edge ( SpartanSpartan )

• Cost and flexibility are key

• “Moderate Performance”

• Shorter time-in-market

In-The-Hand ( CoolRunnerCoolRunner IIII )

• Cost and size are premium

• Power is key

• Shortest time-in-market

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XilinxXilinx ServesServes aa WideWide RangeRange ofof MarketsMarkets

• Infrastructure • Wireless • Infotainment • Instrumentation • •• MilComm Crypto • • Avionics
• Infrastructure
• Wireless
• Infotainment
• Instrumentation
• •• MilComm
Crypto
• • Avionics
Space
• Displays
• Handhelds
• Surveillance
• Test and Measurement
6
Xilinx Confidential

Communications

Automotive

AerospaceAerospace andand DefenseDefense

Consumer

Industrial Scientific and Medical

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OUTLINE OUTLINE • Xilinx introduction • • Products Products overview overview • Aerospace & Defense

OUTLINEOUTLINE

Xilinx introduction

ProductsProducts overviewoverview

Aerospace & Defense introduction

Avionics solutions

Products offering

Atmospheric Environement Testing & Results

RTCA DO-254 / EUROCAE ED-80

Space solutions

Product offering

Space Environment Testing & Results

Mitigations techniques

XTMR architecture & TMRtool

Summary

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Xilinx Confidential

techniques – XTMR architecture & TMRtool • Summary 2008-12-02_Xilinx-CNES CCT FPGA-JLM 7 Xilinx Confidential

ProgrammableProgrammable MethodologyMethodology AbstractingAbstracting AwayAway thethe HardwareHardware

DSPDSP

LogicLogic

ProcessorProcessor

Hardware Hardware DSP DSP Logic Logic Processor Processor System Generator ISE Foundation Simulation Platform Studio
System Generator ISE Foundation Simulation Platform Studio System Design Simulation IP Timing Analysis Utilization
System Generator
ISE Foundation Simulation
Platform Studio
System Design
Simulation
IP
Timing Analysis
Utilization
Power Analysis
HW in the Loop
ChipScope Pro

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Xilinx Confidential

Utilization Power Analysis HW in the Loop ChipScope Pro 2008-12-02_Xilinx-CNES CCT FPGA-JLM 8 Xilinx Confidential

ISEISEDesignDesign SuiteSuite 10.110.1

11 EnvironmentEnvironment forfor Logic,Logic, EmbeddedEmbedded andand DSPDSP DesignDesign

ISE Foundation
ISE
Foundation

Efficient logic implementation

PlanAhead ™
PlanAhead ™

Design

analysis &

planning

ChipScope ™ Pro
ChipScope ™
Pro

Interactive

system

debugging

EDK / Xilinx Platform Studio

Flexible embedded system design & programming

System

Generator

DSP system

design

(Simulink)

AccelDSP ™
AccelDSP ™

DSP algorithm development (MATLAB)

Electronic fulfillment for fast access to updates to updates and evaluation

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Xilinx Confidential

for fast access to updates to updates and evaluation 2008-12-02_Xilinx-CNES CCT FPGA-JLM 9 Xilinx Confidential

IntellectualIntellectual PropertyProperty CoresCores

AugmentAugment YourYour OwnOwn R&DR&D toto MaximizeMaximize ProductivityProductivity andand ReduceReduce riskrisk

Programmable hard IP

Immersed in FPGA fabric

Advantage over soft IP

2x performance

10x lower power

10x less area

Customizable soft IP

Built on FPGA fabric

Examples

LogiCORE (from Xilinx)

AllianceCORE (from partners)

Reference Designs

Advantage over hard IP

Most flexible

Library of >400 blocks

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Example IP for Virtex-5 Platform FPGAs

IP Hard Soft Basic BlockRAM/FIFO, System Monitor BaseBlox, Memory I/Fs… Connectivity PHY (ser./par.), PCIe,
IP
Hard
Soft
Basic
BlockRAM/FIFO,
System Monitor
BaseBlox,
Memory I/Fs…
Connectivity
PHY (ser./par.), PCIe,
GE, timing critical I/O
logic & clocking
Serial and
parallel I/F
protocols…
Processing
PowerPC 440,
Crossbar switch, DMA,
MCI, Bus I/F
MicroBlaze,
peripherals,
accelerators…
DSP
XtremeDSP slice
(MAC)
Algorithms,
FEC…
System
Traffic
functions
Manager…

Xilinx Confidential

DSP XtremeDSP slice (MAC) Algorithms, FEC… System Traffic functions Manager… Xilinx Confidential
® Products Products Solutions Solutions •• 33 ProductProduct FamiliesFamilies:: CPLDsCPLDs ++ SpartanSpartan ++

® ProductsProducts SolutionsSolutions

•• 33 ProductProduct FamiliesFamilies:: CPLDsCPLDs ++ SpartanSpartan ++ VirtexVirtex •• 33 CategoriesCategories::
•• 33 ProductProduct FamiliesFamilies:: CPLDsCPLDs ++ SpartanSpartan ++ VirtexVirtex
•• 33 CategoriesCategories:: XC,XC, XA,XA, XQ(R)XQ(R)
HighHigh--EndEnd
HighHigh--VolumeVolume FPGAsFPGAs
FPGAsFPGAs
HighHigh ReliabilityReliability ProductsProducts
SRAM-based
XC C&I- XA grades
CPLDsCPLDs
XC C&I-grades
Feature Rich
C&I-grades
Low Power
Low Cost
XA
SRAM-based
Feature Rich
High Performance
I M to to B-grades
XQ XC
from
XQR
from
V-grades
Features

512MC

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75KLC

Xilinx Confidential

330LC

from XQR from V-grades Features 512MC 2008-12-02_Xilinx-CNES CCT FPGA-JLM 11 75KLC Xilinx Confidential 330LC Density

Density

OUTLINE OUTLINE • Xilinx introduction • Products overview • • Aerospace Aerospace & & Defense

OUTLINEOUTLINE

Xilinx introduction

Products overview

AerospaceAerospace && DefenseDefense introductionintroduction

Avionics solutions

Products offering

Atmospheric Environement Testing & Results

RTCA DO-254 / EUROCAE ED-80

Space solutions

Product offering

Space Environment Testing & Results

Mitigations techniques

XTMR architecture & TMRtool

Summary

2008-12-02_Xilinx-CNES CCT FPGA-JLM

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Xilinx Confidential

techniques – XTMR architecture & TMRtool • Summary 2008-12-02_Xilinx-CNES CCT FPGA-JLM 12 Xilinx Confidential

XilinxXilinx ContinuousContinuous CommitmentCommitment

Xilinx Xilinx Continuous Continuous Commitment Commitment Virtex-4QV FPGAs: 2008 Virtex-4 QPro ™ FPGAs: 2007

Virtex-4QV FPGAs: 2008

Virtex-4 QPro FPGAs: 2007

Virtex-4QV FPGAs: 2008 Virtex-4 QPro ™ FPGAs: 2007 Xilinx Single-chip Crypto: 2006 Xilinx on Mars: 2004
Virtex-4QV FPGAs: 2008 Virtex-4 QPro ™ FPGAs: 2007 Xilinx Single-chip Crypto: 2006 Xilinx on Mars: 2004

Xilinx Single-chip Crypto: 2006

Xilinx on Mars: 2004

2007 Xilinx Single-chip Crypto: 2006 Xilinx on Mars: 2004 Virtex-II QPro FPGAs: 2004 SEE Consortium formed:
2007 Xilinx Single-chip Crypto: 2006 Xilinx on Mars: 2004 Virtex-II QPro FPGAs: 2004 SEE Consortium formed:
2007 Xilinx Single-chip Crypto: 2006 Xilinx on Mars: 2004 Virtex-II QPro FPGAs: 2004 SEE Consortium formed:

Virtex-II QPro FPGAs: 2004

SEE Consortium formed: 2002

Rad-tolerant Virtex devices : 2000

Consortium formed: 2002 Rad-tolerant Virtex devices : 2000 First Rad-Tolerant devices: 1998 First device qualified to
Consortium formed: 2002 Rad-tolerant Virtex devices : 2000 First Rad-Tolerant devices: 1998 First device qualified to
Consortium formed: 2002 Rad-tolerant Virtex devices : 2000 First Rad-Tolerant devices: 1998 First device qualified to

First Rad-Tolerant devices: 1998 First device qualified to MIL-STD-883: 1989 First field programmable gate array (FPGA): 1985 Xilinx founded: 1984

X i l i n x f o u n d e d : 1 9
X i l i n x f o u n d e d : 1 9

Source: Company reports

1985

1990

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1995

13

2000

Xilinx Confidential

2005

2010

9 8 4 Source: Company reports 1985 1990 2008-12-02_Xilinx-CNES CCT FPGA-JLM 1995 13 2000 Xilinx Confidential

XilinxXilinx inin AerospaceAerospace && DefenseDefense

A&D drives cutting edge technology

Point of Xilinx Technology Spear

2 nd Largest vertical segment within Xilinx

>$240M segment for Xilinx overall

Fastest growing segment within Xilinx

Major area of investment and focus leveraging existing commercial technology

Xilinx is the market leader in A & D with over 50% market share

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Xilinx Confidential

is the market leader in A & D with over 50% market share 2008-12-02_Xilinx-CNES CCT FPGA-JLM

Growth Focused on Transformation

Networked, space-based, precision- guided, rapidly deployable, joint service, modular, and secure.

FPGA’s are the perfect fit!

Flexible and Reconfigurable

Solve new complex Signal Processing demands

System On Chip Capabilities (Feeds SWAP-C *)

Time to Market

Security of HARDWARE vs Software

(*) SWAP-C stands for Size, Weight, Power and Cost

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Xilinx Confidential

vs Software (*) SWAP-C stands for Si ze, Weight, Power and Cost 2008-12-02_Xilinx-CNES CCT FPGA-JLM 15

XilinxXilinx AerospaceAerospace && DefenseDefense IntegrationIntegration SolutionsSolutions

Reduce system complexity and size with integrated features

PowerPC™ processor cores

Ethernet MAC

PCIe™ endpoint blocks

DSP acceleration engines

Digital Clock Management

Increase reliability

Less PCB connections / complexity

SWAP-C: Reduced size, weight, power and cost

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Xilinx Confidential

/ complexity • SWAP-C: Reduced size, weight, power and cost 2008-12-02_Xilinx-CNES CCT FPGA-JLM 16 Xilinx Confidential

OUTLINEOUTLINE

Xilinx introduction

Products overview

Aerospace & Defense introduction

AvionicsAvionics solutionssolutions

• • Avionics Avionics solutions solutions – – Products Products offering offering – –

ProductsProducts offeringoffering

AtmosphericAtmospheric EnvironementEnvironement TestingTesting && ResultsResults

RTCARTCA DODO--254254 // EUROCAEEUROCAE EDED--8080

Space solutions

Product offering

Space Environment Testing & Results

Mitigations techniques

XTMR architecture & TMRtool

Summary

2008-12-02_Xilinx-CNES CCT FPGA-JLM

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Xilinx Confidential

techniques – XTMR architecture & TMRtool • Summary 2008-12-02_Xilinx-CNES CCT FPGA-JLM 17 Xilinx Confidential
SpartanSpartan--33 familyfamily OptimizedOptimized PlatformsPlatforms SaveSave CostCost Spartan-3 Spartan-3 Platform
SpartanSpartan--33 familyfamily
OptimizedOptimized PlatformsPlatforms SaveSave CostCost
Spartan-3 Spartan-3 Platform Platform
– – For For Highest Highest Density Density & & Pin-count Pin-count Appls Appls
Spartan-3E Spartan-3E Platform Platform
– – Logic Logic Optimized Optimized
Spartan-3A Spartan-3A DSP DSP Platform Platform
– – DSP DSP Optimized Optimized
Spartan-3A Spartan-3A & &
Spartan-3AN Spartan-3AN Platform Platform
– – I/O I/O Optimized Optimized
Hibernate mode
Suspend mode
Device DNA
Non-Volatile version
Etc…
I/Os
Logic Cells

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Xilinx Confidential

Device DNA Non-Volatile version Etc… I/Os Logic Cells 2008-12-02_Xilinx-CNES CCT FPGA-JLM 18 Xilinx Confidential

VirtexVirtex--55 FPGAFPGA FamilyFamily

TheThe UltimateUltimate SystemSystem IntegrationIntegration PlatformPlatform

65-nm platforms

Logic On- chip RAM DSP Capabilities Parallel I/Os Serial I/Os PowerPC ®

In Production

LX

High-performance

logic

Logic
Logic

YES

LXT

High-perf. logic w/ low-power serial I/Os

Logic + Serial
Logic + Serial

YES

SXT

DSP and memory- intensive apps w/ low- power serial I/Os

DSP + Serial
DSP + Serial

YES

FXT

Processing and memory- intensive apps w/ highest-speed serial I/Os

Emb. + Serial
Emb. + Serial

Samples Now

EasyPath low-risk, conversion-free cost reduction for all platforms: 30-75% cost savings

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Xilinx Confidential

cost reduct ion for all platforms: 30-75% cost savings 2008-12-02_Xilinx-CNES CCT FPGA-JLM 19 Xilinx Confidential

XilinxXilinx FPGAFPGA roadmaproadmap

MontMont BlancBlanc TXTTXT
MontMont
BlancBlanc
TXTTXT

Greater Logic capacity

• Flexible On-Chip Memory

• Greater performance and more I/O standards

• Broad spectrum of Serdes solutions

St. Andrews Spartan-3
St.
Andrews
Spartan-3

• Abundand DSP resources

• Reducing Power Through Advanced Design and Process

• St. Andrews: The Lowest Cost, Easy to Use FPGA

• Mont Blanc: Highest Performance, Most Advanced FPGA

FPGA • Mont Blanc: Highest Performance, Most Advanced FPGA 2008-12-02_Xilinx-CNES CCT FPGA-JLM 20 Xilinx Confidential

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Xilinx Confidential

FPGA • Mont Blanc: Highest Performance, Most Advanced FPGA 2008-12-02_Xilinx-CNES CCT FPGA-JLM 20 Xilinx Confidential

OUTLINEOUTLINE

Xilinx introduction

Products overview

Aerospace & Defense introduction

AvionicsAvionics solutionssolutions

• • Avionics Avionics solutions solutions – – Products Products offering offering – –

ProductsProducts offeringoffering

AtmosphericAtmospheric EnvironementEnvironement TestingTesting && ResultsResults

RTCARTCA DODO--254254 // EUROCAEEUROCAE EDED--8080

Space solutions

Product offering

Space Environment Testing & Results

Mitigations techniques

XTMR architecture & TMRtool

Summary

2008-12-02_Xilinx-CNES CCT FPGA-JLM

21

Xilinx Confidential

techniques – XTMR architecture & TMRtool • Summary 2008-12-02_Xilinx-CNES CCT FPGA-JLM 21 Xilinx Confidential

TerrestrialTerrestrial SEESEE testingtesting methodologymethodology

SEE SEE testing testing methodology methodology 1 1 - - Qcrit Qcrit simulation simulation - when

11-- QcritQcrit simulationsimulation - when process ground rules available

22-- AcceleratedAccelerated SEESEE testingtesting @@ LANSCELANSCE - when 1st silicon out of fab

33-- AtmosphericAtmospheric testingtesting // RosettaRosetta PlatformsPlatforms - when large quantity of packaged silicon available

a)a) LowLow NoiseNoise UndergroundUnderground testingtesting forfor ReferenceReference «« 00 »» b)b) AltitudeAltitude testingtesting ((higherhigher isis betterbetter))

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Xilinx Confidential

testing testing ( ( higher higher is is better better ) ) 2008-12-02_Xilinx-CNES CCT FPGA-JLM 22

SRAMSRAM CellCell SEUSEU SimulationsSimulations

This activity is still running Under Xilinx – IM2NP – ONERA collaboration

Goal:Goal:

Better understanding at component level (CMC, BRAM) of physical phenomena induced by SEU / MBUs, of physical phenomena induced by SEU / MBUs,

SER prediction(CMC, BRAM) of physical phenomena induced by SEU / MBUs, 2008-12-02_Xilinx-CNES CCT FPGA-JLM 23 Xilinx Confidential

of physical phenomena induced by SEU / MBUs, SER prediction 2008-12-02_Xilinx-CNES CCT FPGA-JLM 23 Xilinx Confidential
of physical phenomena induced by SEU / MBUs, SER prediction 2008-12-02_Xilinx-CNES CCT FPGA-JLM 23 Xilinx Confidential
of physical phenomena induced by SEU / MBUs, SER prediction 2008-12-02_Xilinx-CNES CCT FPGA-JLM 23 Xilinx Confidential

2008-12-02_Xilinx-CNES CCT FPGA-JLM

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Xilinx Confidential

of physical phenomena induced by SEU / MBUs, SER prediction 2008-12-02_Xilinx-CNES CCT FPGA-JLM 23 Xilinx Confidential

AcceleratedAccelerated SEESEE testingtesting

LosLos AlamosAlamos NeutronNeutron ScienceScience CEnterCEnter

Goal:Goal:

Neutron Neutron Science Science CEnter CEnter Goal: Goal: Get access to Cross Sections Testing done on

Get access to Cross SectionsNeutron Neutron Science Science CEnter CEnter Goal: Goal: Testing done on Virtex (220nm) Virtex-E (180nm) Virtex-II

Testing done onCEnter CEnter Goal: Goal: Get access to Cross Sections Virtex (220nm) Virtex-E (180nm) Virtex-II (150nm)

Virtex (220nm)Goal: Goal: Get access to Cross Sections Testing done on Virtex-E (180nm) Virtex-II (150nm) Virtex-IIpro (130nm)

Virtex-E (180nm)Get access to Cross Sections Testing done on Virtex (220nm) Virtex-II (150nm) Virtex-IIpro (130nm) XPLA3 (350nm)

Virtex-II (150nm)Sections Testing done on Virtex (220nm) Virtex-E (180nm) Virtex-IIpro (130nm) XPLA3 (350nm) (*) CoolRunner-II (180nm)

Virtex-IIpro (130nm)done on Virtex (220nm) Virtex-E (180nm) Virtex-II (150nm) XPLA3 (350nm) (*) CoolRunner-II (180nm) Virtex-4 (90nm)

XPLA3 (350nm) (*)Virtex-E (180nm) Virtex-II (150nm) Virtex-IIpro (130nm) CoolRunner-II (180nm) Virtex-4 (90nm) Spartan-3 (90nm)

CoolRunner-II (180nm)Virtex-II (150nm) Virtex-IIpro (130nm) XPLA3 (350nm) (*) Virtex-4 (90nm) Spartan-3 (90nm) Spartan-3E/3A (90nm)

Virtex-4 (90nm)Virtex-IIpro (130nm) XPLA3 (350nm) (*) CoolRunner-II (180nm) Spartan-3 (90nm) Spartan-3E/3A (90nm) Virtex-5 (65nm)

Spartan-3 (90nm)XPLA3 (350nm) (*) CoolRunner-II (180nm) Virtex-4 (90nm) Spartan-3E/3A (90nm) Virtex-5 (65nm) Virtex-II became

Spartan-3E/3A (90nm)(*) CoolRunner-II (180nm) Virtex-4 (90nm) Spartan-3 (90nm) Virtex-5 (65nm) Virtex-II became Calibration component

Virtex-5 (65nm)Virtex-4 (90nm) Spartan-3 (90nm) Spartan-3E/3A (90nm) Virtex-II became Calibration component

(90nm) Spartan-3 (90nm) Spartan-3E/3A (90nm) Virtex-5 (65nm) Virtex-II became Calibration component

Virtex-II became Calibration component

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Xilinx Confidential

(90nm) Virtex-5 (65nm) Virtex-II became Calibration component 2008-12-02_Xilinx-CNES CCT FPGA-JLM 24 Xilinx Confidential

LowLow NoiseNoise UndergroundUnderground TestingTesting

OCAOCA--LSBBLSBB ReferenceReference levellevel

LSBB scientific and technical characteristics insure that no Soft Error can occur coming from other sources e.g. noise.

(No sensitivity from thermal neutrons have been revealed because XILINX devices don't use Bore 10 or BPSG)

because XILINX devices don't use Bore 10 or BPSG) 200 200 Virtex Virtex - - IIpro
because XILINX devices don't use Bore 10 or BPSG) 200 200 Virtex Virtex - - IIpro
because XILINX devices don't use Bore 10 or BPSG) 200 200 Virtex Virtex - - IIpro

200200 VirtexVirtex--IIproIIpro 130nm130nm

or BPSG) 200 200 Virtex Virtex - - IIpro IIpro 130nm 130nm 2 CMC & 0

2 CMC & 0 BRAM upsetsor BPSG) 200 200 Virtex Virtex - - IIpro IIpro 130nm 130nm 3,060,000 3,060,000 devices devices

3,060,0003,060,000 devices devices hours hours 3,060,000 devicesdevices hourshours

CMC: 54 FIT/Mb, from 7 to 197FIT/Mbupsets 3,060,000 3,060,000 devices devices hours hours @ 95% confidence interval BRAM: 86 FIT/Mb, from 0

@

95% confidence interval

BRAM: 86 FIT/Mb, from 0 to 316FIT/Mb54 FIT/Mb, from 7 to 197FIT/Mb @ 95% confidence interval @ 95% confidence interval 100 100

@ 95% confidence interval

100100 VirtexVirtex--55 // 65nm65nm

interval 100 100 Virtex Virtex - - 5 5 / / 65nm 65nm 2 CMC &

2 CMC & 1 BRAM upsetsinterval 100 100 Virtex Virtex - - 5 5 / / 65nm 65nm 663,000 663,000 devices

663,000663,000 devices devices hours hours 663,000 devicesdevices hourshours

CMC: 138 FIT/Mb, from 17 to 498FIT/Mb1 BRAM upsets 663,000 663,000 devices devices hours hours @ 95% confidence interval BRAM: 291 FIT/Mb,

@ 95% confidence interval

BRAM: 291 FIT/Mb, from 7 to 1621FIT/Mb138 FIT/Mb, from 17 to 498FIT/Mb @ 95% confidence interval @ 95% confidence interval 2008-12-02_Xilinx-CNES CCT

@ 95% confidence interval

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Xilinx Confidential

291 FIT/Mb, from 7 to 1621FIT/Mb @ 95% confidence interval 2008-12-02_Xilinx-CNES CCT FPGA-JLM 25 Xilinx Confidential

AltitudeAltitude testingtesting

Altitude Altitude testing testing OMP OMP + + CMB CMB sites sites 300 300 Virtex Virtex

OMPOMP ++ CMBCMB sitessites

Altitude testing testing OMP OMP + + CMB CMB sites sites 300 300 Virtex Virtex -
Altitude testing testing OMP OMP + + CMB CMB sites sites 300 300 Virtex Virtex -
Altitude testing testing OMP OMP + + CMB CMB sites sites 300 300 Virtex Virtex -
Altitude testing testing OMP OMP + + CMB CMB sites sites 300 300 Virtex Virtex -

300300 VirtexVirtex--55 // 65nm65nm

sites sites 300 300 Virtex Virtex - - 5 5 / / 65nm 65nm 2884m and

2884m and 3794m altitudesites sites 300 300 Virtex Virtex - - 5 5 / / 65nm 65nm 39 CMC

39 CMC & 46 BRAM upsetsVirtex - - 5 5 / / 65nm 65nm 2884m and 3794m altitude 13,800,000 13,800,000 devices

13,800,00013,800,000 devices devices hours hours 13,800,000 devicesdevices hourshours

CMC: 141 FIT/Mb, from 101 to 193FIT/Mbupsets 13,800,000 13,800,000 devices devices hours hours @ 95% confidence interval BRAM: 704 FIT/Mb, from 515

@ 95% confidence interval

BRAM: 704 FIT/Mb, from 515 to 939FIT/Mb141 FIT/Mb, from 101 to 193FIT/Mb @ 95% confidence interval @ 95% confidence interval 2008-12-02_Xilinx-CNES CCT

@ 95% confidence interval

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Xilinx Confidential

704 FIT/Mb, from 515 to 939FIT/Mb @ 95% confidence interval 2008-12-02_Xilinx-CNES CCT FPGA-JLM 26 Xilinx Confidential

TheThe RosettaRosetta (SEU)(SEU) StoneStone

The The Rosetta Rosetta (SEU) (SEU) Stone Stone Process FPGA LANSCE >10MeV ROSETTA Lithography

Process

FPGA

LANSCE >10MeV

ROSETTA

Lithography

Family

Cfg MC

BRAM

Cfg MC

BRAM (1)

   

cm2

cm2

FIT/Mb

FIT/Mb

220nm

Virtex

0.99E-14

0.99E-14

157

157

180nm

Virtex-E

1.12E-14

1.12E-14

177

177

150nm

V2

2.56E-14

2.64E-14

396

431

130nm

V2P

2.74E-14

3.91E-14

375

608

90nm

S3

2.40E-14

3.48E-14

190

373

90nm

V4

1.55E-14

2.74E-14

240

380

90nm

S3E/A

1.31E-14

2.73E-14

104

293

65nm

V5

0.67E-14

3.96E-14

138

701

Notes:

CalculationsCalculations accordingaccording JESD89AJESD89A ValidValid forfor NYC:NYC: 40.740.7°°NN latlat,, 286.0286.0°° long,long, SeaSea--levellevel,, NeutronNeutron flux=flux= 1.0001.000

(1)

Error estimates for each Rosetta measurement @ 95% confidence interval:

o

90nm S3 [-50,+80]%, 90nm S3E [-80, 90]%

o

250nm +/-20%, 180nm +/-20%, 150nm V2 +/-8.2%, 130nm V2P +/-11.1%, 90nm V4 +/-17.7%, 65nm V5 [-27, +34]%

(2) Not enough Rosetta Gbit-years for useful prediction accuracy at this point (experiment running), predicted from LANSCE (3) All data as of 26aug08 *Config*Config FIT/MbFIT/Mb doesdoes notnot includeinclude SEUPI=SEUPI= 1010 (no de-rating factor). Divide configuration FIT/Mb by ten to get 1-sigma worst case (most pessimistic) de-rating factor.

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Xilinx Confidential

to get 1-sigma worst case (most pessimistic) de-rating factor. 2008-12-02_Xilinx-CNES CCT FPGA-JLM 27 Xilinx Confidential

OUTLINEOUTLINE

Xilinx introduction

Products overview

Aerospace & Defense introduction

AvionicsAvionics solutionssolutions

• • Avionics Avionics solutions solutions – – Products Products offering offering – –

ProductsProducts offeringoffering

AtmosphericAtmospheric EnvironementEnvironement TestingTesting && ResultsResults

RTCARTCA DODO--254254 // EUROCAEEUROCAE EDED--8080

Space solutions

Product offering

Space Environment Testing & Results

Mitigations techniques

XTMR architecture & TMRtool

Summary

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Xilinx Confidential

techniques – XTMR architecture & TMRtool • Summary 2008-12-02_Xilinx-CNES CCT FPGA-JLM 28 Xilinx Confidential

DODO--254254

RTCARTCA DODO--254254 // EUROCAEEUROCAE EDED--8080

ProductProduct ofof RTCARTCA SCSC--180180 andand EUROCAEEUROCAE WGWG--4646

RTCA: Requirements and Technical Concepts for Aviation

EUROCAE: EURopean Organisation for Civil Aviation Equipment

Title:Title:

DesignDesign AssuranceAssurance GuidanceGuidance forfor AirborneAirborne ElectronicElectronic HardwareHardware(AEH)(AEH)

For PLDs, FPGAs and ASICs

A design flow with checkpoints, verification and expert review

Certification pronounced by

Designated Engineering Representative (DER) in NA, representing FAA,

EASA (European Aviation Safety Agency), directly in Europe.

Represents a consensus of best practices for aviation

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Xilinx Confidential

– Represents a consensus of best practices for aviation 2008-12-02_Xilinx-CNES CCT FPGA-JLM 29 Xilinx Confidential

Manufacturing Process

System Process

DODO--254254

DODO--254254 SectionSection 33

HWHW DesignDesign LifeLife CycleCycle 3 Key Processes / 5 Design phases

(A-B-C)

(1-2-3-4-5)

C- Correctness Process • Validation & Verification process (section 6) A- • Configuration Management (section
C- Correctness Process
• Validation & Verification process (section 6)
A-
• Configuration Management (section 7)
Planning
• Process Assurance (section 8)
• Certification Liaison (section 9)
process
(section 4)
B- Development Process
- 1 - Requirements Capture - 2 - Conceptual Design - 3 - Detailed Design
- 1
-
Requirements
Capture
- 2 -
Conceptual
Design
- 3 -
Detailed
Design
- 4 -
Implementation
- 5 -
Production
Transition
(section 5.4)
(section 5.1)
(section 5.2)
(section 5.3)
(section 5.5)

2008-12-02_Xilinx-CNES CCT FPGA-JLM

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Derived Requirements

Xilinx Confidential

5.2) (section 5.3) (section 5.5) 2008-12-02_Xilinx-CNES CCT FPGA-JLM 30 Derived Requirements Xilinx Confidential

DODO--254254

DODO--254254 FPGAFPGA DesignDesign flowflow

PlanningPlanning Requirements Requirements Capture Capture Requirements Review Conceptual Conceptual Design Design
PlanningPlanning
Requirements Requirements
Capture Capture
Requirements
Review
Conceptual Conceptual
Design Design
Detailed
Design
Design
Validation & Verification
RTLRTL DesignDesign
Design Review
SynthesisSynthesis
Verify Verify RTL RTL Design Design
Verify Verify
Implementation
Gate-Level Gate-Level Design Design
TranslateTranslate
Debug
MMaapingping
DevicDevicee LevLevelel
Works OK?
PlacePlace && RouteRoute
Verification
YES / NO => Back to HDL Design
Review
SySystemstem LevLevelel
Works OK?
Download Download Bitstream Bitstream
YES / NO => Investigate
Silicon
into into
FPGA ® FPGA device device
2008-12-02_Xilinx-CNES CCT FPGA-JLM
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Xilinx Confidential

ProjecProjectt Plans:Plans: PHAC,PHAC, PA/QAPA/QA plan,plan, CCMM plan,plan, DevDev plan,plan, VerVer planplan

SysSysttemem RRequirementsequirements

System Safety Analysis

System architecture

SW & HW allocation

HWHW requirequirrementsements:: Feasible, Verifiable

HWHW DeDesisigngn:: RTL design, Synthesis, P&R

HWHW TeTestst

Functional tests

Normal range tests

Robustness tests:

Power supplies, T°C, Vibrations & shocks, Radiations

Coverage analysis

TTrracaebilityacaebility:: Correlation between req’s,

design, implementation and verification.

HAS:HAS: Identify & Justify Deviations vs PHAC.

req’s, design, implementation and verification. H A S : H A S : Identify & Justify

XilinxXilinx DODO--254254 partnershippartnership

Training and consulting partnerships

partnership • Training and consulting partnerships • Tools for a requirements-driven design methodology –
partnership • Training and consulting partnerships • Tools for a requirements-driven design methodology –

Tools for a requirements-driven design methodology

ReqTracer

HDL Designer*

ModelSim SE

0-In CDC*

Precision, …

HW packages and business models geared for the aviation market

* Customized for a Xilinx Flow

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Xilinx Confidential

geared for the aviation market * Customized for a Xilinx Flow 2008-12-02_Xilinx-CNES CCT FPGA-JLM 32 Xilinx

OUTLINEOUTLINE

Xilinx introduction

Products overview

Aerospace & Defense introduction

Avionics solutions

ProductsProducts offeringoffering

AtmosphericAtmospheric EnvironementEnvironement TestingTesting && ResultsResults

RTCARTCA DODO--254254 // EUROCAEEUROCAE EDED--8080

DO DO - - 254 254 / / EUROCAE EUROCAE ED ED - - 80 80

SpaceSpace solutionssolutions

Product offering

Space Environment Testing & Results

Mitigations techniques

XTMR architecture & TMRtool

Summary

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Xilinx Confidential

techniques – XTMR architecture & TMRtool • Summary 2008-12-02_Xilinx-CNES CCT FPGA-JLM 33 Xilinx Confidential

ChallengesChallenges forfor DesigningDesigning SpaceSpace ApplicationsApplications

Becoming increasingly sophisticated

High data rates and packet processing

ASICs are capable of high performance, but …

Long development times, re-spin risk, and NRE are problems

Space unit volumes are better addressed by FPGAs

Previous FPGA solutions

Not capable of high-performance applications

Not reprogrammable

No built-in processing or I/O capabilities

– No built-in processing or I/O capabilities Designers Need High-Performance FPGAs Capable of Embedded

Designers Need High-Performance FPGAs Capable of Embedded and Signal Processing in Space

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SingleSingle--ChipChip SolutionSolution AddressesAddresses PerformancePerformance RequirementsRequirements

Performance Performance Requirements Requirements • • High-performance High-performance applications

• • High-performance High-performance applications applications

– – Video Video (compression, (compression, encode, encode, decode) decode)

– – Communications Communications (filtering, (filtering, processing) processing)

– – Radar Radar (filtering, (filtering, processing) processing)

– – Encryption Encryption (AES, (AES, 3DES, 3DES, proprietary) proprietary)

– – Packet Packet Processing Processing (802.3, (802.3, web web server) server)

• • Control Control applications applications

– – Motor Motor control control (low (low and and high-performance) high-performance)

– – Bus Bus management management (Ethernet, (Ethernet, Fiber Fiber channel, channel, etc.) etc.)

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(Ethernet, (Ethernet, Fiber Fiber channel, channel, etc.) etc.) 2008-12-02_Xilinx-CNES CCT FPGA-JLM 35 Xilinx Confidential

XilinxXilinx SolutionsSolutions forfor SpaceSpace

Highest Performance, Largest Capacity FPGAs in Space

Selected advanced FPGA products for application in Space-based systems

Complete Single Event Effects testing and analysis

Tools and techniques for SEU mitigation & management

Applications solutions

Configuration Management & Scrubbing

Special architectural feature considerations

Embedded Processing

Reference Designs

TMRTool Software

Processing • Reference Designs – TMRTool Software • Automated Triple Module Redundancy implementation tool

Automated Triple Module Redundancy implementation tool

• Automated Triple Module Redundancy implementation tool 2008-12-02_Xilinx-CNES CCT FPGA-JLM 36 Xilinx Confidential
• Automated Triple Module Redundancy implementation tool 2008-12-02_Xilinx-CNES CCT FPGA-JLM 36 Xilinx Confidential

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• Automated Triple Module Redundancy implementation tool 2008-12-02_Xilinx-CNES CCT FPGA-JLM 36 Xilinx Confidential

GuaranteedGuaranteed QualityQuality forfor SpaceSpace

Radiation-hardened military ceramic package (QML in process)

True “Class-V” Flows

Aerospace

Corporation

Certification

“Class-V” Flows Aerospace Corporation Certification Guaranteed TID of 300 krad (Si) SEL Immunity >125 MeV

Guaranteed TID of 300 krad (Si)

SEL Immunity >125 MeV cm 2 /mg

Full Military Temperature Range (-55°C to +125°C)

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2 /mg Full Military Temperature Range (-55°C to +125°C) 2008-12-02_Xilinx-CNES CCT FPGA-JLM 37 Xilinx Confidential
Xilinx QPro Aerospace Products Aerospace QPro ™ -R Radiation Tolerant FPGAs        

Xilinx QPro Aerospace Products

Xilinx QPro Aerospace Products Aerospace QPro ™ -R Radiation Tolerant FPGAs          

Aerospace QPro-R Radiation Tolerant FPGAs

       
             

SEL Immunity

 

Device

Core

 

Mfg Grades

Packages

 

TID (krad)

(MeV-cm^2/mg)

QPro-R Virtex-IV

XQR4VLX200

1.2V

   

V

 

CF1509

 

300

>80

 

XQR4VSX55

1.2V

   

V

 

CF1140

 

300

>80

 

XQR4VFX140

1.2V

   

V

 

CF1144

 

300

>80

 

XQR4VFX60

1.2V

   

V

 

CF1509

 

300

>80

QPro-R Virtex-II

XQR2V3000

1.5V

   

M, V

BG728, CG717

 

200

>160

 

XQR2V6000

1.5V

   

H

 

CF1144

 

200

>160

QPro-R Virtex

XQVR300

2.5V

   

M, V

 

CB228

 

100

125

 

XQVR600

2.5V

   

M, V

 

CB228

 

100

125

Aerospace QPro™-R Radiation Tolerant Configuration PROMs

     
             

SEL Immunity

 

Device

Core

Storage Bits

Mfg Grades

Packages

TID (krad)

(MeV-cm^2/mg)

QPro-R PROMs

XQR1701L

3.3V

1M

M, V

CC44

50

>120

 

XQR17V16

3.3V

16M

M, V

CC44, VQ44

50

>120

Enhanced Rad Hard by Design products in development

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• Enhanced Rad Hard by Design products in development 2008-12-02_Xilinx-CNES CCT FPGA-JLM 38 Xilinx Confidential

SpaceSpace ProductsProducts RoadmapRoadmap

Rad Hard by Design FPGAs Rad Tolerant FPGAs SIRF Rad Tolerant XQRS5VFX130T FPGAs XQR4VSX55 >300KRad
Rad Hard by
Design
FPGAs
Rad Tolerant
FPGAs
SIRF
Rad Tolerant
XQRS5VFX130T
FPGAs
XQR4VSX55
>300KRad
XQR4VFX60
XQR4VFX140
XQR2V3000
XQR4VLX200
XQR2V6000
300KRad
200KRad
Relative Performance

2002

2004

2008-12-02_Xilinx-CNES CCT FPGA-JLM

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2006

Xilinx Confidential

2008

2010

300KRad 200KRad Relative Performance 2002 2004 2008-12-02_Xilinx-CNES CCT FPGA-JLM 39 2006 Xilinx Confidential 2008 2010

Xilinx Virtex ® -4QV

New in 2008!

Multi-platform FPGA family with embedded hard IP

High-performance logic platform Embedded / Ethernet MACs platform DSP optimized platform
Embedded / Ethernet MACs platform High-performance logic platform DSP optimized platform
High-performance logic platform Embedded / Ethernet MACs platform DSP optimized platform DSP optimized platform

Embedded / Ethernet MACs platform DSP optimized platform • Unmatched capacity and system integration •

Unmatched capacity and system integration

Radiation tolerant devices meet Class-V requirements

Reprogrammable technology enables changes at any time

 

XQR4VSX55

XQR4VSX55

XQR4VFX60

XQR4VFX60

XQR4VFX140

XQR4VFX140

XQR4VLX200

XQR4VLX200

 

Logic Cells

Logic Cells

55,296

55,296

56,880

56,880

142,128

142,128

200,448

200,448

 

CLB Flip-Flops

CLB Flip-Flops

49,152

49,152

50,560

50,560

126,336

126,336

178,176

178,176

Distributed RAM (Kbits)

Distributed RAM (Kbits)

384

384

395

395

987

987

1392

1392

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(Kbits) 384 384 395 395 987 987 1392 1392 2008-12-02_Xilinx-CNES CCT FPGA-JLM 40 Xilinx Confidential

U.S.U.S. GovernmentGovernment AgencyAgency ControlsControls

     
     
     

USUS DepDept.t. ofof CommerceCommerce

USUS DepartmentDepartment ofof StateState

USUS DepartmentDepartment ofof TreasuryTreasury

Bureau of Industry & Security

Directorate of Defense Trade Controls

Office of Foreign Assets Controls

ExportExport AdministrationAdministration RegulationsRegulations “Dual Use” products/ technologies Commerce Control List

International Traffic in Arms Regulations Inherently military products/ technologies U.S. Munitions List

Administration of US economic sanctions & embargoes

Xilinx Virtex-4QV are under US DoC EAR

Administered by Bureau of Industry and Security (BIS)

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Xilinx Confidential

EAR – Administered by Bureau of Industry and Security (BIS) 2008-12-02_Xilinx-CNES CCT FPGA-JLM 41 Xilinx Confidential

SIRF

(Single-Event Immune Reconfigurable FPGA)

Key Development Objectives

Deliver Radiation Hardened by Design, Space qualified Virtex-5 FPGA by CY2010

Minimize design complexities and overhead required Space applications of FPGAs

Eliminate additional design effort and chips for configuration management, scrubbing, TMR and state recovery

Maintain compatibility with commercial V-5 product for rapid development

Feature set, floor plan and footprint compatible with commercial product

Address critical SEE sensitive circuits and eliminate all SEFIs

Transparent to S/W Development Tools

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eliminate all SEFIs • Transparent to S/W Development Tools 2008-12-02_Xilinx-CNES CCT FPGA-JLM 42 Xilinx Confidential

SIRF Phases 3 & 4

• •

Configuration Controller

IOB

BRAM Configuration

 
• IOB • • BRAM Configuration   • •   BRAMBRAM BRAMBRAM  
• IOB • • BRAM Configuration   • •   BRAMBRAM BRAMBRAM  

 

BRAMBRAM

BRAMBRAM

 

DSPDSPDSPDSPDSPDSPDSPDSP

BRAMBRAM

 

CMT

 

BRAMBRAM

DSPDSPDSPDSPDSPDSPDSPDSP

BRAMBRAM

BRAMBRAM

IO BANK

 

BRAMBRAM

 
   

GTX

x2

IO BANK

BRAMBRAM

BRAMBRAM

 

BRAMBRAM

C

LO

I

O

C

K

BRAMBRAM

BRAMBRAM

BRAMBRAM

BRAMBRAM

     

IO BANK

BRAMBRAM

BRAMBRAM

BRAMBRAM

C

O

N

F

IG

BRAMBRAM

BRAMBRAM

BRAMBRAM

BRAMBRAM

     

I

O

PCI EXPRESS

GTX

 
 

P

               

x2

 

BRAMBRAM

BRAMBRAM

O

 

BRAMBRAM

   

BRAMBRAM

 

BRAMBRAM

BRAMBRAM

IO BANK

BRAMBRAM

 

W

E

 

CMT

 
 

BRAMBRAMBRAMBRAM

BRAMBRAM

BRAMBRAM

BRAMBRAM

BRAMBRAMBRAMBRAM

BRAMBRAM

R

DSPDSPDSPDSPDSPDSPDSPDSPDSPDSPDSPDSPDSPDSPDSPDSP

BRAMBRAMBRAMBRAM

BRAMBRAM

BRAMBRAM

BRAMBRAM

BRAMBRAMBRAMBRAM

BRAMBRAM

CMT

BRAMBRAMBRAMBRAM

BRAMBRAM

BRAMBRAM

BRAMBRAM

BRAMBRAMBRAMBRAM

BRAMBRAM

DSPDSPDSPDSPDSPDSPDSPDSPDSPDSPDSPDSPDSPDSPDSPDSP

       

P

   

GTX

 

IO BANKIO

IO BANK

BRAMBRAMBRAMBRAM

BRAMBRAM

BRAMBRAM

BRAMBRAM

BRAMBRAMBRAMBRAM

BRAMBRAM

C

C

LO

I

O

C

K

BRAMBRAMBRAMBRAM

BRAMBRAM

BRAMBRAM

BRAMBRAM

BRAMBRAMBRAMBRAM

BRAMBRAM

BRAMBRAMBRAMBRAM

BRAMBRAM

BRAMBRAM

BRAMBRAM

BRAMBRAMBRAMBRAM

BRAMBRAM

IO BANKIO

IO BANK

BANKIO

BANK

BRAMBRAMBRAMBRAM

BRAMBRAM

BRAMBRAM

BRAMBRAM

BRAMBRAMBRAMBRAM

BRAMBRAM

x2

C

O

I

N

O

F

IG

GTX

x2

BANKIO

BANK

C

O

N

F

IG

PCI EXPRESS

GTX

x2

C

C

LO

O

N

C

F

K

IG

GTX

x2

 

I

O

   
           

C

LO

C

K

               

IO BANKIO

IO BANK

BANKIO

BRAMBRAMBRAMBRAM

BRAMBRAM

BRAMBRAM

BRAMBRAM

BRAMBRAMBRAMBRAM

BRAMBRAM

BRAMBRAMBRAMBRAM

BRAMBRAM

BRAMBRAM

BRAMBRAM

BRAMBRAMBRAMBRAM

BRAMBRAM

 

DSPDSPDSPDSPDSPDSPDSPDSPDSPDSPDSPDSPDSPDSPDSPDSP

BRAMBRAMBRAMBRAM

BRAMBRAM

BRAMBRAM

BRAMBRAM

BRAMBRAMBRAMBRAM

BRAMBRAM

 

I

O

CMT

 

BRAMBRAMBRAMBRAM

BRAMBRAM

BRAMBRAM

BRAMBRAM

BRAMBRAMBRAMBRAM

BRAMBRAM

DSPDSPDSPDSPDSPDSPDSPDSPDSPDSPDSPDSPDSPDSPDSPDSP

BRAMBRAMBRAMBRAM

BRAMBRAM

BRAMBRAM

BRAMBRAM

BRAMBRAMBRAMBRAM

BRAMBRAM

BRAMBRAMBRAMBRAM

BRAMBRAM

BRAMBRAM

BRAMBRAM

BRAMBRAMBRAMBRAM

BRAMBRAM

IO BANKIO

IO BANK

BANKIO

BANK

 

BRAMBRAMBRAMBRAM

BRAMBRAM

BRAMBRAM

BRAMBRAM

BRAMBRAMBRAMBRAM

BRAMBRAM

GTX

x2

P

O

W

E

C

CMT

LO

I

O

C

K

GTX

x2

R

P

C

C

C

O

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x2

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C

LO

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x2

     

43

Xilinx Confidential

LO I O C CMT K GTX x2       43 Xilinx Confidential 2008-12-02_Xilinx-CNES CCT

2008-12-02_Xilinx-CNES CCT FPGA-JLM

SIRFSIRF RadiationRadiation GoalsGoals && DeviceDevice

Total Dose > 300 krad (Si) (requirement) FX130T SEE Latch up Immune LET > 100
Total Dose
> 300 krad (Si) (requirement)
FX130T
SEE Latch up
Immune LET
> 100 MeV-cm 2 /mg
Logic Cells
131,072
To
tal Block RAM (Kbits)
10,836
Upset
Error rate
< 1 ×10 -10 errors/bit-day
DSP48E Slices
301
RocketIO GTP Channels
0
RocketIO GTX Channels
20
Functional
-10
Error rate < 1×10
errors/bit-day
PPC440 Cores
2
Interrupt
PCIe Subsystem Blocks
3
10/100/1000 EMACs
6
Dose Rate
Latch up
Upset
Package
Size
> 1 ×10 10 rad(Si)/sec
> 1 ×10 9 rad(Si)/sec
FF1738
840
42.5

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10 rad(Si)/sec > 1 ×10 9 rad(Si)/sec FF1738 840 42.5 2008-12-02_Xilinx-CNES CCT FPGA-JLM 44 Xilinx Confidential

U.S.U.S. GovernmentGovernment AgencyAgency ControlsControls

     
     
     

USUS DepDep’’t.t. ofof CommerceCommerce

USUS DepartmentDepartment ofof StateState

USUS DepartmentDepartment ofof TreasuryTreasury

Bureau of Industry & Security

Directorate of Defense Trade Controls

Office of Foreign Assets Controls

Export Administration Regulations “Dual Use” products/ technologies Commerce Control List

InternationalInternational TrafficTraffic inin ArmsArms RegulationsRegulations Inherently military products/ technologies U.S. Munitions List

Administration of US economic sanctions & embargoes

Xilinx SIRF will be US DoD ITAR

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Xilinx Confidential

sanctions & embargoes Xilinx SIRF will be US DoD ITAR 2008-12-02_Xilinx-CNES CCT FPGA-JLM 45 Xilinx Confidential

QAQA flowsflows

TEST

Methodology

QPRO V-Grade Ceramic

M-Grade Ceramic

M-Grade Plastic

Specification Control

Xilinx Data Sheet

 

X

 

X

 

X

Mask Control

Per XILINX Controlled Doc.

 

X

 

X

 

X

QML Qualified WaferFab

Per Mil - PRF 38535

 

X

 

X

 

X

Wafer Lot Acceptance

Per Internal Parametric Spec

 

X

 

X

 

X

Lot RHA

Per TM1019 / Per WaferFab L

 

X

       

QML Qualified Assembly

Per Mil - PRF 38535

 

X

 

X

 

X

Destructive Bond Pull

Per TM2011, Sample, SPC

 

X

 

X

 

X

Internal Visual

Per TM2010B, 100%

 

X

Sample

Sample

Temperature Cycling

Per TM1010, 100%

 

X

 

X

   

Constant Acceleration

Per TM2001, 100%

 

X

       

Fine/Gross leakage

Per TM1014, 100%

 

X

 

X

   

Pind-Test

Per TM2020

 

X

       

Radiography Insp / X-Ray

Per TM2012, Sample, SPC

 

X

       

Pre-BI Test @ 25°C

Per SMD or DataSheet

 

X

       

Static Burn-in (240 hours)

Per TM1015B, 100%

 

X

       

Post BI Test @ 25°C

Per SMD or DataSheet

 

X

       

PDA Calculation

Per TM5004

 

X

       

+125°C Electrical Test

Per SMD or DataSheet

 

X

 

X

 

X

-55°C Electrical Test

Per SMD or DataSheet

 

X

       

Marking Permanency

Per TM2015

 

X

 

X

 

X

DPA

Per TM1580

 

X

       

QC Sampling Plan

Per TM5005, Group A (0/116)

 

X

 

X

 

X

QCI

Per TM5005, Groups B, C & D

 

X

       

External Visual Inspection

Per TM2009, 100%

 

X

Com. Std

Com. Std

Xilinx Confidential

    External Visual Inspection Per TM2009, 100%   X Com. Std Com. Std Xilinx Confidential

Xilinx Spaceflight Heritage

MARS Lander (JPL) – Pyrotechnics

MARS Rover (JPL) – Motor Control

MRO (Ball Aerospace) – HiRISE Camera

GRACE (NASA) – Sensor

Venus Express (ESA) – Multiple Virtex designs

FedSat (Univ. Southern Australia)

OPTUS (Raytheon) - DSP

TACSAT2 (NASA)

CIBOLA (LANL) – Remote Sensing