Beruflich Dokumente
Kultur Dokumente
UNIT-I
1
Signal
An information variable represented by physical quantity
For digital systems, the variable takes on discrete values
Two level, or binary values are the most prevalent
values
Binary values are represented abstractly by:
digits 0 and 1
words (symbols) False (F) and True (T)
words (symbols) Low (L) and High (H)
and words On and Off.
Binary values are represented by values or ranges of values
of physical quantities
3
Binary Numbers
Decimal number
Base or radix
aj
a5a4a3a2a1.a1a2a3
Decimal point
Power
Example:
a2 r 2 a1 r1 a0 a1 r 1 a2 r 2
Coefficient: aj = 0 to r 1
a m r m
Binary Numbers
Example: Base-2 number
(11010.11)2 (26.75)10
1 24 1 23 0 22 1 21 0 20 1 21 1 22
Binary Numbers
Arithmetic operation
Arithmetic operations with numbers in base r follow the same rules
as decimal numbers.
Binary Arithmetic
Subtraction
Addition
Minuend:
Augend: 101101
Addend: +100111
Sum:
1010100
Multiplication
Multiplicand
Multiplier
Partial Products
Product
1011
101
1011
0000 1011 - 110111
101101
Subtrahend: 100111
Difference:
000110
Octal Conversions
Binary to octal
Group binary positions in groups of three
Write the octal equivalent
Octal to binary
Reverse the process
Octal to decimal
Multiply by weighting factors
Decimal to octal
Successive division
10
11
12
Hexadecimal Conversions
Binary-to-hexadecimal conversion
Group the binary in groups of four
Write the equivalent hex digit
Hexadecimal-to-binary conversion
Reverse the process
Hexadecimal-to-decimal conversion
Multiply by weighting factors
Decimal-to-hexadecimal conversion
Successive division
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14
Representation of numbers
Decimal - Octal - Hexadecimal number systems
Representation of negative numbers
Complement of a number
Binary arithmetic
Binary codes for decimal numbers
Error detecting and correcting codes
15
Representation of numbers
A number in base-r has coefficients multiplied by powers of r
and is of the form
n1
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18
Complement of a number
Used for
Simplifying subtraction
Logical manipulation
Two types
Radix complement
Diminished radix complement
19
Complement of a number
(r n 1) N
Radix complement
Given a number N in base r having n digits, its diminished
radix complement
((r n 1) N ) 1
21
22
23
Binary arithmetic
Addition
Subtraction
Multiplication
Addition
Similar to normal decimal addition
Rules of addition:
1 + 1 = 0 CY = 1
1+0=0+1=1
24
Binary subtraction
The subtraction of two n-digit unsigned numbers M - N in
base r can be done as follows:
1. Add the minuend M to the r's complement of the subtrahend N.
Mathematically, M + (rn - N) = M - N + rn
2. If M >= N. the sum will produce an end carry rn which can be
discarded. what is left is the result M - N.
3. If M < N. the sum does not produce an end carry and is equal
to rn - (N - M) which is r's complement of (N - M).
4. To obtain the answer, take the r's complement of the sum and
place a negative sign in front.
25
Binary subtraction
Eg: Perform the subtraction a) X Y and b) Y X if X =
1010100 and Y = 1000011 using twos complement form.
Binary multiplication
Just like normal decimal multiplication
Eg: Find (1 0 1)2 (1 1 0)2
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100
10-1
10-2
Tenths Hundredths
2
5
29
0.312510 = 0.01012
How we can represent the whole and fraction part of the
binary rep. in 4 bytes?
30
Solution is Normalization
Every binary number, except the one corresponding to the
number zero, can be normalized by choosing the exponent so
that the radix point falls to the right of the leftmost 1 bit.
37.2510 = 100101.012 = 1.0010101 x 25
7.62510 = 111.1012 = 1.11101 x 22
0.312510 = 0.01012 = 1.01 x 2-2
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So what Happened ?
32
1 2
10
32
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35
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BCD CODE
Decimal numbers 0 9 can be represented using 4 bits.
There are 6 unused combinations in this coding scheme.
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39
Gray Code
Reflection code
Advantage of Gray code
over the straight binary
number sequence is that
only one bit in the code
group changes in going
from one number to the
next.
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41
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Parity
Simplest form of error detection is achieved by using parity
bits.
A parity bit is an extra bit included with a message to make the
total number of 1's either even or odd.
Eg:
44
Hamming code
k parity bits are added to an n-bit data word forming a new
word of n + k bits.
The bit positions are numbered in sequence from 1 to n + k.
The relation between the number of message bits and parity
bits is
Those positions numbered as a power of 2 are reserved for the
parity bits
The remaining bits are the data bits
45
Hamming code
46
Hamming code
Message bit sequence
47
Binary Logic
48
Logic Operators
AND
x
y
xy
x
0
0
1
1
y
0
1
0
1
AND
0
0
0
1
x
0
0
1
1
y NAND
0
1
1
1
0
1
1
0
x
y
xy
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Logic Operators
OR
x
y
x+y
x
0
0
1
1
y
0
1
0
1
OR
0
1
1
1
x
0
0
1
1
y
0
1
0
1
NOR
1
0
0
0
x
y
x+y
50
Logic Operators
XOR (Exclusive-OR)
x
y
x y
xy+xy
XNOR (Exclusive-NOR)
(Equivalence)
x
y
x y
x y
xy+xy
x
0
0
1
1
y
0
1
0
1
XOR
0
1
1
0
x
0
0
1
1
y XNOR
0
1
1
0
0
0
1
1
51
Logic Operators
NOT (Inverter)
NOT
Buffer
Buffer
52
Basic Definitions
Binary Operators
AND
z=xy=xy
OR
z=x+y
NOT
z = x = x
z=1 if x=0
Boolean Algebra
Binary Variables: only 0 and 1 values
Algebraic Manipulation
53
Commutative Law
xy=yx
Identity Element
x1=x
Complement
x x = 0
x+y=y+x
x+0=x
x + x = 1
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Duality
Theorem 1
xx=x
x+x=x
Theorem 2
x0=0
x+1=1
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Theorem 3: Involution
( ) = x
(x)=x
Theorem 5: DeMorgan
( x y ) = +
(xy) =x +y
( x + y ) =
(x+y) = xy
x x+y)=x
x+(xy)=x
Theorem 6: Absorption
56
Operator Precedence
Parentheses
( . . . ) ( . . .)
NOT
x + y
AND
x+xy
OR
x [ y z ( w x)]
( w x)
( w x)
z ( w x)
y z ( w x)
x [ y z ( w x )]
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DeMorgans Theorem
a [b c (d e )]
a [b c (d e )]
a b (c (d e ))
a b (c (d e ))
a b (c (d e))
a b (c d e)
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Boolean Functions
Boolean Expression
Example:
F = x + y z
Truth Table
All possible combinations
of input variables
Logic Circuit
x
y
z
1
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Algebraic Manipulation
Literal:
A single variable within a term that may be complemented or
not.
Use Boolean Algebra to simplify Boolean functions to produce
simpler circuits
Example: Simplify to a minimum number of literals
F = x + x y
( 3 Literals)
= x + ( x y )
Distributive law (+ over )
= ( x + x ) ( x + y )
=(1)(x+y)=x+y
( 2 Literals)
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Complement of a Function
DeMorgans Theorm
F A B C
F A B C
Duality & Literal Complement
F A B C
F A B C
A B C
F A B C
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Canonical Forms
Minterm
Product (AND function)
Contains all variables
Evaluates to 1 for a
specific combination
Example
A=0
A
B C
B=0
(0) (0) (0)
C=0
1 1 1=1
A B C
Minterm
0 0 0
m0
ABC
0 0 1
m1
0 1 0
m2
0 1 1
m3
1 0 0
m4
ABC
ABC
ABC
ABC
1 0 1
m5
1 1 0
m6
1 1 1
m7
ABC
ABC
ABC
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Canonical Forms
Maxterm
Sum (OR function)
Contains all variables
Evaluates to 0 for a
specific combination
Example
A=1
B=1
C=1
A B C
(1) + (1) + (1)
0 + 0 + 0=0
A B C
Maxterm
0 0 0
M0 A B C
0 0 1
0 1 0
M1 A B C
M2 A B C
0 1 1
1 0 0
1 0 1
1 1 0
M5 A B C
M6 A B C
1 1 1
M7 A B C
M3 A B C
M4 A B C
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Canonical Forms
Truth Table to Boolean Function
A B C
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
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Canonical Forms
Sum of Minterms
A B C
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
F (1,4,5,7)
Product of Maxterms
F (0,2,3,6)
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Standard Forms
Sum of Products (SOP)
AB(C C )
AB(1)
AB
AC ( B B)
AC
BC ( A A)
BC
F BC ( A A) AB(C C ) AC ( B B)
F BC AB AC
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Standard Forms
Product of Sums (POS)
AB(C C )
BC ( A A)
AC ( B B)
F AC ( B B) AB(C C ) BC ( A A)
F AC AB BC
F ( A C )( A B)( B C )
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UNIT II
Gate-Level Minimization and
combinational circuits
68
Gate-Level Minimization
The Boolean functions also can be simplified by map
method as Karnaugh map or K-map.
The map is made up of squares, with each square
representing one minterm of the function.
This produces a circuit diagram with a minimum
number of gates and the minimum number of inputs to
the gate.
It is sometimes possible to find two or more expressions
that satisfy the minimization criteria.
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Two-Variable map
Two-variable has four minterms, and consists of four
squares.
m1 + m2 + m3 = xy + xy + xy = x + y
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Three-Variable map
Note that the minterms are not arranged in a binary sequence,
but similar to the Gray code.
For simplifying Boolean functions, we must recognize the basic
property possessed by adjacent squares.
cancel
y
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72
Example
Ex. 3-3 F , , z = , , , ,
F = z
+ xy
73
Four-variable map
1 square = 1 minterm = 4 literals
2 adjacent squares = 1 term = 3 literals
4 adjacent squares = 1 term = 2 literals
8 adjacent squares = 1 term = 1 literal
16 adjacent squares = 1
74
Example
Ex. 3-6 F = ABC + BCD + ABCD + ABC
= BD + BC + ACD
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Prime implicant
A prime implicant is a product term
obtained by combining the maximum
possible number of adjacent squares
in the map.
This shows all possible ways that the
three minterms(m3,m9,m11) can be
covered with prime implicants.
F = BD+BD+CD+AD
= BD+BD+CD+AB
= BD+BD+BC+AD
= BD+BD+BC+AB
77
Five-variable map
Fig.3-12, the left-hand four-variable map represents the 16 squares where A=0,
and the other four-variable map represents the squares where A=1.
In addition, each square in the A=0 map is adjacent to the corresponding
square in the A=1 map.
78
Five-variable map
It is possible to show that any 2k adjacent squares, for
k=(0,1,2,,n) in an n-variable map, will represent an area that
gives a ter of k literals(n>k). When n=k, it is identity function.
79
example
Ex. 3-7 F(A, B, C, D, E) = (0, 2, 4, 6, 9, 13, 21, 23, 25, 29, 31)
Because of both parts of the map have the common term (ABDE+ABDE)
so the sum of products is
F = ABE + BDE + ACE
common
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Example
(a) SOPs
F= BD + BC + ACD
(b) POSs
F= AB + CD + BD
By DeMorgans thm
F= (A+B) .(C+D)
.(B+D)
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Gate implementation
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85
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Two-level implementation
F = AB + CD
Double
complementation, so
can be removed
OR
gate,Fig.3-18
88
To convert a multilevel AND-OR diagram into an allNAND diagram using mixed notation is as follows:
89
,
90
NOR implementation
The NOR operation is the dual of the NAND operation, all
procedures and rules for NOR logic are the dual of NAND logic.
NOR gate is also a universal gate.
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Wired-And
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Nondegenerate forms
We consider four types of gates: AND, OR, NAND, and
NOR. These will have 16 combinations of two-level
forms.
Eight of these combinations are said to be degenerate
forms, because they degenerate to a single operation.
The other eight nondegenerate forms produce an SOPs
or POSs as follows:
AND-OR 3-4
NAND-NAND 3-6
NOR-OR
OR-NAND
OR-AND 3-4
NOR-NOR 3-6
NAND-AND
AND-NOR
95
AND-OR-INVERT implementation
The two forms NAND-AND and AND-NOR are equivalent forms
and can be treated together.
F = (AB + CD + E)
Shift back
96
OR-AND-INVERT implementation
The OR-NAND form resembles the OR-AND form, except for the
inversion done by the bubble in the NAND gate.
F = [(A + B)(C + D)E]
Shift back
97
Example
Ex.3-11 Implement the function of Fig.3-31(a) with the four twolevel forms listed in Table 3-3.
The complement of the function by combining the 0s:
F = xy + xy + z
The normal output for this function
F = (xy + xy + z)
Which is in the AND-OR-INVERT form.
98
Example
The AND-NOR and NAND-AND implementations are
shown as follows.
99
Example
The OR-AND-INVERT forms require a simplified expression of the
complement of the function in POSs.
Combine the 1s in the map
F = xyz + xyz
Complement of the function
F = (x + y + z)(x + y + z)
100
Example
The normal output F
F = (x + y + z)(x + y + z)]
We can implement the function in the OR-NAND and NOR-OR forms
as follows.
101
Exclusive-OR function
The XOR symbol denote as , the Boolean operation: x
= +
The X-NOR symbol denote as , the Boolean operation:
x y = (x = +
The identities of the XOR operation:
x0=x
x =
x =
xx=0
x = y = (x
Exclusive-OR implementations
Fig.3-32(b), the first NAND gate performs the operation (xy) = (x + y).
(x + y)x + (x + y)y = xy + xy = x y
103
Odd function
Boolean expression of three-variable of the XOR:
A B C = (AB + AB)C + (AB + AB)C
= ABC + ABC + ABC + ABC
= , , ,
Odd function defined as the logical sum of the 2n/2 minterms whose
binary numerical values have an odd number of 1s.
104
105
UNIT III
Combinational Circuits
106
Combinational Circuits
Binary adder
Binary adder that produces the arithmetic
sum of binary numbers can be constructed
with full adders connected in cascade, with
the output carry from each full adder
connected to the input carry of the next full
adder in the chain
Note that the input carry C0 in the least
significant position must be 0.
Binary Adder
Binary Adder
For example to add A= 1011 and B= 0011
subscript i: 3 2 1 0
Input carry: 0 1 1 0 Ci
Augend:
1 0 1 1 Ai
Addend:
0 0 1 1 Bi
-------------------------------Sum:
1 1 1 0 Si
Output carry: 0 0 1 1 Ci+1
Binary Subtractor
The subtrcation A B can be done by taking
the s o ple e t of B a d addi g it to A
because A- B = A + (-B)
It ea s if e use the i eters to ake s
complement of B (connecting each Bi to an
inverter) and then add 1 to the least
significant bit (by setting carry C0 to 1) of
binary adder, then we can make a binary
subtractor.
=1
Adder/Subtractor
The addition and subtraction can be combined
into one circuit with one common binary
adder (see next slide).
The mode M controls the operation. When
M=0 the circuit is an adder when M=1 the
circuit is subtractor. It can be don by using
exclusive-OR for each Bi and M. Note that 1
= a d x=x
Checking Overflow
Note that in the previous slide if the numbers
considered to be signed V detects overflow. V=0
means no overflow and V=1 means the result is
wrong because of overflow
Overflow can be happened when adding two
numbers of the same sign (both negative or positive)
and result can not be shown with the available bits.
It can be detected by observing the carry into sign bit
and carry out of sign bit position. If these two carries
are not equal an overflow occurred. That is why
these two carries are applied to exclusive-OR gate to
generate V.
Magnitude Comparator
It is a combinational circuit that compares to
numbers and determines their relative magnitude
The output of comparator is usually 3 binary
variables indicating:
A>B
A=B
A<B
For example to design a comparator for 2 bit binary
numbers A (A1A0) and B (B1B0) we do the following
steps:
Comparators
For a 2-bit comparator we have four inputs A1A0 and B1B0 and three
output E ( is 1 if two numbers are equal) G (is 1 when A > B) and L (is 1
when A < B) If we use truth table and KMAP the result is
E= A A B B + A A B B + A A B B + A A B B
or E=(( A0 B0) + ( A1 B )) (see next slide)
G = A B + A B B + A A B
L= A B + A A B + A B B
A0
E
A1
B0
B1
Comparator
G
L
Magnitude Comparator
Here we use simpler method to find E (called X) and G (called Y) and L
(called Z)
A=B if all Ai= Bi
Ai Bi Xi
-----------0 0 1
0 1 0
1 0 0
1 1 0
It ea s X = A B + A B a d
X = A B + A B
If X0=1 and X1=1 then A0=B0 and A1=B1
Thus, if A=B then X0X1 = 1 it means
X= A B + A B A B + A B si e =
+
X= ( A0 B A B = ( A0 B0) + ( A1 B
It means for X we can NOR the result of two exclusive-OR gates
Magnitude Comparator
A>B means A1 B1 Y1
-----------0 0 0
0 1 0
1 0 1
1 1 0
if A1=B1 (X1=1) then A0 should be 1 and B0 should be 0
A0 B0 Y0
-----------0 0 1
0 1 0
1 0 0
1 1 0
For A> B: A1 > B1 or A1 =B1 and A0 > B0
It ea s Y= A B + X A B should e for A>B
Magnitude Comparator
For B>A B1 > A1
or
A1=B1 and B0> A0
z= A B + X A B
The procedure for binary numbers with more than 2 bits can
also be found in the similar way. For example next slide shows
the 4-bit magnitude comparator, in which
(A= B) = x3x2x1x0
A> B = A B + A B +
A B +
A B
A< B = A B + A B +
A B +
A B
Decoder
Is a combinational circuit that converts binary information
from n input lines to a maximum of 2n unique output lines For
example if the number of input is n=3 the number of output
lines can be m=23 . It is also known as 1 of 8 because one
3 to 8
decoder
enable
Encoder
Encoder is a digital circuit that performs the inverse
operation of a decoder
Generates a unique binary code from several input
lines.
Generally encoders produce2-bit, 3-bit or 4-bit code.
n bit encoder has 2n input lines
2 bit encoder
2-bit encoder
If one of the four input lines is active encoder
produces the binary code corresponding to
that line
If more than one of the input lines will be
activated or all the output is undefined. We
a o sider do t are for these situatio s
but in general we can solve this problem by
using priority encoder.
Multiplexer
It is a combinational circuit that selects binary
information from one of the input lines and directs it
to a single output line
Usually there are 2n input lines and n selection lines
whose bit combinations determine which input line
is selected
For example for 2-to-1 multiplexer if selection S is
zero then I0 has the path to output and if S is one I1
has the path to output (see the next slide)
Uses of Multiplexers
Used in data communications for several
computers to communicate over 1 line
Used in radio to select one channel from many
Used to route data within a computer
Used for function generation
2-to-1 multiplexer
F A,B,C,D = , , ,
Demultiplexers
A demultiplexer has
N control inputs
1 data input
2N outputs
147
Demultiplexers
Out0
Out1
Out2
In
Out3
W
X
Y
Z
W = A'.B'.I
X = A.B'.I
Y = A'.B.I
S1 S0
Z = A.B.I
A B
A
148
UNIT IV
Synchronous & Asynchronous
Sequential Circuits
149
Sequential Circuits
Most digital systems like digital watches, digital
phones, digital computers, digital traffic light
controllers and so on require memory elements
Memory elements are digital circuits that can store
and retrieve data in the form of 1's and 0's.
The output of the systems with memory depends
not only on present inputs but also on what has
happened in the past
SR latch is an example of memory circuits that can
store one bit of information
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SR Latch
When SR latch is storing a 1 then its Q is 1 and
when storing 0 its Q is 0
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Q
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SR Latch
1. If SR=10 then Q=1 and the latch is storing a 1, We
call this setting the Latch.
2. If SR =10 and we change to SR=00 then the latch will
remain set with Q= 1. In other words it
"remembers" to stay set
3. If SR=01 then Q=0 and the latch is storing a 0. We
call this resetting or Clearing the latch
4. If SR =01 and we change to SR=00 then the latch will
remain set with Q= 0.
We call the value of Q at any given time the state of
the latch
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SR Latch
The circuit (in next slide) with NOR gates is able to do
this because of the feedback from the output back to
the input
Note that both Q and Q' are "brought back" and
connected to the inputs of the NOR gates
If both S (set) and R (reset) are 1 an undefined state
with both output equal to 0 occurs ( it means the SET
and RESET commands are issuing at the same time).
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SR Latch
The SR latch with two cross-coupled NAND gate is
shown in next slide.
By setting S to 0 the output Q will be 1 that putting
the latch in the set state
If S goes to 1 the circuit remains in set state
By setting R to 0 the circuit goes to reset state and
stay there even after both input returns to 1
The undefined state is when both input are 0
Because NAND latch requires 0 signal to change its
state it is also alled -R lat h
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JKFF
The JK flip-flop is an SRFF with some additional
gating logic on the inputs in which the SR=11
u deter i ed o ditio does t e ist
J is used for the set and K is used for reset
J K Q
------------------0 0 Q
0 1 0
1 0 1
Q
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TFF
By connecting K and J we can make TFF
Qt T
Qt + 1
---------------------0 0
0
0 1
1
Qt
Qt
1 1
0
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State Table
The time sequence of inputs, outputs and flip-flop
states can be enumerated in a state table or
transition table
In the state table the present state that shows the
state of flip flops comes first. So n flip flops need n
present states. The inputs, next state and output
come after.
The combination of present state and inputs makes
state table. Output and next state can be derived
from the state equations
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State Table
There are two types of for state tables:
Mealy Model: In this model sequential circuit or state
table the outputs depends on inputs as well as states
Moor Model: Where output depends on state. For
example 2-D version of state table for previous
circuit. Where there are only 4 different states and
for each state the next states and outputs should be
found based on the given inputs.
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State Diagram
Is the graphically representation of state table.
Each state should be circled so for example if we have n
flip flops we have 2n states or n circles
Each circle should be labeled by a binary number.
By using the state table the arrows can be drawn which
show changes from each state to another state.
At the top of each arrow input/output is shown
Also at the top of each arrow only input(s) can be
shown. See next slide
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CPS213
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A. Abhari
CPS213
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A. Abhari
CPS213
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A. Abhari
CPS213
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A. Abhari
CPS213
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A. Abhari
CPS213
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A. Abhari
CPS213
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Introduction: Counters
Counters are circuits that cycle through a specified
number of states.
180
J
C
K
CLK
FF0
CLK
Q0
Q1
J
C
K
FF1
Q0
Q0
Q1
Timing diagram
00 01 10 11 00 ...
182
J
CLK
C
K
C
K
Q0
FF0
CLK
Q1
C
K
Q1
FF2
FF1
Q2
Q0
Q1
Q2
0
Recycles back to 0
183
Q0
Q1
Q2
tPLH
(CLK to Q0)
184
J
CLK
Q1
C
K
C
K
FF0
Q2
J
C
K
FF2
FF1
Q3
J
C
K
FF3
CLK
1
10 11 12 13 14 15 16
Q0
Q1
Q2
Q3
185
sequence.
Technique: force counter to recycle before going
through all of the states in the binary sequence.
Example: Given the following circuit, determine the
counting sequence (and hence the modulus no.)
C
All J, K
inputs are
1 (HIGH).
CLK
Q
CLK
K
CLR
CLK
K
CLR
K
CLR
B
C
186
Exercise: How to construct an asynchronous MOD5 counter? MOD-7 counter? MOD-12 counter?
K
CLR
K
CLR
K
CLR
C
D
E
F
K
CLR
CLR
K
CLR
All J = K = 1.
187
CLR
CLR
CLR
CLR
188
HIGH
J
CLK
C
K
C
K
CLR
C
K
CLR
(A.C)'
C
K
CLR
CLR
10
Clock
D
11
NAND
output
189
Q0
Q1
C
K Q'
C
Q'
K
Q2
C
K Q'
3-bit binary
up counter
J
CLK
C
Q'
K
Q0
C
K Q'
Q1
C
K Q'
Q2
3-bit binary
down counter
190
J
CLK
111
001
1
Q0
Q1
C
K Q'
C
Q'
K
Q2
010
C
K Q'
110
011
101
100
CLK
Q0
Q1
Q2
191
C
Q'
K
Q1
J
C
K Q'
Modulus-4 counter
Q2
J
Q3
J
C
Q'
K
C
K Q'
Q4
J
C
K Q'
Modulus-8 counter
192
Count
pulse
A3 A4 A5
3-bit
binary counter
3-bit
binary counter
A5
A4
A3
A2
A1
A0
0
0
0
0
0
0
:
0
0
0
0
0
0
:
0
0
0
0
1
1
:
0
0
:
1
0
0
:
0
0
:
1
0
0
:
0
1
:
1
0
1
:
193
CTENDecade
TC
counter
C
Q3 Q2 Q1 Q0
CLK
freq/10
CTENDecade
TC
counter
C
Q3 Q2 Q 1 Q0
freq/10
0
freq
194
00
01
11
10
Present
state
Next
state
Flip-flop
inputs
A 1 A0
0
0
0
1
1
0
1
1
A1+ A0+
0
1
1
0
1
1
0
0
TA1 TA0
0
1
1
1
0
1
1
1
195
Next
state
Flip-flop
inputs
A 1 A0
0
0
0
1
1
0
1
1
A1+ A0+
0
1
1
0
1
1
0
0
TA1 TA0
0
1
1
1
0
1
1
1
TA1 = A0
TA0 = 1
1
J
C
Q'
K
A0
A1
C
K Q'
CLK
196
A2+
0
0
0
1
1
1
1
0
Next
state
A1+
0
1
1
0
0
1
1
0
A2
A0
TA2 = A1.A0
A2
Flip-flop
inputs
TA2 TA1 TA0
0
0
1
0
1
1
0
0
1
1
1
1
0
0
1
0
1
1
0
0
1
1
1
1
A1
A0+
1
0
1
0
1
0
1
0
1
A0
TA1 = A0
Synchronous (Parallel) Counters
A2
A1
1
A0
TA0 = 1
197
hro ous i ar
ou ter o td .
TA1 = A0 TA0 = 1
TA2 = A1.A0
A2
A1
A0
CP
1
198
199
1
J
C
Q'
K
A0
A1
C
K Q'
A2.A1.A0
Q
C
K Q'
A2
A3
C
K Q'
CLK
200
Q3
Q2
Q1
Q0
Initially
1
2
3
4
5
6
7
8
9
10 (recycle)
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
0
0
0
0
1
0
1
0
1
0
1
0
1
0
T0 = 1
T1 = Q3'.Q0
T2 = Q1.Q0
T3 = Q2.Q1.Q0 + Q3.Q0
201
T0 = 1
T1 = Q3'.Q0
T2 = Q1.Q0
T3 = Q2.Q1.Q0 + Q3.Q0
Q0
Q
C
Q'
Q
C
Q'
Q1
Q
C
Q'
Q2
Q
C
Q3
Q'
CLK
202
203
Clock pulse
Up
0
1
2
3
4
5
6
7
Q2
Q1
Q0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
TQ0 = 1
TQ1 = (Q0.Up) + (Q0'.Up' )
TQ2 = ( Q0.Q1.Up ) + (Q0'. Q1'. Up' )
Down
Up counter
TQ0 = 1
TQ1 = Q0
TQ2 = Q0.Q1
Down counter
TQ0 = 1
TQ1 = Q0
TQ2 = Q0.Q1
204
ou ter o td .
TQ0 = 1
TQ1 = (Q0.Up) + (Q0'.Up' )
TQ2 = ( Q0.Q1.Up ) + (Q0'. Q1'. Up' )
Q0
1
Up
Q
C
Q'
Q1
T
Q
C
Q'
Q
C
Q2
Q'
CLK
205
Introduction: Registers
An n-bit register has a group of n flip-flops and
Introduction: Registers
206
Simple Registers
No external gates.
Example: A 4-bit register. A new 4-bit data is
loaded every clock cycle.
A3
A2
A1
A0
I3
I2
I1
I0
CP
Simple Registers
207
208
Load
D Q
A0
D Q
A1
D Q
A2
D Q
A3
I0
I1
I2
I3
CLK
CLEAR
Registers With Parallel Load
209
Shift Registers
Another function of a register, besides storage, is to
provide for data movements.
Shift Registers
210
Shift Registers
Basic data movement in shift registers (four
bits are used for illustration).
Data in
Data out
Data out
Data in
Data out
Data in
Data out
(e) Parallel in /
parallel out
(f) Rotate right
211
D Q
C
Q0
D Q
C
Q1
D Q
C
Q2
D Q
C
Q3
Serial data
output
CLK
212
Shift register A
SO
SI
Shift register B
SO
CP
Clock
Shift
control
CP
Wordtime
T1
T2
T3
T4
213
Shift register A
1
1
1
0
1
0
1
1
1
0
1
0
1
1
1
1
1
0
1
1
Shift register B
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
Serial output of B
0
1
0
0
1
214
D Q
D Q
D Q
D Q
CLK
Q0
Data input
CLK
Q1
Q2
Q3
SRG 4
Logic symbol
Q0 Q1 Q2 Q3
215
D1
D2
D3
SHIFT/LOAD
D Q
Q0
D Q
Q1
D Q
Q2
D Q
Q3
Serial
data
out
CLK
SHIFT.Q0 + SHIFT'.D1
216
SRG 4
SHIFT/LOAD
CLK
Logic symbol
217
D1
D2
D3
D Q
D Q
D Q
D Q
CLK
Q0
Q1
Q2
Q3
218
RIGHT/LEFT
Serial
data in
RIGHT.Q0 +
RIGHT'.Q2
D Q
D Q
Q1
D Q
C
Q2
D Q
Q3
Q0
CLK
219
A4
A3
A2
A1
4x1
MUX
3 2 1 0
4x1
MUX
3 2 1 0
4x1
MUX
3 2 1 0
4x1
MUX
3 2 1 0
Clear
CLK
s1
s0
Serial input
for shiftright
I4
I3
I2
I1
Serial input
for shiftleft
Parallel inputs
220
0
1
0
1
Register Operation
No change
Shift right
Shift left
Parallel load
221
Fig. 9.1
Block diagram of an
asynchronous
sequential circuit
223
Analysis Procedure
The procedure
Determine all feedback loops
Assign Yi's (excitation variables), yi's (the
secondary variables)
Derive the Boolean functions of all Yi's
Plot each Y function in a map
Construct the state table
Circle the stable states
224
Examples
Fig. Example of an
asynchronous
sequential circuit
225
226
The difference
228
A flow table
Fig. Example of
flow tables
230
Race conditions
when two or more binary state variables change
value
00 11
00 10 11 or 00 01 11
a noncritical race
if they reach the same final state
otherwise, a critical state
231
232
233
Implication Table
the checking of each pair of states for possible
equivalence
234
235
Compatible pairs
(a,b) (a,c) (a,d) (b,e) (b,f) (c,d) (e,f)
Fig. 9.23
Flow and implication
tables
237
UNIT V
MEMORY
240
Memory Devices
Introduction
Memory unit
a collection of cells capable of storing a large quantity of
information and
to hi h i ar i for atio is tra sferred for storage
fro
hi h i for atio is a aila le he eeded for
processing
together with associated circuits needed to transfer
information in and out of the device
binary
241
Memory Devices
Two major types
RAM (Random-access memory): Read + Write
accept new information for storage to be available later for
use
242
Random-Access Memory
A memory unit stores binary information in groups of bits
1 byte = 8 bits
16-bit word = 2 bytes, 32-bit word = 4 bytes
Interface
n data input and output lines
k address selection lines
control lines specifying the direction of transfer
243
Random-A ess Me or
Addressing
each word is assigned to an address
k-bit address: 0 to 2k 1 word
size: K(kilo)=210, M(mega)=220,
G(giga)=230
A decoder accepts an address and
opens the paths needed to select
the word specified
244
1K words of 16 bits
Capacity: 1K * 16 bits = 2K bytes = 2,048 Bytes
245
246
247
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NAND flash
Types of Memories
Random vs. sequential
Random-Access Memory: each word is accessible separately
equal access time
Sequential-Access Memory: information stored is not
immediately accessible but only at certain intervals of time
magnetic disk or tape
access time is variable
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T pes of Me ories
Static vs. dynamic
SRAM: consists essentially of internal latches and remains
valid as long as power is applied to the unit
advantage: shorter read and write cycles
DRAM: in the form of electric charges on capacitors which
are provided inside the chip by MOS transistors
drawback: tend to discharge with time and must be periodically
recharged by refreshing, cycling through the words every few ms
advantage: reduced power consumption and larger storage capacity
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T pes of Me ories
Volatile vs. non-volatile
volatile: stored information is lost when power is turned off
Non-volatile: remains even after power is turned off
magnetic disk, flash memory
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Read-Only Memory
ROM: permanent binary information is stored
pattern is specified by the designer
stays even when power is turned off and on again
Pins
k address inputs and n data outputs
no data inputs since it doses not have a write operation
one or more enable inputs
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32x8 ROM
A 2kxn ROM has an internal k x2k decoder and n OR gates
32 words of 8 bits each
32*8=256 programmable internal connections
5 inputs decoded into 32 distinct outputs by 5x32 decoder
Each of 8 OR gates have 32 inputs
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ROM
programmable
intersection:
crosspoint switch
T o o ditio s
close: two lines
are connected
open: two lines
are disconnected
I ple e ted fuse
normally connects
the two points
ope ed or lo
by applying a
high-voltage pulse
A7(I4,I3,I2,I1,I0)
= , , ,,
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Types of ROM
4 methods to program ROM paths
mask programming ROM
customized and filled out the truth table by customer and
masked by manufacturers during last fabrication process.
costly; economical only if large quantities
257
T pes of ROM
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Memory Decoding
RAM of m words and n bits: m*n binary storage cells
SRAM cell: stores one bit in its internal latch
SR latch with associated gates, 4-6 transistors
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words of n bits:
go into a kx2k
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Address Multiplexing
DRAM: large capacity requires large address decoding
Simpler cell structure
DRAM: a MOS transistor and a capacitor per cell
SRAM: 6 transistors
Higher density: 4 times the density of DRAM
larger capacity
Lower cost per bit: 3-4 times less than SRAM
Lower power requirement
Preferred technology for large memories
64K(=216) bits and 256M(=228) bits may need 16 and 28
address inputs
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Address Multiplexing
Address multiplexing: use a small set of address input pins to
accommodate the address components
A full address is applied in multiple parts at different times
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Sequential Memory
Sequential-Access Memory: information
stored is not immediately accessible but only
at certain intervals of time
magnetic disk or tape
access time is variable
264
Cache Memory
265
LOCALITY
PRINCIPAL OF LOCALITY is the tendency to reference data items
that are near other recently referenced data items, or that
were recently referenced themselves.
TEMPORAL LOCALITY : memory location that is referenced once
is likely to be referenced multiple times in near future.
CACHE MEMORY
Principle of locality helped to speed up main
memory access by introducing small fast
memories known as CACHE MEMORIES that hold
blocks of the most recently referenced
instructions and data items.
Cache is a small fast storage device that holds the
operands and instructions most likely to be used
by the CPU.
LOAD-THROUGH
STORE-THROUGH
Load-Through : When the CPU needs to read a word
from the memory, the block containing the word is
brought from MM to CM, while at the same time the
word is forwarded to the CPU.
Store-Through : If store-through is used, a word to be
stored from CPU to memory is written to both CM (if
the word is in there) and MM. By doing so, a CM
block to be replaced can be overwritten by an incoming block without being saved to MM.
WRITE METHODS
Note: Words in a cache have been viewed simply as
copies of words from main memory that are read
from the cache to provide faster access. However
this view point changes.
There are 3 possible write actions:
Write the result into the main memory
Write the result into the cache
Write the result into both main memory and cache
memory
PLAs
Programmable Logic Array
275
PLA
276
PLA
277
278
Inputs
Outputs
A B C F0 F1 F2 F3
0 1 1 0
1 1 - 0 1 0 0 0 1
1 - 0 0 1 0 0
- 0 0 1 0 1 0
1 0 0 1
1 - -
Input Side:
1 = asserted in term
0 = negated in term
- = does not participate
Output Side:
1 = term connected to output
0 = no connection to output
Reuse
of
terms
Example: Continued
A
F0 = A + B' C'
F1 = A C' + A B
F2 = B' C' + A B
F3 = B' C + A
AB
BC
AC
BC
A
Personality Matrix
Product Inputs
term
A B C
1 1 AB
- 0 1
BC
1 - 0
AC
- 0 0
BC
1 - A
279
Outputs
F0 F1 F2 F3
0 1 1 0
0 0 0 1
0 1 0 0
1 0 1 0
1 0 0 1
F0
Reuse
of
terms
F1
F2
F3
Memory Hierarchies
Some fundamental and enduring properties of
hardware and software:
Fast storage technologies cost more per byte and have less
capacity
Gap between CPU and main memory speed is widening
Well-written programs tend to exhibit good locality
L0:
registers
L1: on-chip L1
cache (SRAM)
L2:
L3:
Larger,
slower,
and
cheaper
(per byte)
storage
devices
L5:
off-chip L2
cache (SRAM)
main memory
(DRAM)
Main memory holds disk
blocks retrieved from local
disks
L4: