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DC-Link Voltage Balancing for a Three-Level

Electric Vehicle Traction Inverter Using an
Innovative Switching Sequence Control Scheme
Abhijit Choudhury, Student Member, IEEE, Pragasen Pillay, Fellow, IEEE,
and Sheldon S. Williamson, Member, IEEE

Abstract This paper presents an advanced switching

sequence for space-vector pulsewidth modulation (SV-PWM)based three level neutral-point clamped inverter. The developed
scheme helps to reduce the number of converter switching
sequences, compared with the conventional SV-PWM strategy,
and keeps the voltage difference between the two dc-link capacitors at the desired voltage level. The developed test bench is
utilized for a permanent magnet synchronous machine (PMSM)
drive for electric vehicle applications. The proposed strategy is
compared with the performance of a PI controller-based voltage
balancing strategy. The proposed control strategy is based on
the nearest three-vector (N3V) scheme, with a hysteresis control
of the dc-link capacitor voltage difference. Conventional N3V
scheme uses a higher number of switching sequences, which
makes the switching losses higher. In addition, these switching
sequences are not same for all subsectors. This makes the
switching frequency to vary extensively. In the proposed control
strategy, a reduced number of switching sequences are used, and
they are same for all subsectors. This makes the system operate
with constant switching frequency. Detailed simulation studies
are performed to verify the performance of the proposed control
strategy. The performance-based test results are then compared
with those of a PI controller-based strategy. Experimental test
results show significant improvement in the performance of the
PMSM with respect to dc-link capacitor voltage variation as well
as wide speed and torque range of machine operation.
Index Terms Electric vehicles, inverters, motor drives,
permanent magnet motors, propulsion, traction.

I. I NTRODUCTION

ULTILEVEL inverters have attracted special attention

in high power applications in the last three decades,
after its introduction in 1981 [1]. Due to low power ratings
of the switches used for multilevel inverters compared with
two-level inverters for same dc-bus voltages, used in machine
Manuscript received September 1, 2013; revised November 15, 2013 and
December 12, 2013; accepted December 17, 2013. Date of publication
January 2, 2014; date of current version April 4, 2014. This work was
supported in part by Hydro-Quebec and in part by the Auto21 Canadian
National Center of Excellence. Recommended for publication by Associate
Editor H. A. Abu-Rub.
A. Choudhury and S. S. Williamson are with the Department of Electrical
and Computer Engineering, Concordia University, Montreal, QC H3G 1M8
Canada (e-mail: ab_ch@encs.concordia.ca; sheldon@encs.concordia.ca).
P. Pillay is with the Department of Electrical and Computer Engineering,
Concordia University, Montreal, QC H3G 1M8 Canada, and also with
the University of Cape Town, Cape Town 7701, South Africa (e-mail:
pillay@ece.concordia.ca).
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/JESTPE.2013.2296973

drive applications specially for electric vehicles, switching

losses goes down as the switching frequency increases [2].
There are other additional advantages like a reduction in
total harmonic distortion (THD) due to an increase in the
number of voltage steps, which then reduces EMI emission
and high dv/dt stress across semiconductor switches. Other
typical problems associated with two-level inverter like stator
winding insulation break down and bearing failures can also be
significantly reduced in three-level inverter [4]. Hence, many
electric vehicle (EV) manufacturing companies are replacing
two-level inverters with three-level inverters, to drive their
electric machines. This also allows them to increase the
dc-bus voltage level of the inverter. The permanent magnet
synchronous motor (PMSM) is one of the most preferred
choices for electric and hybrid electric vehicle applications,
due to its fast torque response and high torque to weight ratio,
compared with the induction motor.
Although three-level neutral point clamped (NPC) inverters
have been studied widely for many years, the dc-link voltage
balancing algorithm is still a main concern therein. When
two capacitors are not balanced, the dc-link neutral point
can significantly fluctuate, which may cause failure of the
switches due to overstress. Increasing the dc-link capacitance
may solve this problem to some extent, but it will increase the
overall cost of the system. There are many topologies, which
are being proposed for balancing the two dc-bus capacitor
voltages, depending on application requirements [1][33]. In
some applications, the two capacitor voltages are kept constant
by using two separate rectifiers [3], where they need two
transformers with isolated secondary windings, which in turn,
increases the total system cost. This type of transformer can
be replaced by connecting two back-to-back NPC converters
[5], [6].
Another type of control technique is based on the PWM
strategy. They can be divided in two categories: 1) carrierbased PWM; and 2) space-vector PWM (SV-PWM) strategy.
In the carrier-based dc-link voltage balancing algorithm, the
zero sequence voltage is generally added in the output voltage
[7][12]. In addition, most SV-PWM strategies operate in
such a way, so as to optimize the redundant voltage vectors,
to balance the dc-link voltage. In this paper, nearest threevector (N3V) scheme is considered, which is a part of the
SV-PWM technique [14]. In the N3V scheme, redundant
voltage vectors are generally used. These redundant vectors

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CHOUDHURY et al.: DC-LINK VOLTAGE BALANCING FOR A THREE-LEVEL EV TRACTION INVERTER

Fig. 1.

297

Three-level NPC inverter.

use the two capacitor voltage alternatively, to make the

neutral point voltage stable. However, due to the difference
in switching sequence in different subsectors, the switching
frequency is not constant for this type of topology [14].
Some techniques described in literature try to overcome this
problem by dividing the first and second subsector into two
parts, which makes the switching frequency for each sector
equal [15], [16], [27]. However, it makes the number of
subsectors six, instead of four.
Some research has been performed to create a virtual neutral
point, depending on the phase current information, as well as
when the summation of three currents goes down to zero [17].
This also creates more number of subsectors and no results are
shown for transient stability for machine drive applications. All
topologies mentioned above use redundant vector states as well
as varying positive and negative redundant voltage vectors,
depending on the capacitor voltage difference. Furthermore,
they use a PI controller at the output of the voltage difference,
to generate the duty cycle [17], [20]. More recently, some
papers propose to take the neutral point current as a reference,
instead of the capacitor voltages. This makes the current zero
or keeps it in a particular band limit, to control and balance
the dc-link voltage. This strategy also uses the sharing of the
ON -time of positive and negative voltage vector [18], [31]. This
increases the THD of the generated voltage, due to variation of
the switching ON-time. In addition, there also exists a specific
time required to calculate the average value of current to
make it zero, which in turn, makes the system slow. Some
research work shows the combination of the NTV and NTV2
schemes, to get the benefit of low switching frequency from
the NTV scheme. It also leads to better controllability, to
keep the neutral point balanced at all load conditions compared
with the NTV2 scheme [19], [20].
All the above techniques try to reduce the switching frequency compared with the conventional one. However, in
each case, the number of switching subsectors is increased.
In addition, as they are sharing the time between the positive
and negative voltage vectors in each cycle, in transient as well
as steady state, it is not possible to get the exact equal time
sharing. This leads to the asymmetry in generated voltage
and introduces higher harmonic distortion in the generated
voltage. There is also no clear application of these techniques
for EV traction drive applications, where wide range speedtorque variation is necessary. Also, the effect of speed-torque
variations on dc-link capacitor voltage balancing has not been
studied, which affects the performance of machine drastically.

Fig. 2.

Phasor diagram of PMSM.

Fig. 3.

Space-vector diagram for three-level NPC inverter.

The proposed control strategy in this paper reduces the

switching sequence more than the modified strategies, which
reduce the switching losses, and also uses an equal distribution
of switching, by tracking the differences between the two
capacitor voltages at each switching cycle. The performance
of the proposed system with wide range of variation in speed
torque is tested and compared with a PI controller-based
topology.
II. P RINCIPLE OF O PERATION
A. Machine Modeling and Performance Analysis
The machine model equations in general reference frame
are given below, where g denotes the general reference frame
g

d = i d r + pd g

(1)
g

q = i q r + pq + g d

(2)

E ph = kb g
(3)

2 
2
2
V ph = E ph + Iq R + Id X + Iq X + Id R
(4)
g

(5)

g
q

g
Iq

(6)
(7)

d = L s I d +

= Ls
Te Tl = (J p ) + Bm g
 g g
g
g
Te = (3P/2) d i q q i d

(8)

where v d and v q are the d- and q-axes components of the

stator voltage, respectively, Id and Iq are the d- and q-axes
components of stator current, respectively, r is the stator

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TABLE I
D IFFERENT S WITCHING S TATES

TABLE II
D IFFERENT S WITCHING C OMBINATIONS
Fig. 4.

First sextant of three-level space vector.

TABLE III

S WITCHING S TATES FOR T HREE -L EVEL I NVERTER IN S ECTOR 1

resistance, d and q are stator flux linkages in the d- and

q-axes, respectively, L s is the stator self-inductance, is the
rotor magnet flux linkage, due to the permanent magnet on
the rotor side, E ph is the induced back EMF, due to rotor
magnet flux linkage, kb is the back EMF constant, X is the
winding reactance of the machine, Is is the reference current
vector, shown in the phasor diagram, is the power factor
angle between Vph and Is , Te and Tl are the electromagnetic
torque and load torque, respectively, and g is the reference
field speed. The steady-state phasor diagram of the PMSM is
shown in Fig. 2.
B. SV-PWM for Three-Level Inverter
As can be seen from the three-level NPC inverter in Fig. 1,
the inverter has four switches for each leg. There exist two
diodes in each leg, whose neutral point is connected to
the common connection point of the two dc-link capacitors.
Hence, there exist a total of 27 switching combinations, out of
which three are null or zero vectors and 24 are active vectors,
as shown in the vector diagram of Fig. 3.
Out of the 24 active vectors,
12 are small, which gives
Vdc /3, six are medium of Vdc / 3, and six are large voltage
vectors of 2V dc /3 each. Table I shows the different switching
combinations and output pole voltages. Table II shows the list
of different null, small, medium, and large voltage vectors.
Similar to the two-level SV-PWM, in a three-level inverter,
the reference voltage vector is generated with a combination
of the available switching states of that sector.
From Fig. 4, it can be seen that when the reference voltage
vector is placed in subsector three, it can be represented by
the available three voltage vectors POO/ONN (V1 ), PNN (V3 ),
and PON (V2 ). Hence, Vref can be represented as
Vref Ts = T1 V1 + T2 V2 + T3 V3 .

Fig. 5. Effects of different voltage vectors on dc-link capacitor voltage.

(a) Null voltage vector (PPP). (b) Medium voltage vector (PON). (c) P-type
small vector (POO). (d) N-type small vector (ONN). (e) P-type small vector
(PPO). (f) N-type small vector (OON). (g) Large voltage vector (PNN).
(h) Large voltage vector (PPN).

(9)

Here, Ts = T1 + T2+ T3 .
2
In Table III, m = 3Vm /Vdc and Vm = V d + Vq2 . In a
similar manner, when the reference voltage vector moves to
the other subsectors, it can be represented by the other three
voltage vectors, which are available there.

Fig. 6.

Three-level inverter and control strategy model.

As shown in Fig. 4, the time duration for those voltage

vectors based on the reference vector trajectory is shown
in Table III. Due to the repetitive sequence of all other

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TABLE IV
V ECTOR S EQUENCE FOR PI C ONTROLLER -BASED DC-L INK V OLTAGE BALANCING

sectors from 0 to 360 duration, similar equations can be

derived [29].

paper, the performances of the proposed scheme with the

PI-based controller as well as hysteresis-type controller [16]
are compared.

C. Conventional DC-Link Voltage Balancing Algorithm

and Associated Problems

1) PI Controller Algorithm: As shown in Fig. 6, in a typical

PI controller, the difference between the capacitor voltages is
passed through a conditional block, which generates the duty
cycle for the switches. The switching sequence for all sectors
is shown in Table IV.
If we take subsector 1 for sextant 1 into consideration, there
are four redundant voltage vectors, out of which two discharge
the upper capacitor C1 (POO, PPO) and two discharge the
lower capacitor C2 (ONN, OON). So, T1 and T2 can be
distributed into two parts: 1) T1P , T2P and 2) T1N , T2N , as
shown in (10). The PI controller will generate the value of k.
As it is clear, at stable condition, value of k will be 0.5,
when both the capacitor voltages are equal. However, in
practical scenarios, k cannot be constant, and it keeps varying
with motor speed and load torque variation. Because of
this variation, the ON-time for the switches for each cycle
keeps varying, which leads to unsymmetrical switching and
increased THD in the generated voltage. This effect is more
visible in low speed regions, which is proved experimentally
later in this paper. Also, due to the difference in availability

As can be seen from Fig. 3 and Table II, in each sextant,

there exists four types of vector combinations. They have
different effects on the dc-link capacitor voltage distribution.
Fig. 5 shows the effect of those vectors on the two capacitor
voltages. Fig. 5(a), (b), (g), and (h) is the null, medium,
and large voltage vectors, while Fig. 5(c)(f) is the small
voltage vectors. Small and medium voltage vectors are mostly
responsible for voltage unbalance, as they differently affect
the dc-link capacitors. For assumed phased current directions,
the positive small voltage vectors, like POO/PPO, help to
discharge the upper capacitor [Fig. 5(c) and (e)] and the
negative voltage vectors, such as ONN/OON [Fig. 5(d) and (f)]
help to discharge the lower capacitor. In a conventional N3V
technique [18], [9], based on the current direction measured
from the machine terminal, a decision has to made, as to
which capacitor needs to be charged and which one needs to
discharge. To overcome this issue, there exist many topologies,
which have been proposed, as discussed in Section I. In this

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TABLE V
H YTERESIS C ONTROLLER -BASED DC-L INK V OLTAGE BALANCING

of the switching vectors, the switching sequence is different

for different subsectors, which also leads to variable switching
frequency
T1 = kT1P + (1 k)T1N
T2 = kT2P + (1 k)T2N .

(10)

2) Hysteresis Controller Algorithm: Two similar approaches

are proposed in [16] and [18], the switching sequence
of which is shown in Table V. It can be seen that

all the subsectors have same number of sequences, compared with the earlier PI controller-based scheme, while
the duty ratio is constant. However, in sector three and
four, both positive and negative sequence vectors are used,
so that the average current drown from the capacitor is
balanced.
Furthermore, the appropriate sequence is selected for subsector one and two, depending on the capacitor voltage
difference. This type of technique may be preferable for

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301

TABLE VI
P ROPOSED DC-L INK V OLTAGE BALANCING S EQUENCE

low transient system operation. However, for EV traction

applications, due to high dynamic performance, the capacitor
voltage may change differently.

3) Proposed DC-Link Voltage Balancing Algorithm: To

overcome the problem with variable switching frequency
for different subsectors in Table V and to increase the

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Fig. 7. Simulation results for PI controller-based algorithm, with change

in speed from 15.70 to 83.77 rad/s. (a) Motor speed. (b) Phase voltage.
(c) Difference in two capacitor voltages. (d) Stator current.

Fig. 8. Simulation results for proposed dc-link voltage balancing algorithm,

with change in speed from 15.70 to 83.77 rad/s. (a) Motor speed. (b) Phase
voltage. (c) Difference in two capacitor voltages. (d) Stator current.

controllability of the dc-link capacitors for wide speed and

torque range with reduced switching losses, a new switching
sequence is proposed, as shown in Table VI. The total number
of switching in each subsector is five, which is less than
the other switching schemes. Also, since switching sequences

Fig. 9. Simulation results for proposed dc-link voltage balancing algorithm,

with reduced low harmonic distortion while change in speed from 15.70 to
83.77 rad/s. (a) Motor speed. (b) Phase voltage. (c) Difference in two capacitor
voltages. (d) Stator current.

Fig. 10. Simulation results for PI controller-based algorithm, with change

in load torque from 6.0 to 26.0 N-m. (a) Motor speed. (b) Phase voltage.
(c) Difference in two capacitor voltages. (d) Stator current.

are selected depending on the difference in the two capacitor

voltages at each time period Ts , this scheme is more useful and robust for PMSM drive applications in transient as
well as steady-state conditions. It can also be observed that,

CHOUDHURY et al.: DC-LINK VOLTAGE BALANCING FOR A THREE-LEVEL EV TRACTION INVERTER

Fig. 13.

Phase voltage at a MI of 0.33 with carrier signal.

Fig. 14.

THD comparison of phase voltages.

Fig. 15.

Experimental setup for the three-level inverter.

303

Fig. 11. Simulation results for proposed dc-link voltage balancing algorithm,
with change in load torque from 6.0 to 26.0 N-m. (a) Motor speed. (b) Phase
voltage. (c) Difference in two capacitor voltages. (d) Stator current.

Fig. 12. Simulation results for proposed dc-link voltage balancing algorithm
with reduced low harmonic distortion, with change in load torque from 6.0 to
26.0 N-m. (a) Motor speed. (b) Phase voltage. (c) Difference in two capacitor
voltages. (d) Stator current.

in each sequence, one of the switching combinations does not

change (for instance, in sector one subsector one, third bit O
is constant), which reduces the switching losses further.

However, once the duty cycle is specified according to

this strategy, due to the change in the capacitor voltage, the switching sequence may change in between total
switching time period Ts , which may lead to asymmetrical
switching.
To overcome this problem, the change in switching state is
allowed only at the start of each Ts cycle. As shown in Fig. 6,
the control logic block takes the difference in two capacitor
voltages and the carrier signal of the SV-PWM as inputs. When
the capacitor voltage difference is positive (V1 > V2 ) or zero
(V2 > V1 ), the output of the control logic block will give one
or zero. This will choose the appropriate voltage vector from
Table VI. To restrict the change of duty in between switching
cycle, the control logic block updates the voltage difference
information only at the beginning of each switching cycle. It
makes the generated PWM more symmetrical.
Detailed simulation and experimental test results are exhibited, to compare the performance of both systems. It can
be observed from the experimental results that low-order
harmonics are less with the second strategy.

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Fig. 16. Experimental results for PI controller-based algorithm, with change

in speed from 15.70 to 83.77 rad/s. (a) Motor speed. (b) Phase voltage.
(c) Difference in two capacitor voltages. (d) Stator current.

Fig. 18. Experimental results for new dc-link voltage balancing algorithm,
with reduced low harmonic distortion, with change in speed from 15.70 to
83.77 rad/s. (a) Motor speed. (b) Phase voltage. (c) Difference in two capacitor
voltages. (d) Stator current.

Fig. 17.
Experimental results for proposed dc-link voltage balancing
algorithm, with change in speed from 15.70 to 83.77 rad/s. (a) Motor speed.
(b) Phase voltage. (c) Difference in two capacitor voltages. (d) Stator current.

III. S IMULATION R ESULTS

All the simulation studies are carried out in MATLAB/
Simulink Platform. Figs. 79 show the performance of
PI controller-based algorithm, the proposed control strategy,
and the proposed control strategy with the reduction in harmonic distortion, respectively, on PMSM. In the simulation
setup machine speed, phase voltage, dc-link capacitor voltage
difference, and the stator currents are compared. Speed is
increased from 15.70 to 83.77 rad/s, and the variations in other
waveforms are observed. From the phase voltage waveform,
it can be observed that number of steps or level has increased
for all the three strategies with change in speed, which makes
the phase voltage more sinusoidal. From the difference of the
capacitor voltages, it can be observed that the PI controllerbased algorithm is good for a system with low transients. The
PI controller has a specific settling time in terms of dynamic
machine performance, which may be lead to switch damage
due to overvoltage.
From the comparison study of the dc-link capacitor voltage
variation, it can be observed that the variation is (Vpp) 1.0 V
for PI controller-based strategy, 0.3 V for the proposed control
strategy, and 1.4 V for the proposed control strategy with loworder harmonic reduction. In addition, the initial difference

Fig. 19. Experimental results for the PI control algorithm, with 6.0 N-m load
torque. (a) Motor speed. (b) Phase voltage. (c) Difference in two capacitor
voltages. (d) Stator current.

in capacitor voltages for PI controller-based algorithm below

0.7 s can also be observed, which is not present for the other
two control algorithms. This initial offset is present, due to
the settling lime of the PI-based controller. There is not much
difference in steady-state currents for all the control strategies.
In Figs. 1012, the load torque is changed from 6.0 to
26.0 N-m, while speed is kept constant at 52.35 rad/s, and
changes in capacitor voltage are observed.
As it is clear from the results, the capacitor voltages are
balanced and the differences for the three control strategies
are as follows: 1) for the PI controller-based topology, it is
4.0 V; 2) for the proposed control strategy, it is 0.4 V; and
3) for the proposed control strategy with low-order harmonic
reduction, it is 4.0 V. It can be observed that capacitor
voltage difference of the proposed control strategy is 10%
of the PI control-based topology. However, in the low-order
harmonic reduction technique, the voltage difference is almost
equal to the PI-based strategy, with reduction in low-order
harmonics, and battery controllability of the dc-link capacitor
voltages, compared with PI-based topology. The difference in

CHOUDHURY et al.: DC-LINK VOLTAGE BALANCING FOR A THREE-LEVEL EV TRACTION INVERTER

Fig. 20. Experimental results for new dc-link voltage balancing algorithm,
with change in load torque from 6.0 to 26.0 N-m. (a) Motor speed. (b) Phase
voltage. (c) Difference in two capacitor voltages. (d) Stator current.

the capacitor voltages between the two new control strategies

exists, due to the fact that the second strategy uses less
number of switching modes, compared with the other one. The
phase voltage waveforms and steady-state armature currents
are almost similar, with good controllability of machine speed,
during change in load torque.
Fig. 13 shows the phase voltage waveform at a modulation index (MI) of 0.33. Two switching cycles of the phase
voltage are shown, with the carrier waveform proving that the
proposed control strategy works with symmetrical switching
frequency. It can be observed that phase voltage is symmetrical
on both sides of the middle of carrier signal.
Fig. 14 shows the comparison of the phase voltage THD of
the three control strategies for different modulation indexes.
The new control strategies depict almost the same THD as
the PI-based controller for low modulation indexes and have
better performance for high modulation indexes.
IV. E XPERIMENTAL S ETUP AND T EST R ESULTS
Detailed experimental studies are carried out to show the
performance of the proposed system. The control strategies
are implemented using dspace-based real time implementation
tool. Simulation step time was kept at 25 s. The switching
frequency of the carrier is kept constant at 3 kHz. During the
experimental procedure, the dc-link voltage was kept constant
at 270 V. Fig. 15 shows the experimental setup for a three-level
inverter, which feeds a surface PMSM. A dc dynamometer was
used to load the machine.
Figs. 1618 show the experimental test results for speed
change from 15.70 to 83.77 rad/s using PI and the two new
proposed control strategies. From the experimental results of
the PI controller-based algorithm, it can be observed that dclink voltage variation is almost 30 V at low speed and at high
speed it is 8.0 V. Hence, as a result, a large voltage deviation
occurs, which may increase the dv/dt value, and damage the
switches.
On the other hand, the voltage deviation between the two
capacitor voltages for the proposed balancing strategies is

305

Fig. 21. Experimental results for new dc-link voltage balancing algorithm,
with reduced low harmonic distortion, with change in load torque from 6.0 to
26.0 N-m. (a) Motor speed. (b) Phase voltage. (c) Difference in two capacitor
voltages. (d) Stator current.

5.0 V. This is much lower than the PI-based control strategy,

which saves the switches from high voltage breakdown. The
proposed control strategy with reduced low-order harmonic
has a much lower dc-link voltage difference compared with the
second control strategy. Also, the capacitor voltage differences
are a steady dc level. Phase voltage wave shapes are almost
similar, with increased in number of voltage levels, with
change in speed. With the PI-based controller, the stator
current has more spikes and transients, compared with the
other controller, which is due to the poor controllability of
the capacitor voltages.
Figs. 1921 show the performance of the system during
change in load torque from 6.0 to 26 N-m. Speed of the motor
is kept fixed at 52.35 rad/s. It can be observed that capacitor
voltage variation is now 30.0 V even at no load, and due to
this large voltage variation, load change was not possible to be
performed for the PI control strategy. This increase in voltage
difference occurs because of the voltage fluctuation in the low
speed region.
Due to the voltage fluctuation in positive and negative
direction in PI controller at low speeds, compared with the
proposed controller, where variation occurs in constant dc, a
large amount of clockwise and counterclockwise forces are
inflicted on the machine shaft. This loosens the coupling,
which in turn, creates large voltage deviations even in the high
speed range. The capacitor voltage deviation for the two new
proposed control strategies is 4.0 V, which is 1.48% of the
total dc-link voltage. For the stator current, the PI controller
has high phase current transients, compared with the other
strategies, even at lower torque values, because of the reason
stated above. All the other control strategies have better phase
current shapes; in addition, the capacitor voltage difference is
also steady.
Fig. 22 shows the THD comparison for the three schemes.
It can be observed that the PI-based topology has much more
distortion compared with the proposed strategy, as predicted.
This is due to the higher switching frequencies and change in

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THD comparison of phase voltages.

TABLE VII
M ACHINE PARAMETER L IST

duty in between switching cycles. The new proposed control

strategy with lower low-order harmonic distortion strategy has
low voltage distortion compared with the basic one.
Table VII shows all the related parameters for the PMSM
used in simulation and for experimental work.
V. C ONCLUSION
This paper proposed a new dc-link voltage balancing strategy based on N3V for a NPC three-level dc/ac traction
inverter for electric vehicle applications. This scheme is further
modified to reduce the low-order switching harmonics. The
performance of both the strategies was compared with a typical
PI controller algorithm. Both simulation and experimental test
results show a significant improvement in terms of dc-link
voltage balancing ability, as well as in terms of reduction in
total harmonic distortion.
R EFERENCES
[1] A. Nabae, I. Takahashi, and H. Akagi, A new neutral-point-clamped
PWM inverter, IEEE Trans. Ind. Appl., vol. 17, no. 5, pp. 518523,
Sep. 1981.
[2] R. Teichmann and S. Bernet, A comparison of three-level converter
versus two-level converters for low-voltage drives, traction, and utility
applications, IEEE Trans. Ind. Appl., vol. 41, no. 3, pp. 855865,
Jun. 2005.
[3] B. P. Schmitt and R. Sommer, Retrofit of fixed induction motors with
medium voltage drive converters using NPC three-level inverter high
voltage IGBT based topology, in Proc. IEEE ISIE, vol. 2. Pusan,
Korea, Jun. 2001, pp. 746751.
[4] H. Abu-Rub, J. Holtz, J. Rodriguez, and G. Baoming, Medium-voltage
multilevel convertersState of the art, challenges, and requirements
in industrial applications, IEEE Trans. Ind. Electron., vol. 57, no. 8,
pp. 25812596, Aug. 2010.
[5] F. Wang, Multilevel PWM VSIs, IEEE Ind. Appl. Mag., vol. 10, no. 4,
pp. 5158, Aug. 2004.

[6] J. Pou, R. Pindado, D. Boroyevich, and P. Rodrguez, Limits of the

neutral-point balance in back-to-back-connected three-level converters,
IEEE Trans. Power Electron., vol. 19, no. 3, pp. 722731, May 2004.
[7] J. Steinke, Switching frequency optimal PWM control of a three-level
inverter, IEEE Trans. Power Electron., vol. 7, no. 3, pp. 487496,
Jul. 1992.
[8] S. Ogasawara and H. Akagi, Analysis of variation of neutral point
potential in neutral-point-clamped voltage source PWM inverters, in
Proc. IEEE Ind. Appl. Soc. Annu. Meeting, Toronto, ON, Canada,
Oct. 1993, pp. 965970.
[9] C. Newton and M. Sumner, Neutral point control for multi-level
inverters: Theory, design and operational limitations, in Proc. IEEE
32nd IAS Annu. Meeting Ind. Appl. Conf., New Orleans, LA, USA,
Oct. 1997, pp. 13361343.
[10] J. Pou, J. Zaragoza, S. Ceballos, M. Saeedifard, and D. Boroyevich,
A carrier-based PWM strategy with zero-sequence voltage injection
for a three-level neutral-point-clamped converter, IEEE Trans. Power
Electron., vol. 27, no. 2, pp. 642651, Feb. 2012.
[11] N. Celanovic and D. Boroyevich, A comprehensive study of neutralpoint voltage balancing problem in three-level neutral-point-clamped
voltage source PWM inverter, IEEE Trans. Power Electron., vol. 15,
no. 2, pp. 535541, Mar. 2000.
[12] A. Videt, P. Le Moigne, N. Idir, P. Baudesson, and X. Cimetiere, A new
carrier-based PWM providing common-mode-current reduction and DCbus balancing for three-level inverters, IEEE Trans. Ind. Electron.,
vol. 54, no. 6, pp. 30013011, Dec. 2007.
[13] N. Celanovic and D. Boroyevich, A fast space-vector modulation
algorithm for multilevel three-phase converters, IEEE Trans. Ind. Appl.,
vol. 37, no. 2, pp. 637641, Mar. 2001.
[14] Y. Katsutoshi and M. H. Ahmet, A novel neutral point potential
stabilization technique using the information of output current polarities and voltage vector, IEEE Trans. Ind. Appl., vol. 38, no. 6,
pp. 15721580, Nov. 2002.
[15] J. Pou, R. Pindado, D. Boroyevich, and P. Rodriguez, Evaluation of
the low-frequency neutral-point voltage oscillations in the three-level
inverter, IEEE Trans. Ind. Electron., vol. 52, no. 6, pp. 15821588,
Dec. 2005.
[16] H. Zhang, S. J. Finney, A. Massoud, and B. W. Williams, An SVM
algorithm to balance the capacitor voltages of the three-level NPC
active power filter, IEEE Trans. Power Electron., vol. 23, no. 6,
pp. 26942702, Nov. 2008.
[17] S. B. Monge, J. Bordonau, D. Boroyevich, and S. Somavilla,
The nearest three virtual space vector PWMA modulation for the
comprehensive neutral point balancing in the three-level NPC inverter,
IEEE Power Electron. Lett., vol. 2, no. 1, pp. 1115, Mar. 2004.
[18] G. I. Orfanoudakis, A. Yuratich, and S. M. Sharkh, Nearest-vector modulation strategies with minimum amplitude of low-frequency neutralpoint voltage oscillations for the neutral-point-clamped converter, IEEE
Trans. Power Electron., vol. 28, no. 10, pp. 44854499, Oct. 2013.
[19] C. Xia, H. Shao, Y. Zhang, and X. He, Adjustable proportional hybrid
SVPWM strategy for neutral-point-clamped three-level inverters, IEEE
Trans. Ind. Electron., vol. 60, no. 10, pp. 42344242, Oct. 2013.
[20] R. Maheshwari, S. M. Nielsen, and S. B. Monge, Neutral-point current
modeling and control for neutral-point clamped three-level converter
drive with small DC-link capacitors, in Proc. IEEE ECCE, Phoenix,
AZ, USA, Sep. 2011, pp. 20872094.
[21] J. Rodriguez, L. G. Franquelo, S. Kouro, J. I. Leon, R. C. Portillo,
M. A. M. Prats, et al., Multilevel converters: An enabling technology for high-power applications, Proc. IEEE, vol. 97, no. 11,
pp. 17861817, Nov. 2009.
[22] T. Bruckner and D. G. Holmes, Optimal pulse-width modulation for
three-level inverters, IEEE Trans. Power Electron., vol. 20, no. 1,
pp. 8289, Jan. 2005.
[23] C. Wang and Y. Li, Analysis and calculation of zero-sequence voltage
considering neutral-point potential balancing in three-level NPC converters, IEEE Trans. Ind. Electron., vol. 57, no. 7, pp. 22622271,
Jul. 2010.
[24] S. B. Monge, J. Bordonau, D. Boroyevich, and S. Somavilla, The
nearest three virtual space vector PWMA modulation for the comprehensive neutral-point balancing in the three-level NPC inverter, IEEE
Power Electron. Lett., vol. 2, no. 1, pp. 1115, Mar. 2004.
[25] J. Pou, J. Zaragoza, P. Rodriguez, S. Ceballos, V. Sala, R. Burgos,
et al., Fast-processing modulation strategy for the neutral-point clamped
converter with total elimination of the low-frequency voltage oscillations
in the neutral point, IEEE Trans. Ind. Electron., vol. 54, no. 4,
pp. 22882299, Aug. 2007.

CHOUDHURY et al.: DC-LINK VOLTAGE BALANCING FOR A THREE-LEVEL EV TRACTION INVERTER

[26] S. B. Monge, J. D. Ortega, J. Bordonau, J. A. Beristain, and J. Rocabert,

Closed-loop control of a three-phase neutral-point-clamped inverter
using an optimized virtual-vector-based pulse width modulation, IEEE
Trans. Ind. Electron., vol. 55, no. 5, pp. 20612071, May 2008.
[27] Y. S. Lai, Y. K. Chou, and S. Y. Pai, Simple PWM technique of
capacitor voltage balance for three-level inverter with DC-link voltage
sensor only, in Proc. 33rd Annu. Conf. IEEE Ind. Electron. Soc., Taipei,
Taiwan, Nov. 2007, pp. 17491754.
[28] K. H. Bhalodi and P. Agarwal, Space vector modulation with DC-link
voltage balancing control for three-level inverters, in Proc. IEEE Int.
Conf. PEDES, New Delhi, India, Dec. 2006, pp. 16.
[29] P. M. Meshram, D. Hanote, and M. M. Renge, A simplified spacevector PWM for three level inverters applied to passive and motor load,
in Proc. 4th IEEE ICIEA, Xian, China, May 2009, pp. 33833393.
[30] O. Dordevic, M. Jones, and E. Levi, A comparison of carrierbased and space vector PWM techniques for three-level five-phase
voltage source inverters, IEEE Trans. Ind. Informat., vol. 9, no. 2,
pp. 609619, May 2013.
[31] A. Lewicki, Z. Krzeminski, and H. Abu-Rub, Space-vector pulse width
modulation for three-level NPC converter with the neutral point voltage
control, IEEE Trans. Ind. Electron., vol. 58, no. 11, pp. 50765086,
Nov. 2011.
[32] K. Rajashekara, Present status and future trends in electric vehicle
propulsion technologies, IEEE J. Emerging Sel. Topics Power Electron.,
vol. 1, no. 1, pp. 310, Mar. 2013.
[33] J. Li, A. Huang, A. Q. Huang, Z. Liang, and S. Bhattacharya, Analysis
and design of active NPC (ANPC) inverters for fault-tolerant operation
of high-power electrical drives, IEEE Trans. Power Electron., vol. 27,
no. 2, pp. 519533, Feb. 2012.

Abhijit Choudhury (S11) received the B.E. degree

from the National Institute of Technology, Agartala,
India, in 2007, the M.Tech. degree in electrical
engineering from IIT, Bombay, India, in 2011. He
is currently pursuing the Ph.D. degree with the
Department of Electrical and Computer Engineering,
Concordia University, Montreal, QC, Canada.
He was a Management Trainee with ABB, Vadodara, India, from 2007 to 2008, and General Motors,
Bangalore, India, from 2011 to 2011, as a Graduate Trainee. His current research interests include
converter control techniques, electrical machine drives, and electric vehicle
architecture.

Pragasen Pillay (S84M87SM92F05) received

the bachelors and masters degrees from the University of Kwa-Zulu Natal, Durban, South Africa, in
1981 and 1983, respectively, and the Ph.D. degree
from Virginia Polytechnic Institute and State University, Blacksburg, VA, USA, in 1987.
He is currently a Professor with the Department
of Electrical and Computer Engineering, Concordia University, Montreal, QC, Canada, where he
holds the NSERC/Hydro Quebec Industrial Research
Chair. From 1988 to 1990, he was with the University of Newcastle-upon-Tyne, Newcastle-upon-Tyne, U.K. From 1990 to
1995, he was with the University of New Orleans, New Orleans, LA, USA.
From 1995 to 2007, he was with Clarkson University, Potsdam, NY, USA,
where he held the Jean Newell Distinguished Professorship in engineering.
He is an Adjunct Professor with the University of Cape Town, Cape Town,
South Africa. His current research interests include modeling, design, and
control of electric motors and drives for industrial and alternate energy
applications.

307

Dr. Pillay is a member of the IEEE Power Engineering, the IEEE Industry
Applications (IAS), the IEEE Industrial Electronics, and the IEEE Power
Electronics Societies. He is a member of the Electric Machines Committee,
and Past Chairman of the IEEE Industrial Drives Committee of the IAS,
the Induction Machinery Subcommittee of the IEEE Power Engineering
Society, and the Awards Committee of the IAS Industrial Power Conversion
Department. He has organized and taught short courses in electric drives at
IAS Annual Meetings. He is a fellow of the Institution of Electrical Engineers
and Technologists, U.K., and a Chartered Electrical Engineer in the U.K. He
is a member of the Academy of Science of South Africa. He was a recipient
of the Fulbright Scholarship and he received the Order of Mapungubwe from
the President of South Africa in 2008 for contributions to South Africa in the
area of energy conservation.

Sheldon S. Williamson (S01M06) received the

B.E. (Hons.) degree in electrical engineering from
the University of Mumbai, Mumbai, India, in 1999,
and the M.S. and the Ph.D. (Hons.) degrees in
electrical engineering from the Illinois Institute of
Technology, Chicago, IL, USA, specializing in automotive power electronics and motor drives at the
Grainger Power Electronics and Motor Drives Laboratory, in 2002 and 2006, respectively.
He has been an Associate Professor with the
Department of Electrical and Computer Engineering,
Concordia University, Montreal, QC, Canada, since 2006. He has offered
numerous conference tutorials, lectures, and short courses in the areas of
automotive power electronics and motor drives. He is the principal author or
co-author of over 150 journal and conference papers. He is the author of the
book entitled Energy Management Strategies for Electric and Plug-in Hybrid
Electric Vehicles (Springer, 2013), four chapters in the book entitled Vehicular
Electric Power Systems (Marcel Dekker, 2003), and two chapters in the book
entitled Energy Efficient Electric Motors (CRC Press, 2004). His current
research interests include the study and analysis of electric drive trains for
electric, hybrid electric, plug-in hybrid electric, fuel cell vehicles, modeling,
analysis, design, and control of power electronic converters and motor drives
for land, sea, air, and space vehicles, as well as the power electronic interface,
and control of renewable energy systems.
Dr. Williamson was the General Chair for the IEEE Transportation Electrification Conference, Bangalore, India, in 2015. He was the Student Activities
Chair for the IEEE Energy Conversion Congress and Exposition, Montreal,
Quebec, in 2014. He served as the Technical Program Chair for various conferences, including the Annual Conference of the IEEE Industrial Electronics
Society in 2012, the IEEE Vehicle Power and Propulsion Conference in 2011,
and the IEEE Canada Electrical Power and Energy Conference in 2009. He
served as the Project Coordination and Awards Chair at the 2007 IEEE Canada
Electrical Power Conference, Montreal, Canada. He was the Conference
Secretary for the 2005 IEEE Vehicle Power and Propulsion Conference,
Chicago, IL, USA. He is the beneficiary of numerous awards and recognitions.
He was a recipient of the prestigious Paper of the Year Award from the IEEE
Vehicular Technology Society (IEEE VTS) in 2006. He received the overall
Best Paper Award at the IEEE PELS and VTS Co-sponsored Vehicle Power
and Propulsion Conference in 2007. He received the Best Paper Award at
the IEEE Canada Electrical Power and Energy Conference, Halifax, Nova
Scotia, Canada, in 2010, the prestigious Sigma Xi/IIT Award for Excellence
in University Research from 2005 to 2006, and the Best Research Student
Award from the Electrical Computer Engineering Department, Illinois Institute
of Technology, Chicago, in 2006. He currently serves as a Distinguished
Lecturer of the IEEE VTS. He serves as Associate Editor for the IEEE
T RANSACTIONS ON I NDUSTRIAL E LECTRONICS , the IEEE T RANSACTIONS
ON P OWER E LECTRONICS , and the IEEE J OURNAL OF E MERGING AND
S ELECTED T OPICS IN P OWER E LECTRONICS . He serves as the IEEE Industry
Applications Society Chapter Chair for the IEEE Montreal Section. He is a
member of the IEEE PELS, IES, and VTS.