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EE241 - Spring 2007

Advanced Digital Integrated


Circuits
Lecture 23: Latches and Flip-Flops

Announcements
Final exam on May 8 in class
Project presentations on May 3, 1-5pm

Class Material
Last lecture
SRAM

Todays lecture
Latches and flip-flops

Latches: Reading
Rabaey et al, Chapters 7 and 10
Chapter 10 in Chandrakasan et al, by Partovi
Stojanovic, Oklobdzija, JSSC 4/99

Latch vs. Flip-Flop


z

Flip-Flop (register)
stores data when
clock rises

Latch
stores data when
clock is low
D Q

D Q

Clk

Clk

Clk

Clk

Q
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Latch vs. Flip-Flop

Courtesy of IEEE Press, New York. 2000

Latch Pair vs. Flip-Flop


Performance metrics
Delay metrics
Delay penalty
Clock skew penalty
Inclusion of logic
Inherent race immunity

Power/Energy Metrics
Power/energy
PDP, EDP

Design robustness
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Latches
Negative latch
(transparent when CLK= 0)

Positive latch
(transparent when CLK= 1)

Latches
Transmission-Gate Latch

C2MOS Latch

Clk
Clk

D
Clk

Clk

Latches

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Courtesy of IEEE Press, New York. 2000

TSPC - True Single Phase Clock Logic

VDD

VDD

M1

VDD

VDD
M1

In

M1

M1

Out

Out

In

M2

M2

M2

M2

Out

Out
In

In

M3

M3

Precharged P

Precharged N

M3

M3

Non-precharged N

Non-precharged P

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TSPC - True Single Phase Clock Logic


VD D

VDD

VDD

VDD

PUN
In

Static
Logic

Out

PDN

Including logic into


the latch

Inserting logic between


latches

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Doubled TSPC Latches

VDD

VDD

VDD

VDD

Out
In

Doubled n-TSPC latch

Out

Doubled p-TSPC latch

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DEC Alpha 21064

Dobberpuhl, JSSC 11/92

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DEC Alpha 21064


L1:

L2:

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DEC Alpha 21064


Integrating logic into latches
Reducing effective overhead

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DEC Alpha 21164

L2 Latch

L1 Latch

L1 Latch with logic


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Latch Pair as a Flip-Flop

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Requirements for the Flip-Flop Design


High speed of operation:
Small Clk-Output delay
Small setup time
Small hold timeInherent race immunity

Low power
Small clock load
High driving capability
Integration of logic into flip-flop
Multiplexed or clock scan
Robustness
Crosstalk insensitivity
- dynamic/high impedance nodes are affected
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Sources of Noise

Courtesy of IEEE Press, New York. 2000

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10

Gate Isolation

Courtesy of IEEE Press, New York. 2000

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Flip-Flop Robustness
Robustness of the storage node
Input isolation
Data stored statically, max resistance limit
Min capacitance limit
Preventing storage node exposure

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Types of Flip-Flops
Latch Pair
(Master-Slave)

Pulse-Triggered Latch
L1
Data

L2

D Q

D Q

Clk

Clk

L
Data
Clk

D Q
Clk

Clk

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Flip-Flop Delay
z

Sum of setup time and Clk-output delay is the true


measure of the performance with respect to the
system speed
T = TClk-Q + TLogic + Tsetup+ Tskew

D Q

Logic

D Q
N

Clk

TClk-Q

Clk

TLogic

TSetup
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Delay vs. Setup/Hold Times


350
300
Minimum Data-Output
Clk-Output [ps]

250
200
150

Setup

Hold

100
50
0
-200

-150

-100

-50

50

100

150

200

Data-Clk [ps]

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Master-Slave Latch Pairs


Positive setup times
z Two clock phases:
z

distributed globally
generated locally

Small penalty in delay for incorporating


MUX
z Some circuit tricks needed to reduce the
overall delay
z

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Master-Slave Latch Pairs


Case 1: PowerPC 603 (Gerosa, JSSC 12/94)
Vdd

Clk

Vdd

Clkb
Q

Clkb

Clk

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T-G Master-Slave Latch


Feedback added for static operation
Unbuffered input
input capacitance depends on the phase of the clock
over-shoot and under-shoot with long routes
wirelength must be restricted at the input
Clock load is high
Low power
Small clk-output delay, but positive setup

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Master-Slave Latches
Vdd

Case 2: C2MOS

Vdd

Ck

Ckb

Ckb

Ck

Vdd

Vdd

Clk

Vdd

Vdd

Ck

Feedback added for static operation


Locally generated clock
Poor driving capability

Vdd

Vdd

Ckb

Ck

Ck

Ckb

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Master-Slave TSPC Flip-flops


VDD

VDD

(a) Positive edge-triggered D flip-flop

VDD

VD D

VDD

VDD

VDD

VDD

(b) Negative edge-triggered D flip-flop

VDD

(c) Positive edge-triggered D flip-flop


using split-output latches

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Pulse-Triggered Latches
First stage is a pulse generator
generates a pulse (glitch) on a rising edge of the clock
Second stage is a latch
captures the pulse generated in the first stage
Pulse generation results in a negative setup time
Frequently exhibit a soft edge property

Note: power is always consumed in the pulse generator

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Pulsed Latch
Simple pulsed latch

Kozu, ISSCC96

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Intel/HP Itanium 2

Naffziger, ISSCC02

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Pulse-Triggered Latches
Hybrid Latch Flip-Flop, AMD K-6
Partovi, ISSCC96
Vdd
Q
Q

D
Clk

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HLFF Operation
1-0 and 0-1 transitions at the input with 0ps setup time

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Hybrid Latch Flip-Flop


Skew absorption

Partovi et al, ISSCC96

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Pulse-Triggered Latches
AMD K-7

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Courtesy of IEEE Press, New York. 2000

Pulse-Triggered Latches
Semi-Dynamic Flip-Flop (SDFF),
Sun UltraSparc III, Klass, VLSI Circuits98
Vdd

Vdd

Q
Q
D
Clk

Pulse generator is dynamic, cross-coupled latch is added for robustness. Loses soft
edge on rising transition
Latch has one transistor less in stack - faster than HLFF, but 1-1 glitch exists
Small penalty for adding logic
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Pulse-Triggered Latches
7474, from early 1960s

Clk

Q
R

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Pulse-Triggered Latches
Case 4: Sense-amplifier-based flip-flop, Matsui 1992.
DEC Alpha 21264, StrongARM 110
First stage is a sense amplifier,
precharged to high, when Clk = 0
After rising edge of the clock sense
amplifier generates the pulse on
S or R
The pulse is captured in
S-R latch
Cross-coupled NAND has different
propagation delays of rising and
falling edges

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Sense Amplifier-Based Flip-Flop

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Courtesy of IEEE Press, New York. 2000

Flip-Flop Performance Comparison


Test bench

Data

Total power consumed


internal power
Clock
data power
clock power
Measured for four cases
no activity (0000 and 1111)
maximum activity (0101010..)
average activity (random sequence)

Clk Q

200fF
200fF

50fF

Delay is (minimum D-Q)


Clk-Q + setup time

Stojanovic, Oklobdzija JSSC 4/99


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Flip-Flop Performance Comparison

70

Total power [uW]

60

TG M-S

50

Original SAFF

HLFF

40
30

mSAFF

20

C MOS

SDFF

10
0
100

150

200

250

300

350

400

450

500

Delay [ps]

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Sampling Window Comparison

Naffziger, JSSC 11/02

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Local Clock Gating


2

CKI
0.85

1.2

0.85

DI

0.5
0.85

0.5

0.5

CKIB

CKIB

0.5

0.5

Data-Transition
Look-Ahead
Pulse
Generator

0.85

0.5

0.85

0.5

XNOR

CKIB
0.85

Clock on demand
Flip-flop

CKI

CP
0.5

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Next Lecture
Timing

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