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1 This tutorial provides a step-by-step guide to simulating a Verilog description of a 2-input AND gate
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1. Start Xilinx ISE Project Navigator
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2. Create a new project
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Click on File, then choose New Project on the drop down menu
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Enter your project name, in this case the project is called AND2gate
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Choose your project location, this project is stored at Z:\Projects\AND2gate
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Leave the working directory entry blank.
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Choose HDL as the source type from the Top-Level Source Type menu.
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Click Next button
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273.You will be asked to select hardware and design flow for the project
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For Device, choose XC3S500E
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For Package, choose FG320
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For Speed, choose -4
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For Simulator, choose ISim (VHDL/Verilog)
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Click Next button
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A project summary will appear. Click on the Finish button.

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535. Now you will be have project named and2gate.v,nnext you want specify files within
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56 Click on Simulation
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64simulation
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Now we want to add a new file to our project.

Click on Project, choose New Source
Choose Verilog Module as the file type

In the File name: box enter the desired file name, in this case the file is named
and2gate.v
Click on the Next button

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1007. now you will be asked to give port names/types you can skip this step by clicking on NEXT button

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A project summary will appear. Click on the Finish button.

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119And2gate.v
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added to

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14910. Click on the and2gate.v tab to show the file contents. You are now ready to specify the
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workspace
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Click on and2gate.vtab
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182 11. Notice that the ISE has already entered a comments sections along with a couple of lines of code
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The line `timescale 1ns/ 1ps is located at the top of the file. The Verilog language uses
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dimensionless time units, and these time units are mapped to real time units within the
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simulator. `timescale is used to map to the real time values using the statement
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`timescale <time1> / <time2>, where <time1> indicates the time units associated with the
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#delay values, and the <time2> indicates the minimum step time used by the simulator.
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The and2gate module is also declared using module and2gate(); and endmodule, but
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the ports are left for us to define.
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We finish specifying the functionality of the and2gate module as shown below.
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Module andgate(a,b,c);
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Input a,b;
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Output c;
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Reg c;
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always@(a,b)
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begin
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c=a&b;
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end
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endmodule
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23212.We also want to add test bench by following same procedure 8-11,then add functionality of it
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timescale 1ns / 1p
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module and2gate_tb();
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reg A_t, B_t;
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wire F_t;
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and2gate and2gate_1(A_t, B_t, F_t);
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initial begin
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// case 0
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A_t<=0; B_t<=0;
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#1 $display("F_t = %b", F_t);
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// case 1
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A_t<=0; B_t<=1;
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#1 $display("F_t = %b", F_t);
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// case 2
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A_t<=1; B_t<=0;
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#1 $display("F_t = %b", F_t);
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// case 3
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A_t<=1; B_t<=1;
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#1 $display("F_t = %b", F_t);
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end

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endmodue

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25613. After saving both and2gate.v and and2gate_tb.v, we want to check the syntax of
257both files.
258 Expand the ISim Simulator menu, double click on Behavioral Check Syntax
259 If the syntax was correct, a checkmark appears beside the Check Syntax menu
260 If the syntax was incorrect, the window at the bottom will list the individual errors.
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267Expand Isim simulator
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298Double click in simulate behavior model
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31114. Now its time to simulate the design.
312 Double-click on the Simulate Behavioral Model icon
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$display ,$monitor will be displayed here
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34015. The ISim Simulator open in a new windows displaying a waveform and run a default
341simulation for some number of time units. We can now check the and2gate modules
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35616. To view the beginning of simulation, click on the Go To Time 0 button.

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Time button

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37517. We can now see the simulation waveform for the beginning of our simulation. Click on
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Click on zoom out button
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40218. To control the simulation time, we can restart the simulation and simulate for a specific
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404We will now have an empty waveform.

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Click on restart button
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43319. To simulate for a specific length of time, enter the desired simulation time and
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Enter simulation time and click on run for
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