A New Basic Unit for Cascaded Multilevel Inverter

A New Basic Unit for Cascaded Multilevel Inverter

with the Capability of Reducing the Number of
Switches
Sara Laali* and Ebrahim Babaei
*

Faculty of Electrical and Computer Engineering, University of Tabriz, Tabriz, Iran

Abstract
In this paper, a new basic unit is proposed. Then, a cascaded multilevel inverter basded on series connection of the n
number of new basic units is proposed. In order to generate all voltage levels (even and odd) at the output, three different
algorithms to determine the magnitude of the dc voltage source are proposed. Reduction the number of power switches, driver
circuits and dc voltage sources in addition to increasing the numbr of output voltage levels are some of the advantages of the
proposed cascaded multilevel inverter. These results are obtained through comparison of the proposed inverter and its algorithms
with the H-bridge cascaded multilevel inverter from the number of power electronic devices points of view. Finally, the ability of
the proposed topology with its proposed algorithms in generation all voltage levels is verified thruogh laboratorary prototype
experimental results on a 49-level inverter.
Key words: Multilevel Inverters, H-Bridge Cascaded Multilevel Inverter, New Basic Unit

I.

INTRODUCTION

The multilevel inverters have received more attention in

comparison with the traditional two level inverters. These
inverters generate stepped waveform by using a number of dc
voltage sources as inputs. With an increasing the number of
dc voltage sources in input side, the sinusoidal like waveform
can be generated at the output that leads to high power
quality, lower harmonic component and electromagnetic
interference. The other advantages of the multilevel inverters
are lower voltage stress on power electronic switches and
high efficiency. In addition, it is possible to use of these
inverters in high power and medium voltage applications
[1-3]. These inverters are utilized as high power static
converters in middle and high voltage applications such as
electric machines drive, dynamic voltage restoration, reactive
power compensators and FACTS devices [4-6].
There are three main topologies and several derivation
topologies for multilevel inverters. The main topologies are
diode-clamped multilevel inverters, flying capacitor
multilevel inverters and cascaded multilevel inverters [3], [6].
The cascaded multilevel inverter has received special
attention due to the modularity, simplicity of the control,
reliability and lower power electronic devices for generation

a specific output voltage level [4-5], [7-8]. The cascaded

multilevel inverters are mainly classified into two groups:
symmetric cascaded multilevel inverter and asymmetric
cascaded multilevel inverter [5]. In symmetric cascaded
multilevel inverter the magnitude of all dc voltage sources are
equal, which causes higher number of insulated gate bipolar
transistors (IGBTs), power diodes and dc voltage sources to
generate high number of output levels. These features lead to
increasing installation space and total cost of the inverter.
These are the main disadvantages of the symmetric cascaded
multilevel inverters while the same value for the dc voltage
sources are the most significant advantage for them. Two
symmetric cascaded multilevel inverters have been presented
in [10-11]. It has been also presented H-bridge cascaded
multilevel inverter in [9]. In [9], two different algorithms
have been presented that lead to symmetric and asymmetric
topologies. In order to increase the number of output voltage
levels asymmetric cascaded multilevel inverters have been
presented in literatures. In asymmetric topology, the
magnitude of dc voltage sources is unequal. Therefore, there
are different algorithms to determine the value of dc voltage
sources. In [12-13] two other algorithms as asymmetric
topologies have been presented for H-bridge cascaded

2
multilevel inverters. In addition, two other topologies for
asymmetric cascaded multilevel inverters have been
presented in [5] and [14]. The major advantage of the
asymmetric cascaded topology is considerable increasing the
number of output voltage levels by using low number of dc
voltage sources and power switches but the high variety in
the magnitude of the dc voltage sources is the most
remarkable disadvantage of them.
In this paper, a cascaded multilevel inverter based on the new
basic unit is proposed. This inverter increases the number of
output voltage level by using minimum number of power
switches, driver circuits and dc voltage sources. Then, three
different algorithms to generate all voltage levels are
proposed. These advantages are confirmed by comparison the
proposed inverter and its algorithms with the H-bridge
cascaded multilevel inverter. Finally, the obtained
experimental results on a 49-level inverter reconfirm the
correct performance of the proposed topology in generation
all voltage levels.

II. PROPOSED TOPOLOGY

The new proposed basic unit is shown in Fig.1. As Fig. 1
shows, the proposed basic unit consists of two dc voltage
sources, two bidirectional switches ( S 3 , S 4 ) and four
unidirectional ones ( S 1 , S 2 , S 5 and S 6 ) from voltage point
of view. The bidirectional switches conduct current and
voltage in two direction but unidirectional switches conduct
current in two direction and blocked voltage in one direction.
In addition, each unidirectional switch consists of an IGBT
with an anti-parallel power diode and a driver circuit,
however the bidirectional ones include of two IGBTs with
two anti-parallel power diodes and a driver circuits if the
switch with common emitter configuration is used. Therefore,
the number of driver circuit for the bidirectional switches is
as same as unidirectional ones in the proposed basic unit.
According to Fig. 1, the switches ( S 1 , S 3 ), ( S 1 , S 5 ), ( S 3 , S 5 ),
( S 2 , S 4 ), ( S 2 , S 6 ) and ( S 4 , S 6 ) should not be turned on
simultaneously, because short-circuit across the dc voltage
sources would be produced. Table I shows the output voltage
levels of the proposed unit based on different switching
patterns. In this Table, 1 and 0 indicate the on and off states
of the switches, respectively. As shown in Table I, the
proposed basic unit is able to generate seven voltage levels
(three positive levels, three negative levels and one zero
level) at the output. It is also obvious that this basic unit is
able to generate all positive and negative voltage levels at the
output.

S1

S2
V1

S3

S4

vo

V2

S5

S6

Fig.1. The proposed basic unit.

TABLE I.
THE OUTPUT VOLTAGE OF THE PROPOSED BASIC UNIT
BASED ON DIFFERENT SWITCHING PATTERNS
State

S1

S2

S3

S4

S5

S6

vo

+V 1

+V 2

+(V 1 +V 2 )

V 1

V 2

(V 1 +V 2 )

A new cascaded multilevel inverter could be made by series

connection of the n number of the basic unit. This new
proposed cascaded multilevel inverter is shown in Fig. 2. The
output voltage of the proposed inverter is equal to adding the
output voltage of each unit and can be written as follows:
v o (t=
) v o ,1 (t ) + v o ,2 (t ) + + v o , n (t )

(1)

where n is the number of series connected of the basic unit.

S 2,1

S 1,1
V 1,1

S 3,1

S 4,1

v o ,1

V 2,1

S 5,1

S 6,1

S 1,n

S 2,n

vo

V 1,n

S 4,n

S 3,n

v o ,n

V 2,n

S 6,n

S 5,n

Fig. 2. Series connection of n number of the basic unit.

In the proposed cascaded multilevel inverter, the number of

switches (N switch ) , IGBTs (N IGBT ) , driver circuits (N driver )
and dc voltage sources (N

source

) are calculated as follows:

A New Basic Unit for Cascaded Multilevel Inverter

N switch = 6 n

(2)

N level =
(3 2n +1 ) 5

(14)

N IGBT = 8 n

(3)

V o ,max =
3 (2n 1)V dc

(15)

N driver = 6 n

(4)

N source = 2n

(5)

C. Third Proposed Algorithm ( P3 )

In this sub-section, the values of the dc voltage sources are

It is important to note that in the basic proposed unit
selected as follows:
determination the magnitude of dc voltage sources has most
significant influence in increasing the number of generated
(16)
V=
1,1 V=
1,1 V dc
output voltage level, used power electronic devices and so the
j 1
(17)
=
V 1, j 3=
V dc
for j 2, 3, , n
amount of installation space and total cost of the inverter.
Therefore, to generate all voltage levels, three different
(18)
V 2, j = 2 3 j 1V dc
algorithms to determine the value of used dc voltage source
In this condition, the number of output voltage levels and the
will be proposed.
maximum magnitude of the output voltage are written as
follows:
A. First Proposed Algorithm ( P1 )
(19)
N level
= 3n +1 4
In this sub-section, the amplitude of the two used dc voltage
in the basic units is written as follows:
3n +1 5
(20)
V o ,max =
V dc
2
First unit:
V 1,1 =V dc

(6)

V 2,1 = 2V dc
n

th

(7)

unit:
n 1 2

V 1,=
V dc + 2V i , j
n

(8)

V 2, n = 2V 1, n

(9)

i 1=
j 1
=

In this algorithm, the number of output voltage levels

(N level ) and the maximum amplitude of the producible

(10)

7 1
= V dc
V o ,max

The most important aim of introducing the new-cascaded

multilevel inverter and its proposed algorithms is increasing
the number of output voltage levels by using less number of
power electronic devices such as switches, IGBTs, power
diodes, driver circuits and so on. In this section, a comparison
between the proposed topology and its algorithms with
H-bridge cascaded multilevel inverter is done to investigate
the advantages and disadvantages of the proposed cascaded
inverter.
The proposed topology based on the first, second and third

output voltage (V o ,max ) are respectively equal to:

N level = 7 n

III. COMPARING THE PROPOSED GENERAL

TOPOLOGY WITH THE H-BRIDGE TOPOLOGY

(11)

proposed algorithms are considered as P1 P3 in this

investigation, respectively. In [9], the H-bridge cascaded
multilevel inverter and two different algorithms have been
presented. One of them is known as the symmetric cascaded
inverter (V=
V=

= V=
V dc ) and another is known
1 V=
2
3
n
as asymmetric ones
(V 1 V=
, V n 2n 1V dc ). In
=
2V dc=
dc ,V 2

B. Second Proposed Algorithm ( P2 )

In the second proposed algorithm, the magnitudes of the dc
voltage sources are determined as follows:

this

comparison,

these two different

algorithms

are

considered as R1 and R 2 , respectively. In order to

V 1, j = 2 j 1V dc

(12)

increasing the number of output voltage levels by using

minimum number of H-bridges, two other algorithms is

V 2, j = 2 jV dc

(13)

presented in [12-13] and are considered by R 3 R 4 in this

Considering this proposed algorithm, the number of output

voltage levels and the maximum magnitude of the output
voltage are calculated as follows:

comparison ( R 3 for V=

= V=
2V dc and
1 V dc , V =
2 V=
3
n

R 4 for V=
V=

= V=
3V dc ). Fig. 3 indicates
1 V dc , V =
2
3
n
the H-bridge cascaded multilevel inverter.

4
Fig. 4 compares the number of power electronic switches in
the proposed cascaded multilevel inverter based on its
proposed algorithms with the H-bridge cascaded inverter. As
shown in this figure, the number of required power switches
in the proposed cascaded inverter based on the first proposed
algorithm is lower than the H-bridge cascaded inverter. In
addition, this proposed algorithm has even better performance
between other presented algorithms for the proposed
topology.

proposed algorithm, is lower than the H-bridge cascaded

inverter and other presented algorithms for the proposed
topology.
200
160

R1

R3

120
N IGBT
80

R4

P3 P2

R2

40
0

20

40 N level

60

P1

80

100

Fig. 5. Variation of N IGBT versus N level

S 2,1

Vn

V2

V1

S1,1

50

S3,1

S1,2

S3,2

S1,n

S3,n

S 4,1

S 2,2

S 4,2

S 2,n

S 4,n

40

R1
30

io

vo

Fig. 3. The H-bridge cascaded multilevel inverter

R1

120
N switch
or 80
N driver
40
0

R2 P3

20

40

N level

60

80

R4

R2

20

40

N level

60

80

P2
P1

100

Fig. 6. Variation of N source versus N level

R4

R3

P3

10

200

160

R3

N source
20

P2
P1

100

Fig. 4. Variation of N switch or N driver versus N level

As mentioned before and based on the used power switches

in the proposed topology and H-bridge cascaded inverter, the
number of power switches in the proposed cascaded
multilevel inverter is equal to the number of driver circuits.
As a result, this topology needs less number of driver circuits
than H-bridge cascaded inverter.
Because of using bidirectional switches in the proposed
topology, it is necessary to compare the number of required
IGBTs in this topology with the H-bridge cascaded multilevel
inverter. This comparison is shown in Fig. 5. As Fig. 5 shows,
the proposed cascaded topology based on the first proposed
algorithm uses lower number of IGBTs than H-bridge
cascaded inverter. However, the unidirectional switches are
only used in the cascaded multilevel inverter. The first
proposed algorithm has also best performance between other
proposed algorithms in the number of required IGBTs points
of view. As mentioned before, the numbers of power diodes
are equal to the number of IGBTs. As a result, the number of
power diodes in the proposed inverter is lower than H-bridge
cascaded inverter.
Fig. 6 compares the number of dc voltage sources in the
proposed topology with the H-bridge cascaded multilevel
inverter. As it is obvious, the number of used dc voltage
sources in the proposed topology especially based on the first

Table II shows the comparison of the value of the blocked

voltage on power switches, IGBTs and driver circuits of the
proposed topology with the H-bridge cascaded inverter. As
shown in this Table, the value of blocked voltage on IGBTs is
completely depends on the magnitude of used dc voltage
sources.
TABLE II
THE COMPARISON OF THE BLOCKED VOLTAGE ON
IGBT IN THE PROPOSED TOPOLOGY AND CASCADED
MULTILEVEL INVERTER
Topology

H-bridge
cascaded
inverter

Algorithms

V block

Presented in [9]
(symmetric)

4nV dc

Presented in [9]
(asymmetric)

4(2n 1)V dc

Presented in [12]
(asymmetric)

4(2n 1)V dc

Presented in [13]
(asymmetric)

4(3n 2)V dc

First proposed

8
V dc (7 n 1)
3

algorithm ( P1 )
Proposed
topology

Second proposed
algorithm ( P2 )
Third proposed
algorithm ( P3 )

16 (2n 1)V dc
(8 3n 14)V dc

A New Basic Unit for Cascaded Multilevel Inverter

As above comparisons indicate, the lower number of required

power electronic switches, driver circuits, IGBTs, power
diodes and dc voltage source are the most important
advantages of the proposed cascaded multilevel inverter that
cause the reduction in the installation space and total cost of
the inverter.

100V

2.5ms

(b)

IV. EXPERIMENTAL RESULTS

The correct performance of the proposed cascaded multilevel
inverter in generation all voltage levels at the output is
verified through experimental results on a 49-level inverter
based on the basic proposed unit and shown Fig. 2. This
inverter consists of two basic units, four dc voltage sources,
four bidirectional switches and eight unidirectional switches.
The magnitude of its dc voltage sources are determined by
using first proposed algorithm. Therefore, by assuming the
value of V 1,1 = 10V , so the amplitude of the dc voltage
sources in the first and second units based on (7), (8) and (9)
are equal to V 2,1 = 20V , V 1,2 = 70V , and V 2,2 = 140V ,
respectively. According to (10) and (11) this inverter is able
to generate 49 levels (twenty-four positive levels, twenty-four
negative levels and one zero level) with the maximum
amplitude of 240V at the output. It is important to note that
the IGBTs used on the prototype are HGTP10N40CID (with
an internal anti-parallel diode). The 89C52 microcontroller by
ATMEL Company has been used to generate all switching
patterns. The connected load to the inverter is considered a
resistive-inductive load with the values of R= 60 and
L = 55 mH . In this paper, the fundamental frequency

switching control method is used. The main reason to select

this control method is its low switching frequency than other
control methods that leads to reduction in switching losses
The experimental output voltage waveforms of the first and
second units are shown in Fig. 7(a) and Fig. 7(b), respectively.
As this figues show, each unit is able to generat a step
waveform with the pasitive and negative amplitude. In
addition, the maximum amplitude of output voltage in each
unit is equal to adding the magnitude of the used dc voltage
surces.

10V

Fig. 7. The output voltages; (a) first bridge; (b) second bridge

Moreover, the experimental output voltage and current

waveforms are indicated in Fig. 8. As it is obvious from Fig.
8, this inverter generates 49 levels with the maximum
amplitude of 240V and 3.87A at the output. In addition, the
step generated output voltage waveform consists of all
pasitive and negative voltage levels and is looklike sinosuidal
one. There are two differences between voltage and current
waveforms while compare to each other. The current
waveform is more looklike to a sinosuidal one than the
voltage waveform. In addition, there is a phase shift between
voltage and current. These differences are because of the
resistive-inductive load feature that acts as a low pass filter.
As mentioned before, the basic proposed unit consists of two
bidirectional switch and four unidirectional ones from voltage
point of view. In order to investigate these facts in the
proposed cascaded multilevel inverter, the blocked voltage on
each switch of the first basic unit are shown in Fig 9 as
instance. It is poited out that all of the obtained results are
based on the first proposed algorithm. Fig. 9(a), 9(b), 9(c) and
9(d) show the blocked voltage on switches S 1,1 , S 2,1 ,
S 5,1 and S 6,1 , respectively. As shown in Figs. 9(a) and 9(b),

the values of the blocked voltage on the switches S 1,1 and

S 2,1 are 10V or 30V, which are depends on the switching

pattern. Moreover, the Fig. 9(c) and 9(d) show the blocked
voltage on the switches S 5,1 and S 6,1 that are either 20V or
30V. It is clear that, the magnitudes of the blocked voltage on
switches are either positive or zero, so there is any negative
amount on them. In addition, the amount of blocked voltage
is equal to add of the magnitude of the used dc voltage
sources in the first basic unit. As a result, the existence of
four unidirectional switches is reconfirmed in the proposed
cascaded multilevel inverter. Fig. 9(e) and Fig. 9(f) show the

blocked voltage by the switches S 3,1 and S 4,1 , respectively.

2.5ms

(a)

As shown in these figures, the values of the blocked voltage

by them are either 10V or 20V based on different switching
patterns. Moreover, there are positive and negative amount of
voltages on power switches. This fact verifies that the

6
switches S 3,1 and S 4,1 are bidirectional ones.
10V
0

100V
500mA

2.5ms

(f)
Fig. 9. The blocked voltage on the power switches in the first
2.5ms

basic unit; (a) S 1,1 ; (b) S 2,1 ; (c) S 5,1 ; (d) S 6,1 ; (e) S 3,1 ; (f)

Fig. 8. Voltage and current output waveforms.

S 4,1 .

It is important to note that these values are directly depends

on the considered algorithm to determine the magnitude of dc
voltage sources and by changing the selected algorithms these
magnitudes will be different but their positive and negative
values will be also same.

10V
0

2.5ms

(a)

V. CONCLUSION
10V
0

2.5ms

(b)

10V
0

2.5ms

(c)

In this paper, a new basic unit for cascaded multilevel

inverters is proposed. Then, three different algorithms to
determine the magnitude of the dc voltage sources are
proposed. Comparisons between the H-bridge cascaded
multilevel inverter and proposed inverter show the significant
advantages of the proposed topology in the number of
switches, driver cicuits, IGBTs, power diodes and dc voltage
sources. In addition, it is obtained that the first proposed
algorithm has the best performance from all proposed
algorithms and the H-bridge cascaded inverter. On the other
hand, if it is required to generate minimum 49 levels at the
output, the proposed topology based on the first proposed
algorithm and equations (2) to (5) needs N switch = 12 ,

N IGBT = 16 , N Driver = 12 and N source = 4 while in the same

10V

conditions, the H-bridge cascaded inverter based on binary

method

that

is

shown

by

R2

requires

N=
N=
N=
24 and N source = 6 . Finally, in
switch
IGBT
Driver
2.5ms

(d)

order to verify the capability of the proposed cascaded

inverter in generation all voltage levels, the experimental
results on a 49-level inverter is used.

10V
0

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Sara Laali was born in Tehran, Iran in

1984. She received the B.S. degree in
electronics engineering from Islamic Azad
University, Tabriz Branch, and the M.S.
degree in electrical engineering from
Islamic Azad University, South Tehran
Branch, Iran, in 2008 and 2010, respectively.
In 2010, she joined the Department of Electrical Engineering,
Adiban Higher Education Institute. Now, she is PhD student in
electrical engineering at the faculty of Electrical and Computer
Engineering, University of Tabriz.

Her major fields of interest include the analysis and control of

power electronic converters, multilevel converters, and FACTS
devices.
Ebrahim Babaei was born in Ahar, Iran in
1970. He received his B.S. and M.S. in
Electrical Engineering from the Department
of Engineering, University of Tabriz, Tabriz,
Iran, in 1992 and 2001, respectively,
graduating with first class honors. He
received his Ph.D. in Electrical Engineering
from the Department of Electrical and
Computer Engineering, University of Tabriz, Tabriz, Iran, in
2007. In 2004, he joined the Faculty of Electrical and Computer
Engineering, University of Tabriz. He was an Assistant Professor
from 2007 to 2011 and has been an Associate Professor since
2011. He is the author of more than 280 journal and conference
papers. He also holds 16 patents in the area of power electronics
and has more applications pending. Dr. Babaei has been the
Editor-in-Chief of the Journal of Electrical Engineering of
University of Tabriz since 2013. In 2013, he was the recipient of
the Best Researcher Award from of the University of Tabirz.
His current research interests include the analysis and control of
power electronic converters and their applications, power system
transients, and power system dynamics.