Measurement 46 (2013) 402410

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Measurement
journal homepage: www.elsevier.com/locate/measurement

A LabVIEW based automatic test system for sieving chips

Zhongyuan Wang a, Yongheng Shang b,, Jiarui Liu b, Xidong Wu a
a
b

School of Information Science and Electronic Engineering, ZheJiang University, China

School of Aeronautics and Astronautics, ZheJiang University, China

a r t i c l e

i n f o

Article history:
Received 26 April 2012
Received in revised form 14 June 2012
Accepted 19 July 2012
Available online 27 July 2012
Keywords:
LabVIEW
PXI
DAQ
CMOS chip
DAC testing
Automatic testing system

a b s t r a c t
The present trend for Complementary Metal Oxide Semiconductor (CMOS) chip designs is
smaller in size and power consumption with multifunction. This results the difculty for
the testing engineer, especially for small amount production without an automatic probe
station, to complete such task. In order to reduce the workload of the engineer, improve
the testing efciency and accuracy, a LabVIEW based automatic test system for such CMOS
chip has been designed in this paper. The details of the overall system which includes the
setup of the testing by using a PXI (PCI extensions for instrumentation) system with Data
Acquisition (DAQ) and Source Measure Units (SMUs) module, and the LabVIEW based automatic testing program has been introduced in this paper. The testing results have shown
that this system is able to improve the testing efciency with great accuracy, at the same
time to evaluate the testing results in real-time. Due to the software is built on different
modules, and it is therefore easy to be extended for different applications.
2012 Elsevier Ltd. All rights reserved.

1. Introduction
As the interface between the digital processing and analog signals, the Digital-to-Analog Converter (DAC) is widely
utilized in Integrated Circuit (IC). And the testing of DAC is
studied by numbers of researchers. An Analog-to-Digital
Converter (ADC) is always used in the testing of DAC in
most case [13]. Therefore, many algorithms based on
the use of ADC have been raised for the signal processing
in recent years [46]. However, with the fast development
of the technology and the testing instruments related to
Data Acquisition (DAQ), the testing of DAC becomes more
convenient and accurate than ever before. And certain
attention should be paid to the architecture of the testing
system.
In this project, a highly integrated multifunction Complementary Metal Oxide Semiconductor (CMOS) chip has

Corresponding author. Tel.: +86 (0)571 8795 1639; mobile: +86

(0)18257146541.
E-mail addresses: zhongyuan_wang@yeah.net (Z. Wang), banylora.
shang@gmail.com (Y. Shang), 20924034@zju.edu.cn (J. Liu), xwu@zju.
edu.cn (X. Wu).
0263-2241/$ - see front matter 2012 Elsevier Ltd. All rights reserved.
http://dx.doi.org/10.1016/j.measurement.2012.07.015

been designed for the application of a transmit-receive

(TR) system. It consists two sets of functions. One is to control the working states of the system with the designed
logical functions. The second is to provide the bias voltages
for all the active devices such as switches and power
ampliers (PAs) by using its build-in DACs. Therefore,
the logic function of the chip must be veried to ensure
the control ow of the chip in designed working order. At
the same time, the voltage levels provided by the DACs
within the chip have to be evaluated, in order to guarantee
the bias voltages supplied to the active devices are in the
designed accuracy range. This is because the different bias
voltage affects the performance of the active devices such
as the gain of the PAs, which further affects the overall performance of the whole system. In general, the testing
system for such chip involves a power supply, signal generator, data acquisition system, testing bench, real-time
analysis system and testing engineer watching over the
processing of the testing. This requires many connections
between instruments which lead to a messy testing station. The most important is that it makes the calibration
of the system error becomes difcult, and also introduces
extra testing error to the nal results. Besides, due to the

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huge amount of data has to be acquired, stored and processed in real-time, therefore, an automatic test system
must be designed to cope with the measurement time
and the data processing time, at the same time reduce
the errors brought by manual operation and the workload
of the testing engineer.
The PCI extensions for instrumentation (PXI) platform
together with Laboratory Virtual Instrument Engineering
Workbench (LabVIEW) programming environment developed by National Instruments (NIs) is adopted as the cornerstone piece of equipment to construct the automatic
test system.
2. System conguration

Fig. 2. PXI platform of NI.

The system conguration is shown in Fig. 1. The system

contains three parts: a PXI platform, a Field Programmable
Gate Array (FPGA) board and a probe station with a probe
card.
The PXI platform is used as the main control part of the
automatic test system. It is responsible for test control,
power supply, and data acquisition, processing and storage. The PXI of NI is a PC-based platform for measurement
and automation. A typical PXI platform is shown in Fig. 2. It
has four components: chassis, controller, modules and
software [7].
The chassis is the backbone of the PXI system. It provides the power, cooling, and communication buses of
Peripheral Component Interface (PCI) and PCI Express for
the controller and modules [8]. In the chassis, there is a
controller slot with an operation system such as Microsoft
Windows for users to operate with display screen. The
modules inserted to the chassis act as a whole system
without any other connection which reduces the system
error produced by the connections between instruments.
Different module has its specied function and can be used
with other modules or independently. In this paper, the NI
X Series DAQ module PXIe 6363 is used for data acquisition. Its resolution is 16 bits, which guarantees the
accuracy of the testing results. It offers 32 single ended
channels, and that means 32 voltages could be acquired
at the same time. A Source Measure Units (SMUs) module
PXIe 4140 is utilized for power supply and current
monitor.
A FPGA board is designed as the sub-control part of the
automatic test system which communicates between the
PXI and the chip on the probe station. First, it receives commands from the PXI through RS232, and then forwards the
corresponding outputs to the CMOS chip through Serial

Fig. 3. Probe card on the probe station.

Peripheral Interface (SPI). The outputs contain power

supply signals and control commands to the CMOS chip.
The control commands allow the DACs of the CMOS produce the corresponding voltage levels and working states
of registers in the chip.
In general, a CMOS chip without pins cannot be connected to the test equipments directly without contaminate its pins. In order to do so, a probe station is utilized
for holding the chip, and connects the pads of the chip to
the corresponding signal channels of the PXI platform
and the FPGA board with a custom-made probe card. The
pins of the probe card are connected to the PXI signal
channels, and its probes are connected to the pads of the
chip. Using a probe station in the test system makes it convenient to exchange chips, keeps the chip from contamination (especially the chip is assembled to a module for
further using), and improves the accuracy. A typical probe
card in the probe station is illustrated in Fig. 3

3. Software system
DAQ module
PXI Chassis

Probe Station
RS232

FPGA

SPI

SMU module

Fig. 1. System conguration.

CMOS Chip

The software level of this testing system is based on the

LabVIEW platform. LabVIEW is a graphical programming
environment which helps engineers quickly to develop
powerful test software with beautiful and convenient
Graphical User Interface (GUI). A LabVIEW program
consists of numbers of Virtual Instrument (VI). A VI consists of a front panel, a block diagram and an icon that rep-

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evaluate the testing results, which includes data acquisition, storage and processing. Then the results are shown
in the form of associated waveform. The software ow
chart is shown in Fig. 4.
First, the hardware related should be congured as
introduced in the previous section. In this system, the
COM port of PXI is used to communicate with FPGA, and
their parameters about communication must be consistent
with each other. The ve parameters related are congured
as follows:






Fig. 4. Software ow chart.

resents the VI. The front panel displays controls and indicators for the users, while the block diagram contains the
code of the VI. LabVIEW contains many basic VIs which allows the programmer to construct a GUI in a much shorter
time than other conventional programming languages
such as C/C++, Visual Basic, and Matlab. Its graphical nature makes it ideal for measurement and automation [9,10].
To meet the testing requirements, the software is divided into three parts. The rst part is to verify the logic
functions of the CMOS chip. The second part is to test the
performances of DACs in the chip. And the third part is to

Baud rate: 115200 bit per second.

Data bit: 8.
Stop bit: 2.
Parity bit: odd.
Flow control: none.

The conguration can be achieved through the VI VISA

Congure Serial Port in the Virtual Instrumentation Software Architecture (VISA) library. VISA regulates the rules
and principles between the modules of the virtual
instruments, which leads to the reducing the number of
instruments needed in the overall system and the connections between those instruments [11]. At the same time, it
eliminates some system errors.
At the same time, the physical addresses of the DAQ and
SMU module need to be congured as well. The drivers of
DAQ and SMU are installed to ensure the right address conguration within the testing system. The CMOS chip under
testing has nine voltage outputs. Therefore, nine DAQ
channel addresses have to be congured to cope with. In
here, a VI DAQmx Create Virtual Channel is utilized. In
the case of logical level testing, seven DAQ channels are
used. There are also two more channels used for DAC testing. The SMU used in here contains four channels and two
of them are selected to provide the +3.3 V and 3.3 V
power supply independently.
Then, it goes to logic test. In this paper, eight working
states of the chip should be tested. A while loop structure
is used to realize the cycle test. Seven output voltages

Fig. 5. Block diagram of logic level test.

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405

Fig. 6. Block diagram of DAC test.

Fig. 7. Calculation of INL and DNL.

should be measured in each state and the currents should

be monitored throughout all the states. If one of the seven
voltages acquired by the DAQ is out of the range or the
currents monitored by the SMU are beyond 10 mA (a maximum designed error margin), it means the chip is not
working properly, such as the connection between the needles of the probes and the pads of the chips are loosen, the
chip is damaged before has been put on the probe card.
Then the software exits and testing is over. The block
diagram of logic test is shown in Fig. 5.
If the voltages and currents from the output of the DAQ
and SMU are normal, the automatic test system performs
the evaluations of the DACs in the CMOS chip. There are
three 8 bit and two 12 bit DACs in the CMOS chip. Two 8
bit DACs are chosen for this paper. The designed range of
the output voltage of the eight bit DACs is from 2 V to
0 V. The eight bit DAC has 256 codes, and each code
corresponds to a voltage output. 256 voltages should be
measured to attain the transfer function of the DAC. The
block diagram of DAC test is shown in Fig. 6.

A while loop structure is adopted to change codes of

DACs in order to complete the cycle test. Two voltages of
the two DACs are measured and acquired by the DAQ module in each cycle. Meanwhile, the currents of the CMOS
chip are monitored by the SMU. If the currents are beyond
the range which is set as an error limit before stating the
program, the testing ends immediately.
If the test is completed successfully, 256 voltages will
be acquired and stored for each DAC. The data could be displayed directly to attain the transfer function. Besides, the
Integral Nonlinearity (INL) and Differential Nonlinearity
(DNL) error of DAC should be displayed as well.
For a DAC, DNL is the difference between the measured
change and the ideal 1 Least Signicant Bit (LSB) change
between any two adjacent codes [12]. For the eight bit
DAC used in here, 1 LSB equals to 2821 V. Usually, DNL is
calculated in LSB, and that means the difference should
be divided by 1 LSB. The calculation of the DNL is given by

DNLi

xi  xi  1  1LSB
1LSB

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Fig. 8. Main user test interface.

Fig. 9. DNL and INL display interface.

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407

Fig. 10. Transfer function of the DAC_A.

Fig. 11. DNL of the DAC_A.

where x[i] represents the measured voltage corresponding

to the code of number i [13,14].
INL is a measurement of the maximum deviation from a
straight line passing through the endpoints of the DAC
transfer function [12]. INL can be calculated from the accumulation of DNL [13]. In this paper, INL is given by

INLi

xi  x0  i  1LSB

1LSB

panel of the software. The using of the tab control allows

all the controls can be managed clearly with respect to
their usage. Two option cards are created in the tab control.
One option card is used to show the main user interface
and the transfer function of the DACs as shown in Fig. 8,
and the other is to show the DNL and INL errors of the
DACs as shown in Fig. 9.

which is derived from denition introduced in [12]. The

block diagram of the calculation of DNL and INL is shown
in Fig. 7. According to Eqs. (1) and (2), the calculation can
be conveniently performed in LabVIEW by using its
arithmetic VIs.
The graphical nature of LabVIEW makes it convenient to
display the result through the waveform control. And the
user interface could be designed friendly, clearly and beautifully. In this program, a tab control is used in the front

4. Test results
In this project, the rst group of 150 chips has been
tested by using the proposed automatic test system. The
testing time for each chip can be done within half a minute
which includes the evaluation of the logic functions and
assessment of the performances of the DACs within the
chip. In order to demonstrate the results of the DACs, one
set of results for a single chip is illustrated as follows.

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Fig. 12. INL of the DAC_A.

Fig. 13. Transfer function of the DAC_B.

Fig. 14. DNL of the DAC_B.

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409

Fig. 15. INL of the DAC_B.

The two tested DACs are represented by the name of

DAC_A and DAC_B.
The transfer function of the DAC_A is shown in Fig. 10.
As shown, the vertical axis is the voltage level and the horizontal axis is the code number of the DAC. The designed
voltage level is from 2 V to 0 V, and the test result shows
there are small deviations from the designed values, but
the slop of the transfer function is a smooth line. In order
to know the details of the error from the designed transfer
function, the DNL and INL are given in Figs. 11 and 12.
As shown in Fig. 11, the DNL of the DAC_A is within
1LSB at the preceding half of the codes. The absolute
value of DNL reaches to almost 3LSB with the increase of
the code, which means the output of the DAC is getting
worse with respect to the increase of the code. The INL is
within 2LSB as shown in Fig. 12, but the points of the
INL are all scattered around the zero lines, which indicates
that the change of the DNL is spread around the center line
as well.
Fig. 13 shows the transfer function of the DAC_B which
is also a smooth line with small deviations from designed
values. The DNL and INL are shown in Figs. 14 and 15.
As illustrated in Fig. 14, the DNL of the DAC_B is within
2LSB, which is better than the DNL of the DAC_A shown in
Fig. 11. This indicates the performance of DAC_B is better
than DAC_A. On the other hand, the plot of the INL for
DAC_B suggests that the changes of the DNL are toward
the negative axis. This is demonstrated that the most of
the DNL points are in the negative sate.
5. Conclusions
In this paper, an advanced automatic test system based
on a NIs PXI and LabVIEW programming environment for a
CMOS chip has been introduced. It has the properties of
increasing the testing accuracy by reducing the connection
induced system error and illuminating the human interaction error; improving the testing efciency by using automatic testing software; and reducing the workload for

the testing engineer during the sieving process. The automatic test system completes the whole test of the CMOS
chip within 5 min and the testing time is more than 2 h
with the normal automatic test system. The test results
have shown that the proposed automatic testing system
is able to perform the chip logical function evaluation
and verify its DACs output in a short time with great accuracy. It also demonstrated that the testing system can work
in real time. Besides, the modularization structure of the
system makes it convenient to be extended or modied
for different applications. Only a little change to the program can help to test some more parameters without
changing the connections of the hardware.
However, the automatic testing system still has room to
be optimized with respect to the testing time. Such as the
trigger function within the NI PXI which allows furthering
reduce the processing time and improve the sieving efciency. On the other hand, the automatic testing system
can be used for device with ADCs with a few modication
of the system.
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