Beruflich Dokumente
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IN AN FPGA DEVICE
Paulo Csar C. de Aguirre, Lucas Teixeira, Crstian Mller, Fernando Lus Herrmann,
Leandro Z. Pieper, Josu de Freitas, Gustavo Dessbesell, Joo Baptista Martins
Electrical Engineers Course Microelectronics Group
Federal University of Santa Maria
Santa Maria, Brazil
email: paulocomassetto@gmail.com, lucasteixeira@mail.ufsm.br,
cristianmuller.50@gmail.com, herrmann@mail.ufsm.br, leandrozaf@gmail.com,
josue.freitas@mail.ufsm.br, gfd@mail.ufsm.br, batista@inf.ufsm.br
ABSTRACT
This paper describes an implementation in hardware
of Internet Protocol version 4. Routing and addressing
features were integrated with Network Interfaces and
synthesized to a Stratix II FPGA device. Our work
showed two implementations of a full duplex Internet
Protocol version 4. The first implementation consists
in a Reference design and the second uses the same
design but with more buffer space. We present the
advantages and disadvantages of each implementation
and also compare in terms of throughput, frame loss
rate and power dissipation. The implementation with
more buffer space presents a better performance in
frame loss rate but it dissipates more power than the
Reference design. Both implementations presented
similar results for throughput tests.
Fig. 1.
1.
INTRODUCTION
2. IPV4 DEVELOPMENT
The IP protocol is responsible for sending and
receiving data packets through the Internet and it is
described in RFC 791 [4]. This protocol is not entirely
reliable, but is a fast mechanism to data transfer. The
version 4 of this protocol was chosen because it is the
most used worldwide and gives a more area-effective
159
Reference design Buffer Increased design Reference design Buffer Increased design
PLL
13.41
13.41
0.00
0.00
I/O
38.43
38.36
0.52
0.55
Dedicated memory
62.30
432.74
4.37
18.94
Combinational cell
55.68
65.17
10.00
10.02
Register cell
127.23
193.91
65.55
122.36
internal FIFOs.
The Hardware layer consists in an ASIC (High
Performance
Triple-Speed
Marvell
88E1111
10/100/1000 Ethernet PHY [7]), available in an
expansion board connected to the development board
which contains the FPGA device. Two daughter
boards were used in this implementation. Each one
contains one network interface and a PHY.
The HDL (Hardware Description Language) used
in the IP-core codification was SystemVerilog. After
verified all functional requirements of the design a
few more blocks were codified to allow the
prototipation in a development board containing an
FPGA device and network interfaces.
The full system that was build to test the Internet
Layer in real application is shown in Fig. 1. Drivers
where coded to adapt the MAC interfaces with
Avalon Streaming [8] communication protocol to
IPv4 interfaces with AMBA AXI [9] communication
protocol. AMBA AXI protocol is used at IPv4 block
because it is simple to implement and allows high
frequency operation. Each input driver contains a
buffer responsible for storing the frame incoming
from the MAC. This buffers can store only one frame,
so that the received frame is stored and just the
Internet Protocol datagram is sent to IPv4-core. The
MAC header is discarded by the driver. Analogous to
the input drivers, the output ones have also buffers
with the same storage capacity and build a frame
header that is sent to the network layer.
A development kit named Nios II Development
Board Stratix II Edition containing a Stratix II
EP2S60-F672C3N FPGA device was used. Both
logic synthesis and power dissipation estimation were
performed using Altera Quartus II 9.0 tool. Synthesis
results are shown in Table 1, while power dissipation
estimates are depicted in Table 2.
FPGA PROTOTIPATION
160
4. PERFORMANCE MEASUREMENTS
4.3. Frame Loss Rate Test
161
http://download.intel.com/design/network/datashts/825
44ei.pdf.
6. CONCLUSIONS
This work presented implementation and
performance results for a reference and a modified
(with more buffer area) design of a hardware IPv4
block featuring a full communication stack..The
modified design consumes 2.5 times more power and
around 26 times more area (mainly memory blocks)
than the original one.
However, frame loss rate shown by then modified
design proved to be significantly lower in some
circumstances, ranging from around 14 times to 1.2
times lower in the best and worst cases, for input rates
over 50%.
Throughput, on the other hand, is considerably
similar for both designs in most cases, but diverges
(for the best and the worst) in some cases. It is
believed that in issue in the memory management
block is preventing the modified design from
presenting better throughput results than the original
one. This issue is under investigation and better
throughput performance is expected on the modified
design for a near future.
[4]
[5]
[6]
[7]
[8]
[9]
[1]
IEEE
Global
Telecommunications, 1997.
[2]
Intel. 82544EI
Datasheet.
Ethernet
[10] Network
REFERENCES
Gigabit
[3]
Controller
Available:
162