SDRAM Technology: An Introduction To The Use of The Technology in The High-Reliability, Spaceflight Environment

SDRAM Technology
An introduction to the use of the

technology in the high-reliability,
spaceflight environment.
Overview
Technology Background
Heavy Ions
Protons
Loss of Functionality
Radiation
Signal Integrity
Upset Predictions
Total Ionizing Dose
References
Appendix - Some Additional Data
User Notes
This represents a sampling of information
Radiation data on each part type, revision,
and lot may be radically different
Test data is only for modes tested; these are
complex devices with many operating modes.
Examples of commands, structures, features,
idiosyncrasies, may vary from device to
devices. Examples are given for illustration
purposes only.
Technology Overview
Some SDRAM Features

Synchronous Timing
Signal generation much simpler than DRAM
Complex devices with state machines,

pipelines, refresh modes, power states, etc.
Like DRAM, startup sequence required
Details available in data sheets
Control Signals
Sampled
Synchronously
Block Diagram
Micron, 64 Mbit
4 Banks
Mode
Register
Block Diagram
Control Signals
Sampled
Synchronously
Micron, 64 Mbit
CKE
CLK
CS*
WE*
CAS*
RAS*
Mode
Register
Control Signal Interpretation

Function
CS*
RAS*
CAS*
WE*
COMMAND INHIBIT
NOP
H
H
X
X
X
X
X
X
LOAD MODE REGISTER

AUTO/SELF REFRESH
PRECHARGE
ACTIVE (SEL BANK/ROW)
WRITE
READ
BURST TERMINATE
L
L
L
L
L
L
L
L
L
L
L
H
H
H
L
L
H
H
L
L
H
L
H
L
H
L
H
L
Example Read w/ Auto Precharge

CAS Latency=2; Burst Length=4
Load Mode Register Command

Address Used As Operation Code
A2:A0
Burst Length
A3
Burst Type {Sequential, Interleaved}
A6:A4
CAS Latency
A8:A7
Operation Mode
A9
Write Burst Mode
A11:A10 Reserved

Examination of Some Fields - Burst Length
A2 A1 A0
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
BURST LENGTH
M3=0
M3=1
1
1
2
2
4
4
8
8
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
FULL PAGE RESERVED

Examination of Some Fields - CAS Latency
A6 A5 A4
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
CAS LATENCY
RESERVED
RESERVED
2
3
RESERVED
RESERVED
RESERVED
RESERVED

Examination of Some Fields - Op Mode
A8 A7
0
0
1
1
0
1
0
1
Operation Mode
Standard Operation
RESERVED
RESERVED
RESERVED
State Diagram, Simplified [3]

Hitachi 256M SDRAM
Self
Refresh
Load
Mode
Reg
Idle
Read/
Write
Power
On
Precharge
Auto
Refresh
Idle
Power
Down
Sample Current Consumption by

Mode @ VCC = 3.3V [3]
Operating Mode
Auto Refresh
Write/Read
Self Refresh
Idle
Current (mA)
4.3
13
2.2
1.1
Mode Register and Device State

Special Considerations
Mode Register likely SEU Soft
Test data supports this
RESERVED states in Mode Register

May be able to load invalid state
May require power cycle
May result in damage to device
Toggling N/C Pins

May require power cycle to recover
May result in damage to device
Poor Signal Integrity or Power/Ground Noise

May upset Mode Register: put into a RESERVED state
Power-On Self-Test (POST)
Since the ultimate value of a DRAM is a highly

reliable memory function, a special control circuit
has been incorporated to map out defective or nonoperational cells from the whole memory section by
a proper distribution of built-in redundant cells. It
appears that the mapping out process takes place
during the power-up. [2]
Discussions with Micron indicated that they did not
have this feature.
Reliability and radiation effects on devices may
significantly differ.
Heavy Ions
Heavy Ion SEUs: 16 Mbit [4]

101
100
Device Cross Section [cm2]
10-1
10-2
Micron MT48LC1M16A1TG-10SIT
10-3
10-4
10-5
SEU Cross Section versus LET

Device 4988
10-6
Averaged data
Edmonds fit of all data
10-7
10-8
20
40
LET [Mev cm2/mg]
60
80
This device was rotated along the short axis of the device to emulate higher LET.
1Mx16
Heavy Ion SEUs, 64 Mbit

Dynamic Test, Samsung [1]
Heavy Ion SEUs, 64 Mbit (Samsung [2])
Cross-section (cm2/bit)
KM44V1600B
LET (MeV-cm2/mg)
Heavy Ion SEUs, 128 Mbit [1]

Dynamic Test, Samsung

Samsung [2]
Cross-section (cm2/device)
SEE Event
SEL
KM44S32030B
LET (MeV-cm2/mg)
Heavy Ion SEUs, 256 Mbit [2]

Samsung
Multiple bit upsets seen
LETTH is around 1 MeV-cm2/mg
Add Figure 5
Hitachi
Multiple bit upsets seen
LETTH is around 1 MeV-cm2/mg
Add Figure 8
Heavy Ion SEL: 16 Mbit [4]

100
SEL Cross Section versus LET

Device 4987
10-1
Averaged data
10-2
10-3
10-4
10-5
10-6
10-7
1Mx16
10-8
20
40
LET [Mev cm2/mg]
60
80
No SELs were observed below 11.5 MeV-cm2/mg Chlorine at normal incidence.
Heavy Ion SEL Data (1 of 2)

64 Mbit Samsung
No SEL at LET = 50 MeV-cm2/mg [1]
128 Mbit Samsung

SEL at LET = 15 MeV-cm2/mg; device destroyed [2]
Rev. A: SEL at ~ 55 MeV-cm2/mg [3]
Rev. B: SEL at ~ 5 MeV-cm2/mg [3]
Heavy Ion SEL Data (2 of 2)

256 MBit Samsung
Latched at LET = 36 MeV-cm2/mg [2]
Current > 200 mA
256 MBit IBM [3]

SEL at LET ~ 30 MeV-cm2/mg
256 MBit Hitachi [3]

No SEL at LET = 61 MeV-cm2/mg, 100 C
256 MBit Hyundai [3]

No SEL at LET = 12 MeV-cm2/mg
Heavy Ion: Stuck Bits

Reference [1] reports 30 stuck bits on one
128 Mb device, after exposure to a large
fluence. Fewer stuck bits observed after
being annealed at room temperature,
unbiased for one week.
Reference [2] reports stuck bits for the
256M Samsung devices. The small number
of stuck bits annealed within a few weeks in
an unbiased condition.
Protons
Proton SEUs, Static

64 Mbit, Samsung [1]
Proton SEUs, Static

128 MBit Samsung [1]
Proton SEUs
SEU Cross-section (cm2/device)
128, 256 MBit Samsung [2]

10-6
10-7
10-8
10-9
KM44S64230A
KM44S32030B
10-10
Proton Energy (MeV)

Note: No multiple-bit upsets, SEFI, or latchup detected.
Protons: Stuck Bits

64 and 128 Mbit Samsung [1]
Total Ionizing Dose
Total Dose
Samsung 64 and 128 Mbit
Dose rates from 13 to 140 krad(Si)/s
64 Mbit fully functional up to 22 krad(Si)
128 Mbit fully functional up to 17 krad(Si)
Total Dose
Samsung 64 and 128 Mbit [1]
and other
Unusual Events
Radiation
Signal Integrity
Large Event - Samsung [1]
Most or all bits wrong were seen a few times for the 128
Mbit Samsung device; it was not seen for the 64 Mbit
Samsung SDRAM.
Loss of Functionality - Early Data

256M Samsung [2]
Often, reset (power cycle) is needed to recover from SEFI
conditions. [2]
Large multiple bit errors (> 100 bits) making an oval patch in
the memory
Multiple-bit errors over many consecutive address locations
Events above may have an increase of about 10 mA in
supply current.
256 Hitachi [2]

Also seen. Add figure.
Anomalous Currents
Ranged from 0.5 to 145 mA [3]
Loss of Functionality [3]

Hyundai 256M (Auto Refresh Operation)
Cross-section (cm2/device)
10-3
10-4
10-5
10-6
10-7
LET (MeV-cm2/mg)
Loss of Functionality [3]
Bias Current (mA)
Hyundai 256M: Bias Current Variation
Xe Fluence (particles/cm2)
Additional Issues
Refreshing MODE Register
Will restore functionality in some cases
But not all!
Different ways of operating SDRAM can result in

different affects from radiation. See Reference [3] for
details.
Protons [3]
Hyundai, Hitachi 256M devices
SEFI not detected at 197 MeV
Loss of Functionality - A Sample

See Ref. 3 for Detailed Data
Self-Refresh Operation: Power Cycle Required
LET
4.1
12
28
HIT256M
X
X
HYND256M
N/A
N/A
X
No problem
N/A Data Not Available
X
Power Cycle Required
SAM128M
SAM256M
X
X
N/A
X
X
Upset Predictions
Event Rates
Galactic and Solar Cosmic Rays [1]
Event Rates
Trapped Protons [1]
Commercial Designs
Employing Error Detection and Correction
Parity
SEC/DED
Protect again loss of an entire chip
References
[1] "SDRAM Space Radiation Effects Measurements and Analysis," B.G.
Henson, P.T. McDonald, and W.J. Stapor, 1999 IEEE Radiation
Effects Data Workshop, Norfolk, Virginia, 1999.
[2] "SEE Sensitivity Determination of High-Density DRAMs with
Limited-Range Heavy Ions," R. Koga, S.H. Crain, P. Yu, and K.B.
Crawford, 2000 IEEE Radiation Effects Data Workshop.
[3] "Permanent Single Event Functional Interrupts (SEFIs) in 128- and
256-megabit Synchronous Dynamic Random Access Memories
(SDRAMs)," R. Koga, P. Yu, K.B. Crawford, S.H. Crain, and V.T.
Tran, 2001 IEEE Radiation Effects Data Workshop.
[4] "SEE Measurement at Brookhaven National Laboratory for the
SDRAMs," Leif Scheick, December 1999, Unpublished
References
[5] "IBM moves to protect DRAM from cosmic invaders, Anthony
Cataldo, EE Times,
http://www.edtn.com/news/june11/061198topstory.html
[6] " Phasor The Next Generation Cosmic Ray Fighter!, Don Swietek,
MicroNews, Second Quarter 1999, Vol. 5, No. 2, IBM, http://www3.ibm.com/chips/micronews/vol5_no2/swietek.html
Appendix
Additional Data

101
100
10-1
10-2
10-3
10-4
10-5

Device 4987
10-6
Averaged data
10-7
10-8
20
40
LET [Mev cm2/mg]
60
80
This device was rotated along the long axis of the device to emulate higher LET.
1Mx16

100
10-1
10-2
10-3
10-4
10-5
10-6

Device 4989
Normal Incidence Only
10-7
Averaged data
10-8
10
20
LET [Mev cm2/mg]
Normal Incidence Only
30
40
1Mx16

Static Test, Samsung [1]

Static Test, Samsung [1]
Proton SEUs, Dynamic

Proton SEUs, Dynamic


SDRAM Technology: An Introduction To The Use of The Technology in The High-Reliability, Spaceflight Environment

Hochgeladen von

Dokumentinformationen

Originaltitel

Copyright

Verfügbare Formate

Dieses Dokument teilen

Dokument teilen oder einbetten

Freigabeoptionen

Stufen Sie dieses Dokument als nützlich ein?

Sind diese Inhalte unangemessen?

Copyright:

Verfügbare Formate

SDRAM Technology: An Introduction To The Use of The Technology in The High-Reliability, Spaceflight Environment

Hochgeladen von

Copyright:

Verfügbare Formate

SDRAM Technology

An introduction to the use of the

Some SDRAM Features

Complex devices with state machines,

Control Signal Interpretation

LOAD MODE REGISTER

Example Read w/ Auto Precharge

Load Mode Register Command

Burst Type {Sequential, Interleaved}

Write Burst Mode

Load Mode Register Command

Load Mode Register Command

Load Mode Register Command

State Diagram, Simplified [3]

Sample Current Consumption by

Mode Register and Device State

RESERVED states in Mode Register

Toggling N/C Pins

Poor Signal Integrity or Power/Ground Noise

Power-On Self-Test (POST)

Since the ultimate value of a DRAM is a highly

Heavy Ion SEUs: 16 Mbit [4]

Device Cross Section [cm2]

SEU Cross Section versus LET

Heavy Ion SEUs, 64 Mbit

Heavy Ion SEUs, 64 Mbit (Samsung [2])

Heavy Ion SEUs, 128 Mbit [1]

Heavy Ion SEUs, 128 Mbit

Heavy Ion SEUs, 256 Mbit [2]

Heavy Ion SEL: 16 Mbit [4]

SEL Cross Section versus LET

Device Cross Section [cm2]

No SELs were observed below 11.5 MeV-cm2/mg Chlorine at normal incidence.

Heavy Ion SEL Data (1 of 2)

128 Mbit Samsung

Heavy Ion SEL Data (2 of 2)

256 MBit IBM [3]

256 MBit Hitachi [3]

256 MBit Hyundai [3]

Heavy Ion: Stuck Bits

Proton SEUs, Static

Proton SEUs, Static

128, 256 MBit Samsung [2]

Proton Energy (MeV)

Protons: Stuck Bits

Total Ionizing Dose

Large Event - Samsung [1]

Loss of Functionality - Early Data

256 Hitachi [2]

Loss of Functionality [3]

Loss of Functionality [3]

Bias Current (mA)

Hyundai 256M: Bias Current Variation

Different ways of operating SDRAM can result in

Loss of Functionality - A Sample

Heavy Ion SEUs: 16 Mbit [4]

Device Cross Section [cm2]

SEU Cross Section versus LET

Heavy Ion SEUs: 16 Mbit [4]

Device Cross Section [cm2]

SEU Cross Section versus LET

Normal Incidence Only

Heavy Ion SEUs, 64 Mbit