Ee270c CDR PDF

Equalization/Compensation of Transmission Media
Channel
(copper or fiber)
EECS 270C / Winter 2014
Prof. M. Green / UC Irvine
Optical Receiver Block Diagram
OE
TIA
-18 dBm
10 A
LA
10 mV p-p
EQ
CDR
DMUX
400 mV p-p
Copper Cable Model
4-foot cable
Copper Cable
( )
H e L
15-foot cable
Where: L is the cable length

a is a cable-dependent
characteristic
Effect of Copper on Broadband Data
waveform
eye diagram
Adaptive Analog Equalizer for Copper
Implemented in Jazz Semiconductor SiGe BiCMOS process:

120 GHz fT npn
0.35 m CMOS
Equalizer Block Diagram
Analog Equalizer Concept (1)
Simple linear circuit (normalized to 1Hz):

1
V2
V1
V3
+0.5
-0.5
C1
1s
1V1
V1
simple channel model
bandpass filter
1 V2
combined flat response

+ peaked response

1
V2
V1
V3
+0.5
-0.5
1s
V1
C1
1V1
V1
V2
(1 ) V

Equalized output pulses:
Rise time = voltage swing/slew rate
V3
Rise time nearly constant over different channels!

Feedforward Path
Vout
Equalizer Frequency Response

Veq
(dB)
Vin
Vcontrol
f (Hz)
10
ISI & Transition Time

VFFE
teq = 45ps
PW = 108ps
0.3
teq = 60ps
PW = 100ps
-0.3
2.4
teq = 75ps
PW = 86ps
2.5
2.6
2.7
2.8
t (ns)
Simulations indicate that ISI correlates strongly with FFE transition time teq.
Optimum teq is observed to be 60 ps.
Nonlinearities affect pulse shape, but not location of zero crossings.
11
Slicer
Restores full logic levels
Exhibits controlled
transition time
12
Feedback Path
13
Transition Time Detector

DC characteristic:
V+
VS
VVS
Transient Characteristic:
ISS
CSS
V+ V
V+ V
(b)
(a)
VS
Rectification & filtering done

in a single stage.
(b)
(a)
14
Integrator
A0
1
H(s) =
1+ s int A0 s int
A0 = gm 1 ro1 || ro2
int
CL
=
gm 1
15
Detector + Integrator
From
FFE
tFFE
From
Slicer
tslicer= 60ps
slope
detector
slope
detector
FFE transition
Time tFFE
Vcontrol (mV)
90ps
60
40
75ps
20
60ps
_
+
Vcontrol
-20
-40
45ps
-60
15ps
10
20
30
40
50
t (ns)
16
System Analysis
tslicer
detector
Kd
Vcontrol
integrator
feedforward
equalizer
H(s)
teq
Keq
detector
Kd
t eq
t slicer
Keq = 1.5 ps/mV

Kd = 2.5 mV/ps
K d K eq H (s )
1 + K d K eq H (s )
1
H (s )
s int
t eq
t slicer
int = 75ns
1
1+ s
int
K d K eq
adapt =
int
= 20ns
Kd Keq
17
Measurement Setup
EQ inputs
Die under test
231 PRBS signal

applied to cable
EQ outputs
18
Measured Eye Diagrams

EQ input
EQ output
4-foot
RU256 cable
(-5 dB atten. @ 5 GHz)
4.0 ps rms jitter
15-foot
RU256 cable
(-15 dB atten. @ 5 GHz)
3.9 ps rms jitter

19
Summary of Measured Performance
Supply voltage
3.3 V
Power Dissipation
350 mW
(155 mW not including output driver)
Die Size
0.81mm X 0.87mm
Output Swing
490 mV single-ended p-p
Random Jitter
4.0 ps rms (4-foot cable)

3.9 ps rms (15-foot cable)
Presented at ISSCC Feb. 2004
20
Equalization vs. Compensation
Equalization is accomplished by inverting the transfer function of the channel.

Compensation is accomplished only by canceling the ISI at each unit interval.
Electronic Dispersion Compensation (EDC) refers to the electronics that
accomplishes compensation of copper or optical transmission media.
EDC is becoming especially critical as bit rates increase on legacy equipment
(e.g., backplane, optical connectors, optical fiber).
21
Pre-Cursor/Post-Cursor ISI
Input pulse (no ISI):
0
T
cursor
Output pulse:
pre-cursor ISI
post-cursor ISI
0
T
22
Feedforward Equalization (FFE)

Idea: To cancel ISI, subtract a weighted & delayed version of the pulse:
output pulse
delayed by T:
d-1
d0
output pulse:
# d &
X% 1 (
$ d0 '
Result with 0
pre-cursor ISI:
23
Feedforward Equalization (2)

Din (t)
Din (t T )
Time domain:
Dout (t) = Din (t) a1 Din (t T )
a1
a1 =
_
+
Dou t (t)
1+ a12
Frequency domain:
H(s) = 1 a1 e sT
H( j ) = 1 a1 e jT
d1
d0
1 a1
= 1 a1 cos T j sin T
| H( j ) |2 = (1+ a12 ) 2a1 cos T
24

N-tap FFE structure:
Din (t)
a0
a1
a2
an

FFE can cancel both pre- and post-cursor distortion.
Dou t (t)
25

3-tap summing circuit:
negative coefficient
R
_
R
Vout +
Din+ (k)
Din (k)
V0
Din+ (k 1)
Din (k 1)
V1
Din+ (k 2)
V2
Din (k 2)
ISS
Coefficients set by gm of each differential pair.

26

Fractional spacing:
1-tap T-spaced FFE frequency response
5-tap T-spaced FFE eye diagram
1-tap T/2-spaced FFE frequency response

5-tap T/2-spaced FFE eye diagram
27
Adaptation (1)
Assume original sequence Din(k) is known.
Define error signal e(k) as:
^
e(k) D^out (k) Dout (k) where Dout(k) is an appropriately delayed version of Din(k).
de2
Steepest Descent Algorithm: Set ai =
dai
e2
a2
step size
a1
optimum
setting
Algorithm moves coefficients in direction of decreasing mean-square error.

Step size should be made sufficiently small to guarantee convergence.
Requires knowledge of properties of mean-square error; usually not available.
28
Adaptation (2)
Least mean-square (LMS) algorithm:
Set ai =
d e 2 (k)
dai
FFE output signal: Dout (k) = a0 Din (k) + a1 Din (k 1) + + an Din (k n)
e 2 (k) = [Dout (k) Dout (k)]
] = 2 D^
d e 2 (k)
dai
out
Dout
dDout
dai
= 2 e(k) Din (k i )
Analog version of LMS:
ai (t) =
e(t) D
in
(t iT )dt
ai = 2 e(k) Din (k i )
both signals are
available on chip.
29
Adaptation (3)
Types of adaptation:
1. Training Sequence
A training sequence with known properties is sent through the channel +
equalizer. The equalizer output is compared to the original sequence and an
error signal is generated.
2. Blind Adapation
Adaptation is continually performed while system is running. Only limited
properties of the signal are known. An error signal must somehow be
generated without having the original sequence.
30
Adaptation (4)
Generation of error signal:
Din
FFE
Dout
Dout
e
Slicer restores logic levels and opens eye vertically.
Bit sequences at slicer input & input
are identical.
Slicer has no effect on placement of zero crossing.
Slicer can be realized using CML buffers with sufficient gain and speed.
31
Decision Feedback Equalization (DFE)

Din (t)
FFE structure:
a0
a1
a2
an
Dou t (t)
Noise applied to FFE input will be retained (perhaps filtered) at the output.
Din (t)
DFE structure:
Dou t (t)
+
- -
bm
b2
T
b1
T
T
32
Decision Feedback Equalization (2)

Din (t)
Dou t (t)
bm
b2
b1
Slicer is embedded in the structure; Dout is a digital signal.

Delay elements are digital -- commonly realized by DFFs.
Use of slicer suppresses input noise.
Cancels post-cursor distortion only.
33
Decision Feedback Equalization (3)

Din (t)
Dou t (t)
+
- -
post-cursor
distortion
1-tap example:
2/3
Din (k)
bm
b2
Dout (k)
(desired)
consistent
with
b1
1/3
Dout (k 1)
Tap weights provide a look-up table, canceling

post-cursor distortion based on last m bits of output
sequence.
DFE can sometimes latch up with wrong tap
weights during adaptation.
Din (k)
1
Dout (k 1)
3
b1 =
2/3
1
3
34
FFE + DFE
Din (t)
a0
T
a1
T
a2
an
Dou t (t)
+
-
Combined FFE and DFE can be used to

cancel both pre- and post-cursor
distortion with low noise.
bm
b2
b1
35
Front-End Circuits for DSP-Based Receivers

from channel
Vin
PGA
VA
ADC
Dout [1:n]
ADC requires strict control
over its input amplitude VA.
VC
AGC
Automatic Gain Control
Programmable Gain Amplifier (PGA):
VA (t) = G(VC ) Vin (t)

#V &
where G(VC ) = V1 exp% C (
$ V2 '
Linear in dB gain characteristic

gives settling time independent of
input amplitude.
36
PGA Design
1. Differential Pair:
Iout-
2. Source Degeneration:
Iout-
Iout+
Vin+
Iout+
Vin+
Vin-
Vin2RS
ISS
3. Op-Amp with Feedback:

Rf
RS
+
V_in RS
+
V_out
Rf
+
VC_
For biasing in weak inversion:
ISS
2nVT
% V V (
= ID0 exp' C T *
& nVT )
Iout =
Iout = gmVin
ISS
gm
Vin
1+ gmRS
Vin
RS
Vout =
Rf
Vin
RS
for gmRS >> 1

RS varied withconstant
dB per step.
37
PGA Example (1)

C.-C. Hsu, J.-T. Wu, A highly linear 125-MHz
CMOS switched-resistor programmable-gain
amplifier, JSSC, Oct. 2003, pp. 1663-1670.
Vout =
Realization of RS:
Rf
Vin
RS
RS1 = 420
RS1 + RS2 = 529
2 dB steps
RS1 + RS2 + RS3 = 666
RS1 + RS2 + ! + RS10

= 4200
38
PGA Example (2)

J. Cao, et al., A 500mW digitally calibrated AFE
in 65nm CMOS for 10Gb/s links over backplane
and multimode fiber, ISSC 2009, pp. 370-371.
Av = gmR
= N nCox
W
IO R
L
gain of single diff. pair
where N = number of diff. pairs turned on
39
Track & Hold Circuit

The T/H circuit is comprised of two switch-capacitor stages and
an amplifier which provides gain and isolation.
Dummy switches are used to cancel channel charge injection
and achieve better linearity.
40
Simulation Results
T/H differential output for fin = 1.5 GHz and fs=10 GS/sec
41
High-speed Comparator
High-Level Clocking:
Improves isolation between the input
and output, reducing kickback from
output.
Cascoding of the clock switches
reduces the Miller effect of the input
transistors.
Reduced headroom
42
Comparator/Latch Results (1)
43
Metastable Behavior (1)

Comp./Latch output
T/H output
Metastable event
What is the probability of this error occurring?

44

For vd v1 v2 :
R
Ct
Ct
+
v1
Ct
+
v2
dvd
v
= d + gmvd
dt
R
% t (
vd (t) = vd (0) exp' *
& m )
m
vd (t)
gm
Ct
1
1
1
gmR
gm = 4.2 mS
R = 400
Ct = 36 fF
m = 30 ps
45

Vout (digital)
11
10
01
00
-Vdec
0
3 Vin (analog)
2
VLSB
2
=
AcompVLSB
Error probability: Perror =

Including comparator gain: Perror
+Vdec
2

2Vdec

VLSB

Vdec = minimum detectable logic level
= minimum input at t = 0 so that output
level is Vdec at t = T/2
46

vd (t)
Recall:
$ t '
vd (t) = vd (0) exp& )
% m (
m = 23 ps
For error-free operation after

half-clock period:
m = 30 ps
vd (Tc 2) Vdec
'T *
Vdec = exp) c ,
( 2 m +
' T *
= Vdec exp) c ,
( 2 m +
Error probability: Perror =

=
2
AcompVLSB
& T )
2Vdec
exp( c +
AcompVLSB
' 2 m *
47
Reducing Metastability Errors

Additional high-speed latches
following the comparator/latch
stage reduces probability of
metastable events at the output.
Latch output
48

Ee270c CDR PDF

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Equalization/Compensation of Transmission Media

EECS 270C / Winter 2014

Prof. M. Green / UC Irvine

Optical Receiver Block Diagram

EECS 270C / Winter 2014

Prof. M. Green / UC Irvine

Copper Cable Model

Where: L is the cable length

EECS 270C / Winter 2014

Prof. M. Green / UC Irvine

Effect of Copper on Broadband Data

EECS 270C / Winter 2014

Prof. M. Green / UC Irvine

Adaptive Analog Equalizer for Copper

Implemented in Jazz Semiconductor SiGe BiCMOS process:

EECS 270C / Winter 2014

Prof. M. Green / UC Irvine

Equalizer Block Diagram

EECS 270C / Winter 2014

Prof. M. Green / UC Irvine

Analog Equalizer Concept (1)

Simple linear circuit (normalized to 1Hz):

simple channel model

EECS 270C / Winter 2014

Prof. M. Green / UC Irvine

combined flat response

Analog Equalizer Concept (2)

EECS 270C / Winter 2014

Prof. M. Green / UC Irvine

Analog Equalizer Concept (3)

Rise time = voltage swing/slew rate

Rise time nearly constant over different channels!

Prof. M. Green / UC Irvine

EECS 270C / Winter 2014

Prof. M. Green / UC Irvine

Equalizer Frequency Response

EECS 270C / Winter 2014

Prof. M. Green / UC Irvine

ISI & Transition Time

EECS 270C / Winter 2014

Prof. M. Green / UC Irvine

Restores full logic levels

EECS 270C / Winter 2014

Prof. M. Green / UC Irvine

EECS 270C / Winter 2014

Prof. M. Green / UC Irvine

Transition Time Detector

Rectification & filtering done

EECS 270C / Winter 2014

Prof. M. Green / UC Irvine

EECS 270C / Winter 2014

Prof. M. Green / UC Irvine

Keq = 1.5 ps/mV

Prof. M. Green / UC Irvine

Die under test

231 PRBS signal

EECS 270C / Winter 2014

Prof. M. Green / UC Irvine

Measured Eye Diagrams

4.0 ps rms jitter

3.9 ps rms jitter

Prof. M. Green / UC Irvine