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PCS-902

Line Distance Relay


Instruction Manual

NR Electric Co., Ltd.

Preface

Preface
Introduction
This guide and the relevant operating or service manual documentation for the equipment provide
full information on safe handling, commissioning and testing of this equipment.
Documentation for equipment ordered from NR is dispatched separately from manufactured goods
and may not be received at the same time. Therefore, this guide is provided to ensure that printed
information normally present on equipment is fully understood by the recipient.
Before carrying out any work on the equipment, the user should be familiar with the contents of
this manual, and read relevant chapter carefully.
This chapter describes the safety precautions recommended when using the equipment. Before
installing and using the equipment, this chapter must be thoroughly read and understood.

Health and Safety


The information in this chapter of the equipment documentation is intended to ensure that
equipment is properly installed and handled in order to maintain it in a safe condition.
When electrical equipment is in operation, dangerous voltages will be present in certain parts of
the equipment. Failure to observe warning notices, incorrect use, or improper use may endanger
personnel and equipment and cause personal injury or physical damage.
Before working in the terminal strip area, the equipment must be isolated.
Proper and safe operation of the equipment depends on appropriate shipping and handling,
proper storage, installation and commissioning, and on careful operation, maintenance and
servicing. For this reason, only qualified personnel may work on or operate the equipment.
Qualified personnel are individuals who:

Are familiar with the installation, commissioning, and operation of the equipment and of the
system to which it is being connected;

Are able to safely perform switching operations in accordance with accepted safety
engineering practices and are authorized to energize and de-energize equipment and to
isolate, ground, and label it;

Are trained in the care and use of safety apparatus in accordance with safety engineering
practices;

Are trained in emergency procedures (first aid).

Instructions and Warnings


The following indicators and standard definitions are used:
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PCS-902 Line Distance Relay


Date: 2013-12-18

Preface

DANGER!
It means that death, severe personal injury, or considerable equipment damage will occur if safety
precautions are disregarded.
WARNING!
It means that death, severe personal, or considerable equipment damage could occur if safety
precautions are disregarded.
CAUTION!
It means that light personal injury or equipment damage may occur if safety precautions are
disregarded. This particularly applies to damage to the device and to resulting damage of the
protected equipment.
WARNING!
The firmware may be upgraded to add new features or enhance/modify existing features, please
make sure that the version of this manual is compatible with the product in your hand.
WARNING!
During operation of electrical equipment, certain parts of these devices are under high voltage.
Severe personal injury or significant equipment damage could result from improper behavior.
Only qualified personnel should work on this equipment or in the vicinity of this equipment. These
personnel must be familiar with all warnings and service procedures described in this manual, as
well as safety regulations.
In particular, the general facility and safety regulations for work with high-voltage equipment must
be observed. Noncompliance may result in death, injury, or significant equipment damage.
DANGER!
Never allow the current transformer (CT) secondary circuit connected to this equipment to be
opened while the primary system is live. Opening the CT circuit will produce a dangerously high
voltage.
WARNING!

Exposed terminals

Do not touch the exposed terminals of this equipment while the power is on, as the high voltage
generated is dangerous

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Preface

Residual voltage

Hazardous voltage can be present in the DC circuit just after switching off the DC power supply. It
takes a few seconds for the voltage to discharge.
CAUTION!

Earth

The earthing terminal of the equipment must be securely earthed

Operating environment

The equipment must only be used within the range of ambient environment detailed in the
specification and in an environment free of abnormal vibration.

Ratings

Before applying AC voltage and current or the DC power supply to the equipment, check that they
conform to the equipment ratings.

Printed circuit board

Do not attach and remove printed circuit boards when DC power to the equipment is on, as this
may cause the equipment to malfunction.

External circuit

When connecting the output contacts of the equipment to an external circuit, carefully check the
supply voltage used in order to prevent the connected circuit from overheating.

Connection cable

Carefully handle the connection cable without applying excessive force.

Copyright 2013 NR. All rights reserved.


We reserve all rights to this document and to the information contained herein. Improper use in particular reproduction and dissemination
to third parties is strictly forbidden except where expressly authorized.
The information in this manual is carefully checked periodically, and necessary corrections will be included in future editions. If
nevertheless any errors are detected, suggestions for correction or improvement are greatly appreciated.
We reserve the rights to make technical improvements without notice.

NR ELECTRIC CO., LTD.

Tel: +86-25-87178185,

Fax: +86-25-87178208

69 Suyuan Avenue. Jiangning, Nanjing 211102, China

Website: www.nrelect.com, www.nari-relays.com

Version: R1.07

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Preface

Documentation Structure
The manual provides a functional and technical description of this relay and a comprehensive set
of instructions for the relays use and application.
All contents provided by this manual are summarized as below:

1 Introduction
Briefly introduce the application, functions and features about this relay.

2 Technical Data
Introduce the technical data about this relay, such as electrical specifications, mechanical
specifications, ambient temperature and humidity range, communication port parameters, type
tests, setting ranges and accuracy limits and the certifications that our products have passed.

3 Operation Theory
Introduce a comprehensive and detailed functional description of all protective elements.

4 Supervision
Introduce the automatic self-supervision function of this relay.

5 Management
Introduce the management function (measurement, recording and remote control) of this relay.

6 Hardware
Introduce the main function carried out by each plug-in module of this relay and providing the
definition of pins of each plug-in module.

7 Settings
List settings including system settings, communication settings, label settings, logic links and etc.,
and some notes about the setting application.

8 Human Machine Interface


Introduce the hardware of the human machine interface (HMI) module and a detailed guide for the
user how to use this relay through HMI. It also lists all the information which can be view through
HMI, such as settings, measurements, all kinds of reports etc.

9 Configurable Function
Introduce configurable function of the device and all configurable signals are listed.

10 Communication
Introduce the communication port and protocol which this relay can support, IEC60970-5-103,
IEC61850 and DNP3.0 protocols are introduced in details.

11 Installation
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Introduce the recommendations on unpacking, handling, inspection and storage of this relay. A
guide to the mechanical and electrical installation of this relay is also provided, incorporating
earthing recommendations. A typical wiring connection to this relay is indicated.

12 Commissioning
Introduce how to commission this relay, comprising checks on the calibration and functionality of
this relay.

13 Maintenance
A general maintenance policy for this relay is outlined.

14 Decommissioning and Disposal


A general decommissioning and disposal policy for this relay is outlined.

15 Manual Version History


List the instruction manual version and the modification history records.

Typographic and Graphical Conventions


Deviations may be permitted in drawings and tables when the type of designator can be obviously
derived from the illustration.
The following symbols are used in drawings:

&

AND gate
1

OR gate

Comparator
BI

SET

EN

Binary signal via opto-coupler


I>

Input signal from comparator with setting

Input signal of logic setting for function enabling

PCS-902 Line Distance Relay


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Preface
SIG

Input of binary signal except those signals via opto-coupler

XXX

Output signal

Timer
t
t

Timer (optional definite-time or inverse-time characteristic)


10ms

0ms

Timer [delay pickup (10ms), delay dropoff (0ms), non-settable]


[XXX]

0ms

Timer (delay pickup, settable)


0ms

[XXX]

Timer (delay dropoff, settable)


[XXX]

[XXX]

Timer (delay pickup, delay dropoff, settable)


IDMT

Timer (inverse-time characteristic)

---xxx is the symbol

Symbol Corresponding Relationship


Basic

Example

A, B, C

L1, L2, L3

Ia, Ib, Ic, I0

IL1, IL2, IL3, IN

AN, BN, CN

L1N, L2N, L3N

Ua, Ub, Uc

VL1, VL2, VL3

ABC

L123

Uab, Ubc, Uca

VL12, VL23, VL31

U (voltage)

U0, U1, U2

VN, V1, V2

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1 Introduction

1 Introduction
Table of Contents
1 Introduction ...................................................................................... 1-a
1.1 Application....................................................................................................... 1-1
1.2 Function ........................................................................................................... 1-3
1.3 Features ........................................................................................................... 1-6

List of Figures
Figure 1.1-1 Typical application of PCS-902 ............................................................................1-1
Figure 1.1-2 Functional diagram of PCS-902...........................................................................1-2

PCS-902 Line Distance Relay

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1 Introduction

PCS-902 Line Distance Relay

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Date: 2013-09-05

1 Introduction

1.1 Application
PCS-902 is a digital line distance protection with the main and back-up protection functions, which
is designed for overhead line or cables and hybrid transmission lines of various voltage levels.

52

52

PCS-902

Optical fibre channel or PLC channel

PCS-902

Communication channel via direct dedicated fibre, MUX or PLC

Figure 1.1-1 Typical application of PCS-902

Main protection of PCS-902 comprises of pilot distance protection (PUTT, POTT, blocking and
unblocking) and pilot directional earth-fault protection (selectable for independent communication
channel or sharing channel with POTT), which can clear any internal fault instantaneously for the
whole line with the aid of protection signal. DPFC distance protection can perform extremely high
speed operation for close-up faults. There is direct transfer trip (DTT) feature incorporated in the
relay.
PCS-902 also includes distance protection (3 forward zones and 1 reverse zone distance
protection with selectable mho or quadrilateral characteristic), 4 stages directional earth fault
protection, 4 stages directional phase overcurrent protection, 2 stages voltage protection
(under/over voltage protection), 4 stages frequency protection (under/over frequency protection),
broken conductor protection, pole discrepancy protection, breaker failure protection, thermal
overload protection, and dead zone protection etc. Morever, a backup overcurrent and earth fault
protection will be automatically enabled when VT circuit fails. In addition, stub overcurrent
protection is provided for one and a half breakers arrangement when transmission line is put into
maintenance.
PCS-902 has selectable mode of single-phase tripping or three-phase tripping and configurable
auto-reclosing mode for 1-pole, 3-poles and 1/3-pole operation.
PCS-902 with appropriate selection of integrated protection functions can be applied for various
voltage levels and primary equipment such as cables, overhead lines, interconnectors and
transformer feeder, etc. It also supports configurable binary inputs, binary outputs, LEDs and IEC
61850 protocol.

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1 Introduction
BUS

52

81
85

21

21D

67G

67P

50G

50P

50GVT

50PVT

50BF

49

46BC

62PD

FR
59

FL
Data Transmitt/Receive
51G
50DZ

51P

27

50STB (Only for one and a half breakers arrangement)


SOTF

25

79

LINE

Figure 1.1-2 Functional diagram of PCS-902


No.

Function

ANSI

Pilot protection

85

DPFC distance protection

21D

Distance protection

21

Earth fault protection

67G

Definite-time earth-fault protection

50G

Inverse-time earth-fault protection

51G

Phase overcurrent protection

67P

Definite-time phase overcurrent protection

50P

10

Inverse-time phase overcurrent protection

51P

11

Overvoltage protection

59

12

Undervoltage protection

27

13

Frequency protection

81

14

Broken conductor protection

46BC

15

Breaker failure protection

50BF

16

Thermal overload protection

49

17

Stub overcurrent protection

50STB

18

Dead zone protection

50DZ

19

Pole discrepancy protection

62PD

20

Switch onto fault

SOTF

21

Phase overcurrent protection when VT circuit failure

50PVT

22

Earth fault protection when VT circuit failure

50GVT

23

Synchronism check

25

24

Automatic reclosure

79

25

Fault recorder

FR

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1 Introduction
26

Fault location

FL

1.2 Function
1.

Protection Function

Distance protection

Three zones forward phase-to-ground distance elements (mho or quadrilateral


characteristic)

One pilot zone phase-to-ground distance element (mho or quadrilateral characteristic)


with weakinfeed distance element

One zone reverse phase-to-ground distance element (mho or quadrilateral characteristic)

Three zones forward phase-to-phase distance elements (mho or quadrilateral


characteristic)

One pilot zone phase-to-phase distance element (mho or quadrilateral characteristic)


with weakinfeed distance element

One zone reverse phase-to-phase distance element (mho or quadrilateral characteristic)

Load encroachment for mho and quadrilateral characteristic distance element

Power swing blocking releasing, selectable for each of above mentioned zones

Deviation of Power Frequency Component (DPFC) distance protection

Current protection

Four stages phase overcurrent protection, selectable time characteristic (definite-time or


inverse-time) and directionality (forward direction, reverse direction or non-directional)

Four stages directional earth fault protection, selectable time characteristic (definite-time
or inverse-time) and directionality (forward direction, reverse direction or non-directional)

Breaker failure protection

Optional instantaneously re-tripping

One stage with two delay timers

Thermal overload protection

Stub overcurrent protection

Dead zone protection

Pole discrepancy protection

Broken conductor protection

Switch onto fault (SOTF)

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1 Introduction

Via distance measurement elements

Via dedicated earth fault element

Backup protection when VT circuit failure

Phase overcurrent protection when VT circuit failure

Earth fault protection when VT circuit failure

Voltage protection

Two stages overvoltage protection

Two stages undervoltage protection

Frequency protection

Four stages overfrequency protection

Four stages underfrequency protection

f/dt block criterion for underfrequency protection

Control function

Synchro-checking

Automatic reclosure (single shot or multi-shot (max. 4) for 1-pole AR and 3-pole AR)

Pilot scheme logic

Phase-segregated communication logic of distance protection

Weak infeed logic of pilot distance protection

Weak infeed logic of pilot directional earth fault protection

Communication scheme of optical pilot channel (Optional)

Direct optical link

Connection to a communication network, support G.703 and C37.94 protocol

Dual-channels redundancy

2.

Measurement and control function

Remote control (open and closing)

Synchronism check for remote and manual closing (only for one circuit breaker)

Energy metering (active and reactive energy are calculated in import respectively export
direction)

3.

Logic

User programmable logic

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1 Introduction

4.

Additional function

Fault location

Fault phase selection

Parallel line compensation for fault location

VT circuit supervision

CT circuit supervision

Self diagnostic

DC power supply supervision

Event Recorder including 1024 disturbance records, 1024 binary events, 1024 supervision
events, 256 control logs and 1024 device logs.

Disturbance recorder including 32 disturbance records with waveforms (The file format of
disturbance recorder is compatible with international COMTRADE file.)

Four kinds of clock synchronization methods

Conventional

PPS (RS-485): Pulse per second (PPS) via RS-485 differential level

IRIG-B (RS-485): IRIG-B via RS-485 differential level

PPM (DIN): Pulse per minute (PPM) via the optical coupler

PPS (DIN): Pulse per second (PPS) via the optical coupler

SAS

SNTP (PTP): Unicast (point-to-point) SNTP mode via Ethernet network

SNTP (BC): Broadcast SNTP mode via Ethernet network

Message (IEC103): Clock messages through IEC103 protocol

Advanced

IEEE1588: Clock message via IEEE1588

IRIG-B (Fiber): IRIG-B via optical-fibre interface

PPS (Fiber) PPS: Pulse per second (PPS) via optical-fibre interface

NoTimeSync

5.

Monitoring

Number of circuit breaker operation (single-phase tripping, three-phase tripping and


reclosing)

Channel status

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1 Introduction

Frequency

6.

Communication

Optional 2 RS-485 communication rear ports conform to IEC 60870-5-103 protocol

1 RS-485 communication rear ports for clock synchronization

Optional 2 or 4 Ethernet ports (depend on the chosen type of MON plug-in module) conform
to IEC 61850 protocol, DNP3.0 protocol or IEC 60870-5-103 protocol over TCP/IP

Optional 2 Ethernet ports via optic fiber (ST interface) conform to IEC 61850 protocol, DNP3.0
protocol or IEC 60870-5-103 protocol over TCP/IP

GOOSE and SV communication function (optional NET-DSP plug-in module)

7.

User Interface

Friendly HMI interface with LCD and 9-button keypad on the front panel.

1 front multiplex RJ45 port for testing and setting

1 RS-232 or RS-485 rear ports for printer

Language switchoverEnglish+ selected language

Auxiliary softwarePCS-Explorer

1.3 Features

The intelligent device integrated with protection, control and monitor provides powerful
protection function, flexible protection configuration, user programmable logic and
configurable binary input and binary output, which can meet with various application
requirements.

High-performance hardware platform and modularized design, MCU (management control


unit)DSP (digital signal processor). MCU manages general fault detector element and DSP
manages protection and metering. Their data acquisition system is completely independent in
electronic circuit. DC power supply of output relay is controlled by the operation of fault
detector element operates, this prevents maloperation due to error from ADC or damage of
any apparatus.

Fast fault clearance for faults within the protected line, the operating time is less than 10 ms
for close-up faults, less than 15ms for faults in the middle portion of protected line and less
than 25ms for remote end faults.

The unique DPFC distance element integrated in the protective device provides extremely
high speed operation and insensitive to power swing.

Self-adaptive floating threshold which only reflects deviation of power frequency component
improves the protection sensitivity and stability under the condition of load fluctuation and
system disturbance.

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1 Introduction

Advanced and reliable power swing blocking releasing feature which ensure distance
protection operate correctly for internal fault during power swing and prevent distance
protection from maloperation during power swing

Flexible automatic reclosure supports various initiation modes and check modes

Multiple setting groups with password protection and setting value saved permanently before
modification

Powerful PC tool software can fulfill protection function configuration, modify setting and
waveform analysis.

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2 Technical Data

2 Technical Data
Table of Contents
2 Technical Data .................................................................................. 2-a
2.1 Electrical Specifications ................................................................................. 2-1
2.1.1 AC Current Input ................................................................................................................ 2-1
2.1.2 AC Voltage Input ................................................................................................................ 2-1
2.1.3 Power Supply ..................................................................................................................... 2-1
2.1.4 Binary Input ........................................................................................................................ 2-1
2.1.5 Binary Output ..................................................................................................................... 2-2

2.2 Mechanical Specifications ............................................................................. 2-3


2.3 Ambient Temperature and Humidity Range .................................................. 2-3
2.4 Communication Port ....................................................................................... 2-3
2.4.1 EIA-485 Port ...................................................................................................................... 2-3
2.4.2 Ethernet Port ...................................................................................................................... 2-3
2.4.3 Optical Fibre Port ............................................................................................................... 2-4
2.4.4 Print Port ............................................................................................................................ 2-5
2.4.5 Clock Synchronization Port ................................................................................................ 2-5

2.5 Type Tests ........................................................................................................ 2-5


2.5.1 Environmental Tests ........................................................................................................... 2-5
2.5.2 Mechanical Tests................................................................................................................ 2-5
2.5.3 Electrical Tests ................................................................................................................... 2-5
2.5.4 Electromagnetic Compatibility ............................................................................................ 2-5

2.6 Certifications ................................................................................................... 2-6


2.7 Terminals ......................................................................................................... 2-7
2.8 Measurement Scope and Accuracy ............................................................... 2-7
2.9 Management Function .................................................................................... 2-7
2.9.1 Control Performance .......................................................................................................... 2-7

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2 Technical Data

2.9.2 Clock Performance ............................................................................................................ 2-7


2.9.3 Fault and Disturbance Recording....................................................................................... 2-8
2.9.4 Binary Input Signal ............................................................................................................. 2-8

2.10 Protective Functions..................................................................................... 2-8


2.10.1 Fault Detector .................................................................................................................. 2-8
2.10.2 Distance Protection .......................................................................................................... 2-8
2.10.3 Phase Overcurrent Protection .......................................................................................... 2-8
2.10.4 Earth Fault Protection ...................................................................................................... 2-8
2.10.5 Overvoltage Protection..................................................................................................... 2-9
2.10.6 Undervoltage Protection................................................................................................... 2-9
2.10.7 Overfrequency Protection ................................................................................................ 2-9
2.10.8 Underfrequency Protection .............................................................................................. 2-9
2.10.9 Breaker Failure Protection ............................................................................................... 2-9
2.10.10 Thermal Overload Protection ....................................................................................... 2-10
2.10.11 Stub Overcurrent Protection ......................................................................................... 2-10
2.10.12 Dead Zone Protection .................................................................................................. 2-10
2.10.13 Pole Discrepancy Protection ........................................................................................ 2-10
2.10.14 Broken Conductor Protection ....................................................................................... 2-10
2.10.15 Auto-reclosing .............................................................................................................. 2-11
2.10.16 Transient Overreach .................................................................................................... 2-11
2.10.17 Fault Locator ................................................................................................................ 2-11

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2 Technical Data

2.1 Electrical Specifications


2.1.1 AC Current Input
Phase rotation

ABC

Nominal frequency (fn)

50Hz, 60Hz

Rated current (In)

1A

Linear to

0.05In~40In (It should measure current without beyond full scale

5A

against 20 times of related current and value of DC offset by 100%.)


Thermal withstand
-continuously

4In

-for 10s

30In

-for 1s

100In

-for half a cycle

250In

Burden

< 0.15VA/phase @In

Number

Up to 7 current input according to various applications

< 0.25VA/phase @In

2.1.2 AC Voltage Input


Phase rotation

ABC

Nominal frequency (fn)

50Hz, 60Hz

Rated voltage (Un)

100V~130V

Linear to

1V~170V

Thermal withstand
-continuously

200V

-10s

260V

-1s

300V

Burden at rated

< 0.20VA/phase @Un

Number

Up to 6 voltage input according to various applications

2.1.3 Power Supply


Standard

IEC 60255-11:2008

Rated voltage

110Vdc/125Vdc/220Vdc/250Vdc

Permissible voltage range

88~300Vdc

Permissible AC ripple voltage

15% of the nominal auxiliary voltage

Burden
Quiescent condition

<30W

Operating condition

<35W

2.1.4 Binary Input


Rated voltage

24Vdc

48Vdc

Rated current drain

1.2mA

2.4mA

Pickup voltage

16.8-28.8Vdc

33.6-57.6Vdc

Dropoff voltage

<12Vdc

<24Vdc

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2 Technical Data
Maximum permissible voltage

100Vdc

Withstand voltage

2000Vac, 2800Vdc (continuously )

Response time for logic input

1ms

Number

Up to 36 binary input according to various hardware configurations

Rated voltage

110Vdc

125Vdc

220Vdc

250Vdc

Rated current drain

1.1mA

1.25mA

2.2mA

2.5mA

Pickup voltage

77-132Vdc

87.5-150Vdc

154-264Vdc

175-300Vdc

Dropoff voltage

<55Vdc

<62.5Vdc

<110Vdc

<125Vdc

Maximum permissible voltage

300Vdc

Withstand voltage

2000Vac, 2800Vdc (continuously )

Response time for logic input

1ms

Number

Up to 36 binary input according to various hardware configurations

2.1.5 Binary Output


1.

Tripping/signaling contact

Output mode

Potential free contact


8A@380Vac

Continuous carry

8A@250Vdc
8A@125Vdc

Pickup time (Typical)

<8ms (3ms)

Dropoff time

<5ms
0.65A@48Vdc
0.25A@110Vdc

Breaking capacity (L/R=40ms)

0.25A@125Vdc
0.15A@220Vdc
0.15A@250Vdc

Burden
Maximal system voltage
Test voltage across open contact

300mW
380Vac
250Vdc
1000V RMS for 1min
10A@3s

Short duration current

15A@1s
20A@0.5s
30A@0.2s

Durability (Loaded contact)

10000 operations

Number

Up to 55 binary output according to various hardware configurations

2.

Fast signaling contact

Output mode
Continuous carry
Pickup time

Potential free contact


5A@380Vac
5A@250Vdc
<1ms
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2 Technical Data
Dropoff time

<5ms
1.0A@48Vdc

Breaking capacity (L/R=0ms)

0.9A@110Vdc
0.4A@220Vdc

Maximal system voltage


Test voltage across open contact

380Vac
250Vdc
1000V RMS for 1min

2.2 Mechanical Specifications


Mounting Way

Flush mounted

Chassis color

Silver grey

Weight per device

Approx. 15kg

Chassis material

Aluminum alloy

Location of terminal

Rear panel of the device

Device structure

Plug-in modular type @ rear side, integrated frontplate

Protection class
Standard

IEC 60255-1:2009

Front side

IP40

Other sides

IP30

Rear side, connection terminals

IP20

2.3 Ambient Temperature and Humidity Range


Standard

IEC 60255-1:2009

Operating temperature

-40C to +70C (Readability of display may be impaired below -20C)

Transport and storage temperature


range

-40C to +70C

Permissible humidity

5%-95%, without condensation

Pollution degree

Altitude

<3000m

2.4 Communication Port


2.4.1 EIA-485 Port
Baud rate

4.8kbit/s, 9.6kbit/s, 19.2kbit/s, 38.4kbit/s, 57.6kbit/s, 115.2kbit/s

Protocol

IEC 60870-5-103:1997

Maximal capacity

32

Transmission distance

<500m

Safety level

Isolation to ELV level

Twisted pair

Screened twisted pair cable

2.4.2 Ethernet Port


Connector type

RJ-45

ST (Multi mode)

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2 Technical Data
Transmission rate

100Mbits/s

Transmission standard

100Base-TX

100Base-FX

Transmission distance

<100m

<2km (1310nm)

Protocol

IEC 60870-5-103:1997, DNP 3.0 or IEC 61850

Safety level

Isolation to ELV level

2.4.3 Optical Fibre Port


2.4.3.1 For Station Level
Characteristic

Glass optical fiber

Connector type

ST

Fibre type

Multi mode

Transmission distance

<2km

Wave length

1310nm

Transmission power

Min. -20.0dBm

Minimum receiving power

Min. -30.0dBm

Margin

Min +3.0dB

2.4.3.2 For Process Level


Characteristic

Glass optical fiber

Connector type

LC

Fibre type

Multi mode

Transmission distance

<2km

Wave length

1310nm

Transmission power

Min. -20.0dBm

Minimum receiving power

Min. -30.0dBm

Margin

Min +3.0dB

2.4.3.3 For Pilot Channel


Characteristic

Glass optical fiber

Connector type

FC

ST

Fibre type

Single mode

Multi mode

Wave length

1310nm

1550nm

850nm

Transmission distance

Max.40km

Max.100km

Max.2km

Transmission power

-13.03.0 dBm

-5.0 dBm3.0 dBm

-12dBm~-20 dBm

Minimum receiving power

Min.-37 dBm

Min.-36 dBm

Min. -30.0dBm

Optical overload point

Min.-3 dBm

Min.-3 dBm

Min.-8 dBm

2.4.3.4 For Synchronization Port


Characteristic

Glass optical fiber

Connector type

ST

Fibre type

Multi mode

Wave length

820nm

PCS-902 Line Distance Relay

2-4
Date: 2013-09-05

2 Technical Data
Minimum receiving power

Min. -25.0dBm

Margin

Min +3.0dB

2.4.4 Print Port


Type

RS-232

Baud Rate

4.8kbit/s, 9.6kbit/s, 19.2kbit/s, 38.4kbit/s, 57.6kbit/s, 115.2kbit/s

Printer type

EPSON 300K printer

Safety level

Isolation to ELV level

2.4.5 Clock Synchronization Port


Type

RS-485

Transmission distance

<500m

Maximal capacity

32

Timing standard

PPS, IRIG-B

Safety level

Isolation to ELV level

2.5 Type Tests


2.5.1 Environmental Tests
Dry cold test

IEC60068-2-1:2007

Dry heat test

IEC60068-2-2:2007

Damp heat test, cyclic

IEC60068-2-30:2005

2.5.2 Mechanical Tests


Vibration

IEC 60255-21-1:1988 Class

Shock and bump

IEC 60255-21-2:1988 Class

2.5.3 Electrical Tests


Standard

IEC 60255-27:2005

Dielectric tests

Test voltage 2kV, 50Hz, 1min

Standard

IEC 60255-5:2000

Impulse voltage tests

Test voltage 5kV

Overvoltage category

Insulation

resistance

measurements

Isolation resistance >100M@500VDC

2.5.4 Electromagnetic Compatibility


IEC 60255-22-1:2007
1MHz burst disturbance test

Common mode: class 2.5kV


Differential mode: class 1.0kV
IEC60255-22-2:2008 class

Electrostatic discharge test

For contact discharge: 8kV


For air discharge: 15kV

PCS-902 Line Distance Relay

2-5
Date: 2013-09-05

2 Technical Data
IEC 60255-22-3:2007 class
Frequency sweep
Radiated amplitude-modulated
10V/m (rms), f=80~1000MHz
Radio frequency interference tests

Spot frequency
Radiated amplitude-modulated
10V/m (rms), f=80MHz/160MHz/450MHz/900MHz
Radiated pulse-modulated
10V/m (rms), f=900MHz
IEC 60255-22-4:2008

Fast transient disturbance tests

Power supply, I/O, Earth: class , 4kV, 2.5kHz, 5/50ns


Communication terminals: class , 2kV, 5kHz, 5/50ns
IEC 60255-22-5:2008

Surge immunity test

Power supply, AC input, I/O port: class , 1.2/50us


Common mode: 4kV
Differential mode: 2kV

Conducted

RF

Electromagnetic

Disturbance

IEC 60255-22-6:2001
Power supply, AC, I/O, Comm. Terminal: Class , 10Vrms, 150
kHz~80MHz

Power Frequency Magnetic Field

IEC 61000-4-8:2001

Immunity

class , 100A/m for 1min, 1000A/m for 3s

Pulse Magnetic Field Immunity

IEC 61000-4-9:2001
class , 6.4/16s, 1000A/m for 3s

Damped oscillatory magnetic field

IEC 61000-4-10:2001

immunity

class , 100kHz & 1MHz100A/m

Auxiliary power supply performance

IEC60255-11: 2008

- Voltage dips

Up to 200ms for dips to 40% of rated voltage without reset

-Voltage short interruptions

100ms for interruption without rebooting

2.6 Certifications

ISO9001:2008

ISO14001:2004

OHSAS18001:2007

ISO10012:2003

CMMI L4

EMC: 2004/108/EC, EN50263:1999

Products safety(PS): 2006/95/EC, EN61010-1:2001

PCS-902 Line Distance Relay

2-6
Date: 2013-09-05

2 Technical Data

2.7 Terminals
Connection Type

Wire Size
2

Crimp terminals, 1.5mm ~4.0mm2 lead


If using 4.0mm2 lead, only dedicated terminal cable lug provided by NR

AC current

can be adopted.
AC voltage

Crimp terminals, 1.0mm2~2.5mm2 lead

Power supply

Crimp terminals, 1.0mm2~2.5mm2 lead

Contact I/O

Crimp terminals, 1.0mm2~2.5mm2 lead

Grounding (Earthing) Connection

BVR type, 2.5mm~6.0mm2 lead

2.8 Measurement Scope and Accuracy


Item

Range

Accuracy

Phase range

0~ 360

Frequency

fn3 Hz

0.02Hz

Currents from protection measurement current transformers


Current

0.05~5.00In

Voltage

0.05~1.50Un

Active power (W)

Reactive power (VAr)

Apparent power (VA)

Energy (Wh)

Energy (VAh)

2.0% of rating (0.05~1.00In)


2.0% of applied quantities (1.00~5.00In)
1.0% of rating (0.05~1.00Un)
1.0% of applied quantities (1.00~1.50Un)

0.05~1.50Un

3.0% of rating (0.05~1.00In, 0.05~1.00Un)

0.05~5.00In

3.0% of applied quantities (1.00~5.00In, 1.00~1.50Un)

0.05~1.50Un

3.0% of rating (0.05~1.00In, 0.05~1.00Un)

0.05~5.00In

3.0% of applied quantities (1.00~5.00In, 1.00~1.50Un)

0.05~1.50Un

3.0% of rating (0.05~1.00In, 0.05~1.00Un)

0.05~5.00In

3.0% of applied quantities (1.00~5.00In, 1.00~1.50Un)

0.05~1.50Un

3.0% of rating (0.05~1.00In, 0.05~1.00Un)

0.05~5.00In

3.0% of applied quantities (1.00~5.00In, 1.00~1.50Un)

0.05~1.50Un

3.0% of rating (0.05~1.00In, 0.05~1.00Un)

0.05~5.00In

3.0% of applied quantities (1.00~5.00In, 1.00~1.50Un)

2.9 Management Function


2.9.1 Control Performance
Control mode

Local or remote

Accuracy of local control

1s

Accuracy of remote control

3s

2.9.2 Clock Performance


Real time clock accuracy

3s/day

Accuracy of GPS synchronization

1ms

External time synchronization

IRIG-B (200-98), PPS, IEEE1588 or SNTP protocol

PCS-902 Line Distance Relay

2-7
Date: 2013-09-05

2 Technical Data

2.9.3 Fault and Disturbance Recording


Maximum duration

10000 sampled points (24 sampled points per cycle)

Recording position

10 cycles before pickup of trigger element

2.9.4 Binary Input Signal


Resolution of binary input signal

1ms

Binary input mode

Potential-free contact

Resolution of SOE

2ms

2.10 Protective Functions


2.10.1 Fault Detector
2.10.1.1 DPFC Current Element
Setting range

0.050In~30.000In (A)

Accuracy

2.5% of setting or 0.02In whichever is greater

2.10.1.2 Residual Current Element


Setting range

0.050In~30.000In (A)

Accuracy

2.5% of setting or 0.02In whichever is greater

2.10.1.3 Overvoltage Element


Setting range

Un~2Unn (V)

Accuracy

2.5% of setting or 0.01Un, whichever is greater

2.10.2 Distance Protection


Setting range

(0.000~4Unn)/In (ohm)

Accuracy

2.5% of setting or 0.1/In whichever is greater

Resetting ratio

105%

Time delay

0.000~10.000 (s)

Accuracy

1%Setting+30ms

2.10.3 Phase Overcurrent Protection


Setting range

0.050In~30.000In (A)

Accuracy

2.5% of setting or 0.02In whichever is greater

Resetting ratio

95%

Time delay

0.000~20.000 (s)

Accuracy (definite-time characteristic)

1% of Setting+30ms (at 2 times current setting)

Accuracy (inverse-time characteristic)

2.5% operating time or 30ms, whichever is greater


(for current between 1.2 and 20 multiples of pickup)

2.10.4 Earth Fault Protection


Setting range

0.050In~30.000In (A)

PCS-902 Line Distance Relay

2-8
Date: 2013-09-05

2 Technical Data
Accuracy

2.5% of setting or 0.02In whichever is greater

Resetting ratio

95%

Time delay

0.000~20.000 (s)

Accuracy (definite-time characteristic)

1% of Setting+30ms (at 2 times current setting)

Accuracy (inverse-time characteristic)

2.5% operating time or 30ms, whichever is greater


(for current between 1.2 and 20 multiples of pickup)

2.10.5 Overvoltage Protection


Setting range

Un~2Unn (V)

Accuracy

2.5% of setting or 0.01Un, whichever is greater

Resetting ratio

95%

Time delay

0.000~30.000 (s)

Accuracy (definite-time characteristic)

1% of Setting+30ms (at 1.2 times voltage setting)

Accuracy (inverse-time characteristic)

2.5% operating time or 30ms, whichever is greater


(for voltage between 1.2 and 2 multiples of pickup)

2.10.6 Undervoltage Protection


Setting range

0~Unn (V)

Accuracy

2.5% of setting or 0.01Un, whichever is greater

Resetting ratio

105%

Time delay

0.000~30.000 (s)

Accuracy (definite-time characteristic)

1%Setting+30ms (at 1.2 times voltage setting)

Accuracy (inverse-time characteristic)

2.5% operating time or 30ms, whichever is greater


(for voltage between 0.5 and 0.8 multiples of pickup)

2.10.7 Overfrequency Protection


Setting range

50.00~65.00 (Hz)

Accuracy

0.02Hz

Resetting ratio

95%

Time delay

0.000~100.000 (s)

Accuracy

1%Setting+30ms (at 1.2 times frequency setting)

2.10.8 Underfrequency Protection


Setting range

45.00~ 60.00 (Hz)

Accuracy

0.02Hz

Resetting ratio

105%

Time delay

0.000s ~ 100.000 (s)

Accuracy

1%Setting+30ms (at 0.8 times frequency setting)

df/dt blocking setting range

0.200~20.000 (Hz/s)

Accuracy

0.02Hz/s

2.10.9 Breaker Failure Protection


Pick-up time

<20ms

PCS-902 Line Distance Relay

2-9
Date: 2013-09-05

2 Technical Data
Drop-off time

<20ms

Setting range of phase current

0.050In~30.000In (A)

Setting range of zero-sequence current

0.050In~30.000In (A)

Setting range of negative-sequence current

0.050In~30.000In (A)

Accuracy

2.5% of setting or 0.02In whichever is greater

Time delay (first)

0.000~10.000 (s)

Time delay (second)

0.000~10.000 (s)

2.10.10 Thermal Overload Protection


Base current setting range

0.050In~30.000In (A)

Accuracy

2.5% of setting or 0.02In whichever is greater

Line thermal time constant

0.100~100.000 (min)

Thermal overload coefficient for trip

1.000~3.000

Thermal overload coefficient for alarm

1.000~3.000

Resetting ratio

95%

Drop-off time

<30ms
2.5% operating time or 30ms, whichever is greater

Time accuracy

(for current between 1.2 and 20 multiples of pickup)

2.10.11 Stub Overcurrent Protection


Setting range

0.050In~30.000In (A)

Accuracy

2.5% of setting or 0.02In whichever is greater

Resetting ratio

95%

Time delay

0.000~10.000 (s)

Accuracy

1% of Setting+30ms (at 2 times current setting)

2.10.12 Dead Zone Protection


Setting range

0.050In~30.000In

Accuracy

2.5% or 0.02In whichever is greater

Time delay

0.000~10.000s

Accuracy

1%Setting+30ms

2.10.13 Pole Discrepancy Protection


Setting range (zero-sequence current)

0.050In~30.000In (A)

Setting range (negative-sequence current)

0.050In~30.000In (A)

Accuracy

2.5% of setting 0.02In whichever is greater

Resetting ratio

95%

Time delay

0.000~600.000 (s)

Accuracy

1% of Setting+30ms (at 2 times current setting)

2.10.14 Broken Conductor Protection


Setting range (I2/I1)

0.20~1.00

Accuracy

2.5% of setting
PCS-902 Line Distance Relay

2-10
Date: 2013-09-05

2 Technical Data
Resetting ratio

95%

Time delay

0.000~600.000 (s)

Accuracy

1% of Setting+30ms

2.10.15 Auto-reclosing
Phase difference setting range

0~89 (Deg)

Accuracy

2.0Deg

Voltage difference setting range

0.02Un~0.8Un (V)

Accuracy

Max(0.01Un, 2.5%)

Frequency difference setting range

0.02~1 (Hz)

Accuracy

0.01Hz

Operating time of synchronism check

1%Setting+20ms

Operating time of energizing check

1%Setting+20ms

Operating time of auto-reclosing

1%Setting+20ms

2.10.16 Transient Overreach


2%

Tolerance for all high-speed protection

2.10.17 Fault Locator


Accuracy for multi-phase faults with single end feed

< 2.5%

Tolerance will be higher in case of single-phase fault with high ground resistance.

PCS-902 Line Distance Relay

2-11
Date: 2013-09-05

2 Technical Data

PCS-902 Line Distance Relay

2-12
Date: 2013-09-05

3 Operation Theory

3 Operation Theory
Table of Contents
3 Operation Theory ............................................................................. 3-a
3.1 System Parameters ......................................................................................... 3-1
3.1.1 General Application ............................................................................................................ 3-1
3.1.2 Function Description .......................................................................................................... 3-1
3.1.3 Settings .............................................................................................................................. 3-1

3.2 Line Parameters .............................................................................................. 3-1


3.2.1 General Application ............................................................................................................ 3-1
3.2.2 Function Description .......................................................................................................... 3-2
3.2.3 Settings .............................................................................................................................. 3-2

3.3 Circuit Breaker Position Supervision ............................................................ 3-2


3.3.1 General Application ............................................................................................................ 3-2
3.3.2 Function Description .......................................................................................................... 3-2
3.3.3 Function Block Diagram ..................................................................................................... 3-3
3.3.4 I/O Signals ......................................................................................................................... 3-4
3.3.5 Logic .................................................................................................................................. 3-4
3.3.6 Settings .............................................................................................................................. 3-5

3.4 Fault Detector (FD) .......................................................................................... 3-5


3.4.1 Application.......................................................................................................................... 3-5
3.4.2 Fault Detector in Fault Detector DSP ................................................................................. 3-5
3.4.3 Protection Fault Detector in Protection Calculation DSP ................................................... 3-8
3.4.4 Function Block Diagram ..................................................................................................... 3-9
3.4.5 I/O Signals ......................................................................................................................... 3-9
3.4.6 Logic .................................................................................................................................. 3-9
3.4.7 Settings ............................................................................................................................ 3-10

3.5 Auxiliary Element .......................................................................................... 3-10

3-a

PCS-902 Line Distance Relay


Date: 2013-12-25

3 Operation Theory

3.5.1 General Application .......................................................................................................... 3-10


3.5.2 Function Description ........................................................................................................ 3-10
3.5.3 Function Block Diagram ................................................................................................... 3-13
3.5.4 I/O Signals ....................................................................................................................... 3-14
3.5.5 Logic ................................................................................................................................ 3-16
3.5.6 Settings ............................................................................................................................ 3-19

3.6 Distance Protection ...................................................................................... 3-21


3.6.1 General Application .......................................................................................................... 3-21
3.6.2 Function Description ........................................................................................................ 3-21
3.6.3 DPFC Distance Protection ............................................................................................... 3-29
3.6.4 Load Encroachment ......................................................................................................... 3-33
3.6.5 Mho Distance Protection .................................................................................................. 3-35
3.6.6 Quadrilateral Distance Protection .................................................................................... 3-50
3.6.7 Pilot Distance Zone .......................................................................................................... 3-60
3.6.8 Power Swing Detection .................................................................................................... 3-63
3.6.9 Power Swing Blocking Releasing..................................................................................... 3-64
3.6.10 Distance SOTF Protection ............................................................................................. 3-70

3.7 Optical Pilot Channel (Option) ..................................................................... 3-75


3.7.1 General Application .......................................................................................................... 3-75
3.7.2 Function Description ........................................................................................................ 3-75
3.7.3 Function Block Diagram ................................................................................................... 3-80
3.7.4 I/O Signals ....................................................................................................................... 3-80
3.7.5 Logic ................................................................................................................................ 3-82
3.7.6 Settings ............................................................................................................................ 3-82

3.8 Pilot Distance Protection .............................................................................. 3-82


3.8.1 General Application .......................................................................................................... 3-82
3.8.2 Function Description ........................................................................................................ 3-83
3.8.3 Function Block Diagram ................................................................................................... 3-93
3.8.4 I/O Signals ....................................................................................................................... 3-93
3.8.5 Settings ............................................................................................................................ 3-94
3-b

PCS-902 Line Distance Relay


Date: 2013-12-25

3 Operation Theory

3.9 Pilot Directional Earth-fault Protection ....................................................... 3-95


3.9.1 General Application .......................................................................................................... 3-95
3.9.2 Function Description ........................................................................................................ 3-96
3.9.3 Function Block Diagram ................................................................................................. 3-101
3.9.4 I/O Signals ..................................................................................................................... 3-101
3.9.5 Settings .......................................................................................................................... 3-102

3.10 Current Direction....................................................................................... 3-103


3.10.1 General Application ...................................................................................................... 3-103
3.10.2 Function Description .................................................................................................... 3-103
3.10.3 Function Block Diagram ............................................................................................... 3-108
3.10.4 I/O Signals ................................................................................................................... 3-108
3.10.5 Settings ........................................................................................................................ 3-109

3.11 Phase Overcurrent Protection ................................................................. 3-109


3.11.1 General Application ...................................................................................................... 3-109
3.11.2 Function Description..................................................................................................... 3-109
3.11.3 Function Block Diagram ............................................................................................... 3-112
3.11.4 I/O Signals.................................................................................................................... 3-112
3.11.5 Logic............................................................................................................................. 3-113
3.11.6 Settings ........................................................................................................................ 3-113

3.12 Earth Fault Protection................................................................................ 3-117


3.12.1 General Application ...................................................................................................... 3-117
3.12.2 Function Description .................................................................................................... 3-117
3.12.3 Function Block Diagram ............................................................................................... 3-119
3.12.4 I/O Signals ................................................................................................................... 3-120
3.12.5 Logic ............................................................................................................................ 3-120
3.12.6 Settings ........................................................................................................................ 3-121

3.13 Overcurrent Protection for VT Circuit Failure ........................................ 3-125


3.13.1 General Application ...................................................................................................... 3-125
3.13.2 Function Block Diagram ............................................................................................... 3-126
3.13.3 I/O Signals ................................................................................................................... 3-126
3-c

PCS-902 Line Distance Relay


Date: 2013-12-25

3 Operation Theory

3.13.4 Logic ............................................................................................................................ 3-127


3.13.5 Settings ........................................................................................................................ 3-127

3.14 Residual Current SOTF Protection .......................................................... 3-128


3.14.1 General Application ...................................................................................................... 3-128
3.14.2 Function Description .................................................................................................... 3-128
3.14.3 Function Block Diagram ............................................................................................... 3-128
3.14.4 I/O Signals ................................................................................................................... 3-128
3.14.5 Logic ............................................................................................................................ 3-129
3.14.6 Settings ........................................................................................................................ 3-129

3.15 Voltage Protection ..................................................................................... 3-129


3.15.1 Overvoltage Protection................................................................................................. 3-130
3.15.2 Undervoltage Protection............................................................................................... 3-136

3.16 Frequency Protection ............................................................................... 3-142


3.16.1 Overfrequency Protection ............................................................................................ 3-142
3.16.2 Underfrequency Protection .......................................................................................... 3-146

3.17 Breaker Failure Protection ....................................................................... 3-151


3.17.1 General Application ...................................................................................................... 3-151
3.17.2 Function Description .................................................................................................... 3-151
3.17.3 Function Block Diagram ............................................................................................... 3-152
3.17.4 I/O Signals ................................................................................................................... 3-153
3.17.5 Logic ............................................................................................................................ 3-154
3.17.6 Settings ........................................................................................................................ 3-155

3.18 Thermal Overload Protection ................................................................... 3-155


3.18.1 General Application ...................................................................................................... 3-155
3.18.2 Function Description .................................................................................................... 3-156
3.18.3 Function Block Diagram ............................................................................................... 3-157
3.18.4 I/O Signals ................................................................................................................... 3-157
3.18.5 Logic ............................................................................................................................ 3-158
3.18.6 Settings ........................................................................................................................ 3-159

3.19 Stub Overcurrent Protection .................................................................... 3-159


3-d

PCS-902 Line Distance Relay


Date: 2013-12-25

3 Operation Theory

3.19.1 General Application ...................................................................................................... 3-159


3.19.2 Function Block Diagram ............................................................................................... 3-160
3.19.3 I/O Signals ................................................................................................................... 3-160
3.19.4 Logic ............................................................................................................................ 3-161
3.19.5 Settings ........................................................................................................................ 3-161

3.20 Dead Zone Protection ............................................................................... 3-162


3.20.1 General Application ...................................................................................................... 3-162
3.20.2 Function Description .................................................................................................... 3-162
3.20.3 Function Block Diagram ............................................................................................... 3-162
3.20.4 I/O Signal ..................................................................................................................... 3-162
3.20.5 Logic ............................................................................................................................ 3-163
3.20.6 Settings ........................................................................................................................ 3-163

3.21 Pole Discrepancy Protection.................................................................... 3-163


3.21.1 General Application ...................................................................................................... 3-163
3.21.2 Function Description .................................................................................................... 3-164
3.21.3 Function Block Diagram ............................................................................................... 3-164
3.21.4 I/O Signals ................................................................................................................... 3-164
3.21.5 Logic ............................................................................................................................ 3-164
3.21.6 Settings ........................................................................................................................ 3-165

3.22 Broken Conductor Protection .................................................................. 3-165


3.22.1 General Application ...................................................................................................... 3-165
3.22.2 Function Description .................................................................................................... 3-166
3.22.3 Function Block Diagram ............................................................................................... 3-166
3.22.4 I/O Signals ................................................................................................................... 3-166
3.22.5 Logic ............................................................................................................................ 3-167
3.22.6 Settings ........................................................................................................................ 3-167

3.23 Synchrocheck ........................................................................................... 3-168


3.23.1 General Application ...................................................................................................... 3-168
3.23.2 Function Description .................................................................................................... 3-168
3.23.3 Function Block Diagram ............................................................................................... 3-171
3-e

PCS-902 Line Distance Relay


Date: 2013-12-25

3 Operation Theory

3.23.4 I/O Signals ................................................................................................................... 3-171


3.23.5 Logic ............................................................................................................................ 3-172
3.23.6 Settings ........................................................................................................................ 3-174

3.24 Automatic Reclosure ................................................................................ 3-175


3.24.1 General Application ...................................................................................................... 3-175
3.24.2 Function Description .................................................................................................... 3-176
3.24.3 Function Block Diagram ............................................................................................... 3-177
3.24.4 I/O Signals ................................................................................................................... 3-177
3.24.5 Logic ............................................................................................................................ 3-179
3.24.6 Settings ........................................................................................................................ 3-191

3.25 Transfer Trip .............................................................................................. 3-193


3.25.1 General Application ...................................................................................................... 3-193
3.25.2 Function Description .................................................................................................... 3-193
3.25.3 Function Block Diagram ............................................................................................... 3-193
3.25.4 I/O Signals ................................................................................................................... 3-193
3.25.5 Logic ............................................................................................................................ 3-194
3.25.6 Settings ........................................................................................................................ 3-194

3.26 Trip Logic ................................................................................................... 3-194


3.26.1 General Application ...................................................................................................... 3-194
3.26.2 Function Description .................................................................................................... 3-194
3.26.3 Function Block Diagram ............................................................................................... 3-195
3.26.4 I/O Signals ................................................................................................................... 3-195
3.26.5 Logic ............................................................................................................................ 3-196
3.26.6 Settings ........................................................................................................................ 3-200

3.27 VT Circuit Supervision.............................................................................. 3-200


3.27.1 General Application ...................................................................................................... 3-200
3.27.2 Function Description .................................................................................................... 3-201
3.27.3 Function Block Diagram ............................................................................................... 3-201
3.27.4 I/O Signals ................................................................................................................... 3-201
3.27.5 Logic ............................................................................................................................ 3-202
3-f

PCS-902 Line Distance Relay


Date: 2013-12-25

3 Operation Theory

3.27.6 Settings ........................................................................................................................ 3-203

3.28 CT Circuit Supervision ............................................................................. 3-203


3.28.1 General Application ...................................................................................................... 3-203
3.28.2 Function Description .................................................................................................... 3-203
3.28.3 Function Block Diagram ............................................................................................... 3-203
3.28.4 I/O Signals ................................................................................................................... 3-204
3.28.5 Logic ............................................................................................................................ 3-204

3.29 Control and Synchrocheck for Manual Closing ..................................... 3-204


3.29.1 General Application ...................................................................................................... 3-204
3.29.2 Function Description .................................................................................................... 3-204
3.29.3 Function Block Diagram ............................................................................................... 3-211
3.29.4 I/O Signals ................................................................................................................... 3-211
3.29.5 Settings ........................................................................................................................ 3-213

3.30 Faulty Phase Selection ............................................................................. 3-214


3.30.1 General Application ...................................................................................................... 3-214
3.30.2 Function Description .................................................................................................... 3-215
3.30.3 Function Block Diagram ............................................................................................... 3-216
3.30.4 I/O Signals ................................................................................................................... 3-216

3.31 Fault Location ........................................................................................... 3-217


3.31.1 Application.................................................................................................................... 3-217
3.31.2 Function Description .................................................................................................... 3-217
3.31.3 Function Block Diagram ............................................................................................... 3-220
3.31.4 I/O Signals ................................................................................................................... 3-220

List of Figures
Figure 3.3-1 Logic diagram of CB position supervision.........................................................3-4
Figure 3.3-2 Logic diagram of trip&closing circuit supervision ............................................3-5
Figure 3.4-1 Flow chart of protection program .......................................................................3-8
Figure 3.4-2 Logic diagram of fault detector ...........................................................................3-9
Figure 3.5-1 Logic diagram of auxiliary element ...................................................................3-19

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3 Operation Theory

Figure 3.6-1 Protected reach of distance protection for each zone ....................................3-22
Figure 3.6-2 Operating time of single-phase fault (50Hz, SIR=1) .........................................3-23
Figure 3.6-3 Operating time of single-phase fault (60Hz, SIR=1) .........................................3-24
Figure 3.6-4 Operating time of two-phase fault (50Hz, SIR=1) .............................................3-24
Figure 3.6-5 Operating time of two-phase fault (60Hz, SIR=1) .............................................3-25
Figure 3.6-6 Operating time of three-phase fault (50Hz, SIR=1) ..........................................3-25
Figure 3.6-7 Operating time of three-phase fault (60Hz, SIR=1) ..........................................3-26
Figure 3.6-8 Operating time of single-phase fault (50Hz, SIR=30) .......................................3-26
Figure 3.6-9 Operating time of single-phase fault (60Hz, SIR=30) .......................................3-27
Figure 3.6-10 Operating time of two-phase fault (50Hz, SIR=30) .........................................3-27
Figure 3.6-11 Operating time of two-phase fault (60Hz, SIR=30) .........................................3-28
Figure 3.6-12 Operating time of three-phase fault (50Hz, SIR=30) ......................................3-28
Figure 3.6-13 Operating time of three-phase fault (60Hz, SIR=30) ......................................3-29
Figure 3.6-14 Operation characteristic for forward fault ......................................................3-30
Figure 3.6-15 Operation characteristic for reverse fault ......................................................3-31
Figure 3.6-16 Logic diagram of DPFC distance protection ..................................................3-32
Figure 3.6-17 Distance element with load trapezoid .............................................................3-33
Figure 3.6-18 Phase-to-ground operation characteristic for forward fault .........................3-35
Figure 3.6-19 Phase-to-phase operation characteristic for forward fault ...........................3-36
Figure 3.6-20 Operation characteristic for reverse fault ......................................................3-38
Figure 3.6-21 Steady-state characteristic of three-phase short-circuit fault ......................3-38
Figure 3.6-22 Operation characteristic of three-phase close up short-circuit fault ...........3-39
Figure 3.6-23 Shift impedance characteristic of zone 1 and zone 2 ....................................3-40
Figure 3.6-24 Operation characteristic of reverse Z4 distance protection .........................3-41
Figure 3.6-25 Logic diagram of enabling distance protection (Mho) ..................................3-43
Figure 3.6-26 Logic diagram of distance protection (Mho zone 1) ......................................3-43
Figure 3.6-27 Logic diagram of distance protection (Mho zone 2) ......................................3-44
Figure 3.6-28 Logic diagram of distance protection (Mho zone 3) ......................................3-45
Figure 3.6-29 Logic diagram of distance protection (Mho zone 4) ......................................3-46
Figure 3.6-30 Quadrilateral forward distance element characteristics ...............................3-50
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3 Operation Theory

Figure 3.6-31 Quadrilateral reverse distance element characteristic..................................3-51


Figure 3.6-32 Logic diagram of enabling distance protection (Quad) .................................3-53
Figure 3.6-33 Logic diagram of distance protection (Quad zone 1) ....................................3-53
Figure 3.6-34 Logic diagram of distance protection (Quad zone 2) ....................................3-54
Figure 3.6-35 Logic diagram of distance protection (Quad zone 3) ....................................3-55
Figure 3.6-36 Logic diagram of distance protection (Quad zone 4) ....................................3-56
Figure 3.6-37 Protected zone of pilot distance protection ...................................................3-60
Figure 3.6-38 Pilot reverse weak infeed element ..................................................................3-61
Figure 3.6-39 Logic diagram of pilot distance zone (Mho characteristic) ...........................3-61
Figure 3.6-40 Logic diagram of pilot distance zone (Quad characteristic) .........................3-62
Figure 3.6-41 Logic diagram of power swing detection .......................................................3-64
Figure 3.6-42 Logic diagram of PSBR ....................................................................................3-68
Figure 3.6-43 Logic diagram of enabling distance SOTF protection ...................................3-71
Figure 3.6-44 Logic diagram of distance SOTF protection by manual closing signal .......3-71
Figure 3.6-45 Logic diagram of distance SOTF protection by 1-pole or 3-pole AR ...........3-72
Figure 3.6-46 Logic diagram of distance SOTF protection by PD condition ......................3-73
Figure 3.7-1 Direct optical link up to 2km with 850nm .........................................................3-76
Figure 3.7-2 Direct optical link up to 40km with 1310nm or up to 100km with 1550nm ....3-76
Figure 3.7-3 Connect to a communication network via communication convertor ...........3-76
Figure 3.7-4 Connect to a communication network via MUX-64 ..........................................3-77
Figure 3.7-5 Connect to a communication network via MUX-2M .........................................3-77
Figure 3.7-6 Schematic diagram of communication channel time ......................................3-79
Figure 3.7-7 Logic diagram of receiving signal n .................................................................3-82
Figure 3.8-1 Enabling/disabling logic of pilot distance protection......................................3-83
Figure 3.8-2 Logic diagram of receiving signal.....................................................................3-83
Figure 3.8-3 Zone extension ...................................................................................................3-84
Figure 3.8-4 Simple schematic of PUTT ................................................................................3-85
Figure 3.8-5 Logic diagram of pilot distance protection (PUTT)..........................................3-85
Figure 3.8-6 Simple schematic of POTT ................................................................................3-86
Figure 3.8-7 Logic diagram of pilot distance protection (POTT) .........................................3-86
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PCS-902 Line Distance Relay


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3 Operation Theory

Figure 3.8-8 Simple schematic of system fault .....................................................................3-87


Figure 3.8-9 Simple schematic of blocking ...........................................................................3-88
Figure 3.8-10 Logic diagram of pilot distance protection (Blocking) ..................................3-88
Figure 3.8-11 Logic diagram of pilot distance protection (Unblocking) ..............................3-89
Figure 3.8-12 Current reversal ................................................................................................3-89
Figure 3.8-13 Logic diagram of current reversal blocking ...................................................3-90
Figure 3.8-14 Line fault description .......................................................................................3-91
Figure 3.8-15 Weak infeed logic during pickup .....................................................................3-91
Figure 3.8-16 Weak infeed logic without pickup ...................................................................3-92
Figure 3.8-17 Simplified CB Echo logic for POTT .................................................................3-92
Figure 3.9-1 Enabling/disabling logic of pilot directional earth-fault protection ...............3-96
Figure 3.9-2 Logic diagram of receiving signal.....................................................................3-96
Figure 3.9-3 Forward/reverse direction of zero-sequence power........................................3-97
Figure 3.9-4 Simple schematic of DEF (permissive scheme) ..............................................3-97
Figure 3.9-5 Logic diagram of DEF (permissive scheme) ....................................................3-98
Figure 3.9-6 Simple schematic of blocking ...........................................................................3-99
Figure 3.9-7 Logic diagram of DEF (Blocking scheme) ........................................................3-99
Figure 3.9-8 Logic diagram for unblocking .........................................................................3-100
Figure 3.10-1 Line fault description .....................................................................................3-103
Figure 3.10-2 Vector diagram of current and voltage .........................................................3-104
Figure 3.10-3 Vector diagram of zero-sequence power ......................................................3-106
Figure 3.11-1 Logic diagram of phase overcurrent protection .......................................... 3-113
Figure 3.12-1 Logic diagram of earth fault protection ........................................................3-120
Figure 3.13-1 Logic diagram of overcurrent protection for VT circuit failure...................3-127
Figure 3.14-1 Logic diagram of residual current SOTF protection ....................................3-129
Figure 3.15-1 Logic diagram of stage x of overvoltage protection ....................................3-134
Figure 3.15-2 Blocking logic of undervoltage protection ...................................................3-140
Figure 3.15-3 Logic diagram of stage x of undervoltage protection .................................3-140
Figure 3.16-1 Logic diagram of overfrequency protection (stage 1) .................................3-143
Figure 3.16-2 Logic diagram of overfrequency protection (stage 2) .................................3-144
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3 Operation Theory

Figure 3.16-3 Logic diagram of overfrequency protection (stage 3) .................................3-144


Figure 3.16-4 Logic diagram of overfrequency protection (stage 4) .................................3-144
Figure 3.16-5 Logic diagram of overfrequency protection (start)......................................3-145
Figure 3.16-6 Logic diagram of underfrequency protection (stag1)..................................3-148
Figure 3.16-7 Logic diagram of underfrequency protection (stag2) ..................................3-148
Figure 3.16-8 Logic diagram of underfrequency protection (stag3) ..................................3-149
Figure 3.16-9 Logic diagram of underfrequency protection (stag4) ..................................3-149
Figure 3.16-10 Logic diagram of underfrequency protection (start) .................................3-150
Figure 3.17-1 Logic diagram of breaker failure protection.................................................3-154
Figure 3.18-1 Characteristic curve of the thermal overload model ...................................3-157
Figure 3.18-2 Logic diagram of thermal overload protection (stage 1) .............................3-158
Figure 3.18-3 Logic diagram of thermal overload protection (stage 2) .............................3-158
Figure 3.19-1 3/2 breakers arrangement ..............................................................................3-160
Figure 3.19-2 Logic diagram of stub overcurrent protection .............................................3-161
Figure 3.20-1 Dead zone protection .....................................................................................3-163
Figure 3.21-1 Logic diagram of pole discrepancy protection ............................................3-165
Figure 3.22-1 Logic diagram of broken conductor protection ...........................................3-167
Figure 3.23-1 Relationship between reference voltage and synchronism voltage ..........3-168
Figure 3.23-2 Line voltage circuit failure supervision logic ...............................................3-170
Figure 3.23-3 Bus Voltage Circuit Failure Supervision logic .............................................3-170
Figure 3.23-4 Synchronism check ........................................................................................3-173
Figure 3.23-5 Dead charge check logic ...............................................................................3-173
Figure 3.23-6 Synchrocheck logic ........................................................................................3-174
Figure 3.24-1 Logic diagram of AR block ............................................................................3-180
Figure 3.24-2 Logic diagram of AR ready ............................................................................3-181
Figure 3.24-3 Logic diagram of tripping condition output .................................................3-182
Figure 3.24-4 Single-phase tripping initiating AR ...............................................................3-183
Figure 3.24-5 Three-phase tripping initiating AR ................................................................3-183
Figure 3.24-6 1-pole AR initiation .........................................................................................3-184
Figure 3.24-7 3-pole AR initiation .........................................................................................3-184
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3 Operation Theory

Figure 3.24-8 One-shot AR ....................................................................................................3-185


Figure 3.24-9 Extra time delay of AR....................................................................................3-185
Figure 3.24-10 Reclosing output logic .................................................................................3-186
Figure 3.24-11 Wait toslave signal........................................................................................3-186
Figure 3.24-12 Reclosing failure and success ....................................................................3-187
Figure 3.24-13 Single-phase transient fault.........................................................................3-190
Figure 3.24-14 Single-phase permanent fault ([79.N_Rcls]=2) ..........................................3-190
Figure 3.25-1 Logic diagram of transfer trip........................................................................3-194
Figure 3.26-1 Tripping logic ..................................................................................................3-198
Figure 3.26-2 Breaker failure initiation logic .......................................................................3-198
Figure 3.26-3 Blocking AR logic ...........................................................................................3-199
Figure 3.27-1 Logic of VT circuit supervision .....................................................................3-202
Figure 3.27-2 Logic of VT neutral point supervision ..........................................................3-202
Figure 3.28-1 Logic diagram of CT circuit failure ...............................................................3-204
Figure 3.29-1 Logic diagram of closing primary equipment ..............................................3-206
Figure 3.29-2 Logic diagram of open primary equipment ..................................................3-207
Figure 3.29-3 Configuration page of control output 01 (default configration)..................3-208
Figure 3.29-4 Configuration page of control output 02 (default configration)..................3-209
Figure 3.30-1 The region of faulty phase selection ............................................................3-216
Figure 3.31-1 Equivalent sequence network .......................................................................3-218

List of Tables
Table 3.1-1 System parameters ................................................................................................3-1
Table 3.2-1 Line parameters ......................................................................................................3-2
Table 3.3-1 I/O signals of CB position supervision .................................................................3-4
Table 3.3-2 Internal settings of CB position supervision .......................................................3-5
Table 3.4-1 I/O signals of fault detector ...................................................................................3-9
Table 3.4-2 Settings of fault detector .....................................................................................3-10
Table 3.5-1 I/O signals of auxiliary element ...........................................................................3-14
Table 3.5-2 Settings of auxiliary element ...............................................................................3-19

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3 Operation Theory

Table 3.6-1 I/O signals of DPFC distance protection ............................................................3-32


Table 3.6-2 Settings of DPFC distance protection ................................................................3-32
Table 3.6-3 I/O signals of load encroachment .......................................................................3-34
Table 3.6-4 Settings of load encroachment ...........................................................................3-34
Table 3.6-5 I/O signals of distance protection (Mho) ............................................................3-42
Table 3.6-6 Settings of distance protection (Mho) ................................................................3-47
Table 3.6-7 I/O signals of distance protection (Quad) ..........................................................3-52
Table 3.6-8 Settings of distance protection (Quad) ..............................................................3-56
Table 3.6-9 Settings of pilot distance zone ............................................................................3-62
Table 3.6-10 I/O signals of power swing detection ...............................................................3-63
Table 3.6-11 Settings of power swing detection ...................................................................3-64
Table 3.6-12 I/O signals of PSBR ............................................................................................3-68
Table 3.6-13 Settings of PSBR ................................................................................................3-69
Table 3.6-14 I/O signals of distance SOTF protection ..........................................................3-70
Table 3.6-15 Settings of distance SOTF protection ..............................................................3-73
Table 3.6-16 Internal settings of distance SOTF protection .................................................3-75
Table 3.7-1 I/O signals of pilot channel ..................................................................................3-80
Table 3.7-2 Settings of pilot channel ......................................................................................3-82
Table 3.8-1 I/O signals of pilot distance protection ..............................................................3-93
Table 3.8-2 Settings of pilot distance protection ..................................................................3-94
Table 3.8-3 Internal settings of pilot distance protection .....................................................3-95
Table 3.9-1 I/O signals of pilot directional earth-fault protection ......................................3-101
Table 3.9-2 Settings of pilot directional earth-fault protection ..........................................3-102
Table 3.9-3 Internal settings of pilot distance protection ...................................................3-102
Table 3.10-1 Direction description .......................................................................................3-105
Table 3.10-2 I/O signals of current direction .......................................................................3-108
Table 3.10-3 Settings of current direction ...........................................................................3-109
Table 3.11-1 Inverse-time curve parameters ........................................................................ 3-111
Table 3.11-2 I/O signals of phase overcurrent protection .................................................. 3-112
Table 3.11-3 Settings of phase overcurrent protection ...................................................... 3-113
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PCS-902 Line Distance Relay


Date: 2013-12-25

3 Operation Theory

Table 3.12-1 Inverse-time curve parameters........................................................................ 3-119


Table 3.12-2 I/O signals of earth fault protection ................................................................3-120
Table 3.12-3 Settings of earth fault protection ....................................................................3-121
Table 3.13-1 I/O signals of overcurrent protection for VT circuit failure ...........................3-126
Table 3.13-2 Settings of overcurrent protection for VT circuit failure ...............................3-127
Table 3.14-1 I/O signals of residual SOTF protection .........................................................3-128
Table 3.14-2 Settings of residual current SOTF protection ................................................3-129
Table 3.15-1 Inverse-time curve parameters........................................................................3-132
Table 3.15-2 I/O signals of overvoltage protection .............................................................3-133
Table 3.15-3 Settings of overvoltage protection .................................................................3-134
Table 3.15-4 Inverse-time curve parameters of phase undervoltage protection ..............3-138
Table 3.15-5 I/O signals of undervoltage protection ...........................................................3-139
Table 3.15-6 Settings of undervoltage protection ...............................................................3-141
Table 3.16-1 I/O signals of overfrequency protection .........................................................3-143
Table 3.16-2 Settings of overfrequency protection .............................................................3-145
Table 3.16-3 I/O signals of underfrequency protection ......................................................3-147
Table 3.16-4 Settings of underfrequency protection ..........................................................3-150
Table 3.17-1 I/O signals of breaker failure protection .........................................................3-153
Table 3.17-2 Settings of breaker failure protection .............................................................3-155
Table 3.18-1 I/O signals of thermal overload protection.....................................................3-157
Table 3.18-2 Settings of thermal overload protection.........................................................3-159
Table 3.19-1 I/O signals of stub overcurrent protection .....................................................3-160
Table 3.19-2 Settings of stub overcurrent protection .........................................................3-161
Table 3.20-1 I/O signals of dead zone protection ................................................................3-162
Table 3.20-2 Settings of dead zone protection ....................................................................3-163
Table 3.21-1 I/O signals of pole discrepancy protection ....................................................3-164
Table 3.21-2 Settings of pole discrepancy protection ........................................................3-165
Table 3.22-1 I/O signals of broken conductor protection ...................................................3-166
Table 3.22-2 Settings of broken conductor protection .......................................................3-167
Table 3.23-1 I/O signals of synchrocheck ............................................................................3-171
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3 Operation Theory

Table 3.23-2 Settings of synchrocheck ................................................................................3-174


Table 3.24-1 I/O signals of auto-reclosing ...........................................................................3-177
Table 3.24-2 Reclosing number ............................................................................................3-189
Table 3.24-3 Settings of auto-reclosing ...............................................................................3-191
Table 3.25-1 I/O signals of transfer trip ................................................................................3-193
Table 3.25-2 Settings of Transfer trip ...................................................................................3-194
Table 3.26-1 I/O signals of trip logic .....................................................................................3-195
Table 3.26-2 Settings of trip logic .........................................................................................3-200
Table 3.27-1 I/O signals of VT circuit supervision ..............................................................3-201
Table 3.27-2 VTS Settings .....................................................................................................3-203
Table 3.28-1 I/O signals of CT circuit supervision ..............................................................3-204
Table 3.29-1 I/O signals of control ........................................................................................ 3-211
Table 3.29-2 Control Settings ...............................................................................................3-213
Table 3.29-3 Synchrocheck Settings ....................................................................................3-213
Table 3.30-1 Relation between UOMAX and faulty phase .............................................3-215
Table 3.30-2 I/O signals of faulty phase selection ..............................................................3-216
Table 3.31-1 I/O signals of fault location..............................................................................3-220

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Date: 2013-12-25

3 Operation Theory

3.1 System Parameters


3.1.1 General Application
The device performs various protection functions by respective algorithms with the information
(currents and voltages) acquired from primary system through current transformer and voltage
transformer, so it is important to configure analog input channels correctly.
Further to correct configuration of analog input channels, other protected system information, such
as the parameters of voltage transformer and current transformer are also required.

3.1.2 Function Description


The device generally considers transmission line as its protected object, current flows from busbar
to line is considered as the forward direction.

3.1.3 Settings
Table 3.1-1 System parameters
No.

Name

Range

Step

Unit

Remark

Active_Grp

1~10

Active setting group

Opt_SysFreq

50 or 60

PrimaryEquip_Name

U1n

33.00~65500.00

0.01

kV

U2n

80.00~220.00

0.01

I1n

100~65500

Primary rated value of CT

I2n

1 or 5

Secondary rated value of CT

Hz

System frequency
The name of primary equipment
Primary rated value of VT (phase to
phase)
Secondary rated value of VT (phase to
phase)

Frequency upper limit setting


8

f_High_FreqAlm

50~65

Hz

The

device

will

issue

an

alarm

[Alm_Freq], when system frequency is


higher than the setting.
Frequency lower limit setting

f_Low_FreqAlm

45~60

Hz

The

device

will

issue

an

alarm

[Alm_Freq], when system frequency is


lower than the setting.

3.2 Line Parameters


3.2.1 General Application
When the device equips with line protection functions, line parameters of protected line are
required, especially for fault location, precise line parameters are the basic criterion for accurate
fault location.

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3 Operation Theory

3.2.2 Function Description


Line parameters mainly include positive-sequence reactance, positive-sequence resistance,
zero-sequence reactance, zero-sequence resistance, mutual zero-sequence reactance, mutual
zero-sequence resistance and line length.
The positive-sequence reactance, zero-sequence reactance, positive-sequence resistance and
zero-sequence resistance are the reactance and resistance value of the whole line. In general, the
device locates the fault through calculating the impedance value from the location of the device to
fault point.

3.2.3 Settings
Table 3.2-1 Line parameters
No.

Name

Range

Step

Unit

Remark
Positive-sequence reactance of the whole
line (secondary value)
Positive-sequence resistance of the whole
line (secondary value)
Zero-sequence reactance of the whole line
(secondary value)
Zero-sequence resistance of the whole line
(secondary value)
Zero-sequence
mutual
reactance
(secondary value)
Zero-sequence mutual resistance of the
whole line (secondary value)

X1L

(0.000~4Unn)/In

0.001

ohm

R1L

(0.000~4Unn)/In

0.001

ohm

X0L

(0.000~4Unn)/In

0.001

ohm

R0L

(0.000~4Unn)/In

0.010

ohm

X0M

(0.000~4Unn)/In

0.001

ohm

R0M

(0.000~4Unn)/In

0.01

ohm

LineLength

0.00~655.35

0.01

km

Total length of the whole line

phi1_Reach

30.00~89.00

0.01

Deg

Phase angle of line positive-sequence


impedance

Real_K0

-4.000~4.000

0.001

10

Imag_K0

-4.000~4.000

0.001

Real

component

of

zero-sequence

compensation coefficient
Imaginary component of zero-sequence
compensation coefficient

3.3 Circuit Breaker Position Supervision


3.3.1 General Application
The status of circuit breaker (CB) position is applied for protection and control functions in this
device, such as, SOTF protection, auto-reclose and VT circuit supervision, etc. The status of CB
position can be applied as input signals for other features configured by user.

3.3.2 Function Description


The signal reflecting CB position is acquired via opto-coupler with settable delay pickup and
dropoff, and forms digital signal used by protection functions. CB position can reflect the status of
each phase by means of phase-segregated inputs.
In order to prevent that wrong status of CB position is input into the device via binary input,
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3 Operation Theory

appropriate monitor method is used to check the rationality of the binary input. When the binary
input of CB open position is detected, the status of CB position will be thought as incorrect and an
alarm [Alm_52b] will be issued if there is current detected in the line.
Together with the status of circuit breaker and the information of external circuit, this function can
be used to supervise control circuit of circuit breaker.
External manual closing binary input (ManCls) is only used for SOTF logic application, the control
of circuit breaker (CB) closing or opening should refer to section 3.29 (Control and Synchrocheck
for Manual Closing).

3.3.3 Function Block Diagram


1.

For phase-segregated circuit breaker


CB Position Supervision
52b_PhA

Alm_52b

52b_PhB
52b_PhC
ManCls

2.

For non-phase segregated circuit breaker


CB Position Supervision
52b

Alm_52b

ManCls

3.

Trip&closing circuit supervision (TCCS)


TCCS
52a

TCCS.Alm

52b
TCCS.Input
ManCls

TCCS will be disabled automatically when it is used for phase-segregated circuit breaker.
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3 Operation Theory

3.3.4 I/O Signals


Table 3.3-1 I/O signals of CB position supervision
No.

Input Signal

Description

52b_PhA

Normally closed contact of A-phase of circuit breaker

52b_PhB

Normally closed contact of B-phase of circuit breaker

52b_PhC

Normally closed contact of C-phase of circuit breaker

ManCls

External manual closing binary input, it is only applied to SOTF logic

52b

Normally closed contact of three-phase of circuit breaker

52a

Normally open contact of three-phase of circuit breaker

TCCS.Input

Control circuit failure (normally closed contact and normally open contact of
three-phase circuit breaker are all de-energized due to DC power loss of control
circuit)
No.

Output Signal

Description

Alm_52b

CB position is abnormal

TCCS.Alm

Control circuit of circuit breaker is abnormal

Note!
The signal [52a] only take effect in the tripping/closing circuit supervision and not affect
any protection function. Only if tripping/closing circuit supervision is configured, this signal
needs to be connected to the device.

3.3.5 Logic
BI

[52b_PhA]

>=1
&
&

BI

[52b_PhB]

>=1
&

BI

[52b_PhC]

>=1

&
>=1

&
BI

[52b]

&
SIG

Ia>I_Line

>=1
&

SIG

10s

>=1

10s

Alm_52b

Ib>I_Line

&
SIG

Ic>I_Line

Figure 3.3-1 Logic diagram of CB position supervision

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>=1

BI

[52a]

BI

[52b]

BI

[TCCS.Input]

>=1
[TCCS.t_DPU]

[TCCS.t_DDO]

TCCS.Alm

Figure 3.3-2 Logic diagram of trip&closing circuit supervision

I_Line is threshold value used to determine whether line is on-load or no-load. Default value
0.06In.

3.3.6 Settings
Table 3.3-2 Internal settings of CB position supervision
No.

Name

Default Value

Unit

Remark

TCCS.t_DPU

0.5

Pickup delay time of control circuit failure alarm

TCCS.t_DDO

0.5

Dropoff delay time of control circuit failure alarm

3.4 Fault Detector (FD)


3.4.1 Application
The device has one DSP module with fault detector DSP and protection DSP for fault detector and
protection calculation respectively. Protection DSP with protection fault detector element is
responsible for calculation of protection elements, and fault detector DSP is responsible to
determine fault appearance on the protected power system. Fault detector in fault detector DSP
picks up to provide positive supply to output relays. The output relays can only operate when both
the fault detector in fault detector DSP and a protection element operate simultaneously.
Otherwise, the output relays would not operate. An alarm message will be issued with blocking
outputs if a protection element operates while the fault detector does not operate.

3.4.2 Fault Detector in Fault Detector DSP


Main part of FD is DPFC current detector element that detects the change of phase-to-phase
power frequency current, and residual current fault detector element that calculates the vector
sum of 3 phase currents as supplementary. They are continuously calculating the analog input
signals.
The FD pickup condition in this device includes:
1.

Pickup condition 1: DPFC current is greater than the setting value

2.

Pickup condition 2: Residual current is greater than the setting value

3.

Pickup condition 3: Phase voltage or phase-to-phase voltage is greater than the voltage
setting of overvoltage protection

4.

Pickup condition 4: Circuit breaker position discrepancy

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Pickup condition 3 and 4 are only available when respective protection elements are enabled.
If any of the above conditions is complied, the FD will operate to activate the output circuit
providing DC power supply to the output relays.
DPFC current fault detector element (pickup condition 1) and residual current fault detector
element (pickup condition 2) are always enabled, and all protection functions are permitted to
operate when they operate.
3.4.2.1 Fault Detector Based on DPFC Current (pickup condition 1)
DPFC phase-to-phase current is obtained by subtracting the phase-to-phase current from that of a
cycle before.

I(k) is the sampling value at a point.


I(k-24) is the value of a sampling point before a cycle, 24 is the sampling points in one cycle.
200
100
0
-100
-200

20

40

60
Original Current

80

100

120

20

40

60
DPFC current

80

100

120

100
50
0
-50
-100

From above figures, it is concluded that DPFC can reflect the sudden change of current at the
initial stage of a fault and has a perfect performance of fault detection.
It is used to determine whether this pickup condition is met according to Equation 3.4-1.
For multi-phase short-circuit fault, the DPFC phase-to-phase current has high sensitivity to ensure
the pickup of protection device. For usual single phase to earth fault, it also has sufficient
sensitivity to pick up except the earth fault with very large fault resistance. Under this condition the
DPFC current is relative small, however, residual current is also used to judge pickup condition
(pickup condition 2).
This element adopts adaptive floating threshold varied with the change of load current
continuously. The change of load current is small and steadily under normal or power swing
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condition, the adaptive floating threshold with the ISet is higher than the change of current under
these conditions and hence maintains the element stability.
The criterion is:
IMAX>1.25ITh+ISet

Equation 3.4-1

Where:
IMAX: The maximum half-wave integration value of phase-to-phase current (=AB, BC, CA)
ISet: The fixed threshold value (i.e. the setting [FD.DPFC.I_Set])
ITh: The floating threshold value
The coefficient, 1.25, is an empirical value which ensures the threshold always higher than the
unbalance output value of the system.
If operating condition is met, DPFC current element will pickup and trigger FD to provide DC power
supply for output relays, the FD operation signal will maintain 7 seconds after DPFC current
element drops off.
3.4.2.2 Fault Detector Based on Residual Current (pickup condition 2)
This pickup condition will be met when 3I0 is greater than the setting [FD.ROC.3I0_Set].
Where:
3I0: residual current calculates from the vector sum of Ia, Ib and Ic
When residual current FD element operates and lasts for longer than 10 seconds, an alarm
[Alm_PersistI0] will be issued.
If operating condition is met, the residual current FD element will pickup and trigger FD to provide
DC power supply for output relay, and pickup signal will be kept for 7 seconds after the residual
current FD element drops off.
3.4.2.3 Fault Detector Based on Overvoltage (pickup condition 3)
Overvoltage fault detector will be automatically effective when overvoltage protection is enabled.
If the logic setting [59Px.Opt_1P/3P] is set as 1 (x=1 or 2), i.e. the protective device adopts
1-out-of-3 mode, when any phase voltage is greater than the setting [59Px.U_Set] (x=1 or 2), the
overvoltage fault detector element will pickup and trigger FD to provide DC power supply for
output relays, the FD operation signal will maintain 7 seconds after overvoltage fault detector
element drops off.
If the logic setting [59Px.Opt_1P/3P] is set as 0 (x=1 or 2), i.e. the protective device adopts
3-out-of-3 mode, when all three phase voltages are greater than the setting [59Px.U_Set] (x=1 or
2), the overvoltage fault detector element will pickup and trigger FD to provide DC power supply
for output relays, the FD operation signal will maintain 7 seconds after overvoltage fault detector
element drops off.

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3.4.2.4 Fault Detector Based on Circuit Breaker Position Discrepancy (pickup condition 4)
When pole discrepancy protection is enabled, i.e. the logic setting [62PD.En] is set as 1, and if
three phases of circuit breaker are not in the same status, pole discrepancy FD element will
operate to provide DC power supply for output relays, and pickup signal will maintain 7 seconds
after pole discrepancy FD element drops out.

3.4.3 Protection Fault Detector in Protection Calculation DSP


The protection device is running either of the two programs: one is Regular program for normal
state, and the other is Fault calculation program after protection fault detector picks up.
Under the normal state, the protection device will perform the following tasks:
1.

Calculate analog quantity

2.

Read binary input

3.

Hardware self-check

4.

Circuit breaker position supervision

5.

Analog quantity input supervision

6.

Channel supervision

Once the protection fault detector element in protection calculation DSP picks up, the protection
device will switch to fault calculation program, for example the calculation of distance protection,
and to determine logic. If the fault is within the protected zone, the protection device will send
tripping command.
The protection program flow chart is shown as Figure 3.4-1.

Main program

Sampling program

No

Regular program

Yes

Pickup?

Fault calculation program

Figure 3.4-1 Flow chart of protection program

The protection FD pickup conditions are the same as the FD in fault detector DSP as shown below.
The operation criteria for the conditions are also the same as that in fault detector DSP. Please
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refer to section 3.4.2 for details.


1.

Pickup condition 1: DPFC current is greater than the setting value

2.

Pickup condition 2: Residual current is greater than the setting value

3.

Pickup condition 3: Phase voltage or phase-to-phase voltage is greater than the setting value

4.

Pickup condition 4: Circuit breaker position discrepancy

When any pickup condition mentioned above is met, the protection device will go to fault
calculation state.
Pickup condition 3 and 4 are not common fault detector elements, only used for respective
protection element. Please refer to section 3.15.1 and section 3.20 for details.

3.4.4 Function Block Diagram


FD
FD.Pkp
FD.DPFC.Pkp
FD.ROC.Pkp

3.4.5 I/O Signals


Table 3.4-1 I/O signals of fault detector
No.

Output Signal

Description

FD.Pkp

The device picks up

FD.DPFC.Pkp

DPFC current fault detector element operates.

FD.ROC.Pkp

Residual current fault detector element operates.

3.4.6 Logic
SIG

Ia

SIG

Ib

SIG

Ic

Calculate DPFC phase-to-phase current:

Iab=(Ia-Ib)
Ibc=(Ib-Ic)
Ica=(Ic-Ia)

Iab>[FD.DPFC.I_Set]

>=1
Ibc>[FD.DPFC.I_Set]
Ica>[FD.DPFC.I_Set]

FD.DPFC.Pkp

>=1
0s

7s

FD.Pkp

Calculate residual current:

3I0=Ia+Ib+Ic

3I0>[FD.ROC.3I0_Set]

FD.ROC.Pkp

Figure 3.4-2 Logic diagram of fault detector

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3.4.7 Settings
Table 3.4-2 Settings of fault detector
No.

Name

Range

Step

Unit

FD.DPFC.I_Set

(0.050~30.000)In

0.001

FD.ROC.3I0_Set

(0.050~30.000)In

0.001

Remark
Current setting of DPFC current fault
detector element
Current setting of residual current fault
detector element

3.5 Auxiliary Element


3.5.1 General Application
Auxiliary element (AuxE) is mainly used to program logics to meet users applications or further
improve operating reliability of protection elements. Reliability of protective elements (such as
distance element or current differential element) is assured, auxiliary element is usually not
required to configure. Auxiliary elements including current change auxiliary element (AuxE.OCD),
residual current auxiliary element (AuxE.ROC), phase current auxiliary element (AuxE.OC),
voltage change auxiliary element (AuxE.UVD), phase under voltage auxiliary element (AuxE.UVG),
phase-to-phase under voltage auxiliary element (AuxE.UVS) and residual voltage auxiliary
element (AuxE.ROV), and they can be enabled or disabled by corresponding logic setting or
binary inputs. Users can configure them according to applications via PCS-Explorer software.

3.5.2 Function Description


1.

Current change auxiliary element AuxE.OCD

It shares DPFC current element of DPFC fault detector. If DPFC fault detector operates
(FD.DPFC.Pkp=1) and current change auxiliary element is enabled, current change auxiliary
element operates.
2.

Residual current auxiliary element AuxE.ROC

There are 3 stages for residual current auxiliary element (AuxE.ROC1, AuxE.ROC2 and
AuxE.ROC3). Each residual current auxiliary element will operate instantly if calculated residual
current amplitude is larger than corresponding current setting
The criteria are:
AuxE.ROC1: 3I0>[AuxE.ROC1.3I0_Set]
AuxE.ROC2: 3I0>[AuxE.ROC2.3I0_Set]
AuxE.ROC3: 3I0>[AuxE.ROC3.3I0_Set]
Where:
3I0: The calculated residual current
3.

Phase current auxiliary element AuxE.OC

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There are 3 stages for phase current auxiliary element (AuxE.OC1, AuxE.OC2 and AuxE.OC3).
Each phase current auxiliary element will operate instantly if phase current amplitude is larger than
corresponding current setting.
The criteria are:
AuxE.OC1: IMAX>[AuxE.OC1.I_Set]
AuxE.OC2: IMAX>[AuxE.OC2.I_Set]
AuxE.OC3: IMAX>[AuxE.OC3.I_Set]
Where:
IMAX: The maximum phase current among three phases
4.

Voltage change auxiliary element AuxE.UVD

AuxE.UVD is based on phase-to-ground voltage change measured in all three phases.


The criterion is:
UMAX>[AuxE.UVD.U_Set]
Where:
UMAX: The maximum phase-to-ground voltage change among three phases
5.

Phase under voltage auxiliary element AuxE.UVG

AuxE.UVG will operate instantly if any phase-to-ground voltage is lower than corresponding
voltage setting.
The criterion is:
UMIN<[ AuxE.UVG.U_Set]
Where:
UMIN: The minimum value among three phase-to-ground voltages
6.

Phase-to-phase under voltage auxiliary element AuxE.UVS

AuxE.UVS will operate instantly if any phase-to-phase voltage is lower than corresponding voltage
setting.
The criterion is:
UMIN<[ AuxE.UVS.U_Set]
Where:
UMIN: The minimum value among three phase-to-phase voltages
7.

Residual voltage auxiliary element AuxE.ROV

AuxE.ROV will operate instantly if calculated residual voltage is larger than corresponding voltage

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setting.
The criterion is:
3U0>[ AuxE.ROV.3U0_Set]
Where:
3U0: The calculated residual voltage

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3.5.3 Function Block Diagram


AuxE
AuxE.OCD.En

AuxE.St

AuxE.OCD.Blk

AuxE.OCD.St_Ext

AuxE.ROCx.En

AuxE.OCD.On

AuxE.ROCx.Blk

AuxE.ROCx.St

AuxE.OCx.En

AuxE.ROCx.On

AuxE.OCx.Blk

AuxE.OCx.St

AuxE.UVD.En

AuxE.OCx.StA

AuxE.UVD.Blk

AuxE.OCx.StB

AuxE.UVG.En

AuxE.OCx.StC

AuxE.UVG.Blk

AuxE.OCx.On

AuxE.UVS.En

AuxE.UVD.St

AuxE.UVS.Blk

AuxE.UVD.St_Ext

AuxE.ROV.En

AuxE.UVD.On

AuxE.ROV.Blk

AuxE.UVG.St
AuxE.UVG.StA
AuxE.UVG.StB
AuxE.UVG.StC
AuxE.UVG.On
AuxE.UVS.St
AuxE.UVS.StAB
AuxE.UVS.StBC
AuxE.UVS.StCA
AuxE.UVS.On
AuxE.ROV.St
AuxE.ROV.On

Where:
x can be 1, 2 or 3

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3 Operation Theory

3.5.4 I/O Signals


Table 3.5-1 I/O signals of auxiliary element
No.

Input Signal

AuxE.OCD.En

AuxE.OCD.Blk

AuxE.ROC1.En

AuxE.ROC1.Blk

AuxE.ROC2.En

AuxE.ROC2.Blk

AuxE.ROC3.En

AuxE.ROC3.Blk

AuxE.OC1.En

10

AuxE.OC1.Blk

11

AuxE.OC2.En

12

AuxE.OC2.Blk

13

AuxE.OC3.En

14

AuxE.OC3.Blk

15

AuxE.UVD.En

16

AuxE.UVD.Blk

17

AuxE.UVG.En

18

AuxE.UVG.Blk

19

AuxE.UVS.En

20

AuxE.UVS.Blk

Description
Current change auxiliary element enabling input, it is triggered from binary input or
programmable logic etc.
Current change auxiliary element blocking input, it is triggered from binary input or
programmable logic etc.
Stage 1 of residual current auxiliary element enabling input, it is triggered from
binary input or programmable logic etc.
Stage 1 of residual current auxiliary element blocking input, it is triggered from
binary input or programmable logic etc.
Stage 2 of residual current auxiliary element enabling input, it is triggered from
binary input or programmable logic etc.
Stage 2 of residual current auxiliary element blocking input, it is triggered from
binary input or programmable logic etc.
Stage 3 of residual current auxiliary element enabling input, it is triggered from
binary input or programmable logic etc.
Stage 3 of residual current auxiliary element blocking input, it is triggered from
binary input or programmable logic etc.
Stage 1 of phase current auxiliary element enabling input, it is triggered from
binary input or programmable logic etc.
Stage 1 of phase current auxiliary element blocking input, it is triggered from
binary input or programmable logic etc.
Stage 2 of phase current auxiliary element enabling input, it is triggered from
binary input or programmable logic etc.
Stage 2 of phase current auxiliary element blocking input, it is triggered from
binary input or programmable logic etc.
Stage 3 of phase current auxiliary element enabling input, it is triggered from
binary input or programmable logic etc.
Stage 3 of phase current auxiliary element blocking input, it is triggered from
binary input or programmable logic etc.
Voltage change auxiliary element enabling input, it is triggered from binary input or
programmable logic etc.
Voltage change auxiliary element blocking input, it is triggered from binary input or
programmable logic etc.
Phase-to-ground under voltage auxiliary element enabling input, it is triggered
from binary input or programmable logic etc.
Phase-to-ground under voltage auxiliary element blocking input, it is triggered
from binary input or programmable logic etc.
Phase-to-phase under voltage auxiliary element enabling input, it is triggered from
binary input or programmable logic etc.
Phase-to-phase under voltage auxiliary element blocking input, it is triggered from

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binary input or programmable logic etc.
21

AuxE.ROV.En

22

AuxE.ROV.Blk

No.

Residual voltage auxiliary element enabling input, it is triggered from binary input
or programmable logic etc.
Residual voltage auxiliary element blocking input, it is triggered from binary input
or programmable logic etc.

Output Signal

Description

AuxE.St

Any auxiliary element of the device operates

AuxE.OCD.St_Ext

Current change auxiliary element operates (7s delayed drop off).

AuxE.OCD.On

Current change auxiliary element is enabled

AuxE.ROC1.St

Stage 1 of residual current auxiliary element operates.

AuxE.ROC1.On

Stage 1 of residual current auxiliary element is enabled

AuxE.ROC2.St

Stage 2 of residual current auxiliary element operates.

AuxE.ROC2.On

Stage 2 of residual current auxiliary element is enabled

AuxE.ROC3.St

Stage 3 of residual current auxiliary element operates.

AuxE.ROC3.On

Stage 3 of residual current auxiliary element is enabled

10

AuxE.OC1.St

Stage 1 of phase current auxiliary element operates.

11

AuxE.OC1.StA

Stage 1 of phase current auxiliary element operates (phase A).

12

AuxE.OC1.StB

Stage 1 of phase current auxiliary element operates (phase B).

13

AuxE.OC1.StC

Stage 1 of phase current auxiliary element operates (phase C).

14

AuxE.OC1.On

Stage 1 of phase current auxiliary element is enabled

15

AuxE.OC2.St

Stage 2 of phase current auxiliary element operates.

16

AuxE.OC2.StA

Stage 2 of phase current auxiliary element operates (phase A).

17

AuxE.OC2.StB

Stage 2 of phase current auxiliary element operates (phase B).

18

AuxE.OC2.StC

Stage 2 of phase current auxiliary element operates (phase C).

19

AuxE.OC2.On

Stage 2 of phase current auxiliary element is enabled

20

AuxE.OC3.St

Stage 3 of phase current auxiliary element operates.

21

AuxE.OC3.StA

Stage 1 of phase current auxiliary element operates (phase A).

22

AuxE.OC3.StB

Stage 1 of phase current auxiliary element operates (phase B).

23

AuxE.OC3.StC

Stage 1 of phase current auxiliary element operates (phase C).

24

AuxE.OC3.On

Stage 3 of phase current auxiliary element is enabled

25

AuxE.UVD.St

Voltage change auxiliary element operates.

26

AuxE.UVD.St_Ext

Voltage change auxiliary element operates (7s delayed drop off).

27

AuxE.UVD.On

Voltage change auxiliary element is enabled

28

AuxE.UVG.St

Phase-to-ground under voltage auxiliary element operates.

29

AuxE.UVG.StA

Phase-to-ground under voltage auxiliary element operates (phase A).

30

AuxE.UVG.StB

Phase-to-ground under voltage auxiliary element operates (phase B).

31

AuxE.UVG.StC

Phase-to-ground under voltage auxiliary element operates (phase C).

32

AuxE.UVG.On

Phase-to-ground under voltage auxiliary element is enabled

33

AuxE.UVS.St

Phase-to-phase under voltage auxiliary element operates.

34

AuxE.UVS.StAB

Phase-to-phase under voltage auxiliary element operates (phase AB).

35

AuxE.UVS.StBC

Phase-to-phase under voltage auxiliary element operates (phase BC).

36

AuxE.UVS.StCA

Phase-to-phase under voltage auxiliary element operates (phase CA).

37

AuxE.UVS.On

Phase-to-phase under voltage auxiliary element is enabled

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38

AuxE.ROV.St

Residual voltage auxiliary element operates.

39

AuxE.ROV.On

Residual voltage auxiliary element is enabled

3.5.5 Logic
SIG

FD.DPFC.Pkp

SIG

AuxE.OCD.En

SIG

AuxE.OCD.Blk

En

AuxE.OCD.En

SIG

Ia

SIG

Ib

SIG

Ic

SIG

&
&

0s

[AuxE.OCD.t_DDO]

AuxE.OCD.St_Ext

AuxE.OCD.On

Calculate residual
current:
3I0=Ia+Ib+Ic
3I0>[AuxE.ROC1.3I0_Set]

AuxE.ROC1.En

&
AuxE.ROC1.St

&
SIG

AuxE.ROC1.Blk

En

AuxE.ROC1.En

SIG

AuxE.ROC2.En

AuxE.ROC1.On
3I0>[AuxE.ROC2.3I0_Set]

&
AuxE.ROC2.St

&
SIG

AuxE.ROC2.Blk

En

AuxE.ROC2.En

SIG

AuxE.ROC3.En

AuxE.ROC2.On
3I0>[AuxE.ROC3.3I0_Set]

SIG

AuxE.ROC3.Blk

En

AuxE.ROC3.En

&
AuxE.ROC3.St

&

AuxE.ROC3.On

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SIG

Ia

Ia>[AuxE.OC1.I_Set]

&
AuxE.OC1.StA

SIG

Ib

Ib>[AuxE.OC1.I_Set]

&
AuxE.OC1.StB

SIG

Ic

Ic>[AuxE.OC1.I_Set]

&
AuxE.OC1.StC

>=1
SIG

&

AuxE.OC1.En

AuxE.OC1.St

&
SIG

AuxE.OC1.Blk

En

AuxE.OC1.En

SIG

Ia

AuxE.OC1.On
Ia>[AuxE.OC2.I_Set]

&
AuxE.OC2.StA

SIG

Ib

Ib>[AuxE.OC2.I_Set]

&
AuxE.OC2.StB

SIG

Ic

Ic>[AuxE.OC2.I_Set]

&
AuxE.OC2.StC

>=1
SIG

&

AuxE.OC2.En

AuxE.OC2.St

&
SIG

AuxE.OC2.Blk

En

AuxE.OC2.En

SIG

Ia

AuxE.OC2.On
Ia>[AuxE.OC3.I_Set]

&
AuxE.OC3.StA

SIG

Ib

Ib>[AuxE.OC3.I_Set]

&
AuxE.OC3.StB

SIG

Ic

Ic>[AuxE.OC3.I_Set]

&
AuxE.OC3.StC

>=1
SIG

&

AuxE.OC3.En

AuxE.OC3.St

&
SIG

AuxE.OC3.Blk

En

AuxE.OC4.En

AuxE.OC3.On

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SIG

Ua

SIG

Ub

SIG

Uc

Ua>[AuxE.UVD.U_Set]

Calculate DPFC phase


voltage
Ua=(Ua-Ufa)
Ub=(Ub-Ufb)
Uc=(Uc-Ufc)

>=1
Ub>[AuxE.UVD.U_Set]

&
AuxE.UVD.St

Uc>[AuxE.UVD.U_Set]
0s

SIG

[AuxE.UVD.t_Ext]

AuxE.UVD.En

AuxE.UVD.St_Ext

&
SIG

AuxE.UVD.Blk

En

AuxE.UVD.En

SET

AuxE.UVD.On

UA<[AuxE.UVG.U_Set]

&
AuxE.UVG.StA

SET

UB<[AuxE.UVG.U_Set]

&
AuxE.UVG.StB

SET

UC<[AuxE.UVG.U_Set]

&
AuxE.UVG.StC
>=1

SIG

&

AuxE.UVG.En

AuxE.UVG.St

&
SIG

AuxE.UVG.Blk

En

AuxE.UVG.En
AuxE.UVG.On

SET

UAB<[AuxE.UVS.U_Set]

&
AuxE.UVS.StAB

SET

UBC<[AuxE.UVS.U_Set]

&
AuxE.UVS.StBC

SET

UCA<[AuxE.UVS.U_Set]

&
AuxE.UVS.StCA
>=1

SIG

&

AuxE.UVS.En

AuxE.UVS.St

&
SIG

AuxE.UVS.Blk

En

AuxE.UVS.En
AuxE.UVS.On

SIG

Ua

SIG

Ub

SIG

Uc

SIG

AuxE.ROV.En

SIG

AuxE.ROV.Blk

En

AuxE.ROV.En

3U0>[AuxE.ROV.3U0_Set]

&
AuxE.ROV.St

Calculate residual voltage


3U0=Ua+Ub+Uc

&
AuxE.ROV.On

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SIG

AuxE.OCD.St_Ext

SIG

AuxE.ROC1.St

SIG

AuxE.ROC2.St

SIG

AuxE.ROC3.St

SIG

AuxE.OC1.St

>=1

>=1
AuxE.St

>=1
SIG

AuxE.OC2.St

SIG

AuxE.OC3.St

SIG

AuxE.UVD.St_Ext

SIG

AuxE.UVG.St

SIG

AuxE.UVS.St

SIG

AuxE.ROV.St

>=1
>=1

>=1

Figure 3.5-1 Logic diagram of auxiliary element

3.5.6 Settings
Table 3.5-2 Settings of auxiliary element
No.
1

Name
AuxE.OCD.t_DDO

Range
0.000~10.000

Step
0.001

Unit
s

Remark
Extended time delay of current change
auxiliary element
Enabling/disabling current change

AuxE.OCD.En

auxiliary element

0 or 1

0: disable
1: enable

AuxE.ROC1.3I0_Set

(0.050~30.000)In

0.001

Current setting of stage 1 residual


current auxiliary element
Enabling/disabling stage 1 residual

AuxE.ROC1.En

current auxiliary element

0 or 1

0: disable
1: enable

AuxE.ROC2.3I0_Set

(0.050~30.000)In

0.001

Current setting of stage 2 residual


current auxiliary element
Enabling/disabling stage 2 residual

AuxE.ROC2.En

current auxiliary element

0 or 1

0: disable
1: enable

AuxE.ROC3.3I0_Set

(0.050~30.000)In

0.001

Current setting of stage 3 residual


current auxiliary element
Enabling/disabling stage 3 residual

AuxE.ROC3.En

current auxiliary element

0 or 1

0: disable
1: enable

AuxE.OC1.I_Set

(0.050~30.000)In

Current setting of stage 1 phase current


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auxiliary element
Enabling/disabling stage 1 phase
10

AuxE.OC1.En

current auxiliary element

0 or 1

0: disable
1: enable

11

AuxE.OC2.I_Set

Current setting of stage 2 phase current

(0.050~30.000)In

auxiliary element
Enabling/disabling stage 2 phase

12

AuxE.OC2.En

current auxiliary element

0 or 1

0: disable
1: enable

13

AuxE.OC3.I_Set

Current setting of stage 3 phase current

(0.050~30.000)In

auxiliary element
Enabling/disabling stage 3 phase

14

AuxE.OC3.En

current auxiliary element

0 or 1

0: disable
1: enable

15

AuxE.UVD.U_Set

0~Un

0.001

16

AuxE.UVD.t_Ext

0.000~10.000

0.001

Voltage setting for voltage change


auxiliary element
Extended time delay of voltage change
auxiliary element
Enabling/disabling voltage change

17

AuxE.UVD.En

auxiliary element

0 or 1

0: disable
1: enable

18

AuxE.UVG.U_Set

0~Un

0.001

Voltage setting for phase-to-ground


under voltage auxiliary element
Enabling/disabling phase-to-ground

19

AuxE.UVG.En

under voltage auxiliary element

0 or 1

0: disable
1: enable

20

AuxE.UVS.U_Set

0~Unn

0.001

Voltage setting for phase-to-phase


under voltage auxiliary element
Enabling/disabling phase-to-phase

21

AuxE.UVS.En

under voltage auxiliary element

0 or 1

0: disable
1: enable

22

AuxE.ROV.3U0_Set

0~Un

0.001

Voltage setting for residual voltage


auxiliary element
Enabling/disabling residual voltage

23

AuxE.ROV.En

auxiliary element

0 or 1

0: disable
1: enable

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3.6 Distance Protection


3.6.1 General Application
When a fault happens on a power system, distance protection will trip circuit breaker to isolate the
fault from power system with its specific time delay if the fault is within the protected zone of
distance protection.

3.6.2 Function Description


The device comprises 3 forward zones, 1 reverse zone and 1 pilot zone. For each independent
distance element zone, full scheme design provides continuous measurement of impedance
separately in three independent phase-to-phase measuring loops as well as in three independent
phase-to-ground measuring loops. Selection of zone characteristic between mho and quadrilateral
is available. Distance protection includes:
1.

DPFC distance protection


It is independent fast protection providing extremely fast speed to clear close up fault
especially on long line and thus improves system stability.

2.

Mho phase-to-phase distance protection


Zone1~3: forward direction
Zone 4: reverse direction including origin

3.

Mho phase-to-ground distance protection


Zone1~3: forward direction
Zone 4: reverse direction including origin

4.

Quadrilateral phase-to-phase distance protection


Zone1~3: forward direction
Zone 4: reverse direction

5.

Quadrilateral phase-to-ground distance protection


Zone1~3: forward direction
Zone 4: reverse direction

6.

Pilot distance protection


The pilot zone is for PUTT, POTT and blocking scheme. The forward direction element is for
sending signal for POTT and tripping upon receiving permissive signal for both PUTT and
POTT scheme. The forward direction element for blocking scheme is used to stop sending
blocking signal. The reverse direction element is only for POTT scheme with weak infeed
condition.

7.

Load encroachment

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It is used to prevent all distance elements from undesired trip due to load encroachment
under heavy load condition especially for long lines.
8.

Power swing detection (PSD)

9.

Power swing blocking releasing (PSBR)


For power swing with external fault, distance protection is always blocked, but for power
swing with internal fault, PSBR will operate to release the blocking for distance protection.

10. SOTF distance protection


For manual closing or automatic closing on to a fault, zone 2 or 3 of distance protection will
accelerate to trip.
When VT circuit fails, VT circuit supervision logic will output a blocking signal to block all distance
protection except DPFC distance protection. The operating threshold will be increased to 1.5UN to
enhance stability.
Distance protection can select line VT or bus VT for protection algorithm by a setting
[VTS.En_LineVT]. When no VT is provided, logic setting [VTS.En_Out_VT] should be set as 1,
all distance protection will be blocked automatically. The coordination among zones of distance
protection is shown in the following figure.

Z4

EM

EN

Z1DZ
Z2

Z3

Figure 3.6-1 Protected reach of distance protection for each zone

Where:
Z1: forward direction zone 1
Z2: forward direction zone 2
Z3: forward direction zone 3
Z4: reverse direction zone 4
DZ: DPFC distance protection
The choice of impedance reach is as follow. (only for reference)
The zone 1 impedance reach setting should be set to cover as much the protected line as possible
but not to respond faults beyond the protected line. The accuracy of the relay distance elements is
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2.5% in general applications, however, the error could be much larger due to errors of current
transformer, voltage transformer and inaccuracies of line parameter from which the relay settings
are calculated. It is recommended the zone 1 reach is set to 80%~85% of the protected line in
consideration the aforesaid errors and safety margin to prevent instantaneously tripping for faults
on adjacent lines. The remaining 20% of the protected line relies on the zone 2 distance elements.
With the pilot scheme distance protection, fast fault clearance could also be achieved for end zone
faults at both ends of the protected line.
The general rule for zone 2 impedance reach setting is set to cover the protected line plus 20% of
the adjacent line. However, the coverage of adjacent line should be extended in the presence of
additional infeed at the remote end of the protected line to ensure 20% coverage of adjacent line.
This assures the fast operation of zone 2 distance element for faults at the remote end of the
protected line since the fault is well within zone 2 reach. This is important for pilot protection as the
impedance reach of pilot zone is the same as that of zone 2 distance element. In a parallel line
situation, a fault cleared sequentially on a line may cause current reversal in the healthy line. If the
pilot zone settings are set to cover 50% of adjacent line and the POTT or Blocking scheme is used,
the current reversal in the healthy line could cause relay mal-operation. Therefore, current reversal
logic is required and explained in section 3.8.2.6.
The Z3 distance element acts as backup protection for protected line and adjacent line but not to
over the zone 2 setting of adjacent line. The zone 3 impedance reach is generally 2 times zone 1
reach, i.e. 160% of protected line.
For different system impedance ratio (SIR), the operating time of distance protection for different
fault location are shown as the following figures.

35
30
25
Operating Time (ms)

20
15
10
5
0
0

10%

20%

30%

40%

50%

60%

70%

80%

90%

100%

Fault Location (% of relay setting)

Figure 3.6-2 Operating time of single-phase fault (50Hz, SIR=1)

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30
25
Operating Time (ms)

20
15
10
5
0
0%

10%

20%

30%

40%

50%

60%

70%

80%

90%

100%

Fault Location (% of relay setting)

Figure 3.6-3 Operating time of single-phase fault (60Hz, SIR=1)

35
30
25
Operating Time (ms)

20
15
10
5
0
0

10%

20%

30%

40%

50%

60%

70%

80%

90%

100%

Fault Location (% of relay setting)

Figure 3.6-4 Operating time of two-phase fault (50Hz, SIR=1)

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30
25
Operating Time (ms)

20
15
10
5
0
0%

10%

20%

30%

40%

50%

60%

70%

80%

90%

100%

Fault Location (% of relay setting)

Figure 3.6-5 Operating time of two-phase fault (60Hz, SIR=1)

35
30
25
Operating Time (ms)

20
15
10
5
0
0

10%

20%

30%

40%

50%

60%

70%

80%

90%

100%

Fault Location (% of relay setting)

Figure 3.6-6 Operating time of three-phase fault (50Hz, SIR=1)

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30
25
Operating Time (ms)

20
15
10
5
0
0%

10%

20%

30%

40%

50%

60%

70%

80%

90%

100%

Fault Location (% of relay setting)

Figure 3.6-7 Operating time of three-phase fault (60Hz, SIR=1)

33
32.5
32
Operating Time (ms)

31.5

31
30.5

30
29.5

29
0%

10%

20%

30%

40%

50%

60%

70%

80%

90% 100%

Fault Location (% of relay setting)

Figure 3.6-8 Operating time of single-phase fault (50Hz, SIR=30)

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27.5
27
Operating Time (ms)

26.5
26
25.5
25
24.5
24
0%

10%

20%

30%

40%

50%

60%

70%

80%

90% 100%

Fault Location (% of relay setting)

Figure 3.6-9 Operating time of single-phase fault (60Hz, SIR=30)

45
40
35
Operating Time (ms)

30
25
20
15
10
5
0
0

10%

20%

30%

40%

50%

60%

70%

80%

90%

100%

Fault Location (% of relay setting)

Figure 3.6-10 Operating time of two-phase fault (50Hz, SIR=30)

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35
30
Operating Time (ms)

25
20
15
10
5
0
0%

10%

20%

30%

40%

50%

60%

70%

80%

90%

100%

Fault Location (% of relay setting)

Figure 3.6-11 Operating time of two-phase fault (60Hz, SIR=30)

33
32
Operating Time (ms)

31
30
29
28
27
0

10%

20%

30%

40%

50%

60%

70%

80%

90%

100%

Fault Location (% of relay setting)

Figure 3.6-12 Operating time of three-phase fault (50Hz, SIR=30)

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27.5
27
Operating Time (ms)

26.5
26

25.5
25

24.5
24

23.5
0%

10%

20%

30%

40%

50%

60%

70%

80%

90% 100%

Fault Location (% of relay setting)

Figure 3.6-13 Operating time of three-phase fault (60Hz, SIR=30)

3.6.3 DPFC Distance Protection


The power system is normally treated as a balanced symmetrical three-phase network. When a
fault occurs in the power system, by applying the principle of superposition, the load current and
voltage can be calculated in the system prior to the fault and the pure fault component can be
calculated by fault current or voltage subtracted by pre-fault load current or voltage. DPFC
distance protection concerns change of current and voltage at power frequency, therefore, DPFC
distance protection is not influenced by load current.
As an independent fast protection, DPFC distance protection is mainly used to clear close up fault
of long line quickly, its protected range can set as 80%~85% of the whole line.
Since DPFC distance protection only reflects fault component and is not influenced by current
change due to load variation and power swing, power swing blocking (PSB) is this not required.
Moreover, there is no transient overreaching due to infeed current from the remote power supply
because it is not influenced by load current.
DPFC distance protection may not overreach, and its protected zone will be inverse-proportion
reduced with system impedance behind it, i.e. the protected zone will be less than setting if the
system impedance is greater. The protected zone will be close to setting value if the system
impedance is smaller. Therefore, DPFC distance protection is usually used for long transmission
line with large power source and it is recommended to disable DPFC distance protection for short
line or the line with weak power source.

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3.6.3.1 Impedance Characteristic


ZZD
M

EM

EN

I
ZS

ZK

jX

Zzd
Zk

Zs+Zk

-Zs

Figure 3.6-14 Operation characteristic for forward fault

Where:
ZZD: the setting of DPFC distance protection
ZS: total impedance between local system and device location
ZK: measurement impedance
: positive-sequence sensitive angle, i.e. [phi1_Reach]
Figure 3.6-14 shows the operation characteristic of DPFC distance protection on R-X plane when
a fault occurs in forward direction, which is the circle with the Zs as the center and theZs+Zzd as
the radius. When measured impedance Zk is in the circle, DPFC distance protection will operate.
DPFC distance protection has a larger capability of enduring fault resistance than distance
protection using positive-sequence as polarized voltage.

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ZZD
F

EM

EN

I
ZK
ZS

jX

Z's

Zzd

-Zk

Figure 3.6-15 Operation characteristic for reverse fault

Z'Stotal impedance between remote system and protective device location


Figure 3.6-15 shows the operation characteristic of the DPFC distance element on R-X plane
when a fault occurs in reverse direction, which is the circle with the ZS as the center and
theZS-Zzdas the radius. The region of operation is in the quadrant 1 but the measured
impedance -Zk is always in the quadrant 3, the DPFC distance protection will not operate.
The DPFC distance protection can be enabled or disabled by logic setting and binary input.
3.6.3.2 Function Block Diagram

21D
21D.En

21D.Op

21D.Blk

21D.On

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3.6.3.3 I/O Signals


Table 3.6-1 I/O signals of DPFC distance protection
No.

Input Signal

21D.En

21D.Blk

No.

Description
DPFC distance protection enabling input, it is triggered from binary input or
programmable logic etc.
DPFC distance protection blocking input, it is triggered from binary input or
programmable logic etc.

Output Signal

Description

21D.Op

DPFC distance protection operates.

21D.On

DPFC distance protection is enabled.

3.6.3.4 Logic
EN

[21D.En]

21D.On

&

SIG

21D.En

SIG

21D.Blk

SIG

FD.Pkp

EN

[VTS.En_Out_VT]

SIG

Manual closing signal

SIG

3-pole reclosing signal

SET

[21D.Z_Set]<0.05/In

SET

Z<[21D.Z_Set]

SIG

UP<0.85Un

SET

Z<[21D.Z_Set]

SIG

UPP<0.85Unn

SIG

PD signal

&

>=1

&
>=1

&
21D.Op

&
&

Figure 3.6-16 Logic diagram of DPFC distance protection

Note!
PD signal only blocks DPFC distance element of corresponding phase (i.e. broken phase),
and healthy phases (operation phases) are not affected.
3.6.3.5 Settings
Table 3.6-2 Settings of DPFC distance protection
No.
1

Name
21D.Z_Set

Range

Step

Unit

Remark

(0.000~4Unn)/In

0.001

ohm

Impedance setting of DPFC distance

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protection
Enabling/disabling
2

21D.En

DPFC

distance

protection

0 or 1

0: disable
1: enable

3.6.4 Load Encroachment


3.6.4.1 Impedance Characteristic
When distance protection is used to protect long, heavily loaded lines, the risk of encroachment of
the load impedance into the tripping characteristic of the distance protection may exist. A load
trapezoid characteristic for all zones is used to exclude the risk of unwanted fault detection by the
distance protection during heavy load flow.
As shown below, if the measured impedance into the load area, distance elements need to be
blocked.

jX

Load

Load

Load Area

Load Area

R
RLoad

RLoad

Figure 3.6-17 Distance element with load trapezoid

Two settings are equipped to exclude the encroachment of the load impedance:
RLoad: the minimum load resistance
Load: the load area angle
These values are common for all zones.

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3.6.4.2 Function Block Diagram

LoadEnch
LoadEnch.En

LoadEnch.St

LoadEnch.Blk

LoadEnch.On

3.6.4.3 I/O Signals


Table 3.6-3 I/O signals of load encroachment
No.

Input Signal

LoadEnch.En

LoadEnch.Blk

No.

Description
Load trapezoid characteristic enabling input, it is triggered from binary input or
programmable logic etc.
Load trapezoid characteristic blocking input, it is triggered from binary input or
programmable logic etc.

Output Signal

Description
Measured impedance into the load area.
If load trapezoid characteristic is enabled and measured impedance into the load

LoadEnch.St

are, LoadEnch.St=1,
If measured impedance is out of the load are or load trapezoid characteristic is
disabled, LoadEnch.St=0

LoadEnch.On

Load trapezoid characteristic is enabled.

3.6.4.4 Settings
Table 3.6-4 Settings of load encroachment
No.

Name

Range

Step

Unit

Remark
Angle

setting

characteristic,
1

LoadEnch.phi_Blinder

0~45

Deg

of
it

load
should

trapezoid
be

set

according to the maximum load area


angle

(Load_Max),

Load_Max+5 is

recommended.
Resistance setting of load trapezoid

LoadEnch.R_Blinder

(0.05~200)/In

0.01

ohm

characteristic,

it

according

the

to

should

be

minimum

set
load

resistance, 70%~90% minimum load


resistance is recommended.
Enabling/disabling
3

LoadEnch.En

load

trapezoid

characteristic

0,1

0: disable
1: enable

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3.6.5 Mho Distance Protection


3.6.5.1 Impedance Characteristic
1.

Zone 1, 2 and 3 of phase-to-ground distance element


ZZD
M

EM

IN

EN

I
ZS

ZK

jX

ZZD

ZK

-2ZS/3

Figure 3.6-18 Phase-to-ground operation characteristic for forward fault

Where:
ZZD: the setting of distance protection
ZS: total impedance between local system and protective device location
ZK: measurement impedance
: positive-sequence sensitive angle, i.e. [phi1_Reach]
Phase-to-neutral positive sequence voltage is used as polarized signal for phase-to-ground
distance protection.
For zone 1 and zone 2:
Operation voltage:

Polarized voltage:
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In short line, phase shift 1 could be applied to the polarized voltage to improve the performance
against high resistance fault. The device provides an angle-shift setting, [ZG.phi_Shift], to set
value of 1 among 0, 15and 30. Their impedance shift characteristics towards quadrant 1 are
respectively shown as the impedance circle A, B and C in Figure 3.6-23.
For zone 3:
Operation voltage:

Polarized voltage:
UP uses phase positive-sequence voltage as polarized voltage. For earth fault, positive-sequence
voltage is mainly formed from healthy phases, basically retaining the phase of the
positive-sequence voltage before fault.
Phase comparison equation is:

The operation characteristic is shown in Figure 3.6-18. Operation characteristic of ZK on R-X plane
is a circle with line connecting ends of ZZD and -2ZS/3 as the diameter. The origin is enclosed in the
circle.
2.

Zone 1, 2 and 3 of phase-to-phase distance element


jX

ZZD

ZK

-ZS/2

Figure 3.6-19 Phase-to-phase operation characteristic for forward fault

Phase-to-phase positive sequence voltage is used as polarized signal for phase-to-phase


distance protection.
For zone 1 and zone 2:
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Operation voltage:

Polarized voltage:
Phase shift 2 could be applied to polarized voltage of zones 1 and 2 just like 1 in
phase-to-ground distance element. It is also used for improving performance against high
resistance fault in short line. The device provides an angle-shift setting, [21M.ZP.phi_Shift], to set
value of 2 among 0, 15and 30. Their impedance shift characteristics towards quadrant 1 are
respectively shown as the impedance circle A, B and C in Figure 3.6-23.
For zone 3:
Operation voltage:

Polarized voltage:
Phase-to-phase positive-sequence voltage is applied as the polarized voltage of this element.
Phase comparison equation is:

The operation characteristic of phase-to-phase distance element is shown in Figure 3.6-19.


Operation characteristic of ZK on R-X plane is a circle with line connecting ends of ZZD and -ZS/2 as
the diameter. The origin is enclosed in the circle.
Figure 3.6-20 shows operation characteristic of measured impedance -ZK on R-X plane when an
asymmetric reverse fault occurs. This characteristic is a circle with line connecting ends of ZZD and
Z'S as the diameter. It will operate only when -ZK is in the circle. Therefore, directionality of the
distanced protection is achieved.
ZZD
F
EM

EN

I
ZK
ZS

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jX
Z'S

ZZD

R
-ZK

Figure 3.6-20 Operation characteristic for reverse fault

Z'S: total impedance between remote system and protective device location
jX

ZZD

ZK

Figure 3.6-21 Steady-state characteristic of three-phase short-circuit fault

Phase-to-phase distance protection is also used for three-phase short-circuit fault. The operation
characteristic is shown in Figure 3.6-21. Operation characteristic of ZK on R-X plane is a circle with
setting impedance ZZD as the diameter.

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jX

ZZD

ZK

R
Circle C
-ZS

Circle B
Circle A

Figure 3.6-22 Operation characteristic of three-phase close up short-circuit fault

Where:
ZZD: the setting of distance protection (zone x)
ZS: total impedance between local system and protective device location
ZK: measured impedance
: positive-sequence characteristic angle, i.e. [phi1_Reach]
Circle A: transient characteristic
Circle B: steady-state characteristic shifting towards quadrant
Circle C: steady-state characteristic shifting towards quadrant
As shown in Figure 3.6-22, the characteristic of the distance protection for a three-phase fault on a
system is an impedance circle cross the origin, and there is a voltage dead zone around the origin.
In order to eliminate the dead zone of the distance protection for a close up three-phase fault
memorized positive-sequence voltage is adopted as polarized voltage when the
positive-sequence voltage drops down to 15%Un or below.
The transient (during process of memory) operation characteristic is shown as the impedance
circle A in the above figure. The circle takes ZZD and -ZZS as diameter and thus the origin is within
the impedance circle. When three-phase fault happens in reverse direction, its transient
characteristic is shown in Figure 3.6-20, i.e. the distance protection has a clearly defined
directionality and no dead zone during the process of memory.
For zone 1, zone 2 and zone 3 of the phase-to-phase distance protection, if distance protection
operates with memorized polarizing voltage, this means a close up forward fault. When the
memory fades out, the operation characteristic will be reverse offset a little to enclose the origin as
impedance circle B shown in Figure 3.6-22 to ensure keeping operating of distance protection until
the fault being cleared. If distance protection does not operate with memorized polarizing voltage,
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it will be a close up reverse fault. When the memory fades out, the operation characteristic will be
forward offset not to enclose the origin as impedance circle C shown in Figure 3.6-22, and the
distance protection will not mal-operate even if voltage is zero.
The distance protection with such design thoroughly eliminates the dead zone when three-phase
close up fault occurs. It also has favorable directivity and will not operate for a reverse three-phase
fault at busbar.
When receiving manual closing signal or 3-pole reclosing signal, the operation characteristic of
phase to phase distance protection will always enclose the origin of impedance, with no dead zone,
i.e. the reverse offset impedance circle B shown in Figure 3.6-22.
jX
B: 15 C: 30
ZZD

A: 0
D

-ZS

Figure 3.6-23 Shift impedance characteristic of zone 1 and zone 2

The impedance characteristic of phase-to-ground distance protection is the circle with line
connecting ends of ZZD and -2ZS/3 as the diameter and that of phase-to-phase distance is the
circle with line connecting ends of ZZD and -ZS/2 as the diameter.
In order to prevent the transient overreach caused by the infeed power supply from the remote
end, the zero-sequence reactance line D is added. These measures have enhanced the capacity
against fault resistance when using distance protection in short lines.
3.

Zone 4
ZZDR
F

ZZDF
M

EM

EN
ZK

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jX

ZZDF

ZK

ZZDR

Figure 3.6-24 Operation characteristic of reverse Z4 distance protection

Where:
ZZDF: impedance setting of zone 4 in forward direction, i.e. [21M.Z4.Z_Fwd]
ZZDR: impedance setting of zone 4 in reverse direction, i.e. [21M.Z4.Z_Rev]
: positive-sequence characteristic angle, i.e. [phi1_Reach]
ZK: measurement impedance
When a fault occurs on the rear busbar, reverse distance element is provided to clear it with
definite time delay and is taken as backup protection for reverse busbar fault. Its operation
characteristic is shown in Figure 3.6-24.

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3.6.5.2 Function Block Diagram


21M
21M.En

21M.Z1.On

21M.Blk

21M.Z2.On

21M.ZGx.En

21M.Z3.On

21M.ZPx.En

21M.Z4.On

21M.ZGx.Blk

21M.Z1.Op

21M.ZPx.Blk

21M.Z2.Op

21M.Zx.En_ShortDly

21M.Z3.Op

21M.Zx.Blk_ShortDly

21M.Z4.Op

21M.Z1.En_Instant

3.6.5.3 I/O Signals


Table 3.6-5 I/O signals of distance protection (Mho)
No.

Input Signal

Description
Distance protection enabling input, it is triggered from binary input or

21M.En

21M.Blk

21M.ZGx.En

21M.ZGx.Blk

21M.ZPx.En

21M.ZPx.Blk

21M.Zx.En_ShortDly

Enable accelerating zone x of distance protection (x=2, 3)

21M.Zx.Blk_ShortDly

Accelerating zone x of distance protection is disabled (x=2, 3)

21M.Z1.En_Instant

Enable zone 1 of distance protection operates without time delay

No.

Output Signal

programmable logic etc.


Distance protection blocking input, it is triggered from binary input or
programmable logic etc.
Zone x of phase-to-ground distance protection enabling input, default value is
1 (x=1, 2, 3, 4)
Zone x of phase-to-ground distance protection blocking input, default value is
0 (x=1, 2, 3, 4)
Zone x of phase-to-phase distance protection enabling input, default value is
1 (x=1, 2, 3, 4)
Zone x of phase-to-phase distance protection blocking input, default value is
0 (x=1, 2, 3, 4)

Description

21M.Z1.On

Zone 1 of distance protection is enabled

21M.Z2.On

Zone 2 of distance protection is enabled

21M.Z3.On

Zone 3 of distance protection is enabled

21M.Z4.On

zone 4 of distance protection is enabled

21M.Z1.Op

Zone 1 of distance protection operates

21M.Z2.Op

Zone 2 of distance protection operates

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3 Operation Theory
7

21M.Z3.Op

Zone 3 of distance protection operates

21M.Z4.Op

zone 4 of distance protection operates

3.6.5.4 Logic
SIG

21M.En

SIG

VTS.Alm

SIG

21M.Blk

EN

[VTS.En_Out_VT]

&
21M.Enable

>=1

Figure 3.6-25 Logic diagram of enabling distance protection (Mho)

SIG

21M.Enable

SIG

21M.ZG1.En

EN

[21M.ZG1.En]

SIG

21M.ZG1.Blk

SIG

21M.ZP1.En

&
21M.ZG1.Enable

&
&

21M.ZP1.Enable

&

EN

[21M.ZP1.En]

SIG

21M.ZP1.Blk

SIG

21M.Z1.Rls_PSBR

SIG

FD.Pkp

SIG

21M.ZG1.Enable

SIG

Flag.21M.ZG1

SIG

LoadEnch.St (PG)

SET

3I0>[FD.ROC.3I0_Set]

SIG

Flag.21M.ZP1

SIG

LoadEnch.St (PP)

SIG

21M.ZP1.Enable

SIG

FD.Pkp

SIG

21M.Z1.En_Instant

SIG

21M.ZG1.Op

SIG

21M.ZP1.Op

>=1
21M.Z1.On

&
&
[21M.ZG1.t_Op]

&

>=1
21M.ZG1.Op

&

&
>=1
21M.Z1.Flg_PSBR

&
&

[21M.ZP1.t_Op]

&

&

>=1
21M.ZP1.Op

>=1
21M.Z1.Op

Figure 3.6-26 Logic diagram of distance protection (Mho zone 1)

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3 Operation Theory

Where:
21M.Z1.Rls_PSBR: Please refer to Figure 3.6-42.
Flag.21M.ZG1 means that measured impedance by zone 1 of phase-to-ground distance
protection is within the range determined by the setting [21M.ZG1.Z_Set].
Flag.21M.ZP1 means that measured impedance by zone 1 of phase-to-phase distance protection
is within the range determined by the setting [21M.ZP1.Z_Set].
LoadEnch.St (PG) means that load trapezoid characteristic for distance element is enabled and
measured phase-to-ground impedance into the load area.
LoadEnch.St (PP) means that load trapezoid characteristic for distance element is enabled and
measured phase-to-phase impedance into the load area.
SIG

21M.Enable

SIG

21M.ZG2.En

EN

[21M.ZG2.En]

SIG

21M.ZG2.Blk

SIG

21M.ZP2.En

&
21M.ZG2.Enable

&

&
21M.ZP2.Enable

&

EN

[21M.ZP2.En]

SIG

21M.ZP2.Blk

SIG

21M.Z2.En_ShortDly

SIG

21M.Z2.Blk_ShortDly

EN

[21M.Z2.En_ShortDly]

SIG

21M.Z2.Enable_ShortDly

SIG

21M.Z2.Rls_PSBR

SIG

FD.Pkp

>=1

21M.Z2.On

&
&
21M.Z2.Enable_ShortDly

&
[21M.ZG2.t_ShortDly]

&

>=1
21M.ZG2.Op

&
SIG

21M.ZG2.Enable

SIG

Flag.21M.ZG2

SIG

LoadEnch.St (PG)

[21M.ZG2.t_Op]

&
>=1

&

SET

3I0>[FD.ROC.3I0_Set]

SIG

Flag.21M.ZP2

SIG

LoadEnch.St (PP)

SIG

21M.ZP2.Enable

21M.Z2.Flg_PSBR

&
&
[21M.ZP2.t_Op]

>=1

&

21M.ZP2.Op

&
[21M.ZP2.t_ShortDly]

SIG

FD.Pkp

SIG

21M.Z2.Enable_ShortDly

SIG

21M.ZG2.Op

SIG

21M.ZP2.Op

>=1
21M.Z2.Op

Figure 3.6-27 Logic diagram of distance protection (Mho zone 2)


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3 Operation Theory

Where:
21M.Z2.Rls_PSBR: Please refer to Figure 3.6-42.
Flag.21M.ZG2 means that measured impedance by zone 2 of phase-to-ground distance
protection is within the range determined by the setting [21M.ZG2.Z_Set].
Flag.21M.ZP2 means that measured impedance by zone 2 of phase-to-phase distance protection
is within the range determined by the setting [21M.ZP2.Z_Set].
SIG

21M.Enable

SIG

21M.ZG3.En

EN

[21M.ZG3.En]

SIG

21M.ZG3.Blk

SIG

21M.ZP3.En

&
21M.ZG3.Enable

&

&
21M.ZP3.Enable

&

EN

[21M.ZP3.En]

SIG

21M.ZP3.Blk

SIG

21M.Z3.En_ShortDly

SIG

21M.Z3.Blk_ShortDly

EN

[21M.Z3.En_ShortDly]

SIG

21M.Z3.Enable_ShortDly

SIG

21M.Z3.Rls_PSBR

SIG

FD.Pkp

SIG

21M.ZG3.Enable

SIG

Flag.21M.ZG3

SET

3I0>[FD.ROC.3I0_Set]

SIG

LoadEnch.St (PG)

SIG

Flag.21M.ZP3

SIG

LoadEnch.St (PP)

SIG

21M.ZP3.Enable

>=1
21M.Z3.On

&
&
21M.Z3.Enable_ShortDly

&
[21M.ZG3.t_ShortDly]

>=1
21M.ZG3.Op

&
&
[21M.ZG3.t_Op]

&
>=1
21M.Z3.Flg_PSBR

&
&
[21M.ZP3.t_Op]

>=1
&

21M.ZP3.Op

&
[21M.ZP3.t_ShortDly] 0

SIG

FD.Pkp

SIG

21M.Z3.Enable_ShortDly

SIG

21M.ZG3.Op

SIG

21M.ZP3.Op

>=1
21M.Z3.Op

Figure 3.6-28 Logic diagram of distance protection (Mho zone 3)

Where:
21M.Z3.Rls_PSBR: Please refer to Figure 3.6-42.
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3 Operation Theory

Flag.21M.ZG3 means that measured impedance by zone 3 of phase-to-ground distance


protection is within the range determined by the setting [21M.ZG3.Z_Set].
Flag.21M.ZP3 means that measured impedance by zone 3 of phase-to-phase distance protection
is within the range determined by the setting [21M.ZP3.Z_Set].
SIG

21M.Enable

SIG

21M.ZG4.En

EN

[21M.ZG4.En]

SIG

21M.Zp4.Blk

SIG

21M.ZP4.En

EN

[21M.ZP4.En]

SIG

21M.ZP4.Blk

SIG

FD.Pkp

SIG

21M.ZG4.Enable

SET

3I0>[FD.ROC.3I0_Set]

SIG

LoadEnch.St (PG)

SIG

Flag.21M.ZG4

SIG

Flag.21M.ZP4

SIG

LoadEnch.St (PP)

SIG

21M.ZP4.Enable

SIG

FD.Pkp

SIG

21M.ZG4.Op

SIG

21M.ZP4.Op

&
21M.ZG4.Enable

&
&

21M.ZP4.Enable

&
>=1
21M.Z4.On

&
&
[21M.ZG4.t_Op]

21M.ZG4.Op

&
>=1
21M.Z4.Flg_PSBR

&
&
[21M.ZP4.t_Op]

21M.ZP4.Op

&

>=1
21M.Z4.Op

Figure 3.6-29 Logic diagram of distance protection (Mho zone 4)

Where:
Flag.21M.ZG4 means that measured impedance by zone 4 of phase-to-ground distance
protection is within the range determined by the settings [21M.Z4.Z_Fwd] and [21M.Z4.Z_Rev].
Flag.21M.ZP4 means that measured impedance by zone 4 of phase-to-phase distance protection
is within the range determined by the settings [21M.Z4.Z_Fwd] and [21M.Z4.Z_Rev].

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3 Operation Theory

3.6.5.5 Settings
Table 3.6-6 Settings of distance protection (Mho)
No.

Name

Range

Step

Unit

21M.ZG.phi_Shift

0, 15 or 30

Deg

21M.ZP.phi_Shift

0, 15 or 30

Deg

21M.ZG1.Z_Set

(0.000~4Unn)/In

0.001

ohm

21M.ZG1.t_Op

0.000~10.000

0.001

Remark
Phase

shift

of

21M.ZG1.En

1,

of

phase-to-ground distance protection


Phase

shift

of

zone

1,

of

phase-to-phase distance protection


Impedance setting of zone 1 of
phase-to-ground distance protection
Time

delay

of

zone

of

phase-to-ground distance protection


Enabling/disabling

zone

zone

of

phase-to-ground distance protection

0 or 1

0: disable
1: enable
Enabling/disabling

phase-to-ground

zone 1 of distance protection operation


6

21M.ZG1.En_BlkAR

0 or 1

to block AR
0: disable
1: enable

21M.ZP1.Z_Set

(0.000~4Unn)/In

0.001

ohm

21M.ZP1.t_Op

0.000~10.000

0.001

Impedance setting of zone 1 of


phase-to-phase distance protection
Time

delay

of

21M.ZP1.En

of

phase-to-phase distance protection


Enabling/disabling

zone

zone

of

phase-to-phase distance protection

0 or 1

0: disable
1: enable
Enabling/disabling

phase-to-phase

zone 1 of distance protection operation


10

21M.ZP1.En_BlkAR

0 or 1

to block AR
0: disable
1: enable

11

21M.ZG2.Z_Set

(0.000~4Unn)/In

0.001

ohm

12

21M.ZG2.t_Op

0.000~10.000

0.001

13

21M.ZG2.t_ShortDly

0.000~10.000

0.001

Impedance setting of zone 2 of


phase-to-ground distance protection
Time

delay

of

21M.ZG2.En

of

phase-to-ground distance protection


Short

time

delay

of

zone

of

phase-to-ground distance protection


Enabling/disabling

14

zone

zone

of

phase-to-ground distance protection

0 or 1

0: disable
1: enable
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3 Operation Theory
Enabling/disabling

phase-to-ground

zone 2 of distance protection operation


15

21M.ZG2.En_BlkAR

0 or 1

to block AR
0: disable
1: enable

16

21M.ZP2.Z_Set

(0.000~4Unn)/In

0.001

ohm

17

21M.ZP2.t_Op

0.000~10.000

0.001

18

21M.ZP2.t_ShortDly

0.000~10.000

0.001

Impedance setting of zone 2 of


phase-to-phase distance protection
Time

delay

of

21M.ZP2.En

of

phase-to-phase distance protection


Short

time

delay

of

zone

of

phase-to-phase distance protection


Enabling/disabling

19

zone

zone

of

phase-to-phase distance protection

0 or 1

0: disable
1: enable
Enabling/disabling

phase-to-phase

zone 2 of distance protection operation


20

21M.ZP2.En_BlkAR

0 or 1

to block AR
0: disable
1: enable
Fixed accelerate zone 2 of distance

21

21M.Z2.En_ShortDly

protection

0 or 1

0: disable
1: enable

22

21M.ZG3.Z_Set

(0.000~4Unn)/In

0.001

ohm

23

21M.ZG3.t_Op

0.000~10.000

0.001

24

21M.ZG3.t_ShortDly

0.000~10.000

0.001

Impedance setting of zone 3 of


phase-to-ground distance protection
Time

delay

of

21M.ZG3.En

of

phase-to-ground distance protection


Short

time

delay

of

zone

of

phase-to-ground distance protection


Enabling/disabling

25

zone

zone

of

phase-to-ground distance protection

0 or 1

0: disable
1: enable
Enabling/disabling

phase-to-ground

zone 3 of distance protection operation


26

21M.ZG3.En_BlkAR

0 or 1

to block AR
0: disable
1: enable

27

21M.ZP3.Z_Set

(0.000~4Unn)/In

0.001

ohm

28

21M.ZP3.t_Op

0.000~10.000

0.001

29

21M.ZP3.t_ShortDly

0.000~10.000

0.001

3-48

Impedance setting of zone 3 of


phase-to-phase distance protection
Time

delay

of

zone

of

phase-to-phase distance protection


Short

time

delay

of

zone

of

PCS-902 Line Distance Relay


Date: 2013-12-25

3 Operation Theory
phase-to-phase distance protection
Enabling/disabling
30

21M.ZP3.En

zone

of

phase-to-phase distance protection

0 or 1

0: disable
1: enable
Enabling/disabling

phase-to-phase

zone 3 of distance protection operation


31

21M.ZP3.En_BlkAR

0 or 1

to block AR
0: disable
1: enable
Fixed accelerate zone 3 of distance

32

21M.Z3.En_ShortDly

protection

0 or 1

0: disable
1: enable

33

21M.Z4.Z_Fwd

(0.000~4Unn)/In

0.001

ohm

34

21M.Z4.Z_Rev

(0.000~4Unn)/In

0.001

ohm

35

21M.Z4.t_Op

0.000~10.000

0.001

Impedance setting of zone 4 of


distance protection in forward direction
Impedance setting of zone 4 of
distance protection in reverse direction
Time delay of zone 4 of distance
protection
Enabling/disabling

36

21M.ZG4.En

zone

of

phase-to-ground distance protection

0 or 1

0: disable
1: enable
Enabling/disabling

phase-to-ground

zone 4 of distance protection operation


37

21M.ZG4.En_BlkAR

to block AR (Internal setting, its default

0 or 1

value is 1)
0: disable
1: enable
Enabling/disabling

38

21M.ZP4.En

zone

of

phase-to-phase distance protection

0 or 1

0: disable
1: enable
Enabling/disabling

phase-to-phase

zone 4 of distance protection operation


39

21M.ZP4.En_BlkAR

to block AR (Internal setting, its default

0 or 1

value is 1)
0: disable
1: enable

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3 Operation Theory

3.6.6 Quadrilateral Distance Protection


3.6.6.1 Impedance Characteristic
Features available with quadrilateral distance protection include 3 forward zones (zone 1~3)
phase-to-ground or phase-to-phase distance elements, 1 reverse zone (zone 4) phase-to-ground
or phase-to-phase distance element and 1 pilot zone distance protection. Each zone can
respectively enable or disable power swing blocking releasing. Quadrilateral distance protection
will be disabled when VT circuit fails.
1.

Zone 1, 2 and 3

Quadrilateral forward distance element characteristic for zone 1, 2 and 3 is shown as follows:

jX
A

ZZD

RZD
C

Figure 3.6-30 Quadrilateral forward distance element characteristics

Where:
ZZD: impedance setting in forward direction
RZD: resistance setting in forward direction
: line positive-sequence characteristic angle
: the angle of directional line in the second quadrant, fixed at 15
: the angle of directional line in the fourth quadrant, fixed at 15
: downward offset angle of the reactance line AB
2.

Zone 4

When a fault occurs on the busbar at the back, reverse distance element zone 4 is provided to
clear it with definite time delay and is used as backup protection for reverse busbar fault.

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3 Operation Theory

jX
C
RZD

ZZD

Figure 3.6-31 Quadrilateral reverse distance element characteristic

Where:
ZZD: impedance setting in reverse direction
RZD: resistance setting in reverse direction
: positive-sequence characteristic angle,
: the angle of directional line, fixed at 15
: the angle of directional line, fixed at 15
: downward offset angle of the reactance line AB
For quadrilateral distance protection, the reactance line should consider downward offset angle
as shown in Figure 3.6-30 and Figure 3.6-31. According to system status, the downward offset
angle can be independently set for phase-to-ground distance element and phase-to-phase
distance element. The downward offset angle of all zones can be settable by the corresponding
settings [21Q.ZGx.RCA] and [21Q.ZPx.RCA]. (x=1, 2, 3, 4)

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3 Operation Theory

3.6.6.2 Function Block Diagram


21Q
21Q.En

21Q.Z1.On

21Q.Blk

21Q.Z2.On

21Q.ZGx.En

21Q.Z3.On

21Q.ZPx.En

21Q.Z4.On

21Q.ZGx.Blk

21Q.Z1.Op

21Q.ZPx.Blk

21Q.Z2.Op

21Q.Zx.En_ShortDly

21Q.Z3.Op

21Q.Zx.Blk_ShortDly

21Q.Z4.Op

21Q.Z1.En_Instant

3.6.6.3 I/O Signals


Table 3.6-7 I/O signals of distance protection (Quad)
No.

Input Signal

Description
Distance protection enabling input, it is triggered from binary input or

21Q.En

21Q.Blk

21Q.ZGx.En

21Q.ZGx.Blk

21Q.ZPx.En

21Q.ZPx.Blk

21Q.Zx.En_ShortDly

Enable accelerating zone x of distance protection (x=2, 3)

21Q.Zx.Blk_ShortDly

Accelerating zone x of distance protection is disabled (x=2, 3)

21Q.Z1.En_Instant

Enable zone 1 of distance protection operates without time delay

No.

programmable logic etc.


Distance protection blocking input, it is triggered from binary input or
programmable logic etc.
Zone x of phase-to-ground distance protection enabling input, default value is
1 (x=1, 2, 3, 4)
Zone x of phase-to-ground distance protection blocking input, default value is
0 (x=1, 2, 3, 4)
Zone x of phase-to-phase distance protection enabling input, default value is
1 (x=1, 2, 3, 4)
Zone x of phase-to-phase distance protection blocking input, default value is 0
(x=1, 2, 3, 4)

Output Signal

Description

21Q.Z1.On

Zone 1 of distance protection is enabled

21Q.Z2.On

Zone 2 of distance protection is enabled

21Q.Z3.On

Zone 3 of distance protection is enabled

21Q.Z4.On

zone 4 of distance protection is enabled

21Q.Z1.Op

Zone 1 of distance protection operates

21Q.Z2.Op

Zone 2 of distance protection operates

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3 Operation Theory
7

21Q.Z3.Op

Zone 3 of distance protection operates

21Q.Z4.Op

zone 4 of distance protection operates

3.6.6.4 Logic
SIG

21Q.En

SIG

21Q.Blk

SIG

VTS.Alm

EN

[VTS.En_Out_VT]

&
21Q.Enable

>=1

Figure 3.6-32 Logic diagram of enabling distance protection (Quad)


SIG

21Q.Enable

EN

[21Q.ZG1.En]

SIG

21Q.ZG1.En

SIG

21Q.ZG1.Blk

EN

[21Q.ZP1.En]

&

>=1
21Q.ZG1.Enable

&

21Q.Z1.On

&
21Q.ZP1.Enable

&

SIG

21Q.ZP1.En

SIG

21Q.ZP1.Blk

SIG

FD.Pkp

SIG

21Q.ZG1.Enable

SIG

LoadEnch.St (PG)

SET

3I0>[FD.ROC.3I0_Set]

SIG

Flag.21Q.ZG1

SIG

21Q.Z1.Rls_PSBR

SIG

FD.Pkp

&
&

&

&
[21Q.ZG1.t_Op]

>=1
21Q.ZG1.Op

&
>=1

&

SIG

21Q.ZP1.Enable

SIG

LoadEnch.St (PP)

SIG

Flag.21Q.ZP1

21Q.Z1.Flg_PSBR

&
&
[21Q.ZP1.t_Op]

>=1

&

SIG

21Q.Z1.En_Instant

SIG

21Q.ZG1.Op

SIG

21Q.ZP1.Op

21Q.ZP1.Op

>=1
21Q.Z1.Op

Figure 3.6-33 Logic diagram of distance protection (Quad zone 1)

Where:
21Q.Z1.Rls_PSBR: Please refer to Figure 3.6-42.

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3 Operation Theory

Flag.21Q.ZG1 means that measured impedance by zone 1 of phase-to-ground distance protection


is within the range determined by the settings [21Q.ZG1.Z_Set] and [21Q.ZG1.R_Set].
Flag.21Q.ZP1 means that measured impedance by zone 1 of phase-to-phase distance protection
is within the range determined by the settings [21Q.ZP1.Z_Set] and [21Q.ZP1.R_Set].
LoadEnch.St (PG) means that load trapezoid characteristic for distance element is enabled and
measured phase-to-ground impedance into the load area.
LoadEnch.St (PP) means that load trapezoid characteristic for distance element is enabled and
measured phase-to-phase impedance into the load area.
SIG

21Q.Enable

EN

[21Q.ZG2.En]

SIG

21Q.ZG2.En

SIG

21Q.ZG2.Blk

EN

[21Q.ZP2.En]

&

>=1
21Q.ZG2.Enable

&

21Q.Z2.On

&
21Q.ZP2.Enable

&

SIG

21Q.ZP2.En

SIG

21Q.ZP2.Blk

SIG

21Q.Z2.En_ShortDly

SIG

21Q.Z2.Blk_ShortDly

EN

[21Q.Z2.En_ShortDly]

SIG

21Q.Z2.Enable_ShortDly

SIG

FD.Pkp

SIG

21Q.ZG2.Enable

&
&
21Q.Z2.Enable_ShortDly

&
&

SET

&

3I0>[FD.ROC.3I0_Set]

SIG

LoadEnch.St (PG)

SIG

Flag.21Q.ZG2

SIG

21Q.Z2.Rls_PSBR

SIG

21Q.ZP2.Enable

SIG

LoadEnch.St (PP)

SIG

Flag.21Q.ZP2

SIG

21Q.ZG2.Op

SIG

21Q.ZP2.Op

[21Q.ZG2.t_ShortDly] 0

&

>=1
21Q.ZG2.Op

&
[21Q.ZG2.t_Op]

>=1
21Q.Z2.Flg_PSBR

&

&
[21Q.ZP2.t_ShortDly] 0

&

>=1
21Q.ZP2.Op

[21Q.ZP2.t_Op]

>=1
21Q.Z2.Op

Figure 3.6-34 Logic diagram of distance protection (Quad zone 2)

Where:
21Q.Z2.Rls_PSBR: Please refer to Figure 3.6-42.
Flag.21Q.ZG2 means that measured impedance by zone 2 of phase-to-ground distance protection
is within the range determined by the settings [21Q.ZG2.Z_Set] and [21Q.ZG2.R_Set].
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3 Operation Theory

Flag.21Q.ZP2 means that measured impedance by zone 2 of phase-to-phase distance protection


is within the range determined by the settings [21Q.ZP2.Z_Set] and [21Q.ZP2.R_Set].
SIG

21Q.Enable

EN

[21Q.ZG3.En]

SIG

21Q.ZG3.En

SIG

21Q.ZG3.Blk

EN

[21Q.ZP3.En]

&

>=1
21Q.ZG3.Enable

&

21Q.Z3.On

&
21Q.ZP3.Enable

&

SIG

21Q.ZP3.En

SIG

21Q.ZP3.Blk

SIG

21Q.Z3.En_ShortDly

SIG

21Q.Z3.Blk_ShortDly

EN

[21Q.Z3.En_ShortDly]

SIG

21Q.Z3.Enable_ShortDly

SIG

FD.Pkp

SIG

21Q.ZG3.Enable

SET

3I0>[FD.ROC.3I0_Set]

SIG

LoadEnch.St (PG)

SIG

Flag.21Q.ZG3

SIG

21Q.Z3.Rls_PSBR

SIG

FD.Pkp

&
&
21Q.Z3.Enable_ShortDly

&
&
&

&
[21Q.ZG3.t_ShortDly] 0

&

>=1
21Q.ZG3.Op

[21Q.ZG3.t_Op]

SIG

21Q.ZP3.Enable

SIG

LoadEnch.St (PP)

SIG

Flag.21Q.ZP3

SIG

21Q.ZG3.Op

SIG

21Q.ZP3.Op

>=1

&

21Q.Z3.Flg_PSBR

&

&
[21Q.ZP3.t_ShortDly] 0

&

>=1
21Q.ZP3.Op

[21Q.ZP3.t_Op]

>=1
21Q.Z3.Op

Figure 3.6-35 Logic diagram of distance protection (Quad zone 3)

Where:
21Q.Z3.Rls_PSBR: Please refer to Figure 3.6-42.
Flag.21Q.ZG3 means that measured impedance by zone 3 of phase-to-ground distance protection
is within the range determined by the settings [21Q.ZG3.Z_Set] and [21Q.ZG3.R_Set].
Flag.21Q.ZP3 means that measured impedance by zone 3 of phase-to-phase distance protection
is within the range determined by the settings [21Q.ZP3.Z_Set] and [21Q.ZP3.R_Set].

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3 Operation Theory
SIG

21Q.Enable

EN

[21Q.ZG4.En]

SIG

21Q.ZG4.En

SIG

21Q.ZG4.Blk

EN

[21Q.ZP4.En]

&

>=1
21Q.ZG4.Enable

&

21Q.Z4.On

&
21Q.ZP4.Enable

&

SIG

21Q.ZP4.En

SIG

21Q.ZP4.Blk

SIG

FD.Pkp

SIG

21Q.ZG4.Enable

SET

3I0>[FD.ROC.3I0_Set]

SIG

LoadEnch.St (PG)

SIG

Flag.21Q.ZG4

SIG

FD.Pkp

SIG

21Q.ZP4.Enable

SIG

LoadEnch.St (PP)

SIG

Flag.21Q.ZP4

SIG

21Q.ZG4.Op

SIG

21Q.ZP4.Op

&
&
[21Q.ZG4.t_Op]

21Q.ZG4.Op

&
>=1
21Q.Z4.Flg_PSBR

&
[21Q.ZP4.t_Op]

21Q.ZP4.Op

&

>=1
21Q.Z4.Op

Figure 3.6-36 Logic diagram of distance protection (Quad zone 4)

Where:
Flag.21Q.ZG4 means that measured impedance by zone 4 of phase-to-ground distance protection
is within the range determined by the settings [21Q.ZG4.Z_Set] and [21Q.ZG4.R_Set].
Flag.21Q.ZP4 means that measured impedance by zone 4 of phase-to-phase distance protection
is within the range determined by the settings [21Q.ZP4.Z_Set] and [21Q.ZP4.R_Set].
3.6.6.5 Settings
Table 3.6-8 Settings of distance protection (Quad)
No.

Name

Range

Step

Unit

Remark
Downward

21Q.ZG1.RCA

0~45

Deg

reactance

offset
line

angle
for

zone

of

the
1

of

phase-to-ground distance protection


2

21Q.ZG1.Z_Set

(0.000~4Unn)/In

0.001

ohm

3-56

Impedance setting of zone 1 of


phase-to-ground distance protection

PCS-902 Line Distance Relay


Date: 2013-12-25

3 Operation Theory
3

21Q.ZG1.R_Set

(0.000~4Unn)/In

0.001

ohm

21Q.ZG1.t_Op

0.000~10.000

0.001

Resistance setting of zone 1


phase-to-ground distance protection
Time

delay

of

21Q.ZG1.En

zone

of

phase-to-ground distance protection


Enabling/disabling

of

zone

of

phase-to-ground distance protection

0 or 1

0: disable
1: enable
Enabling/disabling

phase-to-ground

zone 1 of distance protection operation


6

21Q.ZG1.En_BlkAR

0 or 1

to block AR
0: disable
1: enable
Downward

21Q.ZP1. RCA

0~45

Deg

reactance

offset
line

angle
for

of

zone

the
1

of

phase-to-phase distance protection


8

21Q.ZP1.Z_Set

(0.000~4Unn)/In

0.001

ohm

21Q.ZP1.R_Set

(0.000~4Unn)/In

0.001

ohm

21Q.ZP1.t_Op

0.000~10.000

0.001

10

Impedance setting of zone 1 of


phase-to-phase distance protection
Resistance setting of zone 1
phase-to-phase distance protection
Time

delay

of

21Q.ZP1.En

zone

of

phase-to-phase distance protection


Enabling/disabling

11

of

zone

of

phase-to-phase distance protection

0 or 1

0: disable
1: enable
Enabling/disabling

phase-to-phase

zone 1 of distance protection operation


12

21Q.ZP1.En_BlkAR

0 or 1

to block AR
0: disable
1: enable
Downward

13

21Q.ZG2.RCA

0~45

Deg

reactance

offset
line

angle
for

of

zone

the
2

of

phase-to-ground distance protection


14

21Q.ZG2.Z_Set

(0.000~4Unn)/In

0.001

ohm

15

21Q.ZG2.R_Set

(0.000~4Unn)/In

0.001

ohm

16

21Q.ZG2.t_Op

0.000~10.000

0.001

17

21Q.ZG2.t_ShortDly

0.000~10.000

0.001

18

21Q.ZG2.En

0 or 1

Impedance setting of zone 2

of

phase-to-ground distance protection


Resistance setting of zone 2

of

phase-to-ground distance protection


Time

delay

of

zone

of

phase-to-ground distance protection


Short

time

delay

of

zone

of

phase-to-ground distance protection


Enabling/disabling

zone

of

phase-to-ground distance protection


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3 Operation Theory
0: disable
1: enable
Enabling/disabling

phase-to-ground

zone 2 of distance protection operation


19

21Q.ZG2.En_BlkAR

0 or 1

to block AR
0: disable
1: enable
Downward

20

21Q.ZP2. RCA

0~45

Deg

reactance

offset
line

angle
for

of

zone

the
2

of

phase-to-phase distance protection


21

21Q.ZP2.Z_Set

(0.000~4Unn)/In

0.001

ohm

22

21Q.ZP2.R_Set

(0.000~4Unn)/In

0.001

ohm

23

21Q.ZP2.t_Op

0.000~10.000

0.001

24

21Q.ZP2.t_ShortDly

0.000~10.000

0.001

Impedance setting of zone 2 of


phase-to-phase distance protection
Resistance setting of zone 2
phase-to-phase distance protection
Time

delay

of

21Q.ZP2.En

zone

of

phase-to-phase distance protection


Short time delay of zone 2 of phase-tophase distance protection
Enabling/disabling

25

of

zone

of

phase-to-phase distance protection

0 or 1

0: disable
1: enable
Enabling/disabling

phase-to-phase

zone 2 of distance protection operation


26

21Q.ZP2.En_BlkAR

0 or 1

to block AR
0: disable
1: enable
Fixed accelerate zone 2 of distance

27

21Q.Z2. En_ShortDly

protection

0 or 1

0: disable
1: enable
Downward

28

21Q.ZG3.RCA

0~45

Deg

reactance

offset
line

angle
for

of

zone

the
3

of

phase-to-ground distance protection


29

21Q.ZG3.Z_Set

(0.000~4Unn)/In

0.001

ohm

30

21Q.ZG3.R_Set

(0.000~4Unn)/In

0.001

ohm

31

21Q.ZG3.t_Op

0.000~10.000

0.001

32

21Q.ZG3.t_ShortDly

0.000~10.000

0.001

33

21Q.ZG3.En

0 or 1

Impedance setting of zone 3 of


phase-to-ground distance protection
Resistance setting of zone 3

of

phase-to-ground distance protection


Time

delay

of

zone

of

phase-to-ground distance protection


Short

time

delay

of

zone

of

phase-to-ground distance protection


Enabling/disabling

zone

of

phase-to-ground distance protection

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3 Operation Theory
0: disable
1: enable
Enabling/disabling

phase-to-ground

zone 3 of distance protection operation


34

21Q.ZG3.En_BlkAR

0 or 1

to block AR
0: disable
1: enable
Downward

35

21Q.ZP3. RCA

0~45

Deg

reactance

offset
line

angle
for

of

zone

the
3

of

phase-to-phase distance protection


36

21Q.ZP3.Z_Set

(0.000~4Unn)/In

0.001

ohm

37

21Q.ZP3.R_Set

(0.000~4Unn)/In

0.001

ohm

38

21Q.ZP3.t_Op

0.000~10.000

0.001

39

21Q.ZP3.t_ShortDly

0.000~10.000

0.001

Impedance setting of zone 3 of


phase-to-phase distance protection
Resistance setting of zone 3
phase-to-phase distance protection
Time

delay

of

21Q.ZP3.En

zone

of

phase-to-phase distance protection


Short

time

delay

of

zone

of

phase-to-phase distance protection


Enabling/disabling

40

of

zone

of

phase-to-phase distance protection

0 or 1

0: disable
1: enable
Enabling/disabling

phase-to-phase

zone 3 of distance protection operation


41

21Q.ZP3.En_BlkAR

0 or 1

to block AR
0: disable
1: enable
Fixed accelerate zone 3 of distance

42

21Q.Z3. En_ShortDly

protection

0 or 1

0: disable
1: enable
Downward

43

21Q.ZG4.RCA

0~45

Deg

reactance

offset
line

angle
for

zone

of

the
4

of

phase-to-ground distance protection


44

21Q.ZG4.Z_Set

(0.000~4Unn)/In

0.001

ohm

45

21Q.ZG4.R_Set

(0.000~4Unn)/In

0.001

ohm

46

21Q.ZG4.t_Op

0.000~10.000

0.001

Impedance setting of zone 3 of


phase-to-ground distance protection
Resistance setting of zone 3
phase-to-ground distance protection
Time

delay

of

21Q.ZG4.En

zone

of

phase-to-ground distance protection


Enabling/disabling

47

of

zone

of

phase-to-ground distance protection

0 or 1

0: disable
1: enable
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3 Operation Theory
Enabling/disabling

phase-to-ground

zone 4 of distance protection operation


48

21Q.ZG4.En_BlkAR

to block AR (Internal setting, its default

0 or 1

value is 1)
0: disable
1: enable
Downward

49

21Q.ZP4. RCA

0~45

Deg

reactance

offset
line

angle
for

of

zone

the
4

of

phase-to-phase distance protection


50

21Q.ZP4.Z_Set

(0.000~4Unn)/In

0.001

ohm

51

21Q.ZP4.R_Set

(0.000~4Unn)/In

0.001

ohm

52

21Q.ZP4.t_Op

0.000~10.000

0.001

Impedance setting of zone 3 of


phase-to-phase distance protection
Resistance setting of zone 3
phase-to-phase distance protection
Time

delay

of

21Q.ZP4.En

zone

of

phase-to-phase distance protection


Enabling/disabling

53

of

zone

of

phase-to-phase distance protection

0 or 1

0: disable
1: enable
Enabling/disabling

phase-to-phase

zone 4 of distance protection operation


54

21Q.ZP4.En_BlkAR

to block AR (Internal setting, its default

0 or 1

value is 1)
0: disable
1: enable

3.6.7 Pilot Distance Zone


3.6.7.1 Impedance Characteristic
An independent pilot zone distance protection is used for PUTT and POTT scheme. There is also
a reverse pilot distance element available as an option for application of POTT on weak power
source system.
Pilot.Z_Rev_B

Pilot.Z_Set_B
M

EM

Pilot.Z_Rev_A

Pilot.Z_Set_A

Figure 3.6-37 Protected zone of pilot distance protection

The operation characteristic of pilot zone is same as that of zone 2, including mho and
quadrilateral characteristic.
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3 Operation Theory

When an internal fault occurs, distance protection at weak source end may not operate due to
small fault current. Thus, a reverse distance element is provided to coordinate with the
independent pilot distance protection to implement weak infeed logic, ensure pilot distance
protection can operate to send signal or trip in the weak end. The operation characteristic is shown
in Figure 3.6-38. The reverse weak infeed distance element is forward offset with 1/4 of the
reverse setting to enclose the origin.
Operation characteristics of pilot reverse weak infeed element distance are shown as below.
jX

jX

21Q.Z_Rev/4

21M.Z_Rev/4

21Q.R_Rev

21M.Z_Rev

21Q.Z_Rev

Figure 3.6-38 Pilot reverse weak infeed element

Where:
: positive-sequence characteristic angle, i.e. [phi1_Reach]
: the angle of directional line, fixed at 15
: the angle of directional line, fixed at 15
: tilted angle of the reactance line AC, fixed at 12
3.6.7.2 Logic
SIG

FD.Pkp

SIG

21M.Enable

SIG

21M.Pilot.Rls_PSBR

SET

Flag.21M.Pilot.Z (PG)

SIG

LoadEnch.St (PG)

SET

Flag.21M.Pilot.Z (PP)

SIG

LoadEnch.St (PP)

&
&
&
ZPilotP

&
>=1
21M.Zpilot.Flag_PSBR

&

Figure 3.6-39 Logic diagram of pilot distance zone (Mho characteristic)


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3 Operation Theory
SIG

FD.Pkp

SIG

21Q.Enable

SIG

21Q.Pilot.Rls_PSBR

SET

Flag.21Q.Pilot.Z (PG)

SIG

LoadEnch.St (PG)

SET

Flag.21Q.Pilot.Z (PP)

SIG

LoadEnch.St (PP)

&
&
&
ZPilotP

&
>=1
21Q.Zpilot.Flag_PSBR

&

Figure 3.6-40 Logic diagram of pilot distance zone (Quad characteristic)

Where:
21M.Pilot.Rls_PSBR, 21Q.Pilot.Rls_PSBR: Please refer to Figure 3.6-42.
LoadEnch.St (PG) means that load trapezoid characteristic for distance element is enabled and
measured phase-to-ground impedance into the load area.
LoadEnch.St (PP) means that load trapezoid characteristic for distance element is enabled and
measured phase-to-phase impedance into the load area.
Flag.21Q.Pilot.Z (PG) means that measured impedance by phase-to-ground distance element is
within the range determined by the setting [21Q.Pilot.Z_Set]. (Quad characteristic)
Flag.21Q.Pilot.Z (PP) means that measured impedance by phase-to-phase distance element is
within the range determined by the setting [21Q.Pilot.Z_Set]. (Quad characteristic)
Flag.21M.Pilot.Z (PG) means that measured impedance by phase-to-ground distance element is
within the range determined by the setting [21M.Pilot.Z_Set]. (Mho characteristic)
Flag.21M.Pilot.Z (PP) means that measured impedance by phase-to-phase distance element is
within the range determined by the setting [21M.Pilot.Z_Set]. (Mho characteristic)
3.6.7.3 Settings
Table 3.6-9 Settings of pilot distance zone
No.

Name

Range

Step

Unit

21M.Pilot.Z_Set

(0.000~4Unn)/In

0.001

ohm

21Q.Pilot.Z_Set

(0.000~4Unn)/In

0.001

ohm

Remark
Impedance

21M.Pilot.Z_Rev

(0.000~4Unn)/In

0.001

ohm

of

pilot

distance

protection (Mho characteristic)


Impedance

setting

of

pilot

distance

protection (Quad characteristic)


Impedance

setting

protection

setting
in

of

reverse

pilot

distance

direction

(Mho

characteristic)
4

21Q.Pilot.Z_Rev

(0.000~4Unn)/In

0.001

ohm

3-62

Impedance

setting

of

pilot

distance

protection in reverse direction (Quad

PCS-902 Line Distance Relay


Date: 2013-12-25

3 Operation Theory
characteristic)
5

21Q.Pilot.R_Set

(0.000~4Unn)/In

0.001

ohm

Impedance

21Q.Pilot.R_Rev

(0.000~4Unn)/In

0.001

ohm

of

pilot

distance

protection (Quad characteristic only)


Impedance

setting

setting

of

pilot

distance

protection in reverse direction (Quad


characteristic only)

3.6.8 Power Swing Detection


Power swing is generally a dynamic process when power system is disturbed. When power swing
occurs, the angle between the generators in parallel operation, the frequency of the system, the
voltage on the bus, the current and power of the branch lines are all fluctuating. Power swing may
destroy the normal operation of power systems and even damage electrical equipment, causing
the system to collapse.
3.6.8.1 Function Block Diagram
68
68.En

68.St

68.Blk

3.6.8.2 I/O Signals


Table 3.6-10 I/O signals of power swing detection
No.

Input Signal

Description
Power swing detection enabling input, it is triggered from binary input or

68.En

68.Blk

21.St

Any element of distance protection picks up.

FD.ROC.Pkp

Residual current FD element operates.

52b

Circuit breaker is in closed position.

52a

Circuit breaker is in open position.

No.
1

programmable logic etc.


Power swing detection blocking input, it is triggered from binary input or
programmable logic etc.

Output Signal
68.St

Description
Power swing detection takes into effect.

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3 Operation Theory

3.6.8.3 Logic
EN

[68.En]

SIG

68.En

SIG

68.Blk

SIG

I1>[Y.I_PSBR]

SIG

21.St

SIG

FD.ROC.Pkp

SIG

3 CB Closed

SIG

3 CB open

SIG

Unblocking for SF

SIG

Unblocking for UF

&
&
&

&
&
t1

t2

&
68.St

&
>=1

>=1

Figure 3.6-41 Logic diagram of power swing detection

Y: 21M or 21Q
3.6.8.4 Settings
Table 3.6-11 Settings of power swing detection
No.

Name

Range

Step

Unit

Remark
Enabling/disabling power swing detection

68.En

0 or 1

0: disable
1: enable

3.6.9 Power Swing Blocking Releasing


When power swing occurs on the power system, the impedance measured by the distance
measuring element may vary from the load impedance area into the operating zone of the
distance element. The distance measuring element may operate due to the power swing occurs in
many points of interconnected power systems. To keep the stability of whole power system,
tripping due to operation of the distance measuring element during a power swing is generally not
allowed. Our distance protection adopts power swing blocking releasing to avoid maloperation
resulting from power swing. In another word, distance protection is blocked all along under the
normal condition and power swing when the respective logic settings are enabled. Only when fault
(internal fault or power swing with internal fault) is detected, power swing blocking for distance
protection is released by PSBR element.
Power swing blocking for distance element will be released if any of the following PSBR elements
operates. Each distance zone elements has respective setting for selection this function.

Fault detector PSBR element (FD PSBR)

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3 Operation Theory

Unsymmetrical fault PSBR element (UF PSBR)

Symmetrical fault PSBR element (SF PSBR)

1.

Fault detector PSBR element

If any of the following condition is matched, FD PSBR will operate for 160ms.
1)

Positive sequence current is lower than the setting [I_PSBR] before general fault detector
element operates.

2)

Positive sequence current is higher than the setting [I_PSBR] before general fault detector
element operates, but the duration is less than 10ms.

As shown in figure below, assume normal load impedance locates at position 1, and the
impedance under current I_PSBR locates at position 2, if the condition for FD PSBR mentioned
above operates, it means FD operates between point 1, point 2 and point 3 as example, then FD
PSBR will operate for 160ms.

[I_PSBR]
FD
Normal load
impedance

Point 1

Point 3

Point 2

2.

Unsymmetrical fault PSBR element

The operation criterion:


I0+I2>mI1
The m, an empirical value, is internal fixed coefficient which can ensure UF PSBR operation
during power swing with internal unsymmetrical fault, while no operation during power swing or
power swing with external fault.
This decision mainly utilizes the "discrepancy" that there is no negative-sequence or
zero-sequence current during power swing, and there are negative-sequence and zero-sequence
currents in case of asymmetric fault. In addition, value of m is used to differentiate internal
asymmetric fault and external asymmetric fault in case of power swing.
In case of power swing or both power swing and external fault, asymmetric fault discriminating
element will not operate and distance protection will be blocked:
In case of power swing but no fault, I0 and I2 are near zero, but I1 is very large. Asymmetric fault
discriminating element will not operate.
In case of both power swing and external fault, if center of power swing is in scope of protection,
both phase-to-phase and grounding impedance relays may operate. At this time, selection of
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3 Operation Theory

value of m is used to ensure no operation of asymmetric fault discriminating element, blocking of


distance protection, and no incorrect operation without selectivity. If power swing center is not on
this line, distance protection will not operate incorrectly without selectivity due to power swing.
In case of internal asymmetric fault, asymmetric fault discriminating element operates and
distance protection will be release to clear internal fault:
In case of both power swing and internal fault, if at the instant of short circuit, system electric
potential angle is not laid out, asymmetric fault discriminating element will operate at once. If at the
instant of short circuit, system electric potential angle is laid out, asymmetric fault discriminating
element will operate when system angle gradually decreases, or local side tripping may be
activated after immediate operation of opposite side asymmetric fault discriminating element and
releasing of distance protection tripping. In case of normal internal asymmetric phase-to-phase or
grounding fault in the system, relatively large zero-sequence or negative-sequence component will
exist. At this time, the above equation is true and distance protection will be released.
3.

Symmetrical fault PSBR element

If a three-phase fault occurs and FD PSBR is invalid (160ms after FD operates), neither FD PSBR
nor UF PSBR will be able to release the distance protection. Thus, SF PSBR is provided for this
case specially. This detection is based on measuring the voltage at power swing center, during
power swing, U1cos will constantly change periodically.
UOS=U1COS
Where:
: the angle between positive sequence voltage and current
U1: the positive sequence voltage
As shown in the figure below, assume system connection impedance angle of 90, current vector
will be perpendicular to the line connecting EM and EN, and have the same phase as power swing
center voltage. During normal operation of system or power swing, U1cos just reflects
positive-sequence voltage of power swing center. In case of 3-phase short circuit, U1cos is
voltage drop on arc resistor, transition resistance is arc resistance, and voltage drop on arc resistor
is less than 5%UN. In actual system, line impedance angle is not 90. Through compensation of
angle , power swing center voltage can be measured accurately. After compensation, power
swing center voltage is U1cos(90oL), where L is line impedance angle.
EM

EN

UOS

During power swing, power swing center voltage U1cos has the following characteristics: When
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3 Operation Theory

electric potential phase angle difference between power supplies at two sides is 180o, U1cos0
and change rate dU1cos/dt is the maximum. When this phase angle difference is near 0o, power
swing center voltage change rate dU1cos/dt is the minimum. During short circuit, U1cos
remains unchanged and dU1cos/dt0. However, in early stage of short circuit when normal state
enters short circuit state, dU1cos/dt is very large. Therefore, use of dU1cos/dt solely to
differentiate power swing and short circuit is not complete.
For these reasons, the method to release distance protection on condition that power swing center
voltage U1cos is less than a setting and after a short delay can be used as symmetric fault
discriminating element. This element can accurately differentiate power swing and 3-phase short
circuit fault, and constitute a complete power swing blocking scheme with other elements. The
element to open distance protection if U1cos is less than a certain setting and after a delay is
easy to realize and has short delay, and can trip fault more quickly and accurately trip 3-phase
short circuit fault during power swing.
The criterion of SF PSBR element comprises the following two parts:

when -0.03UN<UOS<0.08UN, the SF PSBR element will operate after 150ms.

when -0.1UN<UOS<0.25UN, the SF PSBR element will operate after 500ms.

The second criterion is a backup of the first criterion allowing longer monitoring period of voltage
variation.
To reduce the time delay for SF PSBR element during power swing, the change rate of voltage at
power swing center is also used which can release SF PSBR element quickly for the fault occurred
during power swing. The typical release time is less than 60ms.
3.6.9.1 Function Block Diagram
21M

21M.En_PSBR

21M.Z1.Rls_PSBR

21M.Blk_PSBR

21M.Z2.Rls_PSBR
21M.Z3.Rls_PSBR
21M.Pilot.Rls_PSBR

21Q

21Q.En_PSBR

21Q.Z1.Rls_PSBR

21Q.Blk_PSBR

21Q.Z2.Rls_PSBR
21Q.Z3.Rls_PSBR
21Q.Pilot.Rls_PSBR

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3.6.9.2 I/O Signals


Table 3.6-12 I/O signals of PSBR
No.

Input Signal

Description

21M.En_PSBR

Enabling power swing blocking releasing (Mho characteristic)

21Q.En_PSBR

Enabling power swing blocking releasing (Quad characteristic)

21M.Blk_PSBR

Blocking power swing blocking releasing (Mho characteristic)

21Q.Blk_PSBR

Blocking power swing blocking releasing (Quad characteristic)

No.

Output Signal

Description

21M.Z1.Rls_PSBR

PSBR operates to release zone 1 (Mho characteristic)

21Q.Z1.Rls_PSBR

PSBR operates to release zone 1 (Quad characteristic)

21M.Z2.Rls_PSBR

PSBR operates to release zone 2 (Mho characteristic)

21Q.Z2.Rls_PSBR

PSBR operates to release zone 2 (Quad characteristic)

21M.Z3.Rls_PSBR

PSBR operates to release zone 3 (Mho characteristic)

21Q.Z3.Rls_PSBR

PSBR operates to release zone 3 (Quad characteristic)

21M.Pilot.Rls_PSBR

PSBR operates to release pilot distance protection (Mho characteristic)

21Q.Pilot.Rls_PSBR

PSBR operates to release pilot distance protection (Quad characteristic)

3.6.9.3 Logic
SIG

Y.En_PSBR

SIG

Y.Blk_PSBR

SIG

FD.Pkp

SIG

Y.Enable_PSBR

EN

[Y.Zx .En_PSBR]

SIG

symmetrical |U1cos|<

&
Y.Enable_PSBR

&
>=1
t

0ms

>=1

Unblocking for SF

&
Y.Zx.Rls_PSBR

Unblocking for UF

>=1
SIG

Unsymmetrical |I0|+|I2|>

SIG

Y.Zx.Flg_PSBR

SET

I1>[Y.I_PSBR]

&

10ms

0ms

&

&
0

SIG

FD.Pkp

SIG

Y.Zx.Flg_PSBR

160ms

>=1

Figure 3.6-42 Logic diagram of PSBR

Y: 21M or 21Q
x: 1, 2, 3 or pilot
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Y.Zx.Flg_PSBR: Please refer to Figure 3.6-26~Figure 3.6-29, Figure 3.6-33~Figure 3.6-36, Figure
3.6-40 and Figure 3.6-39.
3.6.9.4 Settings
Table 3.6-13 Settings of PSBR
No.

Name

Range

Step

Unit

Remark
Enabling/disabling zone 1 of distance
protection controlled by PSBR (Mho

21M.Z1.En_PSBR

0 or 1

characteristic)
0: disable
1: enable
Enabling/disabling zone 1 of distance
protection controlled by PSBR (Quad

21Q.Z1.En_PSBR

0 or 1

characteristic)
0: disable
1: enable
Enabling/disabling zone 2 of distance
protection controlled by PSBR (Mho

21M.Z2.En_PSBR

0 or 1

characteristic)
0: disable
1: enable
Enabling/disabling zone 2 of distance
protection controlled by PSBR (Quad

21Q.Z2.En_PSBR

0 or 1

characteristic)
0: disable
1: enable
Enabling/disabling zone 3 of distance
protection controlled by PSBR (Mho

21M.Z3.En_PSBR

0 or 1

characteristic)
0: disable
1: enable
Enabling/disabling zone 3 of distance
protection controlled by PSBR (Quad

21Q.Z3.En_PSBR

0 or 1

characteristic)
0: disable
1: enable
Enabling/disabling

pilot

distance

zone controlled by PSBR (Mho


7

21M.Pilot.En_PSBR

0 or 1

characteristic)
0: disable
1: enable

21Q.Pilot.En_PSBR

Enabling/disabling

0 or 1

pilot

distance

zone controlled by PSBR (Quad


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characteristic)
0: disable
1: enable
9

21M.I_PSBR

(0.050~30.000)In

0.001

10

21Q.I_PSBR

(0.050~30.000)In

0.001

Current setting for power swing


blocking (Mho characteristic)
Current setting for power swing
blocking (Quad characteristic)

3.6.10 Distance SOTF Protection


When the circuit breaker is closed manually or automatically, it is possible to switch on to a fault.
This is especially critical if the line in the remote station is grounded, since the distance protection
would not clear the fault until overreach zones (zone 2 and/or zone 3) time delays have elapsed. In
this situation, however, the fastest possible clearance is required.
The SOTF (switch onto fault) protection is a complementary function to the distance protection.
With distance SOTF protection, a fast trip is achieved for a fault on the whole line, when the line is
being energized. It shall be responsive to all types of faults anywhere within the protected line.
3.6.10.1 Function Block Diagram
21SOTF
21SOTF.En

21SOTF.On

21SOTF.Blk

21SOTF.Op
21SOTF.Op_PDF

3.6.10.2 I/O Signals


Table 3.6-14 I/O signals of distance SOTF protection
No.

Input Signal

21SOTF.En

21SOTF.Blk

No.

Description
Distance SOTF protection enabling input, it is triggered from binary input or
programmable logic etc.
Distance SOTF protection blocking input, it is triggered from binary input or
programmable logic etc.

Output Signal

21SOTF.Op

21SOTF.Op_PDF

21SOTF.On

Description
Accelerate distance protection to trip when manual closing or auto-reclosing to
fault
Accelerate distance protection to trip when another fault happened under pole
discrepancy conditions
Accelerate distance protection is enabled.

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3.6.10.3 Logic
SIG

21SOTF.En

SIG

21SOTF.Blk

EN

[21SOTF.En]

&
&
21SOTF.On

Figure 3.6-43 Logic diagram of enabling distance SOTF protection

Distance SOTF protection can be enabled or disabled, and can be initiated by several cases,
including manual closing signal, 3-pole reclosing, 1-pole reclosing and pole discrepancy
conditions.
BI

[52b_PhA]

BI

[52b_PhB]

BI

[52b_PhC]

>=1

&
SIG

FD.Pkp

EN

[SOTF.Opt_Mode_ManCls]=1 or 2

EN

[SOTF.Opt_Mode_ManCls]=0 or 2

BI

ManCls

EN

[21SOTF.En_ManCls]

EN

[21SOTF.Z2.En_ManCls]

SIG

Y.Z2.Flg_PSBR

EN

[21SOTF.Z3.En_ManCls]

SIG

Y.Z3.Flg_PSBR

EN

[21SOTF.Z4.En_ManCls]

SIG

Y.Z4.Flg_PSBR

SIG

21SOTF.On

SIG

FD.Pkp

>=1
0

400ms

Manual closing signal

&

&
&
[21SOTF.t_ManCls] 0

&

&

21SOTF.Op

>=1

&

&

Figure 3.6-44 Logic diagram of distance SOTF protection by manual closing signal

When the circuit breaker is in open position while the device does not pick up, or external manual
closing binary input is energized, then manual closing signal will be kept for 400ms, which will
enable SOTF logic only for 400ms.

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SIG

FD.Pkp

SIG

21SOTF.On

EN

[21SOTF.En_3PAR]

SIG

3-pole reclosing signal

EN

[21SOTF.Z2.En_3PAR]

SIG

Y.Z2.Flg_PSBR

EN

[21SOTF.Z2.En_PSBR]

SIG

Y.Z2.Rls_PSBR

EN

[21SOTF.Z3.En_3PAR]

&

SIG

Y.Z3.Flg_PSBR

EN

[21SOTF.Z3.En_PSBR]

SIG

Y.Z3.Rls_PSBR

EN

[21SOTF.Z4.En_3PAR]

SIG

Y.Z4.Flg_PSBR

EN

[21SOTF.Z4.En_PSBR]

SIG

Y.Z4.Rls_PSBR

EN

[21SOTF.En_1PAR]

SIG

PD signal

SIG

Y.Z2.Rls_PSBR

&

&
>=1
&
&
&

[21SOTF.t_3PAR]

&
>=1

>=1
21SOTF.Op

>=1

&

&
>=1
&

&
[21SOTF.t_1PAR]

&

Figure 3.6-45 Logic diagram of distance SOTF protection by 1-pole or 3-pole AR

For single-phase permanent fault, distance SOTF protection for 1-pole reclosing onto the faulty
phase will trip three-phase circuit breaker.

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SIG

21SOTF.On

SIG

FD.Pkp

EN

[21SOTF.En_PDF]

SIG

Y.Z2.Rls_PSBR (Phase A)

SIG

PD signal (Phase A

SIG

PD signal (Phase B or C

SIG

Y.Z2.Rls_PSBR (Phase B)

SIG

PD signal (Phase B

SIG

PD signal (Phase A or C

SIG

Y.Z2.Rls_PSBR (Phase C)

SIG

PD signal (Phase C

SIG

PD signal (Phase A or B

&
&
[21SOTF.t_PDF]

21SOTF.Op_PDF

&

&

>=1

&

Figure 3.6-46 Logic diagram of distance SOTF protection by PD condition

Under pole discrepancy condition after single-phase tripping, distance SOTF protection will
accelerate to operate if another fault happens to the healthy phase.
Y: 21M or 21Q
3.6.10.4 Settings
Table 3.6-15 Settings of distance SOTF protection
No.

Name

Range

Step

Unit

Remark
Enabling/disabling distance SOTF

21SOTF.En

protection

0 or 1

0: disable
1: enable
Enabling/disabling
distance

21SOTF.Z2.En_ManCls

0 or 1

SOTF

zone

of

protection

for

manual closing
1: enable
0: disable
Enabling/disabling
distance

21SOTF.Z3.En_ManCls

0 or 1

SOTF

zone

of

protection

for

manual closing
1: enable
0: disable
Enabling/disabling

21SOTF.Z4.En_ManCls

0 or 1

distance

SOTF

zone

of

protection

for

manual closing
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1: enable
0: disable
Enabling/disabling
distance
5

21SOTF.Z2.En_3PAR

0 or 1

SOTF

zone

of

protection

for

3-pole reclosing
1: enable
0: disable
Enabling/disabling
distance

21SOTF.Z3.En_3PAR

0 or 1

SOTF

zone

of

protection

for

3-pole reclosing
1: enable
0: disable
Enabling/disabling
distance

21SOTF.Z4.En_3PAR

0 or 1

SOTF

of

protection

zone

for

3-pole reclosing
1: enable
0: disable
Enabling/disabling

zone

controlled by PSB of distance


8

21SOTF.Z2.En_PSBR

SOTF

0 or 1

protection

for

3-pole

reclosing
1: enable
0: disable
Enabling/disabling

zone

controlled by PSB of distance


9

21SOTF.Z3.En_PSBR

SOTF

0 or 1

protection

for

3-pole

reclosing
1: enable
0: disable
Enabling/disabling

zone

controlled by PSB of distance


10

21SOTF.Z4.En_PSBR

SOTF

0 or 1

protection

for

3-pole

reclosing
1: enable
0: disable
Enabling/disabling distance SOTF
protection under pole discrepancy

11

21SOTF.En_PDF

0 or 1

conditions
1: enable
0: disable
Time delay of distance protection

12

21SOTF.t_PDF

0.000~10.000

0.001

operating under pole discrepancy


conditions

13

SOTF.Opt_Mode_ManCls

0, 1 or 2

Option of manual SOTF mode

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0: initiated by input signal of
manual closing
1: initiated by CB position
2: initiated by either input signal of
manual closing or CB position
Table 3.6-16 Internal settings of distance SOTF protection
No.

Name

Default Value

Unit

Remark
Enabling/disabling distance SOTF protection for

21SOTF.En_ManCls

manual closing

0: disable
1: enable

21SOTF.t_ManCls

0.025

Time delay of distance protection accelerating to


trip when manual closing
Enabling/disabling distance SOTF protection for

21SOTF.En_3PAR

3-pole reclosing

0: disable
1: enable

21SOTF.t_3PAR

0.025

Time delay of distance protection accelerating to


trip when 3-pole reclosing
Enabling/disabling distance SOTF protection for

21SOTF.En_1PAR

1-pole reclosing

0: disable
1: enable

21SOTF.t_1PAR

0.025

Time delay of distance protection accelerating to


trip when 1-pole reclosing

3.7 Optical Pilot Channel (Option)


3.7.1 General Application
When fibre optical channel is available between the devices at both ends, the devices have an
optional module to transmit permissive signal or blocking signal (subject to the scheme selected),
transfer signal and transfer trip via the fibre ports of the module. The communication rate can be
64kbits/s or 2048kbits/s via optional dedicated optical fibre channel or multiplex channel. By the
setting [FO.Protocol], the device can support G.703 or C37.94.

3.7.2 Function Description


12 digital bits are integrated in each frame of transmission message for various applications. Each
received message frame via fibre optical channel will pass through security check to ensure the
integrity of the message consistently.
The last four digital bits of the 12 have been assigned for pilot scheme protection. The
communication channel can be configured as single channel mode or as dual channels mode.
(FOx, x can be 1 or 2) according to the optical pilot channel module selected.
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3.7.2.1 Channel Interface


The modules can communicate in two modes via multiplexer or dedicated optical fibre.
Communication through dedicated fibre is usually recommended unless the received power does
not meet with the requirement.
Channel of 64kbits/s or 2048kbits/s via dedicated fibre is shown in Figure 3.7-1 and Figure 3.7-2.
Two fibre cores of optical cable are dedicated to pilot scheme protection.
Two fibre cores of optical cable are normally in service, and all data are exchanged via the other
healthy core if one core is failed.

Max 2km for 62.5/125um multi-mode FO C37.94 (N*64kbits/s)

PCS-902

TX

RX

RX

TX

PCS-902

ST connectors

ST connectors

Figure 3.7-1 Direct optical link up to 2km with 850nm

Max 40km/100km for 9/125um single-mode FO

PCS-902

TX

RX

RX

TX

FC connectors

PCS-902

FC connectors

Figure 3.7-2 Direct optical link up to 40km with 1310nm or up to 100km with 1550nm

Channel of 64kbits/s or 2048kbits/s via multiplexer is shown in Figure 3.7-3, Figure 3.7-4 and
Figure 3.7-5.

C37.94 (N*64kbits/s)

Multi-mode FO

Communication convertor

TX

RX

RX

TX

PCS-902

ST connectors

Interface
Link to
communicate
device

ST connectors

Figure 3.7-3 Connect to a communication network via communication convertor


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G.703 (64kbits/s)

MUX-64

Single-mode FO

TX

RX

RX

TX

Interface
Link to
communicate
device

PCS-902

FC connectors

FC connectors

Figure 3.7-4 Connect to a communication network via MUX-64

G.703-E1 (2048kbits/s)

MUX-2M

Single-mode FO

TX

RX

RX

TX

Interface

PCS-902

FC connectors

Link to
communicate
device

FC connectors

Figure 3.7-5 Connect to a communication network via MUX-2M

3.7.2.2 Communication Clock


Valid messages exchange is key factor for digital pilot scheme protection.
The device transmits and receives messages based on respective clocks, which are called
transmit clock (i.e. clock TX) and receive clock (i.e. clock RX) respectively. Clock RX is fixed to be
extracted from message frame, which can ensure no slip frame and no error message received.
Clock TX has two options:
1. Use internal crystal clock, which is called internal clock. (master clock)
2. Use external clock. (slave clock)
Depend on the clock used by the device at both ends, there are three modes.
1.

Master-master mode

Both ends use internal clock.


2.

Slave-slave mode

Both ends use external clock.


3.

Master-slave mode

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One of them uses internal clock, the other uses external clock
The logic setting [FOx.En_IntClock] is used in pilot scheme protection to select the communication
clock. The internal clock is enabled automatically when the logic setting [FOx.En_IntClock] is set
as 1. Contrarily, the external clock is enabled automatically when the logic setting
[FOx.En_IntClock] is set to 0.
If the device uses multiplex PCM channel, logic setting [FOx.En_IntClock] at both ends should be
set as 0 (Mode 2). If the device uses dedicated optical fibre channel, clock Mode 1 and Mode 3
can be used. Mode 1 is recommended in considering simplification to user, i.e. logic setting
[FOx.En_IntClock] at both ends should be set as 1.
3.7.2.3 Identity Code
In order to ensure reliability of the device when digital communication channel is applied, settings
[FO.LocID] and [FO.RmtID] are provided as identity code to distinguish uniquely the device at
remote end using same channel.
Under normal conditions, the identity code of the device at local end should be different with that at
remote end. In addition, it is recommended that the identity code of all devices, i.e., the setting
[FO.LocID], should be unique in the power grid. The setting range is from 0 to 65535. Only for loop
test, they are set as the same.
The setting [FO.LocID] of the device at an end should be the same as the setting [FO.RmtID] of
the device at opposite end and the greater [FO.LocID] between the two ends is chosen as a
master end for sampling synchronism, the smaller [FO.LocID] is slave end. If the setting [FO.LocID]
is set the same as [FO.RmtID], that implies the device in loopback testing state.
The setting [FO.LocID] is packaged in the message frame and transmitted to the remote end.
When the [FO.LocID] of the device at remote end is received by local device is same to the setting
[FO.RmtID] of local device, the message received from the remote end is valid, and protection
information involved in message is read. When these settings are not matched, the message is
considered as invalid and protection information involved in message is ignored, corresponding
alarms will be issued.
3.7.2.4 Channel Statistics
The device has the function of on-line channel monitoring and channel statistics. It can produce
channel statistic report automatically at 9:00 every day and the report can be printed for operator
to check the channel quality. The monitoring contents of channel status are shown as follows, and
they can be viewed by the menu Main MenuTestProt Ch CountChx Counter.
1.

FOx.Start_Time (starting time)

It shows the starting time of the channel status statistics of the device at local end.
2.

FO.RmtID (ID code of the remote end)

It shows the ID information received by the device at local end now.


3.

FOx.t_ChLag (propagation delay of channel x)

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It shows the calculated communication channel time delay of the device at local end now (unit: us).
The calculation is based on the assumption of same channel path for to and from remote end. The
device measures propagation delay of communication channel based on the below principle.
Side S transmits a frame of message to side M, and meanwhile records the transmitting time tss
on the basis of clock on side S. When side M receives the message, it will record receiving time
tmr of the message with its own clock, and return a frame of message to side S at next fixed
transmitting time, meanwhile data of tms-tmr is included in the frame of message. Side S will
receive the message from side M at the time tsr and obtain the data of tms-tmr.
Therefore, the propagation delay of the channel Td is obtained through calculation:

Td

(t sr t ss ) (t ms t mr )
2

By using the above calculated Td, the device automatically compensate time synchronization of
sampling data at each end and transimission time lag.

T1

tss

tsr

tmr
Td

tms

"S"

"M"

T2

Figure 3.7-6 Schematic diagram of communication channel time

4.

FOx.N_CRCFail (total number of error frame of channel x)

It shows the total number of the error frames of the device at local end from starting time of
channel statistics until now. Error frame means that this frame fails in CRC check.
5.

FOx.N_FramErr (total number of abnormal messages of channel x)

It shows the total number of abnormal messages of the device at local end from starting time of
channel statistics until now.
6.

FOx.N_FramLoss (total number of lost frames of channel x)

It shows the total number of the lost frames of the device at local end from starting time of channel
statistics until now.
7.

FOx.N_RmtAbnor (total number of abnormal messages from the remote end of channel x)

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It shows the total number of abnormal messages received from the remote end from starting time
of channel statistics until now.
8.

FOx.N_CRCFailSec (total number of serious error frames of channel x)

It shows the total number of serious error frame seconds of the device at local end from starting
time of the channel statistics until now.
9.

FOx.N_LossSyn (total number of loss synchronous of channel x)

It shows the total number of loss synchronous of the device at local end from starting time of the
channel statistics until now.

3.7.3 Function Block Diagram


FOx
FOx.En

FOx.On

FOx.Send1

FOx.Recv1

FOx.Send2

FOx.Recv2

FOx.Send3

FOx.Recv3

FOx.Send4

FOx.Recv4

FOx.Send5

FOx.Recv5

FOx.Send6

FOx.Recv6

FOx.Send7

FOx.Recv7

FOx.Send8

FOx.Recv8
FOx.Alm
FOx.Alm_ID

3.7.4 I/O Signals


Table 3.7-1 I/O signals of pilot channel
No.

Input Signal

Description

FOx.En

Enabling channel x

FOx.Send1

Sending signal 1 of channel x

FOx.Send2

Sending signal 2 of channel x

FOx.Send3

Sending signal 3 of channel x

FOx.Send4

Sending signal 4 of channel x

FOx.Send5

Sending signal 5 of channel x

FOx.Send6

Sending signal 6 of channel x

FOx.Send7

Sending signal 7 of channel x

FOx.Send8

Sending signal 8 of channel x

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Sending signal 9 of channel x (it is configured fixedly as sending permissive
10

FOx.Send9

signal 1 or sending A-phase permissive signal (only for phase-segregated


command scheme))

11

FOx.Send10

12

FOx.Send11

Sending signal 10 of channel x (it is configured fixedly as sending B-phase


permissive signal (only for phase-segregated command scheme))
Sending signal 11 of channel x (it is configured fixedly as sending C-phase
permissive signal (only for phase-segregated command scheme))
Sending signal 12 of channel x (it is configured fixedly as sending permissive

13

FOx.Send12

signal 1 when pilot directional earth-fault protection sharing pilot channel 1 with
pilot distance protection, or sending permissive signal 2 only for pilot directional
earth-fault protection adopting independent pilot channel 2)

No.

Output Signal

Description

FOx.On

Channel x is enabled.

FOx.Recv1

Receiving signal 1 of channel x

FOx.Recv2

Receiving signal 2 of channel x

FOx.Recv3

Receiving signal 3 of channel x

FOx.Recv4

Receiving signal 4 of channel x

FOx.Recv5

Receiving signal 5 of channel x

FOx.Recv6

Receiving signal 6 of channel x

FOx.Recv7

Receiving signal 7 of channel x

FOx.Recv8

Receiving signal 8 of channel x


Receiving signal 9 of channel x (it is configured fixedly as receiving permissive

10

FOx.Recv9

signal via channel No.1, or receiving permissive signal of A-phase via channel
No.1 (only for phase-segregated command scheme))
Receiving signal 10 of channel x (it is configured fixedly as receiving permissive

11

FOx.Recv10

signal of B-phase via channel No.1 (only for phase-segregated command


scheme))
Receiving signal 11 of channel x (it is configured fixedly as receiving permissive

12

FOx.Recv11

signal of C-phase via channel No.1 (only for phase-segregated command


scheme))
Receiving signal 12 of channel x (it is configured fixedly as receiving permissive

13

FOx.Recv12

signal 1 when pilot directional earth-fault protection sharing pilot channel 1 with
pilot distance protection, or receiving permissive signal 2 only for pilot
directional earth-fault protection adopting independent pilot channel 2)

14

FOx.Alm

15

FOx.Alm_ID

Channel x is abnormal
Received ID from the remote end is not as same as the setting [FO.RmtID] of
the device in local end

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3.7.5 Logic
SIG

Receiving transfer signal n from remote side

SIG

FOx.Alm

SIG

FOx.Alm_ID

SIG

FOx.En

EN

FOx.En

&
FOx.Recvn

>=1

&
FOx.On

Figure 3.7-7 Logic diagram of receiving signal n

Where:
n can be 1~12

3.7.6 Settings
Table 3.7-2 Settings of pilot channel
No.

Name

Range

Step

Unit

Remark

FO.LocID

0-65535

Identity code of the device at local end

FO.RmtID

0-65535

Identity code of the device at remote end

FO.Protocol

FOx.BaudRate

G.703

It is used to select protocol type, G.703 or

C37.94

C37.94

64 or 2048

kbps

Baud rate of optical pilot channel x


Option of internal clock or external clock

FOx.En_IntClock

0 or 1

0: external clock
1: internal clock
Enabling/disabling channel x

FOx.En

0 or 1

0: disable
1: enable

3.8 Pilot Distance Protection


3.8.1 General Application
The instant distance protection with underreaching setting is impossible to isolate the fault at
remote end of the line, while distance protection with overreaching setting needs a time delay to
grade with downstream protection to maintain discrimination. Pilot distance protection that
exchanges distance protection information at both ends of the line can remove the fault within this
line quickly, and will not operate for external fault.
Pilot distance protection requires communication channel to exchange protection information at
both ends. The channel may be dedicated or multiplexed channel through optical fiber or any other
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communication media. Pilot distance protection has schemes of permissive underreaching


transfer trip (PUTT), permissive overreaching transfer trip (POTT) and blocking.

3.8.2 Function Description


Pilot distance protection determines whether it will send the signal to the remote end according to
the discrimination result of the distance element or direction element. Pilot distance protection can
be divided into permissive scheme and blocking scheme according to whether the signal sent is
used to permit tripping or block tripping. For permissive scheme, it can be divided into
overreaching mode or underreaching mode according to the setting of distance element and
scheme selected, furthermore, it will provide the unblocking scheme as auxiliary function. For
overreaching mode, current reversal logic and weak infeed logic are available for parallel line
operation and weak power source situation respectively.
Pilot distance protection with permissive scheme receives permissive signal from the remote end,
so as to combine with local discrimination condition to accelerate tripping, so it has high security.
Blocking scheme will operate with a short time delay [85.t_DPU_Blocking1] if forward pilot zone
element operates and not receiving blocking signal before the short time delay expired.
Pilot distance protection can be enabled or disabled by input signals, logic setting and blocking
signal, as shown in Figure 3.8-1.
SIG

85.Z.En1

SIG

85.Z.En2

EN

[85.Z.En]

SIG

&
&
85.Z.On

85.Z.Blk

Figure 3.8-1 Enabling/disabling logic of pilot distance protection

Pilot distance protection receives and sends signals via pilot channel, and the logic of receiving
signal is shown in Figure 3.8-2.
SET

85.Blocking

&
>=1
Valid_Recv1

SIG

85.Recv1

SIG

85.Abnor_Ch1

SIG

Unblocking1 Valid

EN

[85.PUTT]

EN

[85.POTT]

&
>=1

&
>=1

Figure 3.8-2 Logic diagram of receiving signal

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Pilot distance protection has the following application modes:


3.8.2.1 Zone Extension
When pilot scheme protection is out of service due to pilot channel failure or no pilot scheme
protection is provided. The fault outside zone 1 only can be cleared by zone 2 with a time delay. It
can not ensure that all faults within protected line are cleared instantaneously. As a supplement of
pilot scheme protection, zone extension can clear the fault within the whole line instantaneously.
Different with pilot distance protection, zone extension can also operate for external close up fault
in parallel line, but power supply can be restored by AR. So zone extension should be blocked
when AR is out of service and is not ready.
In order to prevent too many lines from disconnecting with system due to zone extension operate
when the circuit breaker is closed into permanent fault, zone extension should be blocked when
AR operates. For temporary fault, the line can be into service again after AR operates successfully.
For permanent fault in either local line or parallel line, distance protection with a time delay will
operate.
SIG

FD.Pkp

SIG

85.ZX.En1

SIG

85.ZX.En2

EN

[85.ZX.En]

SIG

85.ZX.Blk1

SIG

85.ZX.Blk2

SIG

79.Ready

SIG

Zpilot

&
&
&
85.ZX.On

>=1
&
[85.t_DPU_ZX]

&

0ms

85.Op_ZX

Figure 3.8-3 Zone extension

Zone extension uses the setting of pilot zone (ZPilot), and its operation characteristic can be Mho
or Quad.
3.8.2.2 Permissive Underreaching Transfer Trip (PUTT)
Distance elements zone 1 (Z1) with underreaching setting and pilot zone (ZPilot) with
overreaching setting are used for this scheme. Z1 element will send permissive signal to the
remote end and release tripping after Z1 time delay expired. After receiving permissive signal with
ZPilot element pickup, a tripping signal will be released.
The signal transmission element for PUTT is set according to underreaching mode, so current
reversal need not be considered.
For PUTT, there may be a dead zone under weak power source condition. If the fault occurs
outside Z1 zone at strong power source side, Z1 at weak power supply side may not operate to trip
and transmit permissive signal, and pilot distance protection will not operate. Therefore, the
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system fault can only be removed by Z2 at strong power source side with time delay.
ZPilot
Z2
Z1
M

EM

Fault

Z1

EN

Z2
ZPilot

Relay A

Relay B

Z1

Z1

&

&
85.Op_Z

85.Op_Z

ZPilot

ZPilot

Figure 3.8-4 Simple schematic of PUTT

Pilot distance protection always adopts pilot channel 1, and the logic of PUTT is shown in Figure
3.8-5.
SIG

21M/21Q.Z1.Op

0ms

100ms

SIG

85.ExTrp

0ms

150ms

SET

85.PUTT

&

SIG

85.Z.On

SIG

FD.Pkp

SIG

Valid_Recv1

SIG

ZPilot

>=1
&
Send1

&
&
8ms

0ms

85.Op_Z

Figure 3.8-5 Logic diagram of pilot distance protection (PUTT)

3.8.2.3 Permissive Overreaching Transfer Trip (POTT)


ZPilot will send permissive signal to remote end once it picks up and release tripping signal upon
receiving permissive signal from the remote end.
When POTT is applied on parallel lines arrangement and the ZPilot setting covers 50% of the
parallel line, there may be a problem under current reversal condition, settings for current reversal
condition should be considered, please refer to section 3.8.2.6 for details.

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Under weak power source condition, the problem of dead zone at weak power source end is
eliminated by the weak infeed logic, please refers to section 3.8.2.7 for details.
ZPilot
Z2

EM

Zpilot_Rev
A

Fault

EN

N
Zpilot_Rev

Z2
ZPilot

Relay A
ZPilot

&
85.Op_Z

>=1

Relay B

&
85.Op_Z

>=1

WI

ZPilot

WI

Figure 3.8-6 Simple schematic of POTT


SIG

Zpilot

SIG

85.ExTrp

SIG

CB open position

SIG

Valid_Recv1

0ms

150ms

>=1

&

&
200ms

0ms

&
Send1

SIG

ZPilot

SIG

85.Z.On

SIG

WI

&

&
>=1

&
t1

t2

&
85.Op_Z

&
SIG

FD.Pkp

SET

[85.POTT]

8ms

0ms

Figure 3.8-7 Logic diagram of pilot distance protection (POTT)

Where:
t1: pickup time delay of current reversal, the setting [85.t_DPU_CR1]
t2: dropoff time delay of current reversal, the setting [85.t_DDO_CR1]

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3.8.2.4 Blocking
Permissive scheme has high security, but it relies on pilot channel seriously. Pilot distance
protection will not operate when there is an internal fault with abnormal channel. Blocking scheme
could be considered as an alternative.
Blocking scheme takes use of pilot distance element Zpilot operation to terminate sending of
blocking signal. Blocking signal will be sent once fault detector picks up without pilot zone Zpilot
operation. Pilot distance protection will operate with a short time delay if pilot distance element
operates and not receiving blocking signal after timer expired.
The setting of pilot zone element Zpilot in Blocking scheme is overreaching, so current reversal
condition should be considered. However, the short time delay of pilot distance protection has an
enough margin for current reversal, that this problem has been resolved.
The short time delay must consider channel delay and with a certain margin to set. As shown in
Figure 3.8-8, an external fault happens to line MN. The fault is behind the device at M side, for
blocking scheme, the device at M side will send blocking signal to the device at N side. If channel
delay is too long, the device at side N has operated before receiving blocking signal. Hence, the
time delay of pilot distance protection adopted in blocking scheme should be set according to
channel delay.
Blocking signal
EM

Fault

EN

Figure 3.8-8 Simple schematic of system fault

For blocking scheme, pilot distance protection will operate when there is an internal fault with
abnormal channel, however, it is possible that pilot distance protection issue an undesired trip
when there is an external fault with abnormal channel.
ZPilot

EM

Zpilot_Rev
A

Fault

EN

Zpilot_Rev
ZPilot

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Relay A

Relay B

FD.Pkp

&

Zpilot

&
[85.t_DPU_Blocking1]

85.Op_Z

85.Op_Z

&

FD.Pkp

&

Zpilot

[85.t_DPU_Blocking1]

Figure 3.8-9 Simple schematic of blocking

SIG

Zpilot

SIG

85.ExTrp

0ms

150ms

&
SIG

CB open position

&
200ms

SIG

>=1

0ms

&

Valid_Recv1

Send1

&
SIG

FwdDir_ZPilot

SIG

WI

SIG

FD.Pkp

SET

85.Blocking

SIG

85.Z.On

>=1
&
[85.t_DPU_Blocking1]

85.Op_Z

&

Figure 3.8-10 Logic diagram of pilot distance protection (Blocking)

Current reversal logic is only used for permissive scheme. For blocking scheme, the time delay of
pilot distance protection has enough margin for current reversal, so current reversal need not be
considered.
3.8.2.5 Unblocking
Permissive scheme will trip only when it receives permissive signal from the remote end. However,
it may not receive permissive signal from the remote end when pilot channel fails. For this case,
pilot distance protection can adopt unblocking scheme. Under normal conditions, the signaling
equipment works in the pilot frequency, and when the device operates to send permissive signal,
the signaling equipment will be switched to high frequency. While pilot channel is blocked, the
signaling equipment will receive neither pilot frequency signal nor high frequency signal. The
signaling equipment will provide a contact to the device as unblocking signal. When the device
receives unblocking signal from the signaling equipment, it will recognize channel failure, and
unblocking signal will be taken as permissive signal temporarily.
The unblocking function can only be used together with PUTT and POTT.

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SIG

[85.En_Unblocking1]

SIG

85.Unblocking1

&
&
[85.t_Unblocking1] 0ms

SIG

Detecting multi-phase fault

EN

[85.Opt_PilotCh1]

SIG

Pilot distance forward element

>=1
&
Unblocking1 Valid

Figure 3.8-11 Logic diagram of pilot distance protection (Unblocking)

3.8.2.6 Current Reversal


When there is a fault in one of the parallel lines, the direction of the fault current may change
during the sequence tripping of the circuit breaker at both ends as shown in Figure 3.8-12: When a
fault occurs on line CD near breaker D, the fault current through line A-B to D will flow from A to B.
When breaker D is tripped, but breaker C is not tripped, the fault current in line A-B will then flow
from B to A. This process is the current reversal.
M
Strong
source
EM

N
A

M
Weak
source
EN

N
A

B
EN

EM

Direction of fault current


flow before CBDopen

Direction of fault current


flow after CBDopen

Figure 3.8-12 Current reversal

As shown above, the device A judges a forward fault while the device B judges a reverse fault
before break D is tripped. However, the device A judges a reverse fault while the device B judges a
forward fault after breaker D is tripped. There is a competition between pickup and drop off of pilot
zones in the device A and the device B when the fault measured by the device A changes from
forward direction into reverse direction and vice versa for the device B. There may be
maloperation for the device in line A-B if the forward direction of the device B has operated but the
forward direction of the device A drops off slightly slower or the forward direction of the device B
has operated but the forward direction information of the device A is still received due to the
channel delay (the permissive signal is received).
In general, the following two methods shall be adopted to solve the problem of current reversal:
1.

The fault shall be measured by means of the reverse element of the device B. Once the
reverse element of the device B operates, the send signals and the tripping circuit will be
blocked for a period of time after a short time delay. This method can effectively solve the
problem of competition between the device A and the device B, but there shall be a
precondition. The reverse element of the device B must be in cooperation with the forward
element of the device A, i.e. in case of a fault in adjacent lines, if the forward element of the
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device A operates, and the reverse element of the device B must also operate. Once the
bilateral cooperation fails, the anticipated function cannot be achieved. In addition, the
blocking time for sending signals and the tripping circuit after the reverse element of the
device B operates shall be set in combination with the channel time delay.
2.

Considering the pickup and drop off time difference of distance elements and the channel time
delay between the device A and the device B, the maloperation due to current reversal shall
be eliminated by setting the time delay. The reverse direction element of the device is not
required for this method, the channel time delay and the tripping time of adjacent breaker
shall be taken into account comprehensively.

This protection device adopts the second method to eliminate the maloperation due to current
reversal.
SIG

Pilot forward zone start condition

SIG

Signal received conditon

&
t1

t2

Current reversal blocking

Figure 3.8-13 Logic diagram of current reversal blocking

t1: [85.t_DPU_CR1]
t2: [85.t_DDO_CR1]
Referring to above figure, when signal from the remote end is received without pilot forward zone
pickup, the current reversal blocking logic is enabled after t1 delay.
The time delay of t1 [85.t_DPU_CR1] shall be set the shortest possible but allowing sufficient time
for pilot forward zone pickup, generally set as 25ms.
Once the current reversal logic is enabled, the healthy line device B transfer tripping is blocked.
The logic will be disabled by either the dropoff of signal or the pickup of pilot forward zone. A time
delay t2 [85.t_DDO_CR1] is required to avoid maloperation for the case that the pilot forward zone
(or forward element of pilot directional earth-fault protection) of device B picks up before the signal
from device A drops off. Considering the channel propagation delay and the pickup and drop-off
time difference of pilot forward zone (or pilot directional earth-fault element) with margin, t2 is
generally set between 25ms~40ms.
Because the time delay of pilot distance protection has an enough margin to current reversal,
current reversal blocking only used for permissive scheme not blocking scheme.
3.8.2.7 Weak Infeed
In case of a fault in line at one end of which there is a weak power source, the fault current
supplied to the fault point from the weak power source is very small or even nil, and the
conventional distance element could not operate. The weak infeed logic combines the protection
information from the strong power source end and the electric feature of the local end to cope with
the case.
The weak infeed logic can be only applied for BOTT and POTT. The weak infeed logic has options
for echo or both echo and tripping.
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ZPilot
Z1
M

EM

Fault

Zpilot_Rev
B

Z1

Zpilot_Rev

EN

ZPilot
Load

Figure 3.8-14 Line fault description

When the weak infeed logic is enabled, distance forward and reverse element and direction
element of directional earth-fault protection do not operate with the voltage lower than the setting
[85.U_UV_WI] after the device picks up, upon receiving signal from remote end, the weak infeed
logic will echo the signal back to remote end for 200ms if the weak infeed echo is enabled, the
weak infeed end will echo signal and release tripping according to the logic.
ZPilot_Rev at weak source end must coordinate with ZPilot_Set of the remote end. The coverage
of ZPilot_Rev must exceed that of ZPilot_Set of the remote end. ZPilot_Rev only activates in the
protection calculation when the weak infeed logic is enabled. In case of the weak infeed logic not
enabled, the setting coordination is not required.
If the device does not pick up, and the weak infeed logic is enabled, upon receiving signal from
remote end with the voltage lower than the setting [85.U_UV_WI], the weak infeed logic will echo
back to remote end for 200ms. When either weak infeed echo or weak infeed tripping is enabled,
then the weak infeed logic is deemed to be enabled. During the device picking up, the weak infeed
logic is shown in Figure 3.8-15.
SIG

FD.Pkp

SIG

Valid_Recv1

SIG

Pilot DEF forward direction

SIG

Pilot DEF reverse direction

SIG

Pilot distance forward direction

SIG

Pilot distance reverse direction

EN

[85.En_WI]

SET

Up<[85.U_UV_WI]

SET

Upp<[85.U_UV_WI]

>=1
&

&
Forward direction (WI)

>=1

>=1

200ms

0ms

&

Figure 3.8-15 Weak infeed logic during pickup

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If the device does not pick up, the weak infeed logic is shown as the following figure:
SIG

Signal receive condition

EN

[85.En_WI]

SET

Up<[85.U_UV_WI]

&
&
WI echo

>=1
200ms

SET

0ms

&

Upp<[85.U_UV_WI]

Figure 3.8-16 Weak infeed logic without pickup

For permissive scheme, the signal receive condition means that the permissive signal is received
or the unblocking signal is valid.
3.8.2.8 CB Echo
A feature is also provided which enables fast tripping to be maintained along the whole length of
the protected line, even when one terminal is open. The device will initiate sending a pulse of
200ms permissive signal when signal receive condition is met during CB is in open position.
SIG

FD.Pkp

SIG

CB open position

SIG

Valid_Recv1

EN

85.POTT

&
&
200ms

0ms

&
Send permissive signal

&

Figure 3.8-17 Simplified CB Echo logic for POTT

CB Echo logic is only applied to permissive overreach mode not underreach mode, and it is
processed without the device pickup. This logic will be terminated immediately once the device
picks up.

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3.8.3 Function Block Diagram


85
85.Z.En1

85.Z.On

85.Z.En2

85.ZX.On

85.Z.Blk

85.Op_Z

85.Abnor_Ch1

85.Send1

85.Rcv1

85.SendB

85.RcvB

85.SendC

85.RcvC

85.Op_ZX

85.ExTrp

85.ZX_St

85.Unblocking1
85.ZX.En1
85.ZX.En2
85.ZX.Blk1
85.ZX.Blk2
79.Ready

3.8.4 I/O Signals


Table 3.8-1 I/O signals of pilot distance protection
No.

Input Signal

85.Z.En1

85.Z.En2

85.Z.Blk

85.Abnor_Ch1

Description
Pilot distance protection enabling input 1, it is triggered from binary input or
programmable logic etc.
Pilot distance protection enabling input 2, it is triggered from binary input or
programmable logic etc.
Pilot distance protection blocking input, it is triggered from binary input or
programmable logic etc.
Input signal of indicating that pilot channel 1 is abnormal
Input signal of receiving permissive signal via channel No.1, or input signal of

85.Recv1

receiving

permissive

signal

of

A-phase

via

channel

No.1

(only

for

phase-segregated command scheme)


6

85.RecvB

85.RecvC

85.ExTrp

Input signal of receiving permissive signal of B-phase via channel No.1 (only for
phase-segregated command scheme)
Input signal of receiving permissive signal of C-phase via channel No.1 (only for
phase-segregated command scheme)
Input signal of initiating sending permissive signal from external tripping signal

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9

85.Unblocking1

10

85.ZX.En1

11

85.ZX.En2

12

85.ZX.Blk1

13

85.ZX.Blk2

14

79.Ready

No.

Unblocking signal 1
Zone Extension enabling input 1, it is triggered from binary input or programmable
logic etc.
Zone Extension enabling input 2, it is triggered from binary input or programmable
logic etc.
Zone Extension blocking input 1, it is triggered from binary input or programmable
logic etc.
Zone Extension blocking input 2, it is triggered from binary input or programmable
logic etc.
AR has been ready for reclosing cycle.

Output Signal

Description

85.Z.On

Pilot distance protection is enabled.

85.ZX.On

Zone extension protection is enabled.

85.Op_Z

Pilot distance protection operates.

85.Send1

85.SendB

85.SendC

85.Op_ZX

Zone extension protection operates.

85.ZX_St

Zone extension protection starts

Output signal of sending permissive signal 1 or sending A-phase permissive


signal (only for phase-segregated command scheme)
Output signal of sending B-phase permissive signal (only for phase-segregated
command scheme)
Output signal of sending C-phase permissive signal (only for phase-segregated
command scheme)

3.8.5 Settings
Table 3.8-2 Settings of pilot distance protection
No.

Name

Range

Step

Unit

Remark
Option of pilot scheme

85.Opt_PilotMode

0~2

0: POTT

1: PUTT
2: Blocking
Option

of

phase-segregated

signal scheme or three-phase


2

85.Opt_Ch_PhSeg

signal scheme

0 or 1

0: three-phase signal scheme


1:

phase-segregated

signal

scheme
Enabling/disabling weak infeed
3

85.En_WI

scheme

0 or 1

0: disable
1: enable

85.U_UV_WI

0~Unn

85.Z.En

0 or 1

0.001

Undervoltage setting of weak


infeed logic
Enabling/disabling

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distance protection
0: disable
1: enable
Enabling/disabling unblocking
6

85.En_Unblocking1

scheme

0 or 1

0: disable
1: enable
Time

85.t_DPU_Blocking1

0.000~1.000

0.001

delay

scheme

of

for

blocking

pilot

distance

protection operation
8

85.t_DDO_CR1

0.000~1.000

0.001

85.t_DPU_CR1

0.000~1.000

0.001

Time delay dropoff for current


reversal logic
Time delay pickup for current
reversal logic
Enabling/disabling

10

85.ZX.En

zone

extension protection

0 or 1

0: disable
1: enable

11

85.t_DPU_ZX

0.000~10.000

0.001

Pickup time delay for zone


extension protection operation

Table 3.8-3 Internal settings of pilot distance protection


No.
1

Name
85.t_Unblocking1

Default Value
0.1

Unit
s

Remark
Pickup time delay of unblocking scheme for pilot
channel 1
Option of PLC channel for pilot channel 1

85.Opt_PilotCh1

0: phase-to-phase channel
1: phase-to-ground channel

3.9 Pilot Directional Earth-fault Protection


3.9.1 General Application
Directional earth fault protection needs to coordinate with downstream protection with definite or
inverse time delay so it cannot clear an internal fault quickly. Pilot directional earth-fault protection
takes use of directional earth fault elements on both ends, it can detect high resistance fault and
maintain high-speed operation.
Pilot protection requires communication channel to exchange the protection information at both
ends. The channel may be dedicated or multiplexed channel through optical fiber or any other
communication media.
Pilot directional earth-fault protection can be used independently, for example, no distance
protection is equipped with the device but fast operation is required for the whole line, or it is used
as backup protection of pilot distance protection to enhance the sensitivity for an earth fault with
high fault resistance.
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3.9.2 Function Description


Sending permissive signal (or terminating sending signal) to the opposite end is controlled by
forward direction element. Current reversal logic is available for parallel line operation and CB
echo logic is provided once pilot directional earth fault protection is enabled. Current reversal logic
is only used for permissive scheme. For blocking scheme, current reversal need not be considered
because there is a settable time delay in pilot directional earth-fault protection.
Pilot directional earth-fault protection can be enabled or disabled by input signals, logic setting and
blocking signal, as shown in Figure 3.9-1.
SIG

85.DEF.En1

SIG

85.DEF.En2

EN

[85.DEF.En]

SIG

85.DEF.Blk

&
&
85.DEF.On

Figure 3.9-1 Enabling/disabling logic of pilot directional earth-fault protection

Pilot directional earth-fault protection comprises permissive scheme and blocking scheme. It can
share pilot channel 1 ([85.DEF.En_IndepCh]=0) with pilot distance protection, or uses independent
pilot channel 2 ([85.DEF.En_IndepCh]=1) by setting logic setting [85.DEF.En_IndepCh]. For
underreach mode, pilot directional earth-fault always adopts independent pilot channel 2. The
logic of receiving signal is shown in Figure 3.9-2.
SET

85.Blocking

SIG

85.Recv1

&
>=1
&

SIG

85.Abnor_Ch1

SIG

Unblocking1 Valid

SET

85.PUTT

&
>=1

>=1
Valid_Recv_DEF

EN

[85.DEF.En_IndepCh]

SET

85.Blocking

&

&
>=1

SIG

85.Recv2

SIG

85.Abnor_Ch2

SIG

Unblocking2 Valid

&

Figure 3.9-2 Logic diagram of receiving signal

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SIG

FwdDir_ROC

&
85.FwdDir_DEF_Pilot

SIG

3I0>[85.DEF.3I0_Set]

SIG

RevDir_ROC

&
85.RevDir_DEF_Pilot

SIG

FD.ROC.Pkp

Figure 3.9-3 Forward/reverse direction of zero-sequence power

3.9.2.1 Permissive Transfer Trip (PTT)


Pilot protection with permissive scheme receives permissive signal from the device of remote end,
so as to combine with local discrimination condition to accelerate tripping, so it has high security.
Operation of forward directional earth fault element is used to send permissive signal to the
remote end when the protection is enabled and will release tripping signal upon receiving
permissive signal from the remote end with further guarded by no operation of reverse directional
earth fault element. This ensures the security of the protection.
The following figure shows the schematic of permissive transfer trip.
FWD_DEF_Pilot

EM

Rev_DEF_Pilot
A

Fault

EN

Rev_DEF_Pilot
FWD_DEF_Pilot

Relay A
FWD_DEF_Pilot

&

&
85.DEF.t_DPU

85.Op_DEF

85.Op_DEF

85.DEF.t_DPU
FWD_DEF_Pilot
Relay B

Figure 3.9-4 Simple schematic of DEF (permissive scheme)

For blocking scheme, pilot directional earth-fault protection will operate when there is an internal
fault with abnormal channel, however, it is possible that pilot directional earth-fault protection issue
an undesired trip when there is an external fault with abnormal channel.

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SIG

[85.ExTrp]

SIG

CB open position

SIG

Valid_Recv_DEF

SIG

FD.Pkp

SIG

85.FwdDir_DEF_Pilot

SIG

85.RevDir_DEF_Pilot

SIG

Valid_Recv_DEF

SIG

FD.Pkp

SET

85.PUTT

SET

85.POTT

SIG

85.DEF.On

0ms

150ms

&

>=1

&
200ms

0ms

&
85.Send_DEF

&
&
&
t1

t2

&
>=1
&
&

&
[85.DEF.t_DPU]

>=1

85.Op_DEF

&
EN

85.DEF.En_IndepCh

Figure 3.9-5 Logic diagram of DEF (permissive scheme)

t1: pickup time delay of current reversal


t2: dropoff time delay of current reversal
When adopting independent pilot channel 2, settings of t1
[85.t_DDO_CR2] should be considered individually from channel 1.

[85.t_DPU_CR2] and t2

When sharing pilot channel 1 with pilot distance protection, t1 and t2 are the settings
[85.t_DPU_CR1] and [85.t_DDO_CR1] respectively.
3.9.2.2 Blocking
Permissive scheme has high security, but it relies on pilot channel seriously. Pilot directional
earth-fault protection will not operate when there is an internal fault with abnormal channel.
Blocking scheme could be considered as an alternative.
Blocking scheme sends blocking signal when fault detector picks up if and zero-sequence forward
element does not operate or both zero-sequence forward element and zero-sequence reverse
element do not operate. Pilot directional earth-fault protection will operate if forward directional
zero-sequence overcurrent element operates and not receiving blocking signal.

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FWD_DEF_Pilot
Rev_DEF_Pilot

EM

Fault

EN

Rev_DEF_Pilot
FWD_DEF_Pilot

Relay B

Relay A
Pkp_FD_Prot

Pkp_FD_Prot

&
REV_DEF_Pilot

&

&

REV_DEF_Pilot

&

FWD_DEF_Pilot

FWD_DEF_Pilot

&

&
85.Op_DEF

&

85.Op_DEF

&

[t_DEF_PilotP]

[t_DEF_PilotP]

Figure 3.9-6 Simple schematic of blocking


SIG

Trp

SIG

85.ExTrp

SIG

CB open position

SIG

Valid_Recv_DEF

SIG

85.FwdDir_DEF_Pilot

SIG

85.RevDir_DEF_Pilot

SIG

FD.Pkp

SET

85.Blocking

SIG

85.DEF.On

>=1
0ms

150ms

>=1
&
Send_DEF

&
&
&
[85.DEF.t_DPU]

85.Op_DEF

&

Figure 3.9-7 Logic diagram of DEF (Blocking scheme)

When DEF shares pilot channel 1 with pilot distance protection, time delay of pilot directional
earth-fault protection will change from the setting [85.DEF.t_DPU] to the setting
[85.t_DPU_Blocking1].
Because the time delay of pilot directional earth-fault protection has enough margin for current
reversal, so blocking scheme should not consider the current reversal condition.

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3.9.2.3 Unblocking
Permissive scheme will operate only when it receives permissive signal from the remote end.
However, it may not receive permissive signal from the remote end when pilot channel fails. For
this case, pilot directional earth-fault protection can adopt unblocking scheme. Under normal
conditions, the signaling equipment works in the pilot frequency, and when the device operates to
send permissive signal, the signaling equipment will be switched to high frequency. While the
channel is blocked, the signaling equipment will receive neither pilot frequency signal nor high
frequency signal. The signaling equipment will provide a contact to the device as unblocking signal.
When the device receives unblocking signal from the signaling equipment, it will recognize
channel failure, and unblocking signal will be taken as permissive signal temporarily.
The unblocking scheme can only be used together with permissive scheme.
EN

[85.En_Unblocking2]

BI

85.Unblocking2

&
&
&
[85.t_Unblocking2]

SIG

Selection of multi-phase

EN

[85.Opt_PilotCh2]

SIG

Pilot DEF forward detection

Unblocking2 Valid

0ms

>=1

Figure 3.9-8 Logic diagram for unblocking

3.9.2.4 Current Reversal


The reach of directional earth-fault protection is difficult to define. There may have problem for
pilot direction earth-fault protection applied on parallel line arrangement due to current reversal
phenomenon. Current reversal blocking logic using time delay method is adopted in the device. It
is the same logic as pilot distance protection. Please refer to section 3.8.2.6 for details. The only
difference is that different signal receive terminal is used if independent channel is selected.
3.9.2.5 CB Echo
It is the same logic as pilot distance protection. Please refer to section 3.8.2.8 for details. The only
difference is that different signal receive terminal is used if independent channel is selected.

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3.9.3 Function Block Diagram


85
85.DEF.En1

85.DEF.On

85.DEF.En2

85.Op_DEF

85.DEF.Blk

85.DEF_BlkAR

85.Abnor_Ch1

85.Send1

85.Abnor_Ch2

85.Send2

85.Rcv1
85.Rcv2
85.ExTrp
85.Unblocking1
85.Unblocking2

3.9.4 I/O Signals


Table 3.9-1 I/O signals of pilot directional earth-fault protection
No.

Input Signal

Description
Pilot directional earth-fault protection enabling input 1, it is triggered from binary

85.DEF.En1

85.DEF.En2

85.DEF.Blk

85.Abnor_Ch1

Input signal of indicating that pilot channel 1 is abnormal

85.Abnor_Ch2

Input signal of indicating that pilot channel 2 is abnormal

85.Recv1

Input signal of receiving permissive signal via channel 1

85.Recv2

Input signal of receiving permissive signal via channel 2

85.ExTrp

Input signal of initiating sending permissive signal from external tripping signal

85.Unblocking1

Unblocking signal 1

10

85.Unblocking2

Unblocking signal 2

No.

input or programmable logic etc.


Pilot directional earth-fault protection enabling input 2, it is triggered from binary
input or programmable logic etc.
Pilot directional earth-fault protection blocking input, it is triggered from binary
input or programmable logic etc.

Output Signal

Description

85.DEF.On

Pilot directional earth-fault protection is enabled.

85.Op_DEF

Pilot directional earth-fault protection operates.

85.DEF_BlkAR

Pilot directional earth-fault protection operates to block AR.

85.Send1

85.Send2

Output signal of sending permissive signal 1 when pilot directional earth-fault


protection sharing pilot channel 1 with pilot distance protection
Output signal of sending permissive signal 2 only for pilot directional earth-fault
protection adopting independent pilot channel 2

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3.9.5 Settings
Table 3.9-2 Settings of pilot directional earth-fault protection
No.

Name

Range

Step

Unit

Remark
Enabling/disabling pilot directional

85.DEF.En

earth-fault protection

0 or 1

0: disable
1: enable
Enabling/disabling pilot directional
earth-fault protection operate to
block AR

85.DEF.En_BlkAR

0 or 1

0: selective phase tripping and not


blocking AR
1: three-phase tripping and blocking
AR
Enabling/disabling
channel

for

independent

pilot

directional

earth-fault protection
3

85.DEF_En_IndepCh

0:

0 or 1

pilot

directional

earth-fault

protection sharing same channel


with pilot distance protection
1:

pilot

directional

earth-fault

adopting independent pilot channel


Enabling/disabling

unblocking

scheme for pilot DEF via pilot


4

85.En_Unblocking2

0 or 1

channel 2
0: disable
1: enable

85.DEF.3I0_Set

(0.050~30.000)In

0.001

85.DEF.t_DPU

0.001~10.000

0.001

Current setting of pilot directional


earth-fault protection
Time

85.t_DPU_CR2

0.000~1.000

0.001

of

pilot

directional

earth-fault protection
Time

delay

delay

pickup

for

current

reversal logic when pilot directional


earth-fault

protection

adopts

independent pilot channel 2


Time delay dropoff for current
8

85.t_DDO_CR2

0.000~1.000

0.001

reversal logic when pilot directional


earth-fault

protection

adopts

independent pilot channel 2


Table 3.9-3 Internal settings of pilot distance protection
No.
1

Name
85.t_Unblocking2

Default Value
0.2

Unit

Remark

Pickup time delay of unblocking scheme for pilot

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channel 2
Option of PLC channel for pilot channel 2
2

85.Opt_PilotCh2

0: phase-to-phase channel
1: phase-to-ground channel

3.10 Current Direction


3.10.1 General Application
Overcurrent protection is widely used in the power system as backup protection, but in some
cases, the direction of current is necessary to aid to complete the selective tripping. As shown
below:
L
EM

M
C

Fault

N
A

EN

Figure 3.10-1 Line fault description

When line LM has an earth fault, the fault currents flowing through the relay A and the relay D are
of similar magnitude in most cases. It is desirable that the fault is isolated from the power system
by tripping the circuit breaker C and circuit breaker D. Hence, the overcurrent protection of relay A
and relay D require to associate with current direction to fulfill selective tripping.
Directional earth fault protection has a time delay due to coordinate with that of downstream so it
cannot clear the fault quickly. Pilot directional earth-fault protection, which is fulfilled by directional
earth fault element on both ends, it can maintain fast operation and achieve high sensitivity to
detect high resistance fault.

3.10.2 Function Description


The module computes direction of phase current and phase-to-phase current, zero-sequence
current and negative-sequence current.
The direction of phase current and phase-to-phase current equips with an under-voltage direction
function to ensure that phase or phase-to-phase overcurrent protection has explicit directionality
when the polarized voltage is too low for close up fault.
The direction of zero-sequence current and negative-sequence current direction equips with an
impedance compensation function to ensure that zero-sequence or negative-sequence
overcurrent protection has explicit directionality when the zero-sequence voltage or the
negative-sequence voltage is too low.
3.10.2.1 Phase/Phase-to-phase Current Direction
By setting the characteristic angle [RCA_OC] to determine the most sensitive forward angle of
phase current and phase-to-phase current, power value is calculated using phase current with
phase polarized voltage or phase-to-phase current with phase-to-phase polarized voltage to
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determine the direction of phase current or phase-to-phase current respectively in forward


direction or reverse direction. When the power value is zero, neither forward direction nor reverse
direction is considered. As shown below:
jX
U

Forward direction

Reverse direction

Figure 3.10-2 Vector diagram of current and voltage

Where:
is the setting [RCA_OC]
is the phase angle between polarized voltage and current
The power value is calculated as below:
P=U[ICOS(-)]
1.

If P>0, the current direction polarized by U is forward direction

2.

If P<0, the current direction polarized by U is reverse direction

From above diagram can be seen, when =, P reaches to the maximum value. It is considered
as the most sensitive forward direction. Hence, is called as sensitivity angle of phase
overcurrent protection.
1.

Polarized voltage of phase or phase-to-phase current direction

In the event of asymmetrical fault, because phase or phase-to-phase voltage may decrease to
very low voltage whereas positive-sequence voltage does not, the polarized voltage of phase or
phase-to-phase current direction uses positive-sequence voltage to avoid wrong direction due to
too low polarized voltage. Therefore, using positive-sequence voltage as polarized voltage can
ensure that the direction determination has no dead zone for asymmetrical fault. For symmetric
fault, if positive-sequence voltage decreases to 15%Un, the device uses memorized
positive-sequence voltage as polarized voltage, the memorized positive-sequence voltage is 1.5
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cycles pre-fault positive-sequence voltage.


2.

Phase or phase-to-phase current direction under normal polarized voltage condition

When using normal polarized voltage to calculate phase and phase-to-phase current direction,
there are total twelve direction determination algorithm including forward direction and reverse
direction.
Table 3.10-1 Direction description
Direction
Phase A

Phase B

Phase C

Phase AB

Phase BC

Phase CA

3.

Polarized Voltage

Current

Forward direction

U1a

Ia

Reverse direction

U1a

Ia

Forward direction

U1b

Ib

Reverse direction

U1b

Ib

Forward direction

U1c

Ic

Reverse direction

U1c

Ic

Forward direction

U1ab

Iab

Reverse direction

U1ab

Iab

Forward direction

U1bc

Ibc

Reverse direction

U1bc

Ibc

Forward direction

U1ca

Ica

Reverse direction

U1ca

Ica

Phase or phase-to-phase current direction for under-voltage conditions

When the symmetrical fault occurs on a power system, positive-sequence voltage may reduce to
less than 0.15Un, the device will switch to phase or phase-to-phase current direction for
under-voltage condition. The 1.5 cycle pre-fault positive-sequence voltage is used as polarized
voltage with reverse threshold to ensure stable direction decision when three-phase voltage goes
to approximately zero due to close up fault.
At first, the threshold is forward offset before direction is determined, and the threshold will be
reversed offset after direction is determined.
3.10.2.2 Zero-sequence/Negative-sequence Current Direction
By setting the characteristic angle [RCA_ROC] and [RCA_NegOC] to determine the most
sensitive forward angle of zero-sequence current and negative-sequence current, power value is
calculated using zero-sequence current with zero-sequence voltage or negative-sequence current
with negative-sequence voltage to determine the direction of zero-sequence current and
negative-sequence current respectively in forward direction or reverse direction.
When the power value is between 0 and -0.1In, neither forward direction nor reverse direction is
considered.

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jX

3U0

-180

-3I0

R
O
3I0

Reverse direction

Forward direction

Figure 3.10-3 Vector diagram of zero-sequence power

Vector diagram of negative-sequence power is similar to that of zero-sequence power.


Where:
is the setting [RCA_ROC] or the setting [RCA_NegOC]
is the phase angle between zero/negative-sequence voltage and zero/negative-sequence
current
3I0: calculated zero-sequence current by vector sum of Ia, Ib and Ic
The power value is calculated as below:
P=U[ICOS(-)]

If P>0, the direction of zero /negative-sequence current is reverse direction

If P<-0.1InVA, the direction of zero /negative-sequence current is forward direction

1.

The direction of zero-sequence current

Calculating the power value using zero-sequence current (3I0) and zero-sequence voltage (3U0)
to determine the direction of zero-sequence current
According to the equation:

The zero-sequence current and the zero-sequence voltage can be gained by calculation
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Zero-sequence power is: P=3U0[3I0COS(-)]


2.

The direction of negative-sequence current

Calculating the power value using negative-sequence current (3I2) and negative-sequence
voltage (3U2) to determine the direction of negative-sequence current
According to the equation:

The negative-sequence current and the negative-sequence voltage can be gained by calculation
Negative-sequence power is: P=3U2[3I2COS(-)]
3.

The direction of zero-sequence/negative-sequence current with impedance compensation

When zero-sequence impedance or negative-sequence impedance behind the device is very


small, if the fault in forward direction happens, the measured zero-sequence voltage or
negative-sequence voltage by the device may be relatively small to determine correct direction. In
order to solve this problem, compensated zero-sequence voltage and negative-sequence voltage
are used for power calculation.
The compensation formula is as follows:

is the setting [Z0_Comp], which cannot exceed the total zero-sequence impedance of
the protected line
is the setting [Z2_Comp], which cannot exceed the total negative-sequence impedance
of the protected line

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3.10.3 Function Block Diagram


DIR
FwdDir_ROC
RevDir_ROC
FwdDir_NegOC
RevDir_NegOC
FwdDir_A
FwdDir_B
FwdDir_C
RevDir_A
RevDir_B
RevDir_C
FwdDir_AB
FwdDir_BC
FwdDir_CA
RevDir_AB
RevDir_BC
RevDir_CA

3.10.4 I/O Signals


Table 3.10-2 I/O signals of current direction
No.

Output Signal

Description

FwdDir_ROC

The forward direction of zero-sequence power

RevDir_ROC

The reverse direction of zero-sequence power

FwdDir_NegOC

The forward direction of negative-sequence power

RevDir_NegOC

The reverse direction of negative-sequence power

FwdDir_A

The forward direction of phase-A current

FwdDir_B

The forward direction of phase-B current

FwdDir_C

The forward direction of phase-C current

RevDir_A

The reverse direction of phase-A current

RevDir_B

The reverse direction of phase-B current

10

RevDir_C

The reverse direction of phase-C current

11

FwdDir_AB

The forward direction of phase-AB current

12

FwdDir_BC

The forward direction of phase-BC current

13

FwdDir_CA

The forward direction of phase-CA current

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14

RevDir_AB

The reverse direction of phase-AB current

15

RevDir_BC

The reverse direction of phase-BC current

16

RevDir_CA

The reverse direction of phase-CA current

3.10.5 Settings
Table 3.10-3 Settings of current direction
No.

Name

Range

Step

Unit

RCA_OC

30.00~89.00

0.01

Deg

RCA_ROC

30.00~89.00

0.01

Deg

RCA_NegOC

30.00~89.00

0.01

Deg

Z0_Comp

(0.000~4Unn)/In

0.001

ohm

Z2_Comp

(0.000~4Unn)/In

0.001

ohm

Remark
The characteristic angle of directional
phase overcurrent element
The characteristic angle of directional earth
fault element
The characteristic angle of directional
negative-sequence overcurrent element
The

compensated

zero-sequence

impedance
The

compensated

negative-sequence

impedance

3.11 Phase Overcurrent Protection


3.11.1 General Application
When a fault occurs in power system, usually the fault current would be very large and phase
overcurrent protection operates monitoring fault current is then adopted to avoid further damage to
protected equipment. Directional element can be selected to improve the sensitivity and selectivity
of the protection. For application on feeder-transformer circuits, second harmonic can also be
selected to block phase overcurrent protection to avoid the effect of inrush current on the
protection.

3.11.2 Function Description


Phase overcurrent protection has following functions:
1.

Four-stage phase overcurrent protection with independent logic, current and time delay
settings.

2.

All stages can be selected as definite-time or inverse-time characteristic. The inverse-time


characteristic is selectable among IEC and ANSI/IEEE standard inverse-time characteristics,
and a user-defined inverse-time curve is available for stage 1 of phase overcurrent protection.

3.

Direction control element can be selected to control each stage phase overcurrent protection
with three options: no direction, forward direction and reverse direction.

4.

Second harmonic can be selected to block each stage of phase overcurrent protection.

3.11.2.1 Overview
Phase overcurrent protection consists of following three elements:
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1.

Overcurrent element: each stage is independent overcurrent element.

2.

Direction control element: one direction control element shared by all overcurrent elements,
and each overcurrent element can individually select protection direction.

3.

Harmonic blocking element: one harmonic blocking element shared by all overcurrent
elements and each phase overcurrent element can individually enable the output signal from
harmonic element as a blocking input.

3.11.2.2 Overcurrent Element


The operation criterion for each stage of overcurrent element is:
Ip> [50/51Px.I_Set]

Equation 3.11-1

Where:
Ip is measured phase current.
[50/51Px.I_Set] is the current setting of stage x (x=1, 2, 3, or 4) of overcurrent element.
3.11.2.3 Direction Control Element
Please refer to section 3.10 for details.
3.11.2.4 Harmonic Blocking Element
When phase overcurrent protection is used to protect feeder transformer circuits harmonic
blocking function can be selected for each stage of phase overcurrent element by configuring logic
setting [50/51Px.En_Hm2_Blk] (x=1, 2, 3 or 4) to prevent maloperation due to inrush current.
When the percentage of second harmonic component to fundamental component of any phase
current is greater than the setting [50/51P.K_Hm2], harmonic blocking element operates to block
stage x overcurrent element if corresponding logic setting [50/51Px.En_Hm2_Blk] enabled.
Operation criterion:
Equation 3.11-2

Where:
is second harmonic of phase current

is fundamental component of phase current.


[50/51P.K_Hm2] is harmonic blocking coefficient.
If fundamental component of any phase current is lower than the minimum operating current
(0.1In), then harmonic calculation is not carried out and harmonic blocking element does not
operate.

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3.11.2.5 Characteristic Curve


All stages can be selected as definite-time or inverse-time characteristic, inverse-time operating
characteristic is as follows.

Where:
Iset is current setting [50/51Px.I_Set].
Tp is time multiplier setting [50/51Px.TMS].
is a constant.
K is a constant.
C is a constant.
I is measured phase current from line CT
The user can select the operating characteristic from various inverse-time characteristic curves by
setting [50/51Px.Opt_Curve], and parameters of available characteristics for selection are shown
in the following table.
Table 3.11-1 Inverse-time curve parameters
50/51Px.Opt_Curve

Time Characteristic

Definite time

IEC Normal inverse

0.14

0.02

IEC Very inverse

13.5

1.0

IEC Extremely inverse

80.0

2.0

IEC Short-time inverse

0.05

0.04

IEC Long-time inverse

120.0

1.0

ANSI Extremely inverse

28.2

2.0

0.1217

ANSI Very inverse

19.61

2.0

0.491

ANSI Inverse

0.0086

0.02

0.0185

ANSI Moderately inverse

0.0515

0.02

0.114

10

ANSI Long-time extremely inverse

64.07

2.0

0.25

11

ANSI Long-time very inverse

28.55

2.0

0.712

12

ANSI Long-time inverse

0.086

0.02

0.185

13

Programmable user-defined

If all available curves do not comply with user application, user may set [50/51Px.Opt_Curve] as
13 to customize the inverse-time curve characteristic with constants , K and C. (only stage 1)
When inverse-time characteristic is selected, if calculated operating time is less than setting
[50/51Px.tmin], then the operating time of the protection changes to the value of setting
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[50/51Px.tmin] automatically.
Define-time or inverse-time phase overcurrent protection drops off instantaneously after fault
current disappears.

3.11.3 Function Block Diagram


50/51Px
50/51Px.En1

50/51Px.On

50/51Px.En2

50/51Px.StA

50/51Px.Blk

50/51Px.StB
50/51Px.StC
50/51Px.St
50/51Px.Op

3.11.4 I/O Signals


Table 3.11-2 I/O signals of phase overcurrent protection
No.

Input Signal

50/51Px.En1

50/51Px.En2

50/51Px.Blk

No.

Output Signal

Description
Stage x of phase overcurrent protection enabling input 1, it is triggered from binary
input or programmable logic etc.
Stage x of phase overcurrent protection enabling input 2, it is triggered from binary
input or programmable logic etc.
Stage x of phase overcurrent protection blocking input, it is triggered from binary
input or programmable logic etc.
Description

50/51Px.On

Stage x of phase overcurrent protection is enabled.

50/51Px.Op

Stage x of phase overcurrent protection operates.

50/51Px.St

Stage x of phase overcurrent protection starts.

50/51Px.StA

Stage x of phase overcurrent protection starts (A-Phase).

50/51Px.StB

Stage x of phase overcurrent protection starts (B-Phase).

50/51Px.StC

Stage x of phase overcurrent protection starts (C-Phase).

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3.11.5 Logic
SET

Ia>[50/51Px.I_Set]

SET

Ib>[50/51Px.I_Set]

SET

Ic>[50/51Px.I_Set]

SET

[50/51Px.Opt_Dir]=1

SIG

Forward DIR

SET

[50/51Px.Opt_Dir]=2

&
50/51Px.StA

&

&

50/51Px.StB

&

&
50/51Px.StC

>=1

SIG

Reverse DIR

SET

[50/51Px.Opt_Dir]=0

SIG

I3P

SET

[50/51Px.En_Hm2_Blk]

EN

[50/51Px.En]

SIG

50/51Px.En1

SIG

50/51Px.En2

SIG

50/51Px.Blk

SIG

FD.Pkp

&

>=1
2nd Hm Detect

50/51Px.St

&
Timer
t

50/51Px.Op

t
&
&
50/51Px.On
&

Figure 3.11-1 Logic diagram of phase overcurrent protection

Where:
x=1, 2, 3, 4

3.11.6 Settings
Table 3.11-3 Settings of phase overcurrent protection
No.

Name

Range

Step

Unit

Remark
Setting

50/51P.K_Hm2

0.000~1.000

0.001

of

component

second
for

harmonic

blocking

phase

overcurrent elements
2

50/51P1.I_Set

(0.050~30.000)In

0.001

50/51P1.t_Op

0.000~20.000

0.001

Current setting for stage 1 of phase


overcurrent protection
Time delay for stage 1 of phase
overcurrent protection
Enabling/disabling stage 1 of phase

50/51P1.En

overcurrent protection

0 or 1

0: disable
1: enable

50/51P1.En_BlkAR

Enabling/Disabling

0 or 1

auto-reclosing

blocked when stage 1 of phase

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overcurrent protection operates
0: disable
1: enable
Direction option for stage 1 of phase
overcurrent protection
6

50/51P1.Opt_Dir

0, 1 or 2

0: no direction
1: forward direction
2: reverse direction
Enabling/disabling second harmonic
blocking for stage 1 of phase

50/51P1.En_Hm2_Blk

0 or 1

overcurrent protection
0: disable
1: enable
Option of characteristic curve for

50/51P1.Opt_Curve

0~13

stage

of

phase

overcurrent

protection
Time multiplier setting for stage 1 of
9

50/51P1.TMS

0.010~200.000

0.001

inverse-time

phase

overcurrent

protection
Minimum operating time for stage 1
10

50/51P1.tmin

0.000~20.000

0.001

of inverse-time phase overcurrent


protection
Constant

11

50/51P1.Alpha

0.010~5.000

for

stage

customized

0.001

of

inverse-time

characteristic

phase

overcurrent

protection
Constant
12

50/51P1.C

0.000~20.000

for

stage

customized

0.001

of

inverse-time

characteristic

phase

overcurrent

protection
Constant
13

50/51P1.K

0.050~20.000

for

stage

customized

0.001

characteristic

of

inverse-time
phase

overcurrent

protection
14

50/51P2.I_Set

(0.050~30.000)In

0.001

15

50/51P2.t_Op

0.000~20.000

0.001

Current setting for stage 2 of phase


overcurrent protection
Time delay for stage 2 of phase
overcurrent protection
Enabling/disabling stage 2 of phase

16

50/51P2.En

overcurrent protection

0 or 1

0: disable
1: enable

17

50/51P2.En_BlkAR

Enabling/Disabling

0 or 1

auto-reclosing

blocked when stage 2 of phase

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overcurrent protection operates
0: disable
1: enable
Direction option for stage 2 of phase
overcurrent protection
18

50/51P2.Opt_Dir

0, 1 or 2

0: no direction
1: forward direction
2: reverse direction
Enabling/disabling second harmonic
blocking for stage 2 of phase

19

50/51P2.En_Hm2_Blk

0 or 1

overcurrent protection
0: disable
1: enable
Option of characteristic curve for

20

50/51P2.Opt_Curve

0~12

stage

of

phase

overcurrent

protection
Time multiplier setting for stage 2 of
21

50/51P2.TMS

0.010~200.000

0.001

inverse-time

phase

overcurrent

protection.
Minimum operating time for stage 2
22

50/51P2.tmin

0.000~20.000

0.001

of inverse-time phase overcurrent


protection

23

50/51P3.I_Set

(0.050~30.000)In

0.001

24

50/51P3.t_Op

0.000~20.000

0.001

Current setting for stage 3 of phase


overcurrent protection
Time delay for stage 3 of phase
overcurrent protection
Enabling/disabling stage 3 of phase

25

50/51P3.En

overcurrent protection

0 or 1

0: disable
1: enable
Enabling/Disabling

auto-reclosing

blocked when stage 3 of phase


26

50/51P3.En_BlkAR

0 or 1

overcurrent protection operates


0: disable
1: enable
Direction option for stage 3 of phase
overcurrent protection

27

50/51P3.Opt_Dir

0, 1 or 2

0: no direction
1: forward direction
2: reverse direction
Enabling/disabling second harmonic

28

50/51P3.En_Hm2_Blk

blocking for stage 3 of phase

0 or 1

overcurrent protection
0: disable
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1: enable
Option of characteristic curve for
29

50/51P3.Opt_Curve

0~12

stage

of

phase

overcurrent

protection
Time multiplier setting for stage 3 of
30

50/51P3.TMS

0.010~200.000

0.001

inverse-time

phase

overcurrent

protection.
Minimum operating time for stage 3
31

50/51P3.tmin

0.000~20.000

0.001

of inverse-time phase overcurrent


protection

32

50/51P4.I_Set

(0.050~30.000)In

0.001

33

50/51P4.t_Op

0.000~20.000

0.001

Current setting for stage 4 of phase


overcurrent protection
Time delay for stage 4 of phase
overcurrent protection
Enabling/disabling stage 4 of phase

34

50/51P4.En

overcurrent protection

0 or 1

0: disable
1: enable
Enabling/Disabling

auto-reclosing

blocked when stage 4 of phase


35

50/51P4.En_BlkAR

0 or 1

overcurrent protection operates


0: disable
1: enable
Direction option for stage 4 of phase
overcurrent protection

36

50/51P4.Opt_Dir

0, 1 or 2

0: no direction
1: forward direction
2: reverse direction
Enabling/disabling second harmonic
blocking for stage 4 of phase

37

50/51P4.En_Hm2_Blk

0 or 1

overcurrent protection
0: disable
1: enable
Option of characteristic curve for

38

50/51P4.Opt_Curve

0~12

stage

of

phase

overcurrent

protection
Time multiplier setting for stage 4 of
39

50/51P4.TMS

0.010~200.000

0.001

inverse-time

phase

overcurrent

protection.
Minimum operating time for stage 4
40

50/51P4.tmin

0.010~20.000

0.001

of inverse-time phase overcurrent


protection

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3.12 Earth Fault Protection


3.12.1 General Application
During normal operation of power system, there is trace residual current, whereas a fault current
flows to earth will result in greater residual current. Therefore, residual current is adopted for the
calculation of earth fault protection.
In order to improve the selectivity of earth fault protection in power grid with multiple power
sources, directional element can be selected to control earth fault protection. For application on
line-transformer unit, second harmonic also can be selected to block earth fault protection to avoid
the effect of sympathetic current on the protection.

3.12.2 Function Description


Earth fault protection has following functions:
1.

Four-stage earth fault protection with independent logic, current and time delay settings.

2.

All stages can be selected as definite-time or inverse-time characteristic. The inverse-time


characteristic is selectable, among IEC and ANSI/IEEE standard inverse-time characteristics,
and a user-defined inverse-time curve is available for stage 1 of earth fault protection.

3.

Directional element can be selected to control each stage of earth fault protection with three
options: no direction, forward direction and reverse direction.

4.

Second harmonic can be selected to block each stage of earth fault protection.

3.12.2.1 Overview
Earth fault protection consists of following three elements:
1.

Overcurrent element: each stage equipped with one independent overcurrent element.

2.

Directional control element: one direction control element shared by all overcurrent elements,
and each overcurrent element can individually select protection direction.

3.

Harmonic blocking element: one harmonic blocking element shared by all overcurrent
elements and each overcurrent element can individually enable the output signal of harmonic
blocking element as a blocking input.

3.12.2.2 Directional Earth-fault Element


The operation criterion for each stage of earth fault protection is:
3I0>[50/51Gx.3I0_Set]

Equation 3.12-1

Where:
3I0 is the calculated residual current.
[50/51Gx.3I0_Set] is the current setting of stage x (x=1, 2, 3, or 4) of earth fault protection.

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3.12.2.3 Direction Control Element


Please refer to section 3.10 for details.
3.12.2.4 Harmonic Blocking Element
In order to prevent effects of inrush current on earth fault protection, harmonic blocking function
can be selected for each stage of earth fault element by configuring logic setting
[50/51Gx.En_Hm2_Blk] (x=1, 2, 3 or 4).
When the percentage of second harmonic component to fundamental component of residual
current is greater than the setting [50/51G.K_Hm2], harmonic blocking element operates to block
stage x of earth fault protection if corresponding logic setting [50/51Gx.En_Hm2_Blk] is enabled
Operation criterion:
Equation 3.12-2

Where:
is second harmonic of residual current

is fundamental component of residual current.


[50/51G.K_Hm2] is harmonic blocking coefficient.
If fundamental component of residual current is lower than the minimum operating current (0.1In)
then harmonic calculation is not carried out and harmonic blocking element does not operate.
3.12.2.5 Characteristic Curve
All 4 stages earth fault protection can be selected as definite-time or inverse-time characteristic,
and inverse-time operating time curve is as follows.

Equation 3.12-3

Where:
Iset

is residual current setting [50/51Gx.3I0_Set].

Tp is time multiplier setting [50/51Gx.TMS].


K is a constant
C is a constant.
is a constant.
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3 Operation Theory

3I0 is the calculated residual current.


The user can select the operating characteristic from various inverse-time characteristic curves by
setting [50/51Gx.Opt_Curve], and parameters of available characteristics for selection are shown
in the following table.
Table 3.12-1 Inverse-time curve parameters
50/51Gx.Opt_Curve

Time Characteristic

Definite time

IEC Normal inverse

0.14

0.02

IEC Very inverse

13.5

1.0

IEC Extremely inverse

80.0

2.0

IEC Short-time inverse

0.05

0.04

IEC Long-time inverse

120.0

1.0

ANSI Extremely inverse

28.2

2.0

0.1217

ANSI Very inverse

19.61

2.0

0.491

ANSI Inverse

0.0086

0.02

0.0185

ANSI Moderately inverse

0.0515

0.02

0.114

10

ANSI Long-time extremely inverse

64.07

2.0

0.25

11

ANSI Long-time very inverse

28.55

2.0

0.712

12

ANSI Long-time inverse

0.086

0.02

0.185

13

Programmable User-defined

If all available curves do not comply with user application, user may set [50/51Gx.Opt_Curve] as
13 to customize the inverse-time curve characteristic, and constants K, and C with
configuration tool software. (only stage 1)
When inverse-time characteristic is selected, if calculated operating time is less than setting
[50/51Gx.tmin], then the operating time of the protection changes to the value of setting
[50/51Gx.tmin] automatically.
Define-time or inverse-time directional earth-fault protection drops off instantaneously after fault
current disappears.

3.12.3 Function Block Diagram


50/51Gx
50/51Gx.En1

50/51Gx.On

50/51Gx.En2

50/51Gx.St

50/51Gx.Blk

50/51Gx.Op

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3.12.4 I/O Signals


Table 3.12-2 I/O signals of earth fault protection
No.

Input Signal

50/51Gx.En1

50/51Gx.En2

50/51Gx.Blk

No.

Description
Stage x of earth fault protection enabling input 1, it is triggered from binary input or
programmable logic etc.
Stage x of earth fault protection enabling input 2, it is triggered from binary input or
programmable logic etc.
Stage x of earth fault protection blocking input, it is triggered from binary input or
programmable logic etc.

Output Signal

Description

50/51Gx.On

Stage x of earth fault protection is enabled.

50/51Gx.St

Stage x of earth fault protection starts.

50/51Gx.Op

Stage x of earth fault protection operates.

3.12.5 Logic
SIG

FD.Pkp

EN

[50/51Gx.En]

SIG

50/51Gx.En1

SIG

50/51Gx.En2

SIG

50/51Gx.Blk

SET

3I0>[50/51Gx.3I0_Set]

EN

[50/51Gx.En_Abnor_Blk]

&

&
&
50/51Gx.On

>=1

&

&
50/51Gx.St

&
SIG

No abnormal conditions

>=1
Timer
t

&

50/51Gx.Op

SET

[50/51Gx.Opt_Dir]=1

SIG

Forward DIR

SET

[50/51Gx.Opt_Dir]=2

SIG

Reverse DIR

SET

[50/51Gx.Opt_Dir]=0

SIG

CTS.Alm

EN

[50/51Gx.En_CTS_Blk]

SIG

I3P

SET

[50/51Gx.En_Hm2_Blk]

&

&

>=1

&
>=1
2nd Hm Detect

&

Figure 3.12-1 Logic diagram of earth fault protection

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Where:
x=1, 2, 3, 4
Abnormal condition 1: when the system is under pole disagreement condition, for 1-pole AR, earth
fault protection will operate. If the logic setting [50/51Gx.En_Abnor_Blk] is set as 1, the stage x of
earth fault protection will be blocked. If the logic setting [50/51Gx.En_Abnor_Blk] is set as 0,
earth fault protection is not controlled by direction element.
Abnormal condition 2: When manually closing circuit breaker, three phases of the circuit breaker
maybe not operate simultaneously, and SOTF protection should operate. If the logic setting
[50/51Gx.En_Abnor_Blk] is set as 1, the stage x of earth fault protection will be blocked. If the
logic setting [50/51Gx.En_Abnor_Blk] is set as 0, earth fault protection is not controlled by
direction element.
Abnormal condition 3: VT circuit failure. If the logic setting [50/51Gx.En_Abnor_Blk] is set as 1,
the stage x of earth fault protection will be blocked. If the logic setting [50/51Gx.En_Abnor_Blk] is
set as 0, earth fault protection is not controlled by direction element.

3.12.6 Settings
Table 3.12-3 Settings of earth fault protection
No.

Name

Range

Step

Unit

Remark
Setting

50/51G.K_Hm2

0.000~1.000

0.001

of

second

harmonic

component for blocking earth


fault elements

50/51G1.3I0_Set

(0.050~30.000)In

0.001

50/51G1.t_Op

0.000~20.000

0.001

Current setting for stage 1 of


earth fault protection
Time delay for stage 1 of earth
fault protection
Enabling/disabling stage 1 of

50/51G1.En

earth fault protection

0 or 1

0: disable
1: enable
Enabling/Disabling auto-reclosing
blocked when stage 1 of earth

50/51G1.En_BlkAR

0 or 1

fault protection operates


0: disable
1: enable
Direction option for stage 1 of
earth fault protection

50/51G1.Opt_Dir

0, 1 or 2

0: no direction
1: forward direction
2: reverse direction

50/51G1.En_Hm2_Blk

Enabling/disabling

0 or 1

second

harmonic blocking for stage 1 of

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earth fault protection
0: disable
1: enable
Enabling/disabling blocking for
stage 1 of earth fault protection
8

50/51G1.En_Abnor_Blk

0 or 1

under abnormal conditions


0: disable
1: enable
Enabling/disabling blocking for
stage 1 of earth fault protection

50/51G1.En_CTS_Blk

0 or 1

under CT failure conditions


0: disable
1: enable

10

50/51G1.Opt_Curve

0~13

Option of characteristic curve for

stage 1 of earth fault protection


Time multiplier setting for stage 1

11

50/51G1.TMS

0.010~200.000

0.001

of

inverse-time

earth

fault

protection
Minimum operating time for stage
12

50/51G1.tmin

0.050~20.000

0.001

1 of inverse-time earth fault


protection
Constant for stage 1 of

13

50/51G1.Alpha

0.010~5.000

customized

0.001

characteristic

inverse-time
earth

fault

protection
Constant C for stage 1 of
14

50/51G1.C

0.000~20.000

customized

0.001

characteristic

inverse-time
earth

fault

protection
Constant K for stage 1 of
15

50/51G1.K

0.050~20.000

customized

0.001

characteristic

inverse-time
earth

fault

protection
16

50/51G2.3I0_Set

(0.050~30.000)In

0.001

17

50/51G2.t_Op

0.000~20.000

0.001

Current setting for stage 2 of


earth fault protection
Time delay for stage 2 of earth
fault protection
Enabling/disabling stage 2 of

18

50/51G2.En

earth fault protection

0 or 1

0: disable
1: enable
Enabling/Disabling auto-reclosing

19

50/51G2.En_BlkAR

0 or 1

blocked when stage 2 of earth


fault protection operates

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0: disable
1: enable
Direction option for stage 2 of
earth fault protection
20

50/51G2.Opt_Dir

0, 1 or 2

0: no direction
1: forward direction
2: reverse direction
Enabling/disabling

second

harmonic blocking for stage 2 of


21

50/51G2.En_Hm2_Blk

0 or 1

earth fault protection


0: disable
1: enable
Enabling/disabling blocking for
stage 2 of earth fault protection

22

50/51G2.En_Abnor_Blk

0 or 1

under abnormal conditions


0: disable
1: enable
Enabling/disabling blocking for
stage 2 of earth fault protection

23

50/51G2.En_CTS_Blk

0 or 1

under CT failure conditions


0: disable
1: enable

24

50/51G2.Opt_Curve

Option of characteristic curve for

0~12

stage 2 of earth fault protection


Time multiplier setting for stage 2

25

50/51G2.TMS

0.010~200.000

0.001

of

inverse-time

earth

fault

protection
Minimum operating time for stage
26

50/51G2.tmin

0.050~20.000

0.001

2 of inverse-time earth fault


protection

27

50/51G3.3I0_Set

(0.050~30.000)In

0.001

28

50/51G3.t_Op

0.000~20.000

0.001

Current setting for stage 3 of


earth fault protection
Time delay for stage 3 of earth
fault protection
Enabling/disabling stage 3 of

29

50/51G3.En

earth fault protection

0, 1 or 2

0: disable
1: enable
Enabling/Disabling auto-reclosing
blocked when stage 3 of earth

30

50/51G3.En_BlkAR

0 or 1

fault protection operates


0: disable
1: enable

31

50/51G3.Opt_Dir

0 or 1

Direction option for stage 3 of


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earth fault protection
0: no direction
1: forward direction
2: reverse direction
Enabling/disabling

second

harmonic blocking for stage 3 of


32

50/51G3.En_Hm2_Blk

0 or 1

earth fault protection


0: disable
1: enable
Enabling/disabling blocking for
stage 3 of earth fault protection

33

50/51G3.En_Abnor_Blk

0 or 1

under abnormal conditions


0: disable
1: enable
Enabling/disabling blocking for
stage 3 of earth fault protection

34

50/51G3.En_CTS_Blk

0 or 1

under CT failure conditions


0: disable
1: enable

35

50/51G3.Opt_Curve

Option of characteristic curve for

0~12

stage 3 of earth fault protection


Time multiplier setting for stage 3

36

50/51G3.TMS

0.010~200.000

0.001

of

inverse-time

earth

fault

protection
Minimum operating time for stage
37

50/51G3.tmin

0.050~20.000

0.001

3 of inverse-time earth fault


protection

38

50/51G4.3I0_Set

(0.050~30.000)In

0.001

39

50/51G4.t_Op

0.000~20.000

0.001

Current setting for stage 4 of


earth fault protection
Time delay for stage 4 of earth
fault protection
Enabling/disabling stage 4 of

40

50/51G4.En

earth fault protection

0, 1 or 2

0: disable
1: enable
Enabling/Disabling auto-reclosing
blocked when stage 4 of earth

41

50/51G4.En_BlkAR

0 or 1

fault protection operates


0: disable
1: enable
Direction option for stage 4 of

42

50/51G4.Opt_Dir

earth fault protection

0 or 1

0: no direction
1: forward direction

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2: reverse direction
Enabling/disabling

second

harmonic blocking for stage 4 of


43

50/51G4.En_Hm2_Blk

0 or 1

earth fault protection


0: disable
1: enable
Enabling/disabling blocking for
stage 4 of earth fault protection

44

50/51G4.En_Abnor_Blk

0 or 1

under abnormal conditions


0: disable
1: enable
Enabling/disabling blocking for
stage 4 of earth fault protection

45

50/51G4.En_CTS_Blk

0 or 1

under CT failure conditions


0: disable
1: enable

46

50/51G4.Opt_Curve

Option of characteristic curve for

0~12

stage 4 of earth fault protection


Time multiplier setting for stage 4

47

50/51G4.TMS

0.010~200.000

0.001

of

inverse-time

earth

fault

protection
Minimum operating time for stage
48

50/51G4.tmin

0.050~20.000

0.001

4 of inverse-time earth fault


protection

3.13 Overcurrent Protection for VT Circuit Failure


3.13.1 General Application
When protection VT circuit fails, distance protection will be disabled. As a substitute, definite-time
phase overcurrent protection and ground overcurrent protection will be enabled automatically, if
selected, as backup protection of distance protection.

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3.13.2 Function Block Diagram


50PVT/50GVT
50PVT.En1

50PVT.On

50PVT.En2

50PVT.Op

50PVT.Blk

50PVT.St

50GVT.En1

50PVT.StA

50GVT.En2

50PVT.StB

50GVT.Blk

50PVT.StC
50GVT.On
50GVT.Op
50GVT.St

3.13.3 I/O Signals


Table 3.13-1 I/O signals of overcurrent protection for VT circuit failure
No.

Input Signal

50PVT.En1

50PVT.En2

50PVT.Blk

50GVT.En1

50GVT.En2

50GVT.Blk

No.

Output Signal

Description
Phase overcurrent protection for VT circuit failure enabling input 1, it is triggered
from binary input or programmable logic etc.
Phase overcurrent protection for VT circuit failure enabling input 2, it is triggered
from binary input or programmable logic etc.
Phase overcurrent protection for VT circuit failure blocking input, it is triggered
from binary input or programmable logic etc.
Ground overcurrent protection for VT circuit failure enabling input 1, it is triggered
from binary input or programmable logic etc.
Ground overcurrent protection for VT circuit failure enabling input 2, it is triggered
from binary input or programmable logic etc.
Ground overcurrent protection for VT circuit failure blocking input, it is triggered
from binary input or programmable logic etc.
Description

50PVT.On

Phase overcurrent protection for VT circuit failure is enabled.

50PVT.Op

Phase overcurrent protection for VT circuit failure operates.

50PVT.St

Phase overcurrent protection for VT circuit failure starts.

50PVT.StA

Phase overcurrent protection for VT circuit failure starts (A-Phase).

50PVT.StB

Phase overcurrent protection for VT circuit failure starts (B-Phase).

50PVT.StC

Phase overcurrent protection for VT circuit failure starts (C-Phase).

50GVT.On

Ground overcurrent protection for VT circuit failure is enabled.

50GVT.Op

Ground overcurrent protection for VT circuit failure operates.

50GVT.St

Ground overcurrent protection for VT circuit failure starts.

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3.13.4 Logic
SIG

50GVT.En1

SIG

50GVT.En2

EN

[50GVT.En]

SIG

50GVT.Blk]

SIG

FD.Pkp

&
&
50GVT.On
&
50GVT.St
&
SET

3I0>[50GVT.3I0_Set]

SIG

FD.ROC.Pkp

SIG

VTS.Alm

SIG

50PVT.En1

SIG

50PVT.En2

EN

50PVT.En]

SIG

50PVT.Blk]

[50GVT.t_Op]

0ms

50GVT.Op

&

&
&
50PVT.On

>=1

&

[50PVT.t_Op]

&
SIG

FD.Pkp

SIG

VTS.Alm

SET

Ia>[50PVT.I_Set]

0ms

50PVT.Op
50PVT.St

&
50PVT.StA

&
50PVT.StB
SET

Ib>[50PVT.I_Set]
&
50PVT.StC

SET

Ic>[50PVT.I_Set]

Figure 3.13-1 Logic diagram of overcurrent protection for VT circuit failure

3.13.5 Settings
Table 3.13-2 Settings of overcurrent protection for VT circuit failure
No.

Name

Range

Step

Unit

50PVT.I_Set

(0.050~30.000)In

0.001

50PVT.t_Op

0.000~10.000

0.001

Remark
Current setting of phase overcurrent
protection when VT circuit failure
Time delay of phase overcurrent
protection when VT circuit failure
Enabling/disabling phase overcurrent

50PVT.En

protection when VT circuit failure

0 or 1

0: disable
1: enable

50GVT.3I0_Set

(0.050~30.000)In

0.001

50GVT.t_Op

0.000~10.000

0.001

50GVT.En

0 or 1

Current setting of ground overcurrent


protection when VT circuit failure
Time delay of ground overcurrent
protection when VT circuit failure
Enabling/disabling

ground

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overcurrent protection when VT circuit
failure
0: disable
1: enable

3.14 Residual Current SOTF Protection


3.14.1 General Application
When the circuit breaker is closed manually or automatically, it is possible to switch on to an
existing fault. This is especially critical if the line in the remote station is grounded, since earth fault
protection would not clear the fault until their time delays had elapsed. In this situation, however,
the fastest possible clearance is desired.
Residual current SOTF (switch onto fault) protection is a complementary function to earth fault
protection. With residual current SOTF protection, a fast trip is achieved for a fault on the line,
when the line is being energized. It shall be responsive to all types of earth faults anywhere within
the protected line, and it shall be enabled for a period of 400ms when the circuit is energized either
manually or via an auto-reclosing system.

3.14.2 Function Description


Residual current SOTF protection will operate to trip three-phase circuit breaker with a time delay
of 60ms when 1-pole auto-reclosing.
Residual current SOTF protection will operate to trip three-phase circuit breaker with a time delay of
100ms when 3-pole auto-reclosing or closing manually.

3.14.3 Function Block Diagram


50GSOTF
50GSOTF.En1

50GSOTF.On

50GSOTF.En2

50GSOTF.Op

50GSOTF.Blk

50GSOTF.St

3.14.4 I/O Signals


Table 3.14-1 I/O signals of residual SOTF protection
No.

Input Signal

50GSOTF.En1

50GSOTF.En2

50GSOTF.Blk

Description
Residual current SOTF protection enabling input 1, it is triggered from binary input
or programmable logic etc.
Residual current SOTF protection enabling input 2, it is triggered from binary input
or programmable logic etc.
Residual current SOTF protection blocking input, it is triggered from binary input

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or programmable logic etc.
No.

Output Signal

Description

50GSOTF.On

Residual current SOTF protection is enabled.

50GSOTF.Op

Residual current SOTF protection operates.

50GSOTF.St

Residual current SOTF protection starts.

3.14.5 Logic
SIG

3-pole AR signal

SIG

Manual closing signal

SET

3I0>[50GSOTF.3I0_Set]

>=1
&

SIG

FD.ROC.Pkp

SIG

1-pole AR signal

SIG

50GSOTF.En1

SIG

50GSOTF.En2

SIG

50GSOTF.Blk

EN

[50GSOTF.En_3I0]

100ms

0ms

&

>=1
50GSOTF.Op

&
60ms

0ms

>=1
50GSOTF.St

&
&
50GSOTF.On

Figure 3.14-1 Logic diagram of residual current SOTF protection

3.14.6 Settings
Table 3.14-2 Settings of residual current SOTF protection
No.

Name

Range

Step

Unit

50GSOTF.3I0_Set

(0.050~30.000)In

0.001

Remark
Current setting of residual current
SOTF protection
Enabling/disabling residual current

50GSOTF.En_3I0

SOTF protection

0 or 1

0: disable
1: enable

3.15 Voltage Protection


Voltage protection has the function of protecting device against undervoltage and overvoltage.
Both operational states are unfavorable as overvoltage may cause insulation breakdown while
undervoltage may cause stability problem. Each voltage protection function has two individual
stages with respective time delay. These voltage protection functions can be switched on or off
separately. Selectable definite-time characteristic and multiple inverse-time characteristics are
available.

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3.15.1 Overvoltage Protection


3.15.1.1 General Application
Abnormal high voltages often occur e.g. in low loaded, long distance transmission lines, in
islanded systems when generator voltage regulation fails, or load rejection of a generator. Even if
compensation reactors are provided to avoid line overvoltage by compensation of the line
capacitance and thus reduction of the overvoltage, the overvoltage will endanger the insulation if
the reactors fail. The line must be de-energized within a very short time.
The overvoltage protection in this device detects the phase voltages Ua, Ub and Uc or the
phase-to-phase voltages Uab, Ubc and Uca with an option of any phase or all phases operation
for output. The overvoltage protection can be used for tripping purpose as well as to initiate
transfer trip, which selectable controlled by local circuit breaker.
3.15.1.2 Function Description
Phase overvoltage protection has following functions:
1.

Two-stage phase overvoltage protection with independent logic, voltage and time delay
settings.

2.

Stage 1 and stage 2 can be selected as definite-time or inverse-time characteristic. The


inverse-time characteristic is selectable, among IEC and ANSI/IEEE standard inverse-time
characteristics.

3.

Phase voltage or phase-to-phase voltage can be selected for protection calculation.

4.

1-out-of-3 or 3-out-of-3 logic can be selected for protection criterion. (1-out-of-3 means any
of three phase voltages, 3-out-of-3 means all three phase voltages)

1.

Operation Criterion

Users can select phase voltage or phase-to-phase voltage for the protection calculation. If setting
[59Px.Opt_Up/Upp] is set to 0, phase voltage criterion is selected and if [59Px.Opt_Up/Upp] is
set to 1, phase-to-phase voltage criterion is selected.
When phase voltage or phase-to-phase voltage is greater than any enabled stage voltage setting,
the stage protection picks up and operates after delay, which will drop off instantaneously when
fault voltage disappears.

Phase voltage criterion

Two operation criteria of definite-time overvoltage protection are shown as follows, which of them
is applied depending on the logic setting [59Px.Opt_1P/3P].
U_max>[ 59Px.U_Set]

Equation 3.15-1

or
Ua>[59Px.U_Set] & Ub>[59Px.U_Set] & Uc>[59Px.U_Set]
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Where:
U_max is the maximum value among three phase-voltage.
Ua, Ub, Uc are three phase voltages.
[59Px.U_Set] is the setting of stage x (x=1 or 2) overvoltage protection.
When [59Px.Opt_1P/3P] is set as 0, 1-out-of-3 logic (Equation 3.15-1) is selected as operation
criterion, and when set as 1, 3-out-of-3 logic (Equation 3.15-2) is selected.

Phase-to-phase voltage criterion

Two operation criteria of definite-time overvoltage protection are shown as follows, which of them
is applied depending on the logic setting [59Px.Opt_1P/3P].
U_max>[ 59Px.U_Set]

Equation 3.15-3

or
Uab>[59Px.U_Set] & Ubc>[59Px.U_Set] & Uca>[59Px.U_Set]

Equation 3.15-4

[59Px.U_Set] is the setting of stage x (x =1 or 2) overvoltage protection.


When [59Px.Opt_1P/3P] is set as 0, 1-out-of-3 logic (Equation 3.15-3) is selected as operation
criterion, and when set as 1, 3-out-of-3 logic (Equation 3.15-4) is selected.
2.

Characteristic Curve

Phase overvoltage protection stage 1 and stage 2 can be selected as definite-time or inverse-time
characteristic, and inverse-time operating time curve is as follows.

Where:
Uset is the voltage setting [59Px.U_Set] (x=1 or 2).
Tp is time multiplier setting [59Px.TMS].
K is a constant.
C is a constant.
is a constant.
U is the measured voltage
For stage 1 and stage 2 of overvoltage protection, operating characteristic can be chosen from
definite-time characteristic and 12 inverse-time characteristics by setting the logic setting
[59Px.Opt_Curve]. The parameters of each characteristic are listed in the following table.

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Table 3.15-1 Inverse-time curve parameters
59Px.Opt_Curve

Time Characteristic

Definite time

IEC Normal inverse

0.14

0.02

IEC Very inverse

13.5

1.0

IEC Extremely inverse

80.0

2.0

IEC Short-time inverse

0.05

0.04

IEC Long-time inverse

120.0

1.0

ANSI Extremely inverse

28.2

2.0

0.1217

ANSI Very inverse

19.61

2.0

0.491

ANSI Inverse

0.0086

0.02

0.0185

ANSI Moderately inverse

0.0515

0.02

0.114

10

ANSI Long-time extremely inverse

64.07

2.0

0.25

11

ANSI Long-time very inverse

28.55

2.0

0.712

12

ANSI Long-time inverse

0.086

0.02

0.185

When inverse-time characteristic is selected, if calculated operating time is less than setting
[59Px.tmin], then the operating time changes to the value of setting [59Px.tmin] automatically.
Define-time or inverse-time phase overvoltage protection drops off instantaneously when
measured voltage is lower than reset voltage.
3.15.1.3 Function Block Diagram
59Px
59Px.En1

59Px.On

59Px.En2

59Px.St

59Px.Blk

59Px.St1
59Px.St2
59Px.St3
59Px.Op
59Px.Alm
59Px.Op_InitTT

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3.15.1.4 I/O Signals


Table 3.15-2 I/O signals of overvoltage protection
No.

Input Signal

59Px.En1

59Px.En2

59Px.Blk

No.

Description
Stage x of overvoltage protection enabling input 1, it is triggered from binary input
or programmable logic etc.
Stage x of overvoltage protection enabling input 2, it is triggered from binary input
or programmable logic etc.
Stage x of overvoltage protection blocking input, it is triggered from binary input or
programmable logic etc.

Output Signal

Description

59Px.On

Stage x of overvoltage protection is enabled.

59Px.Op

Stage x of overvoltage protection operates.

59Px.St

Stage x of overvoltage protection starts.

59Px.St1

Stage x of overvoltage protection starts (A or AB).

59Px.St2

Stage x of overvoltage protection starts (B or BC).

59Px.St3

Stage x of overvoltage protection starts (C or CA).

59Px.Op_InitTT

Stage x of overvoltage protection operates to initiate transfer trip.

59Px.Alm

Stage x of overvoltage protection alarms.

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3.15.1.5 Logic
EN

[59Px.En]

SIG

59Px.En1

SIG

59Px.En2

SIG

59Px.Blk

&
&
59Px.On

BI

[52b_PhA]

BI

[52b_PhB]

BI

[52b_PhC]

EN

[59Px.En_52b_TT]

EN

[59Px.En_TT]

EN

[59Px.En_Alm]

SIG

&
&
&
>=1
59Px.Op_InitTT

&

FD.Pkp

&

SIG

59Px.On

EN

[59Px.Opt_Up/Upp]

&

&
>=1

SET

Timer
t

&

UA>[59Px.U_Set]

&

&
SET

UAB>[59Px.U_Set]

&

&
>=1

SET

Timer
t

&

UB>[59Px.U_Set]

59Px.Op

&
SET

&

UBC>[59Px.U_Set]

>=1
&

&
>=1

SET

>=1

Timer
t
t

UC>[59Px.U_Set]

&
SET

59Px.Alm

&

>=1
59Px.St

UCA>[59Px.U_Set]

59Px.St1
59Px.St2
EN

[59Px.Opt_1P/3P]

59Px.St3

Figure 3.15-1 Logic diagram of stage x of overvoltage protection

x=1, 2
3.15.1.6 Settings
Table 3.15-3 Settings of overvoltage protection
No.

Name

Range

Step

Unit

59P1.U_Set

Un~2Unn

0.001

59P1.t_Op

0.000~30.000

0.001

Remark
Voltage setting for stage 1 of overvoltage
protection
Time delay for stage 1 of overvoltage
protection
Enabling/disabling stage 1 of overvoltage

59P1.En

protection

0 or 1

0: disable
1: enable

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Option of 1-out-of-3 mode or 3-out-of-3
4

59P1.Opt_1P/3P

mode

0 or 1

0: 3-out-of-3 mode
1: 1-out-of-3 mode
Option of phase-to-phase voltage or phase

59P1.Opt_Up/Upp

voltage

0 or 1

0: phase voltage
1: phase-to-phase voltage
Enabling/disabling stage 1 of overvoltage

59P1.En_Alm

protection for alarm purpose

0 or 1

0: disable
1: enable
Enabling/disabling transfer trip controlled
by CB open position for stage 1 of

59P1.En_52b_TT

0 or 1

overvoltage protection
0: disable
1: enable
Enabling/disabling stage 1 of overvoltage

59P1.En_TT

protection operate to initiate transfer trip

0 or 1

0: disable
1: enable

Option of characteristic curve for stage 1 of

59P1.Opt_Curve

0~13

10

59P1.TMS

0.010~200.000

0.001

11

59P1.tmin

0.050~20.000

0.001

12

59P2.U_Set

Un~2Unn

0.001

13

59P2.t_Op

0.000~30.000

0.001

overvoltage protection
Time multiplier setting for stage 1 of
inverse-time overvoltage protection
Minimum delay for stage 1 of inverse-time
overvoltage protection
Voltage setting for stage 2 of overvoltage
protection
Time delay for stage 2 of overvoltage
protection
Enabling/disabling stage 2 of overvoltage

14

59P2.En

protection

0 or 1

0: disable
1: enable
Option of 1-out-of-3 mode or 3-out-of-3

15

59P2.Opt_1P/3P

mode

0 or 1

0: 3-out-of-3 mode
1: 1-out-of-3 mode
Option of phase-to-phase voltage or phase

16

59P2.Opt_Up/Upp

voltage

0 or 1

0: phase voltage
1: phase-to-phase voltage

17

59P2.En_Alm

0 or 1

Enabling/disabling stage 2 of overvoltage


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protection for alarm purpose
0: disable
1: enable
Enabling/disabling transfer trip controlled
by CB open position for stage 2 of
18

59P2.En_52b_TT

0 or 1

overvoltage protection
0: disable
1: enable
Enabling/disabling stage 2 of overvoltage

19

59P2.En_TT

protection operate to initiate transfer trip

0 or 1

0: disable
1: enable
Option of characteristic curve for stage 2 of

20

59P2.Opt_Curve

0~12

21

59P2.TMS

0.010~200.000

0.001

22

59P2.tmin

0.050~20.000

0.001

overvoltage protection
Time multiplier setting for stage 2 of
inverse-time overvoltage protection
s

Minimum delay for stage 2 of inverse-time


overvoltage protection

3.15.2 Undervoltage Protection


3.15.2.1 General Application
The undervoltage protection can be applied to trip when fault occurs in a system. Two stages of
undervoltage protection are available measuring phase voltages UA, UB and UC or phase-to-phase
voltages UAB, UBC and UCA. The protection output can be selected for either any phase or all
phases operation. The undervoltage protection is normally used as decoupling system rather than
load shedding.
3.15.2.2 Function Description
Phase undervoltage protection has following functions:
1.

Two-stage phase undervoltage protection with independent logic, voltage and time delay
settings.

2.

Stage 1 and stage 2 can be selected as definite-time or inverse-time characteristic. The


inverse-time characteristic is selectable, among IEC and ANSI/IEEE standard inverse-time
characteristics.

3.

Phase voltage or phase-to-phase voltage can be selected for protection calculation.

4.

1-out-of-3 or 3-out-of-3 logic can be selected for protection criterion. (1-out-of-3 means any
of three phase voltages, 3-out-of-3 means all three phase voltages)

1.

Operation Criterion

Users can select phase voltage or phase-to-phase voltage for the protection calculation. If setting
[27Px.Opt_Up/Upp] is set to 0, phase voltage criterion is selected and if [27Px.Opt_Up/Upp] is

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set to 1, phase-to-phase voltage criterion is selected.


When phase voltage or phase-to-phase voltage is less than any enabled stage voltage setting, the
stage protection picks up and operates after delay, which will drop off instantaneously when fault
voltage disappears.

Phase voltage criterion

Two operation criteria of definite-time undervoltage protection are shown as follows, which of them
is applied depending on the logic setting [27Px.Opt_1P/3P].
U_min<[ 27Px.U_Set]

Equation 3.15-5

or
Ua<[ 27Px.U_Set] & Ub<[27Px.U_Set] & Uc<[27Px.U_Set]

Equation 3.15-6

Where:
U_min is the minimum value among three phase voltages.
Ua, Ub and Uc are three phase voltages.
[27Px.U_Set] is the setting of stage x (x=1 or 2) undervoltage protection.
When [27Px.Opt_1P/3P] is set as 0, 1-out-of-3 logic (Equation 3.15-5) is selected as operation
criterion, and when set as 1, 3-out-of-3 logic (Equation 3.15-6) is selected.

Phase-to-phase voltage criterion

Two operation criteria of definite-time undervoltage protection are shown as follows, which of them
is applied depending on the logic setting [27Px.Opt_Up/Upp].
U_min<[ 27Px.U_Set]

Equation 3.15-7

or
Uab<[27Px.U_Set] & Ubc<[27Px.U_Set] & Uca<[27Px.U_Set]

Equation 3.15-8

Where:
U_min is the minimum value among three phase-to-phase voltages.
Uab, Ubc and Uca are three phase-to-phase voltages.
[27Px.U_Set] is the setting of stage x (x =1 or 2) undervoltage protection.
When the setting [27Px.Opt_1P/3P] is set as 0, 1-out-of-3 logic (Equation 3.15-7) is selected as
operation criterion, and when it is set as 1, 3-out-of-3 logic (Equation 3.15-8) is selected.
2.

Characteristic Curve

Undervoltage protection stage 1 and stage 2 can be selected as definite-time or inverse-time


characteristic, and inverse-time operating time curve is as follows.

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Where:
Uset is the setting [27Px.U_Set] (x=1 or 2).
Tp is time multiplier setting [27Px.TMS].
K is a constant.
C is a constant.
is a constant.
U is the measured voltage
For stage 1 and stage 2 of undervoltage protection, operating characteristic can be chosen from
definite-time characteristic and twelve inverse-time characteristics by setting the logic setting
[27Px.Opt_Curve]. The parameters of each characteristic are listed in the following table.
Table 3.15-4 Inverse-time curve parameters of phase undervoltage protection
27Px.Opt_Curve

Time Characteristic

Definite time

IEC Normal inverse

0.14

0.02

IEC Very inverse

13.5

1.0

IEC Extremely inverse

80.0

2.0

IEC Short-time inverse

0.05

0.04

IEC Long-time inverse

120.0

1.0

ANSI Extremely inverse

28.2

2.0

0.1217

ANSI Very inverse

19.61

2.0

0.491

ANSI Inverse

0.0086

0.02

0.0185

ANSI Moderately inverse

0.0515

0.02

0.114

10

ANSI Long-time extremely inverse

64.07

2.0

0.25

11

ANSI Long-time very inverse

28.55

2.0

0.712

12

ANSI Long-time inverse

0.086

0.02

0.185

When inverse-time characteristic is selected, if calculated operating time is less than setting
[27Px.tmin], then the operating time changes to the value of setting [27Px.tmin] automatically.

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Define-time or inverse-time phase under voltage protection drops off instantaneously when
measured voltage is higher than reset voltage.
3.15.2.3 Function Block Diagram
27Px
27Px.En1

27Px.On

27Px.En2

27Px.Alm

27Px.Blk

27Px.Op
27Px.St
27Px.St1
27Px.St2
27Px.St3

3.15.2.4 I/O Signals


Table 3.15-5 I/O signals of undervoltage protection
No.

Input Signal

27Px.En1

27Px.En2

27Px.Blk

No.

Description
Stage x of undervoltage protection enabling input 1, it is triggered from binary
input or programmable logic etc.
Stage x of undervoltage protection enabling input 2, it is triggered from binary
input or programmable logic etc.
Stage x of undervoltage protection blocking input, it is triggered from binary input
or programmable logic etc.

Output Signal

Description

27Px.On

Stage x of undervoltage protection is enabled.

27Px.Op

Stage x of undervoltage protection operates.

27Px.Alm

Stage x of undervoltage protection alarms.

27Px.St

Stage x of undervoltage protection starts.

27Px.St1

Stage x of undervoltage protection starts (A or AB).

27Px.St2

Stage x of undervoltage protection starts (B or BC).

27Px.St3

Stage x of undervoltage protection starts (C or CA).

3.15.2.5 Logic
When FD element reflecting current operates, including DPFC current element and residual
current element, the undervoltage protection is released for operation.
When any of the following conditions is fulfilled, the undervoltage protection will be blocked.
1.

VT signal failsif the voltage comes from busbar VT, the voltage will restore to the normal
immediately after the fault being cleared away. However, if the voltage comes from line VT,
the voltage will drop to zero immediately after the fault is cleared. The undervoltage protection
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will be continuously in operation, thus an auxiliary current criterion is provided to solve it.
2.

Any phase is out of service, i.e. Up<0.01Un and IP<0.06In.

3.

Any phase of circuit breaker is open (binary input of normal close contact of breaker is
energized) and the corresponding phase current is smaller than 0.06In.
SIG

20ms

Pole dead

100ms
>=1

SIG

VTS.Alm

Block UV

SIG

CB open position

Figure 3.15-2 Blocking logic of undervoltage protection


EN

[27Px.En]

SIG

27Px.En1

SIG

27Px.En2

SIG

27Px.Blk

EN

[27Px.En_Alm]

SET

[27P1.Opt_1P/3P]

SIG

FD.Pkp

SIG

27Px.On

SIG

Block UV

SET

[27Px.Opt_Up/Upp]

&
&
27Px.On

&

&

&
>=1

SET

Timer
t

&
&

UA<[27Px.U_Set]
&

SET

UAB<[27Px.U_Set]
&

&
>=1

SET

&

Timer
t

27Px.Op

UB<[27Px.U_Set]

&

&
SET

>=1

27Px.Alm

&

UBC<[27Px.U_Set]
>=1
&

&
>=1

SET

UC<[27Px.U_Set]
&

Timer
t
t

>=1
27Px.St

SET

UCA<[27Px.U_Set]
27Px.St1
27Px.St2
27Px.St3

Figure 3.15-3 Logic diagram of stage x of undervoltage protection

x=1, 2

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3.15.2.6 Settings
Table 3.15-6 Settings of undervoltage protection
No.

Name

Range

Step

Unit

27P1.U_Set

0~Unn

0.001

27P1.t_Op

0.000~30.000

0.001

Remark
Voltage setting for stage 1 of undervoltage
protection
Time delay for stage 1 of undervoltage
protection
Enabling/disabling stage 1 of undervoltage

27P1.En

protection

0 or 1

0: disable
1: enable
Option of 1-out-of-3 mode or 3-out-of-3

27P1.Opt_1P/3P

mode

0 or 1

0: 3-out-of-3 mode
1: 1-out-of-3 mode
Option

27P1.Opt_Up/Upp

of

voltage

criterion

adopting

phase-to-phase voltage or phase voltage

0 or 1

0: phase voltage
1: phase-to-phase voltage
Enabling/disabling stage 1 of undervoltage

27P1.En_Alm

protection operate to alarm

0 or 1

0: disable
1: enable
Option of characteristic curve for stage 1

27P1.Opt_Curve

0~13

27P1.TMS

0.010~200.000

0.001

27P1.tmin

0.050~20.000

0.001

10

27P2.U_Set

0~Unn

0.001

11

27P2.t_Op

0.000~30.000

0.001

of undervoltage protection
Time multiplier setting for stage 1 of
inverse-time undervoltage protection
Minimum delay for stage 1 of inverse-time
undervoltage protection
Voltage setting for stage 2 of undervoltage
protection
Time delay for stage 2 of undervoltage
protection
Enabling/disabling stage 2 of undervoltage

12

27P2.En

protection

0 or 1

0: disable
1: enable
Option of 1-out-of-3 mode or 3-out-of-3

13

27P2.Opt_1P/3P

mode

0 or 1

0: 3-out-of-3 mode
1: 1-out-of-3 mode

14

27P2.Opt_Up/Upp

Option

0 or 1

of

voltage

criterion

adopting

phase-to-phase voltage or phase voltage


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0: phase voltage
1: phase-to-phase voltage
Enabling/disabling stage 2 of undervoltage
15

27P2.En_Alm

protection operate to alarm

0 or 1

0: disable
1: enable
Option of characteristic curve for stage 2

16

27P2.Opt_Curve

0~12

17

27P2.TMS

0.010~200.000

0.001

18

27P2.tmin

0.050~20.000

0.001

of undervoltage protection
Time multiplier setting for stage 2 of
inverse-time undervoltage protection
s

Minimum delay for stage 2 of inverse-time


undervoltage protection

3.16 Frequency Protection


3.16.1 Overfrequency Protection
3.16.1.1 General Application
If the power frequency of regional rises due to the active power excess demand, overfrequency
protection operates to perform generator rejection to shed part of the generators automatically
according to the rising frequency so that power supply and the load are re-balanced.
3.16.1.2 Function Description
Overfrequency protection consists of the four stages (stage 1 to stage 4). When system frequency
is greater than the setting [81O.f_Pkp], overfrequency protection will put into service.
In order to prevent possible maloperation of overfreqency protection in conditions of high
harmonics, voltage circuit failures and so on, such blocking measures are carried out as follows:
1.

Blocking in undervoltage condition

If the positive voltage U1<0.15Un, the calculation of protection is not carried out and the output
relay will be blocked.
2.

Frequency abnormality condition

When f<40Hz or f>65Hz, overfrequency protection will be blocked


Operation criteria of overfrequency protection is shown in the following equation.
f>[81O.OFx.f_Set]

Equation 3.16-1

Where:
f is system frequency.
[81O.OFx.f_Set] is the frequency setting of stage x (x=1, 2, 3, or 4) of overfrequency protection.

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3.16.1.3 Function Block Diagram


81O.OFx
81O.En1

81O.OFx.On

81O.En2

81O.St

81O.Blk

81O.OFx.Op

3.16.1.4 I/O Signals


Table 3.16-1 I/O signals of overfrequency protection
No.

Input Signal

81O.En1

81O.En2

81O.Blk

No.

Description
Overfrequency protection enabling input 1, it is triggered from binary input or
programmable logic etc.
Overfrequency protection enabling input 2, it is triggered from binary input or
programmable logic etc.
Overfrequency protection blocking input, it is triggered from binary input or
programmable logic etc.

Output Signal

Description

81O.OFx.On

Stage x of overfrequency protection is enabled (x=1, 2, 3 or 4).

81O.OFx.Op

Stage x of overfrequency protection operates (x=1, 2, 3 or 4).

81O.St

Overfrequency protection starts.

3.16.1.5 Logic
SIG

81O.En1

SIG

81O.En2

EN

[81O.OF1.En]

SIG

81O.Blk

SIG

FD.Pkp

OTH

U1<0.15Un

SIG

f40 or f65

OTH

f>[81O.f_Pkp]

&
&
81O.OF1.On

&
1

&
50ms

0ms
81O.St1

&
SET

f>[81O.OF1.f_Set]

EN

[81O.OF1.En]

[81O.OF1.t_Op]

&

0ms

81O.OF1.Op

Figure 3.16-1 Logic diagram of overfrequency protection (stage 1)

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SIG

81O.En1

SIG

81O.En2

EN

[81O.OF2.En]

SIG

81O.Blk

SIG

FD.Pkp

OTH

U1<0.15Un

SIG

f40 or f65

OTH

f>[81O.f_Pkp]

&
&
81O.OF2.On

&
1

&
50ms

0ms
81O.St2

&
SET

f>[81O.OF2.f_Set]

EN

[81O.OF2.En]

[81O.OF2.t_Op]

&

0ms

81O.OF2.Op

Figure 3.16-2 Logic diagram of overfrequency protection (stage 2)


SIG

81O.En1

SIG

81O.En2

EN

[81O.OF3.En]

SIG

81O.Blk

SIG

FD.Pkp

OTH

U1<0.15Un

SIG

f40 or f65

OTH

f>[81O.f_Pkp]

&
&
81O.OF3.On

&
1

&
50ms

0ms
81O.St3

&
SET

f>[81O.OF3.f_Set]

EN

[81O.OF3.En]

[81O.OF3.t_Op]

&

0ms

81O.OF3.Op

Figure 3.16-3 Logic diagram of overfrequency protection (stage 3)


SIG

81O.En1

SIG

81O.En2

EN

[81O.OF4.En]

SIG

81O.Blk

SIG

FD.Pkp

OTH

U1<0.15Un

SIG

f40 or f65

OTH

f>[81O.f_Pkp]

&
&
81O.OF4.On

&
1

&
50ms

0ms
81O.St4

&
SET

f>[81O.OF4.f_Set]

EN

[81O.OF4.En]

[81O.OF4.t_Op]

&

0ms

81O.OF4.Op

Figure 3.16-4 Logic diagram of overfrequency protection (stage 4)

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SIG

81O.St1

SIG

81O.St2

SIG

81O.St3

SIG

81O.St4

1
81O.St

Figure 3.16-5 Logic diagram of overfrequency protection (start)

3.16.1.6 Settings
Table 3.16-2 Settings of overfrequency protection
No.

Name

Range

Step

Unit

81O.f_Pkp

50.000~65.000 (Hz)

0.001

Hz

81O.OF1.f_Set

50.000~65.000 (Hz)

0.001

Hz

81O.OF1.t_Op

0.050~20.000 (s)

0.001

Remark
Frequency

pickup

81O.OF1.En

for

overfrequency protection
Frequency setting for stage 1 of
overfrequency protection
Time

delay

for

stage

of

of

overfrequency protection
Enabling/disabling

setting

stage

overfrequency protection

0 or 1

0: disable
1: enable

81O.OF2.f_Set

50.000~65.000 (Hz)

0.001

Hz

81O.OF2.t_Op

0.050~20.000 (s)

0.001

Frequency setting for stage 2 of


overfrequency protection
Time

delay

for

81O.OF2.En

of

of

overfrequency protection
Enabling/disabling

stage

stage

overfrequency protection

0 or 1

0: disable
1: enable

81O.OF3.f_Set

50.000~65.000 (Hz)

0.001

Hz

81O.OF3.t_Op

0.050~20.000 (s)

0.001

Frequency setting for stage 3 of


overfrequency protection
Time

delay

for

81O.OF3.En

of

of

overfrequency protection
Enabling/disabling

10

stage

stage

overfrequency protection

0 or 1

0: disable
1: enable

11

81O.OF4.f_Set

50.000~65.000 (Hz)

0.001

Hz

12

81O.OF4.t_Op

0.050~20.000 (s)

0.001

13

81O.OF4.En

0 or 1

Frequency setting for stage 4 of


overfrequency protection
Time

delay

for

stage

of

of

overfrequency protection
Enabling/disabling

stage

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overfrequency protection
0: disable
1: enable

3.16.2 Underfrequency Protection


3.16.2.1 General Application
In case of frequency decline due to lack of active power in the power system, underfrequency
protection operates to shed part of the load according to the declined value of frequency to
re-balance the power supply and the load.
3.16.2.2 Function Description
Underfrequency protection consists of the four stages (stage 1 to stage 4). When system
frequency is smaller than the setting [81U.f_Pkp], underfrequency protection will put into service.
In order to prevent possible maloperation of underfrequency protection in conditions of high
harmonics, voltage circuit failures and so on, such blocking measures are carried out as follows:
1.

Blocking in undervoltage condition

If the positive voltage U1<0.15Un, the calculation of protection is not carried out and the output
relay will be blocked.
2.

df/dt blocking element

If df/dt[81U.df/dt_Blk], the calculation of protection is not carried out and the output relay will
be blocked. The blocking element will not be released automatically until the system frequency
recovers to be less than the setting [81U.f_Pkp].
3.

Frequency abnormality condition

When f<40Hz or f>65Hz, underfrequency protection will be blocked


Operation criteria of underfrequency protection is shown in the following equation.
f<[81U.UFx.f_Set]

Equation 3.16-2

Where:
f is system frequency.
[81U.UFx.f_Set] is the frequency settings of stage x (x=1, 2, 3 or 4) of underfrequency protection.
The equation of df/dt blocking function is as follows.
df/dt[81U.df/dt_Blk]

Equation 3.16-3

Where:
df/dt is the frequency slip speed and the time step (i.e. dt) for the calucation is equal to 5 cycle.
[81U.df/dt_Blk] is the setting of df/dt blocking underfrequency protection.
Underfrequency protection can be blocked by the frequency slip speed (df/dt). If the logic setting
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[81U.UFx.En_df/dt_Blk] (x=1, 2, 3 or 4) is set as 1, when Equation 3.16-2 and Equation 3.16-3


are met, it is decided that a fault occurred and the corresponding stage underfrequency protection
is blocked at the same time for the purpose of waiting for operation of other related protection. The
blocking signal will not reset until the system frequency recovers, i.e. the system frequency is
greater than the setting [81U.f_Pkp]. If the logic setting is set as 0, when Equation 3.16-2 and
Equation 3.16-3 are met, the stage underfrequency protection will be released to operate.
3.16.2.3 Function Block Diagram
81U.UFx
81U.En1

81U.UFx.On

81U.En2

81U.St

81U.Blk

81U.UFx.Op

3.16.2.4 I/O Signals


Table 3.16-3 I/O signals of underfrequency protection
No.

Input Signal

81U.En1

81U.En2

81U.Blk

No.

Description
Underfrequency protection enabling input 1, it is triggered from binary input or
programmable logic etc.
Underfrequency protection enabling input 2, it is triggered from binary input or
programmable logic etc.
Underfrequency protection blocking input, it is triggered from binary input or
programmable logic etc.

Output Signal

Description

81U.UFx.On

Stage x of underfrequency protection is enabled (x=1, 2, 3 or 4).

81U.UFx.Op

Stage x of underfrequency protection operates (x=1, 2, 3 or 4).

81U.St

Underfrequency protection starts.

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3.16.2.5 Logic
SIG

81U.En1

SIG

81U.En2

EN

[81U.UF1.En]

SIG

81U.Blk

SIG

FD.Pkp

OTH

U1<0.15Un

SIG

f<40 or f>65

OTH

f<[81U.f_Pkp]

50ms

SET

-df/dt>[81U.df/dt_Blk]

>=1

&
&
81U.UF1.On

&
&
1

0ms
81U.St1

&
[81U.UF1.t_Op]

EN

81U.UF1.En_df/dt_Blk

SET

f<[81U.UF1.f_Set]

EN

[81U.UF1.En]

0ms

81U.UF1.Op

&

Figure 3.16-6 Logic diagram of underfrequency protection (stag1)


SIG

81U.En1

SIG

81U.En2

EN

[81U.UF2.En]

SIG

81U.Blk

SIG

FD.Pkp

OTH

U1<0.15Un

SIG

f<40 or f>65

OTH

f<[81U.f_Pkp]

50ms

SET

-df/dt>[81U.df/dt_Blk]

>=1

&
&
81U.UF2.On

&
&
1

0ms
81U.St2

&
[81U.UF2.t_Op]

EN

81U.UF2.En_df/dt_Blk

SET

f<[81U.UF2.f_Set]

EN

[81U.UF2.En]

0ms

81U.UF2.Op

&

Figure 3.16-7 Logic diagram of underfrequency protection (stag2)

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SIG

81U.En1

SIG

81U.En2

EN

[81U.UF3.En]

SIG

81U.Blk

SIG

FD.Pkp

OTH

U1<0.15Un

SIG

f<40 or f>65

OTH

f<[81U.f_Pkp]

50ms

SET

-df/dt>[81U.df/dt_Blk]

>=1

&
&
81U.UF3.On

&
&
1

0ms
81U.St3

&
[81U.UF3.t_Op]

EN

81U.UF3.En_df/dt_Blk

SET

f<[81U.UF3.f_Set]

EN

[81U.UF3.En]

0ms

81U.UF3.Op

&

Figure 3.16-8 Logic diagram of underfrequency protection (stag3)


SIG

81U.En1

SIG

81U.En2

EN

[81U.UF4.En]

SIG

81U.Blk

SIG

FD.Pkp

OTH

U1<0.15Un

SIG

f<40 or f>65

OTH

f<[81U.f_Pkp]

50ms

SET

-df/dt>[81U.df/dt_Blk]

>=1

&
&
81U.UF4.On

&
&
1

0ms
81U.St4

&
[81U.UF4.t_Op]

EN

81U.UF4.En_df/dt_Blk

SET

f<[81U.UF4.f_Set]

EN

[81U.UF4.En]

0ms

81U.UF4.Op

&

Figure 3.16-9 Logic diagram of underfrequency protection (stag4)

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SIG

81U.St1

SIG

81U.St2

SIG

81U.St3

SIG

81U.St4

>=1
>=1
81U.St

>=1

Figure 3.16-10 Logic diagram of underfrequency protection (start)

3.16.2.6 Settings
Table 3.16-4 Settings of underfrequency protection
No.

Name

Range

Step

Unit

81U.f_Pkp

45.000~60.000

0.01

Hz

81U.df/dt_Blk

0.200~20.000

0.01

Hz/s

81U.UF1.f_Set

45.000~60.000

0.001

Hz

81U.UF1.t_Op

0.050~30.000

0.01

Remark
Frequency

pickup

81U.UF1.En

for

underfrequency protection
Rate

of

frequency

change

for

blocking underfrequency protection


Frequency setting for stage 1 of
underfrequency protection
Time

delay

for

stage

of

of

underfrequency protection
Enabling/disabling

setting

stage

underfrequency protection

0 or 1

0: disable
1: enable
Enabling/disabling rate of frequency
change

81U.UF1.En_df/dt_Blk

0 or 1

to

block

stage

of

underfrequency protection
0: disable
1: enable

81U.UF2.f_Set

45.000~60.000

0.001

Hz

81U.UF2.t_Op

0.050~30.000

0.01

Frequency setting for stage 2 of


underfrequency protection
Time

delay

for

81U.UF2.En

of

of

underfrequency protection
Enabling/disabling

stage

stage

underfrequency protection

0 or 1

0: disable
1: enable
Enabling/disabling rate of frequency
change

10

81U.UF2.En_df/dt_Blk

0 or 1

to

block

stage

of

underfrequency protection
0: disable
1: enable

11

81U.UF3.f_Set

45.000~60.000

0.001

3-150

Hz

Frequency setting for stage 3 of


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3 Operation Theory
underfrequency protection
12

81U.UF3.t_Op

0.050~30.000

0.01

Time

delay

for

81U.UF3.En

of

of

underfrequency protection
Enabling/disabling

13

stage

stage

underfrequency protection

0 or 1

0: disable
1: enable
Enabling/disabling rate of frequency
change

14

81U.UF3.En_df/dt_Blk

0 or 1

to

block

stage

of

underfrequency protection
0: disable
1: enable

15

81U.UF4.f_Set

45.000~60.000

0.001

Hz

16

81U.UF4.t_Op

0.050~30.000

0.01

Frequency setting for stage 4 of


underfrequency protection
Time

delay

for

81U.UF4.En

of

of

underfrequency protection
Enabling/disabling

17

stage

stage

underfrequency protection

0 or 1

0: disable
1: enable
Enabling/disabling rate of frequency
change

18

81U.UF4.En_df/dt_Blk

0 or 1

to

block

stage

of

underfrequency protection
0: disable
1: enable

3.17 Breaker Failure Protection


3.17.1 General Application
Duplicated protection configurations are usually adopted for EHV power system, but the primary
equipment, circuit breaker, is not duplicated. Breaker failure protection is adopted to cater circuit
breaker tripping failure.
Breaker failure protection issues a back-up trip command to trip adjacent circuit breakers in case
of a tripping failure of the circuit breaker, and clears the fault as requested by the device. To utilize
the protection information of faulty equipment and the electrical information of failure circuit
breaker to constitute the criterion of breaker failure protection, it can ensure that the adjacent
circuit breakers of failure circuit breaker are tripped with a shorter time delay, so that the affected
area is minimized, and ensure stable operation of the entire power grid to prevent generators,
transformers and other components from seriously damaged.

3.17.2 Function Description


The instantaneous re-tripping function, after receiving tripping signal from other device and the
corresponding phase overcurrent element operating, is available and provides phase-segregated
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binary output contact, which can ensure the circuit breaker is still tripped in case the secondary
circuit between the device and the circuit breaker is abnormal, to avoid undesired tripping of
breaker failure protection and the expansion of the affected area. Instantaneous re-tripping
function does not block AR.
When both the phase-segregated tripping contact from line protection and the corresponding
phase overcurrent element operate, or both the three-phase tripping contact and any phase
overcurrent element operate, breaker failure protection will send three-phase tripping command to
trip local circuit breaker after time delay of [50BF.t1_Op] and trip all adjacent circuit breakers after
time delay of [50BF.t2_Op].
When the protection element except undervoltage element within this device operates and issues
tripping signal, breaker failure protection will also be initiated.
Taking into account that the faulty current is too small for generator or transformer fault, the
sensitivity of phase current element may not meet the requirements, zero-sequence current
criterion and negative-sequence current criterion are provided in addition to the phase overcurrent
element for breaker failure protection initiated by input signal [50BF.ExTrp3P_GT] from generator
and transformer protection. They can be enabled or disabled by logic settings [50BF.En_3I0_3P]
and [50BF.En_I2_3P] respectively.
For some special fault (for example, mechanical protection or overvoltage protection operating),
maybe faulty current is very small and current criterion of breaker failure protection is not met, in
order to make breaker failure protection can also operate under the above situation, an input
signal [50BF.ExTrp_WOI] is equipped to initiate breaker failure protection, once the input signal is
energized, normally closed auxiliary contact of circuit breaker is chosen in addition to breaker
failure current check to trigger breaker failure timer. The device takes current as priority with CB
auxiliary contact (52b) as an option criterion for breaker failure check.

3.17.3 Function Block Diagram


50BF
50BF.ExTrp3P_L

50BF.On

50BF.ExTrp3P_GT

50BF.Op_ReTrpA

50BF.ExTrp_WOI

50BF.Op_ReTrpB

50BF.ExTrpA

50BF.Op_ReTrpC

50BF.ExTrpB

50BF.Op_ReTrp3P

50BF.ExTrpC

50BF.Op_t1

50BF.En

50BF.Op_t2

50BF.Blk

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3.17.4 I/O Signals


Table 3.17-1 I/O signals of breaker failure protection
No.

Input Signal

Description

50BF.ExTrp3P_L

Input signal of three-phase tripping contact from line protection

50BF.ExTrp3P_GT

50BF.ExTrpA

Input signal of phase-A tripping contact from external device

50BF.ExTrpB

Input signal of phase-B tripping contact from external device

50BF.ExTrpC

Input signal of phase-C tripping contact from external device

Input signal of three-phase tripping contact from generator or transformer


protection

Input signal of three-phase tripping contact from external device. Once it is


6

50BF.ExTrp_WOI

energized, normally closed auxiliary contact of circuit breaker is chosen in


addition to breaker failure current check to trigger breaker failure timers.

50BF.En

50BF.Blk

No.

Output Signal

Input signal of enabling breaker failure protection


Breaker failure protection blocking input, such as function blocking binary input.
When the input is 1, breaker failure protection is reset and time delay is cleared.
Description

50BF.On

Breaker failure protection is enabled

50BF.Op_ReTrpA

Breaker failure protection operates to re-trip phase-A circuit breaker

50BF.Op_ReTrpB

Breaker failure protection operates to re-trip phase-B circuit breaker

50BF.Op_ReTrpC

Breaker failure protection operates to re-trip phase-C circuit breaker

50BF.Op_ReTrp3P

Breaker failure protection operates to re-trip three-phase circuit breaker

50BF.Op_t1

Stage 1 of breaker failure protection operates

50BF.Op_t2

Stage 2 of breaker failure protection operates

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3.17.5 Logic
SIG

50BF.En

EN

[50BF.En]

SIG

50BF.Blk

SIG

50BF.On

SIG

FD.Pkp

EN

[50BF.En_ReTrp]

EN

[50BF.En_3I0_1P]

SET

3I0>[50BF.3I0_Set]

SIG

BFI_A

&
50BF.On

&

>=1

>=1

&

&
>=1

BI

[50BF.ExTrpA]

SET

IA>[50BF.I_Set]

SIG

BFI_B

>=1

&

[50BF.ExTrpB]

SET

IB>[50BF.I_Set]

SIG

BFI_C

>=1

&

[50BF.ExTrpC]

SET

IC>[50BF.I_Set]

SIG

BFI_3P

BI

[50BF.ExTrp3P_L]

[50BF.t_ReTrp] 0ms

[50BF.Op_ReTrpB]

[50BF.t_ReTrp] 0ms

[50BF.Op_ReTrpC]

&
>=1

BI

[50BF.Op_ReTrpA]

&
>=1

BI

[50BF.t_ReTrp] 0ms

>=1
>=1
>=1
&
>=1

BI

[50BF.ExTrp3P_GT]

BI

[50BF.ExTrp_WOI]

EN

[50BF.En_3I0_3P]

[50BF.Op_ReTrp3P]

&

>=1

&

SET

3I0>[50BF.3I0_Set]

EN

[50BF.En_I2_3P]

SET

I2>[50BF.I2_Set]

EN

[50BF.En_CB_Ctrl]

BI

[52b_PhA]

&

>=1
>=1
&

&

&

[50BF.t1_Op]

0ms

[50BF.Op_t1]

[50BF.t2_Op]

0ms

[50BF.Op_t2]

&

&
BI

[52b_PhB]

BI

[52b_PhC]

SIG

50BF.On

SIG

FD.Pkp

&

Figure 3.17-1 Logic diagram of breaker failure protection

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3.17.6 Settings
Table 3.17-2 Settings of breaker failure protection
No.

Name

Range

Step

Unit

Remark
Current setting of phase current
criterion for BFP
Current setting of zero-sequence
current criterion for BFP
Current
setting
of
negative-sequence
current
criterion for BFP

50BF.I_Set

(0.050~30.000 )In

0.001

50BF.3I0_Set

(0.050~30.000 )In

0.001

50BF.I2_Set

(0.050~30.000 )In

0.001

50BF.t_ReTrp

0.000~10.000

0.001

Time delay of re-tripping for BFP

50BF.t1_Op

0.000~10.000

0.001

Time delay of stage 1 for BFP

50BF.t2_Op

0.000~10.000

0.001

Time delay of stage 2 for BFP

50BF.En

0 or 1

50BF.En_ReTrp

0 or 1

50BF.En_3I0_1P

0 or 1

10

50BF.En_3I0_3P

0 or 1

11

50BF.En_I2_3P

0 or 1

12

50BF.En_CB_Ctrl

0 or 1

Enabling/disabling breaker failure


protection
0: disable
1: enable
Enabling/disabling re-trip function
for BFP
0: disable
1: enable
Enabling/disabling zero-sequence
current criterion for BFP initiated by
single-phase tripping contact
0: disable
1: enable
Enabling/disabling zero-sequence
current criterion for BFP initiated by
three-phase tripping contact
0: disable
1: enable
Enabling/disabling
negative-sequence current criterion
for BFP initiated by three-phase
tripping contact
0: disable
1: enable
Enabling/disabling breaker failure
protection can be initiated by
normally closed contact of circuit
breaker
0: disable
1: enable

3.18 Thermal Overload Protection


3.18.1 General Application
During overload operation of a transmission line (specially for cable), great current results in
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greater heat to lead temperature increase and if the temperature reaches too high values the
equipment might be damaged.
Thermal overload protection estimates the internal heat content (temperature) continuously. This
estimation is made by using a thermal model with two time constants, which is based on current
measurement.
When the temperature increases to the alarm value, the protection issues alarm signals to remind
the operator for attention, and if the temperature continues to increase to the trip value, the
protection sends trip command to disconnect the protected line.

3.18.2 Function Description


Thermal overload protection has following functions:

Thermal time characteristic adopting IEC 60255-8

Two stages for alarm purpose and two stages for trip purpose

Thermal accumulation can be cleared by external input signal

The device provides a thermal overload model which is based on the IEC60255-8 standard. The
thermal overload formulas are shown as below.
1.

Criterion of cooling start characteristic:

I2
T ln 2
I (k I B ) 2
2.

Criterion of hot start characteristic:

T ln

I 2 I p2
I 2 (k I B ) 2

Where:
T = Time to operate (in seconds)

= Thermal time constant of the equipment to be protected, the setting [49.Tau]


IB = Full load current rating, the setting [49.Ib_Set]
I = The RMS value of the largest phase current
IP = Steady state pre-loading before application of the overload
k = Factor associated to the thermal state formula, the setting [49.K]
ln = Natural logarithm
The characteristic curve of thermal overload model is shown in Figure 3.18-1.

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Refer to IEC60255-8

Ip
P=
IB

P = 0.0
P = 0.6
P = 0.8
P = 0.9

kIB

Figure 3.18-1 Characteristic curve of the thermal overload model

The hot start characteristic is adopted in the device. The calculation is carried out at zero of Ip, so
users need not to set the value of Ip.
Tripping outputs of the protection is controlled by current, even if the thermal accumulation value is
greater than the setting for tripping, the protection drops off instantaneously when current
disappears. Alarm outputs of the protection is not controlled by current, and only if the thermal
accumulation value is greater than the setting for alarm, alarm output contacts, which can be
connected to block the auto-reclosure, will operate.

3.18.3 Function Block Diagram


49
49.Clr_Cmd

49.On

49.En

49.St

49.Blk

49-1.Alm
49-1.Op
49-2.Alm
49-2.Op

3.18.4 I/O Signals


Table 3.18-1 I/O signals of thermal overload protection
No.

Input Signal

49.Clr_Cmd

49.En

49.Blk

Description
Input signal of clear thermal accumulation value
Thermal overload protection enabling input, it is triggered from binary input or
programmable logic etc.
Thermal overload protection blocking input, it is triggered from binary input or

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programmable logic etc.
No.

Output Signal

Description

49.On

Thermal overload protection is enabled.

49.St

Thermal overload protection starts.

49-1.Op

Stage 1 of thermal overload protection operates to trip.

49-2.Op

Stage 2 of thermal overload protection operates to trip.

49-1.Alm

Stage 1 of thermal overload protection operates to alarm.

49-2.Alm

Stage 2 of thermal overload protection operates to alarm.

3.18.5 Logic
SIG

49.En

SIG

49.Blk

EN

[49-1.En_Trp]

EN

[49-1.En_Alm]

SIG

FD.Pkp

&
&
49.On
>=1

&
49.St
&

Timer
t

49-1.Op

t
SIG

I3P
Timer
t

&
SET

[49.Ib_Set]

BI

[49.Clr_Cmd]

49-1.Alm

Figure 3.18-2 Logic diagram of thermal overload protection (stage 1)

SIG

49.En

SIG

49.Blk

EN

[49-2.En_Trp]

EN

[49-2.En_Alm]

SIG

FD.Pkp

&
&
49.On
>=1

&
49.St
&

Timer
t

49-2.Op

t
SIG

I3P
&

SET

[49.Ib_Set]

BI

[49.Clr_Cmd]

Timer
t

49-2.Alm

Figure 3.18-3 Logic diagram of thermal overload protection (stage 2)

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3.18.6 Settings
Table 3.18-2 Settings of thermal overload protection
No.

Name

Range

Step

Unit

49-1.K

1.000~3.000

0.001

49-2.K

1.000~3.000

0.001

49.Ib_Set

(0.050~30.000 )In

0.001

49.Tau

0.100~100.000

0.001

min

49-1.En_Alm

0 or 1

49-1.En_Trp

0 or 1

49-2.En_Alm

0 or 1

49-2.En_Trp

0 or 1

Remark
The factor setting for stage 1 of
thermal overload protection which
is associated to the thermal state
formula
The factor setting for stage 2 of
thermal overload protection which
is associated to the thermal state
formula
The reference current setting of the
thermal overload protection
The time constant setting of the
IDMT overload protection
Enabling/disabling stage 1 of
thermal overload protection for
alarm purpose
0: disable
1: enable
Enabling/disabling stage 1 of
thermal overload protection for trip
purpose
0: disable
1: enable
Enabling/disabling stage 2 of
thermal overload protection for
alarm purpose
0: disable
1: enable
Enabling/disabling stage 2 of
thermal overload protection for trip
purpose
0: disable
1: enable

3.19 Stub Overcurrent Protection


3.19.1 General Application
Stub overcurrent protection is mainly designed for one and a half breakers arrangement. When
line disconnector is open and transmission line is put into maintenance, line VT is no voltage.
Distance protection is disabled, and stub overcurrent protection is enabled. It is used to protect
stub section among for two circuit breakers and line disconnector. Usually, stub overcurrent
protection is enabled automatically by normally closed auxiliary contact of line disconnector.

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CT1

CT2

Bus

Bus

To the device

Line

Line

Figure 3.19-1 3/2 breakers arrangement

3.19.2 Function Block Diagram


50STB
50STB.En1

50STB.On

50STB.En2

50STB.Op

50STB.Blk

50STB.St

50STB.89b_DS

50STB.StA
50STB.StB
50STB.StC

3.19.3 I/O Signals


Table 3.19-1 I/O signals of stub overcurrent protection
No.

Input Signal

50STB.En1

50STB.En2

50STB.Blk

50STB.89b_DS

No.

Output Signal

Description
Stub overcurrent protection enabling input 1, it is triggered from binary input or
programmable logic etc.
Stub overcurrent protection enabling input 2, it is triggered from binary input or
programmable logic etc.
Stub overcurrent protection blocking input, it is triggered from binary input or
programmable logic etc.
Normally closed auxiliary contact of line disconnector
Description

50STB.On

Stub overcurrent protection is enabled.

50STB.Op

Stub overcurrent protection operates.

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50STB.St

Stub overcurrent protection starts.

50STB.StA

Phase A of stub overcurrent protection starts.

50STB.StB

Phase B of stub overcurrent protection starts.

50STB.StC

Phase C of stub overcurrent protection starts.

3.19.4 Logic
Only one stage is available to stub overcurrent protection. Based on calculating summation
current from dual CTs, the logic scheme of stub overcurrent protection is shown as Figure 3.19-2.
SIG

50STB.En1

SIG

50STB.En2

SIG

50STB.Blk

EN

[50STB.En]

SIG

FD.Pkp

SIG

50STB.89b_DS

&
&
50STB.On

&

>=1

[50STB.t_Op]

50STB.Op

50STB.St

&
50STB.StA
SET

Ia>[50STB.I_Set]

&
50STB.StB
SET

Ib>[50STB.I_Set]

&
50STB.StC
SET

Ic>[50STB.I_Set]

Figure 3.19-2 Logic diagram of stub overcurrent protection

3.19.5 Settings
Table 3.19-2 Settings of stub overcurrent protection
No.

Name

Range

Step

Unit

50STB.I_Set

(0.050~30.000)In

0.001

50STB.t_Op

0.000~10.000

0.001

Remark
Current setting of stub overcurrent
protection
Time delay of stub overcurrent
protection
Enabling/disabling stub overcurrent

50STB.En

protection

0 or 1

1: enable
0: disable

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3.20 Dead Zone Protection


3.20.1 General Application
Generally, fault current is very large when multi-phase fault occurs between CT and circuit breaker
(i.e. dead zone) and it will have a greater impact on the system. Breaker failure protection can
operate after a longer time delay, in order to clear the dead zone fault quickly and improve the
system stability, dead zone protection with shorter time delay (compared with breaker failure
protection) is adopted.

3.20.2 Function Description


For some wiring arrangement (for example, circuit breaker is located between CT and the line), if
fault occurs between CT and circuit breaker, line protection can operate to trip circuit breaker
quickly, but the fault have not been cleared since local circuit breaker is tripped. Here dead zone
protection is needed in order to trip relevant circuit breaker.
The criterion for dead zone protection is: when dead zone protection is enabled, binary input of
initiating dead zone protection is energized (by default, three-phase tripping signal is used to
initiate dead zone protection), if overcurrent element for dead zone protection operates, then
corresponding circuit breaker is tripped and three phases normally closed contact of the circuit
breaker are energized, dead zone protection will operate to trip adjacent circuit breaker after a
time delay.

3.20.3 Function Block Diagram


50DZ
50DZ.En1

50DZ.On

50DZ.En2

50DZ.Op

50DZ.Blk

50DZ.St

50DZ.Init

3.20.4 I/O Signal


Table 3.20-1 I/O signals of dead zone protection
No.

Input Signal

Description

50DZ.En1

Dead zone protection enabling input 1, it can be binary inputs or logic link.

50DZ.En2

Dead zone protection enabling input 2, it can be binary inputs or logic link.

50DZ.Blk

50DZ.Init

No.

Dead zone protection blocking input, such as function blocking binary input. When
the input is 1, dead zone protection is reset and time delay is cleared.
Initiation signal input of the dead zone protection.

Output Signal

Description

50DZ.On

Dead zone protection is enabled.

50DZ.St

Dead zone protection starts.

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50DZ.Op

Dead zone protection operates.

3.20.5 Logic
EN

[50DZ.En]

SIG

50DZ.En1

SIG

50DZ.En2

SIG

50DZ.Blk

SIG

FD.Pkp

BI

[52b_PhA]

BI

[52b_PhB]

BI

[52b_PhC]

SET

Ia > [50DZ.I_Set]

SET

Ib > [50DZ.I_Set]

SET

Ic > [50DZ.I_Set]

SIG

&
&
50DZ.On

&

&

50DZ.St

&
>=1

[50DZ.t_Op]

&

0ms

50DZ.Op

50DZ.Init

Figure 3.20-1 Dead zone protection

3.20.6 Settings
Table 3.20-2 Settings of dead zone protection
No.

Name

Range

Step

Unit

Remark
Current

50DZ.I_Set

(0.050~30.000)In

0.001

setting

for

dead

zone

protection. This setting shall ensure the


protection being sensitive enough if
dead zone fault occurs.

50DZ.t_Op

0.000~10.000

0.001

Time delay of dead zone protection.


Enabling/disabling

50DZ.En

0 or 1

dead

zone

protection.
1: enable
0: disable

3.21 Pole Discrepancy Protection


3.21.1 General Application
The pole discrepancy of circuit breaker may occur during operation of a breaker with segregated
operating gears for the three phases. The reason could be an interruption in the tripping/closing
circuits, or mechanical failure. A pole discrepancy can only be tolerated for a limited period. When
there is loading, zero-sequence or negative-sequence current will be generated in the power

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system, which will result in overheat of the generator or the motor. With the load current increasing,
overcurrent elements based on zero-sequence current or negative-sequence current may operate.
Pole discrepancy protection is required to operate before the operation of these overcurrent
elements.

3.21.2 Function Description


Pole discrepancy protection determines three-phase breaker pole discrepancy condition by its
phase segregated CB auxiliary contacts. In order to improve the reliability of pole discrepancy
protection, the asymmetrical current component can be selected as addition criteria when needed.

3.21.3 Function Block Diagram


62PD
62PD.En1

62PD.On

62PD.En2

62PD.Op

62PD.Blk

62PD.St

3.21.4 I/O Signals


Table 3.21-1 I/O signals of pole discrepancy protection
No.

Input Signal

62PD.En1

62PD.En2

62PD.Blk

No.

Description
Pole discrepancy protection enabling input 1, it is triggered from binary input or
programmable logic etc.
Pole discrepancy protection enabling input 2, it is triggered from binary input or
programmable logic etc.
Pole discrepancy protection blocking input, it is triggered from binary input or
programmable logic etc.

Output Signal

Description

62PD.On

Pole discrepancy protection is enabled.

62PD.Op

Pole discrepancy protection operates to trip

62PD.St

Pole discrepancy protection starts

3.21.5 Logic
Phase-segregated circuit breaker auxiliary contacts are connected to the device. When the state
of three phase-segregated circuit breaker auxiliary contacts are inconsistent, pole discrepancy
protection will be started and initiate output after a time delay [62PD.t_Op].
Pole discrepancy protection can be blocked by external input signal [62PD.Blk]. In general, this
input signal is usually from the output of 1-pole AR initiation, so as to prevent pole discrepancy
protection from operation during 1-pole AR initiation.

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SIG

62PD.En1

SIG

62PD.En2

EN

[62PD.En]

BI

[62PD.Blk]

SIG

BI

&
&
62PD.On

&

FD.Pkp

62PD.St

&
[62PD.t_Op]

[62PD.In_PD]

EN

[62PD.En_3I0/I2_Ctrl]

SET

3I0>[62PD.3I0_Set]

SET

I2>[62PD.I2_Set]

0ms

62PD.Op

>=1
>=1

Figure 3.21-1 Logic diagram of pole discrepancy protection

The signal 62PD.In_PD is input signal of pole discrepancy status, which is always from PD signal
of circuit breaker position supervison module. When the states of three auxiliary contacts of
phase-segregate circuit breaker are inconsistent, the signal is energized.

3.21.6 Settings
Table 3.21-2 Settings of pole discrepancy protection
No.

Name

Range

Step

Unit

62PD.3I0_Set

(0.050~30.000 )In

0.001

62PD.I2_Set

(0.050~30.000 )In

0.001

62PD.t_Op

0.000~600.000

0.001

62PD.En

0 or 1

62PD.En_3I0/I2_Ctrl

0 or 1

Remark
Current setting of residual current
criterion for pole discrepancy
protection
Current
setting
of
negative-sequence current criterion
for pole discrepancy protection
Time delay of pole discrepancy
protection
Enabling/disabling
pole
discrepancy protection
0: disable
1: enable
Enabling/disabling
residual
current
criterion
and
negative-sequence current criterion
for pole discrepancy protection
0: disable
1: enable

3.22 Broken Conductor Protection


3.22.1 General Application
Single-phase earthing fault and two-phases earthing fault are the most common fault on circuits,
the fault is easy to detect because the fault current will increase obviously.
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Broken-conductor fault is difficult to detect since there is no increase of current but


negative-sequence current, so negative-sequence overcurrent protection can be considered to
clear broken-conductor fault. However, under heavy load condition, negative-sequence current is
relative large due to unbalance loading, but negative-sequence current because of
broken-conductor fault under light load condition is relative small. If negative-sequence current
protection is set larger than maximum negative-sequence current under loading, the protection
may be failure to operate if broken-conductor fault happens under light load condition,
negative-sequence overcurrent protection is therefore not suitable to apply for broken-conductor
fault.
The network of single-phase broken condition is similar to that of two-phases earthing fault,
positive-sequence, negative-sequence and zero-sequence network is connected in parallel, I2/I1=
Z0/(Z0+Z2), generally, zero-sequence impedance is larger than positive-sequence impedance, i.e.
I2/I1>0.5. The network of two-phases broken condition is similar to that of single-phase earthing
fault, positive-sequence, negative-sequence and zero-sequence network is connected in series,
so I2/I1=1.

3.22.2 Function Description


Broken-conductor fault mainly is single-phase broken or two-phases broken. According to the ratio
of negative-sequence current to positive-sequence current (I2/I1), it is used to judge whether there
is an broken-conductor fault. Negative-sequence current under normal operating condition (i.e.
unbalance current) is due to CT error and unbalance load, so the ratio of negative-sequence
current to positive-sequence current (amplitude) is relative steady. The value with margin can then
be used as the setting of broken conductor protection. It is mainly used to detect broken-conductor
fault and CT circuit failure as well.

3.22.3 Function Block Diagram


46BC
46BC.En1

46BC.On

46BC.En2

46BC.St

46BC.Blk

46BC.Op
46BC.Alm

3.22.4 I/O Signals


Table 3.22-1 I/O signals of broken conductor protection
No.

Input Signal

46BC.En1

46BC.En2

Description
Enable broken conductor protection input 1, it is triggered from binary input or
programmable logic etc.
Enable broken conductor protection input 2, it is triggered from binary input or
programmable logic etc.

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3

Broken conductor protection blocking input, it is triggered from binary input or

46BC.Blk

No.

programmable logic etc.

Output Signal

Description

46BC.On

Broken-conductor protection is enabled.

46BC.St

Broken-conductor protection starts.

46BC.Op

Broken-conductor protection operates to trip.

46BC.Alm

Broken-conductor protection operates to alarm.

3.22.5 Logic
SIG

[46BC.En1]

&
&

SIG

[46BC.En2]

SIG

[46BC.Blk]

SET

Ia>[46BC.I_Min]

46BC.On
46BC.St
&
[46BC.t_Op] 0ms

>=1
SET

Ib>[46BC.I_Min]

SET

Ic>[46BC.I_Min]

SET

SET

&

I2/I1>[46BC.I2/I1_Set]

46BC.Op

[46BC.En_Trp]
&
46BC.Alm

SET

[46BC.En_Alm]

Figure 3.22-1 Logic diagram of broken conductor protection

3.22.6 Settings
Table 3.22-2 Settings of broken conductor protection
No.

Name

Range

Step

Unit

46BC.I2/I1_Set

0.20~1.00

0.001

46BC.t_Op

0.000~600.000

0.001

46BC.I_Min

(0.050~30.000)In

0.001

46BC.En_Trp

0 or 1

46BC.En_Alm

0 or 1

Remark
negative-sequence
current
to
positive-sequence current of broken
conductor protection
Time delay of broken conductor
protection
Minimum operation current of broken
conductor protection
Enabling/disabling broken conductor
protection to operate to trip
0: disable
1: enable
Enabling/disabling broken conductor
protection to operate to alarm
0: disable
1: enable

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3.23 Synchrocheck
3.23.1 General Application
The purpose of synchrocheck is to ensure two systems are synchronism before they are going to
be connected.
When two asynchronous systems are connected together, due to phase difference between the
two systems, larger impact will be led to the system during closing. Thus auto-reclosing and
manual closing are applied with the synchrocheck to avoid this situation and maintain the system
stability. The synchrocheck includes synchronism check and dead charge check.

3.23.2 Function Description


The synchronism check function measures the conditions across the circuit breaker and compares
them with the corresponding settings. The output is only given if all measured quantities are
simultaneously within their set limits.
The dead charge check function measures the amplitude of line voltage and bus voltage at both
sides of the circuit breaker, and then compare them with the live check setting [25.U_Lv] and the
dead check setting [25.U_Dd]. The output is only given when the measured quantities comply with
the criteria.
Synchrocheck in this device can be used for auto-reclosing and manual closing for both
single-breaker and dual-breakers. Details are described in the following sections.
When used for the synchrocheck of single-breaker, comparative relationship between reference
voltage (UL, three-phase protection voltage) and synchronism voltage (UB, single-phase
synchronism voltage) for synchronism check is as follows.
UL

UB

Figure 3.23-1 Relationship between reference voltage and synchronism voltage

Figure 3.23-1 shows the characteristics of synchronism check element used for the auto-reclosing
if both line and busbar are live. The synchronism check element operates if voltage difference,
phase angle difference and frequency difference are all within their setting values.
1.

The voltage difference is checked by the following equations.

UB[25.U_Lv]
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UL[25.U_Lv]
|UB-UL|[25.U_Diff]
2.

The phase difference is checked by the following equations.

UBULcos0
UBULsin([25.phi_Diff])UBULsin([25.phi_Diff])
Where,
is phase difference between UB and UL
3.

The frequency difference is checked by the following equations.

|f(UB)-f(UL)|[25.f_Diff]
If frequency check is disabled (i.e. [25.En_fDiffChk] is set as 0), a detected maximum slip cycle
can also be determined by the following equation based on phase difference setting and the
synchronism check time setting:
f =[25.phi_Diff]/(180[25.t_SynChk])
Where:
f is slip cycle
If frequency check is enabled (i.e. [25.En_fDiffChk] is set as 1), then [25.t_SynChk] can be set to
be a very small value (default value is 50ms).
3.23.2.1 Synchronism Voltage Circuit Failure Supervision
If synchronism voltage from line VT or busbar VT is used for auto-reclosing with synchronism or
dead line or busbar check, the synchronism voltage is monitored.
If the circuit breaker is in closed state (52b of three phases are de-energized), but the synchronism
voltage is lower than the setting [25.U_Lv], it means that synchronism voltage circuit fails and an
alarm [25.Alm_VTS_UB] or [25.Alm_VTS_UL] will be issued with a time delay of 10s.
If auto-reclosing is disabled, or the logic setting [25.En_NoChk] is set as 1, synchronism voltage
is not required and synchronism voltage circuit failure supervision will be disabled.
When synchronism voltage circuit failure is detected, function of synchronism check and dead
check in auto-reclosing logic will be disabled.
After synchronism voltage reverted to normal condition, the alarm will be reset automatically with a
time delay of 10s.

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SIG

FD.Pkp

SIG

79.Inprog

SIG

UL<[25.U_Lv]

BI

>=1
&
10s

10s

>=1
&

25.MCB_VT_UL

EN

25.En_SynChk

SIG

25.En_DdL_DdB

SIG

25.En_DdL_LvB

SIG

25.En_LvL_DdB

SIG

25.Blk_VTS_UL

25.Alm_VTS_UL

>=1
&

Figure 3.23-2 Line voltage circuit failure supervision logic

SIG

FD.Pkp

SIG

79.Inprog

SIG

UB<[25.U_Lv]

BI

>=1
&
10s

10s

>=1
&
25.Alm_VTS_UB

25.MCB_VT_UB

EN

25.En_SynChk

SIG

25.En_DdL_DdB

SIG

25.En_DdL_LvB

SIG

25.En_LvL_DdB

SIG

25.Blk_VTS_UB

>=1
&

Figure 3.23-3 Bus Voltage Circuit Failure Supervision logic

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3.23.3 Function Block Diagram


25
25.Blk_Chk

25.Ok_fDiffChk

25.Blk_SynChk

25.Ok_UDiffChk

25.Blk_DdChk

25.Ok_phiDiffChk

25.Start_Chk

25.Ok_DdL_DdB

25.Blk_VTS_UB

25.Ok_DdL_LvB

25.Blk_VTS_UL

25.Ok_LvL_DdB

25.MCB_VT_UB

25.Chk_LvL

25.MCB_VT_UL

25.Chk_DdL
25.Chk_LvB
25.Chk_DdB
25.Ok_DdChk
25.Ok_SynChk
25.Ok_Chk
25.Alm_VTS_UL
25.Alm_VTS_UB
f_Prot
f_Syn
U_Diff
f_Diff
Phi_Diff

3.23.4 I/O Signals


Table 3.23-1 I/O signals of synchrocheck
No.

Input Signal

Description

25.Blk_Chk

Input signal of blocking synchrocheck function for AR.

25.Blk_SynChk

25.Blk_DdChk

25.Start_Chk

25.Blk_VTS_UB

VT circuit supervision (UB) is blocked

25.Blk_VTS_UL

VT circuit supervision (UL) is blocked

Input signal of blocking synchronism check for AR. If the value is 1, the output of
synchronism check is 0.
Input signal of blocking dead charge check for AR.
Input signal of starting synchronism check, usually it was starting signal of AR
from auto-reclosing module.

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7

25.MCB_VT_UB

Binary input for VT MCB auxiliary contact (UB)

25.MCB_VT_UL

Binary input for VT MCB auxiliary contact (UL)

No.

Output Signal

Description
To indicate that frequency difference condition for synchronism check of AR is

25.Ok_fDiffChk

25.Ok_UDiffChk

25.Ok_phiDiffChk

25.Ok_DdL_DdB

Dead line and dead bus condition is met

25.Ok_DdL_LvB

Dead line and live bus condition is met

25.Ok_LvL_DdB

Live line and dead bus condition is met

25.Chk_LvL

Line voltage is greater than the voltage setting [25.U_Lv]

25.Chk_DdL

Line voltage is smaller than the voltage setting [25.U_Dd]

25.Chk_LvB

Bus voltage is greater than the voltage setting [25.U_Lv]

10

25.Chk_DdB

Bus voltage is smaller than the voltage setting [25.U_Dd]

11

25.Ok_DdChk

To indicate that dead charge check condition of AR is met

12

25.Ok_SynChk

To indicate that synchronism check condition of AR is met

13

25.Ok_Chk

To indicate that synchrocheck condition of AR is met

14

25.Alm_VTS_UB

Synchronism voltage circuit is abnormal (UB)

15

25.Alm_VTS_UL

Reference voltage circuit is abnormal (UL)

16

f_Prot

Frequency of the voltage used by protection calculation

17

f_Syn

Frequency of the voltage used by synchrocheck

18

U_Diff

Voltage difference for synchronism check

19

f_Diff

Frequency difference for synchronism check

20

phi_Diff

Phase difference for synchronism check

met, frequency difference between UB and UL is smaller than [25.f_Diff].


To indicate that voltage difference condition for synchronism check of AR is met,
voltage difference between UB and UL is smaller than [25.U_Diff]
To indicate phase difference condition for synchronism check of AR is met, phase
difference between UB and UL is smaller than [25.phi_Diff].

3.23.5 Logic
These logic diagrams give the introduction to the working principles of the synchronism check and
dead charge check.
3.23.5.1 Synchronism Check Logic
The frequency difference, voltage difference, and phase difference of voltages from both sides of
the circuit breaker are calculated in the device, they are used as input conditions of the
synchronism check.
When the synchronism check function is enabled and the voltages of both ends meets the
requirements of the voltage difference, phase difference, and frequency difference, and there is no
synchronism check blocking signal, it is regarded that the synchronism check conditions are met.

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SIG

25.Blk_Chk

SIG

25.Blk_SynChk

EN

[25.En_SynChk]

SIG

25.Start_Chk

SIG

UB>[25.U_Lv]

SIG

UL>[25.U_Lv]

SIG

25.Ok_UDiff

SIG

25.Ok_phiDiff

SIG

25.Ok_fDiff

>=1
&

&

&
50ms

0ms

[25.t_SynChk]

&

0ms

25.Ok_SynChk

Figure 3.23-4 Synchronism check

3.23.5.2 Dead Charge Check Logic


The dead charge check conditions have three types, namely, live-bus and dead-line check,
dead-bus and live-line check and dead-bus and dead-line check. The above three modes can be
enabled and disabled by the corresponding logic settings. The device can calculate the measured
bus voltage and line voltage at both sides of the circuit breaker and compare them with the
settings [25.U_Lv] and [25.U_Dd]. When the voltage is higher than [25.U_Lv], the bus/line is
regarded as live. When the voltage is lower than [25.U_Dd], the bus/line is regarded as dead.
SIG

25.Blk_Chk

SIG

25.Blk_DdChk

SIG

25.Start_Chk

EN

[25.En_DdL_DdB]

SIG

Uref<[25.U_Dd]

SIG

Usyn>[25.U_Lv]

EN

[25.En_DdL_LvB]

SIG

Uref<[25.U_Dd]

SIG

Usyn>[25.U_Lv]

EN

[25.En_LvL_DdB]

SIG

Uref>[25.U_Lv]

SIG

Usyn<[25.U_Dd]

SIG

25.Alm_VTS_UB

SIG

25.Alm_VTS_UL

>=1
&
&
[25.t_DdChk]

>=1

0ms

25.Ok_DdChk

&
25.Ok_DdL_DdB
&

&
25.Ok_DdL_LvB
&

&
25.Ok_LvL_DdB
&

>=1

Figure 3.23-5 Dead charge check logic


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3.23.5.3 Synchrocheck Logic


SIG

25.Ok_SynChk

EN

25.En_NoChk

SIG

25.Ok_DdChk

>=1
25.Ok_Chk

Figure 3.23-6 Synchrocheck logic

This device comprises two synchrocheck modules, correspond to circuit breaker 1 and circuit
breaker 2 respectively.

3.23.6 Settings
Table 3.23-2 Settings of synchrocheck
No.

Name

Range

Step

Unit

Remark
Voltage selecting mode of line.
0: A-phase voltage
1: B-phase voltage

25.Opt_Source_UL

0~5

2: C-phase voltage
3: AB-phase voltage
4: BC-phase voltage
5: CA-phase voltage
Voltage selecting mode of bus.
0: A-phase voltage
1: B-phase voltage

25.Opt_Source_UB

0~5

2: C-phase voltage
3: AB-phase voltage
4: BC-phase voltage
5: CA-phase voltage

25.U_Dd

0.05Un~0.8Un

0.001

Voltage threshold of dead check

25.U_Lv

0.5Un~Un

0.001

Voltage threshold of live check

25.K_Usyn

0.20-5.00

25.phi_Diff

0~ 89

Compensation

Deg

25.phi_Comp

0~359

for

Phase

difference

Deg

limit

of

synchronism check for AR


Compensation

coefficient

synchronism voltage

difference

for

phase

between

two

synchronism voltages
8

25.f_Diff

0.02~1.00

0.01

25.U_Diff

0.02Un~0.8Un

10

25.t_DdChk

0.010~25.000

3-174

Hz

Frequency

difference

limit

of

synchronism check for AR


Voltage

difference

limit

of

synchronism check for AR


Time delay to confirm dead check

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condition
11

25.t_SynChk

0.010~25.000

Time

delay

to

confirm

synchronism check condition


Enabling/disabling

12

25.En_fDiffChk

frequency

difference check

0 or 1

0: disable
1: enable
Enabling/disabling

13

25.En_SynChk

synchronism

check

0 or 1

0: disable
1: enable
Enabling/disabling dead line and

14

25.En_DdL_DdB

dead bus (DLDB) check

0 or 1

0: disable
1: enable
Enabling/disabling dead line and

15

25.En_DdL_LvB

live bus (DLLB) check

0 or 1

0: disable
1: enable
Enabling/disabling live line and

16

25.En_LvL_DdB

dead bus (LLDB) check

0 or 1

0: disable
1: enable
Enabling/disabling AR without any

17

25.En_NoChk

check

0 or 1

0: disable
1: enable

3.24 Automatic Reclosure


3.24.1 General Application
To maintain the integrity of the overall electrical transmission system, the device is installed on the
transmission system to isolate faulted segments during system disturbances. Faults caused by
lightning, wind, or tree branches could be transient in nature and may disappear once the circuit is
de-energized. According to statistics, for overhead transmission line, 80%~90% of the faults on
overhead lines are the transient faults. Auto-reclosing systems are installed to restore the faulted
section of the transmission system once the fault is extinguished (providing it is a transient fault).
For certain transmission systems, auto-reclosure is used to improve system stability by restoring
critical transmission paths as soon as possible.
Besides overhead lines, other equipment failure, such as cables, busbar, transformer fault and so
on, are generally permanent fault, and auto-reclosing is not initiated after faulty feeder is tripped.
For some mixed circuits, such as overhead line with a transformer unit, hybrid transmission lines,
etc., it is required to ensure that auto-reclosing is only initiated for faults overhead line section, or

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make a choice according to the situation.

3.24.2 Function Description


This auto-reclosing logic can be used with either integrated device or external device. When the
auto-reclosure is used with integrated device, the internal protection logic can initiate AR,
moreover, a tripping contact from external device can be connected to the device via opto-coupler
input to initiate integrated AR function.
When external auto-reclosure is used, the device can output some configurable output to initiate
external AR, such as, contact of initiating AR, phase-segregated tripping contact, single-phase
tripping contact, three-phase tripping contact and contact of blocking AR. According to
requirement, these contacts can be selectively connected to external auto-reclosure device to
initiate AR.
For phase-segregated circuit breaker, AR mode can be 1-pole AR for single-phase fault and
3-pole AR for multi-phase fault, or always 3-pole AR for any kinds of fault according to system
requirement. For persistent fault or multi-shot AR number preset value is reached, the device will
send final tripping command. The device will provide appropriate tripping command based on
faulty phase selection if adopting 1-pole AR.
AR can be enabled or disabled by logic setting or external signal via binary input. When AR is
enabled, the device will output contact [79.On], otherwise, output contact [79.Off]. After some
reclosing conditions, such as, CB position, CB pressure and so on, is satisfied, the device will
output contact [79.Ready].
According to requirement, the device can be set as one-shot or multi-shot AR. When adopting
multi-shot AR, the AR mode of first time reclosing can be set as 1-pole AR, 3-pole AR or 1/3-pole
AR. The rest AR mode is only 3-pole AR and its number is determined by the maximum 3-pole
reclosing number.
For one-shot AR or first reclosing of multi-shot AR, AR mode can be selected by logic setting
[79.En_1PAR], [79.En_3PAR] and [79.En_1P/3PAR] or external signal via binary inputs. When
3-pole or 1/3-pole AR mode is selected, the following three types of check modes can be selected:
dead charge check, synchronism check and no check.

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3.24.3 Function Block Diagram


79
79.En

79.On

79.Blk

79.Off

79.Sel_1PAR

79.Close

79.Sel_3PAR

79.Ready

79.Sel_1P/3PAR

79.AR_Blkd

79.Trp

79.Active

79.Trp3P

79.Inprog

79.TrpA

79.Inprog_1P

79.TrpB

79.Inprog_3P

79.TrpC

79.Inprog_3PS1

79.LockOut

79.Inprog_3PS2

79.PLC_Lost

79.Inprog_3PS3

79.WaitMaster

79.Inprog_3PS4

79.CB_Healthy

79.WaitToSlave

79.Clr_Counter

79.Perm_Trp1P

79.Ok_Chk

79.Perm_Trp3P

79.Rcls_Status
79.Fail_Rcls
79.Succ_Rcls
79.Fail_Chk
79.Mode_1PAR
79.Mode_3PAR
79.Mode_1/3PAR

3.24.4 I/O Signals


Table 3.24-1 I/O signals of auto-reclosing
No.

Input Signal

79.En

79.Blk

Description
Binary input for enabling AR. If the logic setting [79.En_ExtCtrl]=1,
enabling AR will be controlled by the external signal via binary input
Binary input for disabling AR. If the logic setting [79.En_ExtCtrl]=1,
disabling AR will be controlled by the external input
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Input signal for selecting 1-pole AR mode of corresponding circuit

79.Sel_1PAR

79.Sel_3PAR

79.Sel_1P/3PAR

79.Trp

Input signal of single-phase tripping from line protection to initiate AR

79.Trp3P

Input signal of three-phase tripping from line protection to initiate AR

79.TrpA

Input signal of A-phase tripping from line protection to initiate AR

79.TrpB

Input signal of B-phase tripping from line protection to initiate AR

10

79.TrpC

Input signal of C-phase tripping from line protection to initiate AR

breaker
Input signal for selecting 3-pole AR mode of corresponding circuit
breaker
Input signal for selecting 1/3-pole AR mode of corresponding circuit
breaker

Input signal of blocking reclosing, usually it is connected with the


11

79.LockOut

operating signals of definite-time protection, transformer protection


and busbar differential protection, etc.

12

79.PLC_Lost

13

79.WaitMaster

14

79.CB_Healthy

15

79.Clr_Counter

Clear the reclosing counter

16

79.Ok_Chk

Synchrocheck condition of AR is met

No.

Input signal of indicating the alarm signal that signal channel is lost
Input signal of waiting for reclosing permissive signal from master
AR (when reclosing multiple circuit breakers)
The input for indicating whether circuit breaker has enough energy to
perform the close function

Output Signal

Description

79.On

Automatic reclosure is enabled

79.Off

Automatic reclosure is disabled

79.Close

Output of auto-reclosing signal

79.Ready

Automatic reclosure have been ready for reclosing cycle

79.AR_Blkd

Automatic reclosure is blocked

79.Active

Automatic reclosing logic is actived

79.Inprog

Automatic reclosing cycle is in progress

79.Inprog_1P

The first 1-pole AR cycle is in progress

79.Inprog_3P

3-pole AR cycle is in progress

10

79.Inprog_3PS1

First 3-pole AR cycle is in progress

11

79.Inprog_3PS2

Second 3-pole AR cycle is in progress

12

79.Inprog_3PS3

Third 3-pole AR cycle is in progress

13

79.Inprog_3PS4

Fourth 3-pole AR cycle is in progress

14

79.WaitToSlave

15

79.Perm_Trp1P

16

79.Perm_Trp3P

17

79.Rcls_Status

Waiting signal of automatic reclosing which will be sent to slave


(when reclosing multiple circuit breakers)
Single-phase circuit breaker will be tripped once protection device
operates
Three-phase circuit breaker will be tripped once protection device
operates
Automatic reclosure status
0: AR is ready.

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1: AR is in progress.
2: AR is successful.
18

79.Fail_Rcls

Auto-reclosing fails

19

79.Succ_Rcls

Auto-reclosing is successful

20

79.Fail_Chk

Synchrocheck for AR fails

21

79.Mode_1PAR

Output of 1-pole AR mode

22

79.Mode_3PAR

Output of 3-pole AR mode

23

79.Mode_1/3PAR

Output of 1/3-pole AR mode


Automatic reclosure counter

24

79.N_Total_Rcls

Recorded number of all reclosing attempts

25

79.N_1PS1

Recorded number of first 1-pole reclosing attempts

26

79.N_3PS1

Recorded number of first 3-pole reclosing attempts

27

79.N_3PS2

Recorded number of second 3-pole reclosing attempts

28

79.N_3PS3

Recorded number of third 3-pole reclosing attempts

29

79.N_3PS4

Recorded number of fourth 3-pole reclosing attempts

3.24.5 Logic
3.24.5.1 AR Ready
For the first reclosing of multi-shot AR, AR mode can be 1-pole AR or 3-pole AR, however, the
selection is valid only to the first reclosing, after that it can only be 3-pole AR.
When logic setting [79.SetOpt] is set as 1, AR mode is determined by logic settings. When logic
setting [79.SetOpt] is set as 0, AR mode is determined by external signal via binary inputs.
An auto-reclosure must be ready to operate before performing reclosing. The output signal
[79.Ready] means that the auto-reclosure can perform at least one time of reclosing function, i.e.,
breaker open-close-open.
When the device is energized or after the settings are modified, the following conditions must be
met before the reclaim time begins:
1.

AR function is enabled.

2.

The circuit breaker is ready, such as, normal storage energy and no low pressure signal.

3.

The duration of the circuit breaker in closed position before fault occurrence is not less than
the setting [79.t_CBClsd].

4.

There is no block signal of auto-reclosing.

After the auto-reclosure operates, the auto-reclosure must reset, i.e., [79.Active]=0, in addition to
the above conditions for reclosing again.
The logic of AR ready is shown in Figure 3.24-2.
When there is a fault on an overhead line, the concerned circuit breakers will be tripped normally.
After fault is cleared, the tripping command will drop off immediately. In case the circuit breaker is
in failure, etc., and the tripping signal of the circuit breaker maintains and in excess of the time
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delay [79.t_PersistTrp], AR will be blocked, as shown in the following figure.


SIG

Any tripping signal

SIG

79.LockOut

SIG

1-pole AR Initiation

SIG

Any tripping signal

En

[79.En_PDF_Blk]

SIG

79.Sel_1PAR

[79.t_PersistTrp] 0ms

>=1
0ms [79.t_DDO_BlkAR]
[79.t_SecFault] 0ms

&

&

>=1
&

En

[79.N_Rcls]=1

SIG

Three phase trip

SIG

Phase A open

SIG

Phase B open

79.AR_Blkd

>=1
&

&

>=1

&
SIG

Phase C open

Figure 3.24-1 Logic diagram of AR block

The input signal [79.CB_Healthy] must be energized before auto-reclosure gets ready. Because
most circuit breakers can finish one complete process: open-closed-open, it is necessary that
circuit breaker has enough energy before reclosing. When the time delay of AR is exhausted, AR
will be blocked if the input signal [79.CB_Healthy] is still not energized within time delay
[79.t_CBReady]. If this function is not required, the input signal [79.CB_Healthy] can be not to
configure, and its state will be thought as 1 by default.
In orde to block AR reliably even if the signal of manually open circuit breaker not connected to the
input of blocking AR, when the circuit breaker is open by manually and there is CB position input
under normal conditions, AR will be blocked with the time delay of 100ms if AR is not initated and
no any trip signal.
When auto-reclosure is blocked, auto-reclosing failure, synchrocheck failure or last shot is
reached, or when the internal blocking condition of AR is met (such as, zone 3 of distance
protection operates, the device operates for multi-phase fault, three-phase fault and so on. These
flags of blocking AR have been configured in the device, additional configuration is not required.),
auto-reclosure will be discharged immediately and next auto-reclosing will be disabled.
When the input signal [79.LockOut] is energized, auto-reclosure will be blocked immediately. The
blocking flag of AR will be also controlled by the internal blocking condition of AR. When the
blocking flag of AR is valid, auto-reclosure will be blocked immediately.

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SIG

3 CB closed

[79.t_CBClsd]

SIG

79.Active

>=1

SIG

Any tripping signal

100ms

&

>=1

&

&
100ms

SIG

79.Ready

79.Inprog
[79.CB_Healthy]

0ms

SIG

79.AR_Blkd

>=1

SIG

BlockAR

SIG

79.Fail_Rcls

SIG

79.Fail_Chk

SIG

Last shot is made

EN

[79.En]

EN

[79.En_ExtCtrl]

BI

[79.t_CBReady]

&

>=1
&
>=1

&
>=1
79.On

&
SIG

79.En

SIG

79.Blk

&

Figure 3.24-2 Logic diagram of AR ready

When a fault occurs under pole disagreement condition, blocking AR can be enabled or disabled.
The time delay [79.t_SecFault] is used to discriminate another fault which begins after 1-pole AR
initiated. AR will be blocked if another fault happens after this time delay if the logic setting
[79.En_PDF_Blk] is set as 1, and 3-pole AR will be initiated if [79.En_PDF_Blk] is set as 1.
AR will be blocked immediately once the blocking condition of AR appears, but the blocking
condition of AR will drop off with a time delay [79.t_DDO_BlkAR] after blocking signal disappears.
When one-shot and 1-pole AR is enabled, auto-reclosure will be blocked immediately if there are
binary inputs of multi-phase CB position is energized.
When any protection element operates to trip, the device will output a signal [79.Active] until AR
drop off (Reset Command). Any tripping signal can be from external protection device or internal
protection element.
AR function can be enabled by internal logic settings of AR mode or external signal via binary
inputs in addition to internal logic setting [79.En]. When logic setting [79.En_ExtCtrl] is set as 1,
AR enable are determined by external signal via binary inputs and logic settings. When logic
setting [79.En_ExtCtrl] set as 0, AR enable are determined only by logic settings.
For one-shot reclosing, if 1-pole AR mode is selected, auto-reclosure will reset when there is
three-phase tripping signal or input signal of multi-phase open position.
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SIG

79.On

SIG

79.Mode_3PAR

SIG

79.Ready

SIG

79.Trp

SIG

79.Trp3P

SIG

79.TrpA

SIG

79.TrpB

SIG

79.TrpC

SIG

Phase A open

SIG

Phase B open

SIG

Phase C open

Logic

79.Perm_Trp3P
79.Perm_Trp1P

Figure 3.24-3 Logic diagram of tripping condition output

When AR is enabled, the device will output the signal [79.Perm_Trp3P] if AR is not ready, or AR
mode is set as 3-Pole AR, or another fault occurs after the circuit breaker is open.
3.24.5.2 AR Initiation
AR mode can be selected by external signal via binary inputs or internal logic settings. If the logic
setting [79.SetOpt] set as 1, AR mode is determined by the internal logic settings. If the logic
settings [79.SetOpt] set as 0, AR mode is determined by the external inputs.
1.

AR initiated by tripping signal of line protection

AR can be initiated by tripping signal of line protection, and the tripping signal may be from internal
trip signal or external trip signal.
When selecting 1-pole AR or 1/3-pole AR, line single-phase fault will trigger 1-pole AR. When AR
is ready to reclosing (79.Ready=1) and the single-phase tripping command is received, this
single-phase tripping command will be kept in the device, and 1-pole AR will be initiated after the
single-phase tripping command drops off. The single-phase tripping command kept in the device
will be cleared after the completion of auto-reclosing sequence (Reset Command). Its logic is
shown in Figure 3.24-4.

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SIG

Reset Command

&
>=1

SIG

Single-phase Trip

&
SIG

&

79.Ready

SIG

79.Sel_1PAR

SIG

79.Sel_1P/3PAR

1-pole AR Initiation

>=1

Figure 3.24-4 Single-phase tripping initiating AR

When selecting 3-pole AR or 1/3-pole AR, three-phase tripping will trigger 3-pole AR. When AR is
ready to reclosing (79.Ready=1) and the three-phase tripping command is received, this
three-phase tripping command will be kept in the device, and 3-pole AR will be initiated after the
three-phase tripping command drops off. The three-phase tripping command kept in the device will
be cleared after the completion of auto-reclosing sequence (Reset Command). Its logic is shown
in Figure 3.24-5.
SIG

Reset Command

&
>=1

SIG

Three-phase Trip

&
SIG

&

79.Ready

SIG

79.Sel_3PAR

SIG

79.Sel_1P/3PAR

3-pole AR Initiation

>=1

Figure 3.24-5 Three-phase tripping initiating AR

2.

AR initiated by CB state

A logic setting [79.En_CBInit] is available for selection that AR is initiated by CB state. Under
normal conditions, when AR is ready to reclosing (79.Ready=1), AR will be initiated if circuit
breaker is open and corresponding phase current is nil. AR initiated by CB state can be divided
into initiating 1-pole AR and 3-pole AR, their logics are shown in Figure 3.24-6 and Figure 3.24-7
respectively. Usually normally closed contact of circuit breaker is used to reflect CB state.

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SIG

Phase A open

SIG

Phase B open

>=1
&
&

&
&

SIG

Phase C open

EN

[79.En_CBInit]

SIG

79.Ready

SIG

79.Sel_1PAR

SIG

79.Sel_1P/3PAR

1-pole AR Initiation

>=1

Figure 3.24-6 1-pole AR initiation

SIG

Phase A open

SIG

Phase B open

SIG

Phase C open

EN

[79.En_CBInit]

SIG

79.Ready

EN

[79.Sel_3PAR]

EN

[79.Sel_1P/3PAR]

&

&

&
3-pole AR Initiation

>=1

Figure 3.24-7 3-pole AR initiation

3.24.5.3 AR Reclosing
After AR is initiated, the device will output the initiating contact of AR. For 1-pole AR, in order to
prevent pole discrepancy protection from maloperation under pole discrepancy conditions, the
contact of 1-pole AR initiation can be used to block pole discrepancy protection.
When the dead time delay of AR expires after AR is initiated, as for 1-pole AR, the result of
synchronism check will not be judged, and reclosing command will be output directly. As far as the
3-pole AR, if the synchronism check is enabled, the release of reclosing command shall be subject
to the result of synchronism check. After the dead time delay of AR expires, if the synchronism
check is still unsuccessful within the time delay [79.t_wait_Chk], the signal of synchronism check
failure (79.Fail_Syn) will be output and the AR will be blocked. If 3-pole AR with no-check is
enabled, the condition of synchronism check success (25.Ok_Chk) will always be established.
And the signal of synchronism check success (25.Ok_Chk) from the synchronism check logic can
be applied by auto-reclosing function inside the device or external auto-reclosure device.

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79.Inprog_1P

>=1
79.Inprog

79.Inprog_3P

SIG

1-pole AR Initiation

[79.t_Dd_1PS1]

0ms

SIG

3-pole AR Initiation

[79.t_Dd_3PS1]

0ms

>=1
AR Pulse

&

&
[79.t_Wait_Chk] 0ms
SIG

79.Fail_Chk

79.Ok_Chk

Figure 3.24-8 One-shot AR

In the process of channel abnormality, an internal fault occurs on the transmission line, backup
protection at both ends of line will operate to trip the circuit breaker of each end. The operation
time of backup protection at both ends of the line is possibly non-accordant, whilst the time delay
of AR needs to consider the arc-extinguishing and insulation recovery ability for transient fault, so
the time delay of AR shall be considered comprehensively according to the operation time of the
device at both ends. When the communication channel of main protection is abnormal (input
signal [79.PLC_Lost] is energized), and the logic setting [79.En_AddDly] is set as 1, then the
dead time delay of AR shall be equal to the original dead time delay of AR plus the extra time
delay [79.t_AddDly], so as to ensure the recovery of insulation intensity of fault point when
reclosing after transient fault. This extra time delay [79.t_AddDly] is only valid for the first shot AR.

>=1
SIG

BI

Any tripping signal

&
&

[79.PLC_Lost]

SIG

79.Active

EN

[79.En_AddDly]

&
Extend AR time

Figure 3.24-9 Extra time delay of AR

Reclosing pulse length may be set through the setting [79.t_PW_AR]. For the circuit breaker
without anti-pump interlock, a logic setting [79.En_CutPulse] is available to control the reclosing
pulse. When this function is enabled, if the device operates to trip during reclosing, the reclosing
pulse will drop off immediately, so as to prevent multi-shot reclosing onto fault. After the reclosing
command is issued, AR will drop off with time delay [79.t_Reclaim], and can carry out next
reclosing.

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SIG

SIG

WaitMasterValid

&
0ms

50ms

0ms

[79.t_PW_AR]

>=1

AR Pulse

SIG

Single-phase Trip

SIG

Three-phase Trip

EN

[79.En_CutPulse]

79.AR_Out

>=1
&
&

>=1
&
SIG

[79.t_Reclaim]

79.AR_Out

0ms

Reset Command

Figure 3.24-10 Reclosing output logic

The reclaim timer defines a time from the issue of the reclosing command, after which the
reclosing function resets. Should a new trip occur during this time, it is treated as a continuation of
the first fault. The reclaim timer is started when the CB closing command is given.
SIG

1-pole AR Initiation

>=1
0ms

SIG

3-pole AR Initiation

SIG

79.Fail_Rcls

SET

[79.Opt_Priority]=High

[79.t_Fail]

>=1
&
79.WaitToSlave

Figure 3.24-11 Wait toslave signal

The output signal 79.WaitToSlave is usually configured to the signal 79.WaitMaster of slave AR.
Slave AR is permissible to reclosing only if master AR is reclosed successfully.
3.24.5.4 Reclosing Failure and Success
For transient fault, the fault will be cleared after the device operates to trip. After the reclosing
command is issued, AR will drop off after time delay [79.t_Reclaim], and can carry out next
reclosing. When the reclosing is unsuccessful or the reclosing condition is not met after AR
initiated, the reclosing will be considered as unsuccessful, including the following cases.
1.

If any protection element operates to trip when AR is enabled ([79.On]=1) and AR is not ready
([79.Ready]=0), the device will output the signal (79.Fail_Rcls).

2.

For one-shot AR, if the tripping command is received again within reclaim time after the
reclosing pulse is issued, the reclosing shall be considered as unsuccessful.

3.

For multi-shot AR, if the reclosing times are equal to the setting value of AR number and the

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tripping command is received again after the last reclosing pulse is issued, the reclosing shall
be considered as unsuccessful.
4.

The logic setting [79.En_FailCheck] is available to judge whether the reclosing is successful
by CB state, when it is set as 1. If CB is still in open position with a time delay [79.t_Fail] after
the reclosing pulse is issued, the reclosing shall be considered as unsuccessful. For this case,
the device will issue a signal (79.Fail_Rcls) to indicate that the reclosing is unsuccessful, and
this signal will drop off after (Reset Command). AR will be blocked if the reclosing shall be
considered as unsuccessful.

SET

[79.Opt_Priority]=Low

SIG

79.WaitMaster

SIG

79.On

SIG

79.Ready

SIG

Any tripping command

&
WaitMaster Valid

&

&

>=1
0ms

SIG

Last shot is made

SIG

79.Inprog

SIG

79.AR_Blkd

SIG

WaitMasterValid

200ms

>=1
79.Fail_Rcls

&

&
[79.t_WaitMaster]

0ms

>=1
SIG

AR Pulse

SIG

3 CB closed

EN

[79.En_FailCheck]

&
[79.t_Fail]

0ms

&
&
&

79.Succ_Rcls

[79.t_Fail]

Figure 3.24-12 Reclosing failure and success

After unsuccessful AR is confirmed, AR will be blocked. AR will not enter into the ready state
unless the circuit breaker position drops off , and can only begin to enter into the ready state again
after the circuit breaker is closed.
3.24.5.5 Reclosing Numbers Control
The device may be set up into one-shot or multi-shot AR. Through the setting [79.N_Rcls], the
maximum number of reclosing attempts may be set up to 4 times. Generally, only one-shot AR is
selected. Some corresponding settings may be hidden if one-shot AR is selected.
1.

1-pole AR
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[79.N_Rcls]=1 means one-shot reclosing. For one-shot 1-pole AR mode, 1-pole AR will be initiated
only for single-phase fault and respective faulty phase selected, otherwise, AR will be blocked. For
single-phase transient fault on the line, line protection device will operate to trip and 1-pole AR is
initiated. After the dead time delay for 1-pole AR is expired, the device will send reclosing pulse,
and then the auto-reclosure will drop off after the time delay [79.t_Reclaim] to ready for the next
reclosing. For permanent fault, the device will operate to trip again after the reclosing is performed,
and the device will output the signal of reclosing failure [79.Fail_Rcls].
[79.N_Rcls]>1 means multi-shot reclosing. For multi-shot reclosing in 1-pole AR mode, the first
reclosing is 1-pole AR, and the subsequent reclosing can only be 3-pole AR. For single-phase
transient fault on the line, line protection device will operate to trip and then 1-pole AR is initiated.
After the dead time delay of the first reclosing is expired, the device will send reclosing pulse, and
then the auto-reclosure will drop off after the time delay [79.t_Reclaim] to ready for the next
reclosing. For permanent fault, the device will operate to trip again after the reclosing is performed,
and then 3-pole AR is initiated. At this time, the time delay applies the setting [79.t_Dd_3PS2].
After the time delay is expired, if the reclosing condition is met, the device will send reclosing pulse.
The sequence is repeated until the reclosing is successful or the maximum permit reclosing
number [79.N_Rcls] is reached. If the first fault is multi-phase fault, the device operates to trip
three-phase and initiate 3-pole AR. At this time, the time delay applies the setting [79.t_Dd_3PS1].
For the possible reclosing times of 3-pole AR in 1-pole AR mode, please refer to Table 3.24-2.
2.

3-pole AR

[79.N_Rcls]=1 means one-shot reclosing. For one-shot 3-pole AR mode, line protection device will
operate to trip when a transient fault occurs on the line and 3-pole AR will be initiated. After the
dead time delay for 3-pole AR is expired, the device will send reclosing pulse, and then the
auto-reclosure will drop off after the time delay [79.t_Reclaim] to ready for the next reclosing. For
permanent fault, the device will operate to trip again after the reclosing is performed, and the
device will output the signal of reclosing failure [79.Fail_Rcls].
[79.N_Rcls]>1 means multi-shot reclosing. For multi-shot reclosing in 3-pole AR mode, line
protection device will operate to trip when a transient fault occurs on the line and 3-pole AR will be
initiated. After the dead time delay of the first reclosing is expired, the device will send reclosing
pulse, and then the auto-reclosure will drop off after the time delay [79.t_Reclaim] to ready for the
next reclosing. For permanent fault, the device will operate to trip again after the reclosing is
performed, and then 3-pole AR is initiated after the tripping contact drops off. After the time delay
for AR is expired, the device will send reclosing pulse. The sequence is repeated until the
reclosing is successful or the maximum permit reclosing number [79.N_Rcls] is reached.
3.

1/3-pole AR

[79.N_Rcls]=1 means one-shot reclosing. For one-shot 1/3-pole AR mode, line protection device
will operate to trip when a transient fault occurs on the line and 1-pole AR will be initiated for
single-phase fault and 3-pole AR will be initiated for multi-phase fault. After respective dead time
delay for AR is expired, the device will send reclosing pulse, and then the auto-reclosure will drop
off after the time delay [79.t_Reclaim] to ready for the next reclosing. For permanent fault, the
device will operate to trip again after the reclosing is performed, and the device will output the

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signal of reclosing failure [79.Fail_Rcls].


[79.N_Rcls]>1 means multi-shot reclosing. For multi-shot reclosing in 1/3-pole AR mode, line
protection device will operate to trip when a transient fault occurs on the line and AR will be
initiated. After the dead time delay of the first reclosing is expired, the device will send reclosing
pulse, and then the auto-reclosure will drop off after the time delay [79.t_Reclaim] to ready for the
next reclosing. For permanent fault, the device will operate to trip again after the reclosing is
performed, and then 3-pole AR is initiated after the tripping contact drops off. After the time delay
for AR is expired, the device will send reclosing pulse. The sequence is repeated until the
reclosing is successful or the maximum permit reclosing number [79.N_Rcls] is reached. For the
possible reclosing times of 3-pole AR in 1/3-pole AR mode, please refer to Table 3.24-2.
The table below shows the number of reclose attempts with respect to the settings and AR modes.
Table 3.24-2 Reclosing number

Setting Value

1-pole AR

3-pole AR

1/3-pole AR

N-1AR

N-3AR

N-1AR

N-3AR

N-1AR

N-3AR

N-1AR: the reclosing number of 1-pole AR


N-3AR: the reclosing number of 3-pole AR
4.

Coordination between dual auto-reclosures

Duplicated protection configurations are normally applied for UHV lines. If reclosing function is
integrated within line protections, the auto-reclosing function can be enabled in any or both of the
line protections without coordination.
If both sets of reclosing functions are enabled, when one of them first recloses onto a permanent
fault, the other will block the reclosing pulse according to the latest condition of the faulty phase.
For one-shot AR mode, if the current is detected in the faulty phase, AR will be blocked
immediately to prevent the circuit breaker from repetitive reclosing. For multi-shot AR mode, if the
current is detected in the faulty phase, the current reclosing pulse will be blocked and go into the
next reclosing pulse logic automatically. If the maximum permitted reclosing number [79.N_Rcls] is
reached, the auto-reclosure will drop off after the time delay [79.t_Reclaim].
For one-shot or multi-shot AR, there is a corresponding reclosing counter at each stage. After
reclosing pulse is sent, the corresponding reclosing counter will plus 1 and the reclosing counter
may be cleared by the submenu Clear Counter. If the circuit breaker is reclosed by other
devices during AR initiation, the auto-reclosure will go into the next reclosing pulse logic.
3.24.5.6 AR Time Sequence Diagram
The following two examples indicate typical time sequence of AR process for transient fault and
permanent fault respectively.
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Signal

Fault
Trip
CB 52b

Open
[79.t_Reclaim]

79.t_Reclaim
79.Active
79.Inprog

[79.t_Dd_1PS1]

79.Inprog_1P

[79.t_Dd_1PS1]

79.Ok_Chk
AR Out

[79.t_PW_AR]

79.Perm_Trp3P
79.Fail_Rcls
Time

Figure 3.24-13 Single-phase transient fault


Signal

Fault
Trip
52b

Open

Open
[79.t_Reclaim]

79.t_Reclaim
79.Active
79.Inprog
79.Inprog_1P
79.Inprog_3PS2

[79.t_Dd_1PS1]
[79.t_Dd_3PS2]

79.Ok_Chk
AR Out

[79.t_PW_AR]

[79.t_PW_AR]

79.Perm_Trp3P
79.Fail_Rcls

200ms
Time

Figure 3.24-14 Single-phase permanent fault ([79.N_Rcls]=2)

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3.24.6 Settings
Table 3.24-3 Settings of auto-reclosing
No.

Name

Range

Step

Unit

Remark

79.N_Rcls

1~4

Maximum number of reclosing attempts

79.t_Dd_1PS1

0.000~600.000

0.001

Dead time of first shot 1-pole reclosing

79.t_Dd_3PS1

0.000~600.000

0.001

Dead time of first shot 3-pole reclosing

79.t_Dd_3PS2

0.000~600.000

0.001

79.t_Dd_3PS3

0.000~600.000

0.001

79.t_Dd_3PS4

0.000~600.000

0.001

79.t_CBClsd

0.000~600.000

0.001

Dead time of second shot 3-pole


reclosing
Dead time of third shot 3-pole reclosing
Dead

time

of

fourth

shot

3-pole

reclosing
Time delay of circuit breaker in closed
position before reclosing
Time delay to wait for CB healthy, and
begin to timing when the input signal

79.t_CBReady

0.000~600.000

0.001

[79.CB_Healthy] is de-energized and if


it is not energized within this time delay,
AR will be blocked.
Maximum wait time for synchronism

79.t_Wait_Chk

0.000~600.000

0.001

10

79.t_Fail

0.000~600.000

0.001

11

79.t_PW_AR

0.000~600.000

0.001

Pulse width of AR closing signal

12

79.t_Reclaim

0.000~600.000

0.001

Reclaim time of AR

13

79.t_PersistTrp

0.000~600.000

0.001

check
Time delay allow for CB status change
to conform reclosing successful

Time delay of excessive trip signal to


block auto-reclosing
Drop-off time delay of blocking AR,

14

79.t_DDO_BlkAR

0.000~600.000

0.001

when

blocking

disappears,

signal

AR

blocking

for

AR

condition

drops off after this time delay


15

79.t_AddDly

0.000~600.000

0.001

16

79.t_WaitMaster

0.000~600.000

0.001

Additional time delay for auto-reclosing


Maximum

wait

time

for

reclosing

permissive signal from master AR


Time delay of discriminating another
fault, and begin to times after 1-pole AR

17

79.t_SecFault

0.000~600.000

0.001

initiated, 3-pole AR will be initiated if


another fault happens during this time
delay. AR will be blocked if another fault
happens after that.

18

79.En_PDF_Blk

0 or 1

Enabling/disabling

auto-reclosing

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blocked when a fault occurs under pole
disagreement condition
0: disable
1: enable
Enabling/disabling auto-reclosing with
19

79.En_AddDly

an additional dead time delay

0 or 1

0: disable
1: enable
Enabling/disabling adjust the length of

20

79.En_CutPulse

reclosing pulse

0 or 1

0: disable
1: enable
Enabling/disabling confirm whether AR

21

79.En_FailCheck

is successful by checking CB state

0 or 1

0: disable
1: enable
Enabling/disabling auto-reclosing

22

79.En

0 or 1

0: disable
1: enable
Enabling/disabling AR by external input

23

79.En_ExtCtrl

signal besides logic setting [79.En]

0 or 1

0: only logic setting


1: logic setting and external input signal
Enabling/disabling AR be initiated by

24

79.En_CBInit

open state of circuit breaker

0 or 1

0: disable
1: enable
Option of AR priority
None: single-breaker arrangement

25

79.Opt_Priority

None, High or

High:

Low

arrangement
Low:

master

slave

AR

AR

of

multi-breaker

of

multi-breaker

arrangement
Control option of AR mode
1: select AR mode by internal logic
26

79.SetOpt

0 or 1

settings
0: select AR mode by external input
signals
Enabling/disabling 1-pole AR mode

27

79.En_1PAR

0 or 1

0: disable
1: enable
Enabling/disabling 3-pole AR mode

28

79.En_3PAR

0 or 1

0: disable
1: enable

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Enabling/disabling 1/3-pole AR mode
29

79.En_1P/3PAR

0 or 1

0: disable
1: enable

3.25 Transfer Trip


3.25.1 General Application
This function module provides a binary input [TT.Init] for receiving transfer trip from the remote end.
This feature ensures simultaneous tripping at both ends.

3.25.2 Function Description


Transfer trip can be controlled by local fault detector by logic settings [TT.En_FD_Ctrl]. In addition,
the binary input [TT.Init] is always supervised, and the device will issue an alarm [TT.Alm] and
block transfer trip once the binary input is energized for longer than 4s and drop off after resumed
to normal with a time delay of 10s.

3.25.3 Function Block Diagram


TT
TT.Init

TT.Alm

TT.En

TT.Op

TT.Blk

TT.On

3.25.4 I/O Signals


Table 3.25-1 I/O signals of transfer trip
No.

Input Signal

TT.Init

TT.En

TT.Blk

No.

Description
Input signal of initiating transfer trip after receiving transfer trip
Transfer trip enabling input, it is triggered from binary input or programmable logic
etc.
Transfer trip blocking input, it is triggered from binary input or programmable logic
etc.

Output Signal

Description

TT.Alm

Input signal of receiving transfer trip is abnormal

TT.Op

Transfer trip operates

TT.On

Transfer trip is enabled

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3.25.5 Logic
SIG

TT.En

&
TT.On

SIG

TT.Blk
4s

BI

[TT.Init]

SIG

TT.Alm

EN

[TT.En_FD_Ctrl]

SIG

FD.Pkp

BI

[TT.Init]

10s

TT.Alm

&
TT.Op

>=1

Figure 3.25-1 Logic diagram of transfer trip

3.25.6 Settings
Table 3.25-2 Settings of Transfer trip
No.
1

Name
TT.t_Op

TT.En_FD_Ctrl

Range

Step

Unit

0.000~600.000

0.001

Remark
Time delay of transfer trip
Transfer trip controlled by local fault detector
element
0: not controlled by local fault detector
element
1: controlled by local fault detector element

0 or 1

3.26 Trip Logic


3.26.1 General Application
For any enabled protection tripping elements, their operation signal will convert to appropriate
tripping signals through trip logics and then trigger output contacts by configuration.

3.26.2 Function Description


This module gathers signals from phase selection and protection tripping elements and then
converts the operation signal from protection tripping elements to appropriate tripping signals.
The device can implement phase-segregated tripping or three-phase tripping, and may output the
contact of blocking AR and the contact of initiating breaker failure protection.

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3.26.3 Function Block Diagram


PTRC
En

TrpA

Blk

TrpB

Faulty phase selection

TrpC

PrepTrp3P

Trp

Line tripping element

Trp3P

Breaker tripping element

BFI_A

Initiating BFP element

BFI_B
BFI_C
BFI
Trp3P_PSFail
BlkAR
On

3.26.4 I/O Signals


Table 3.26-1 I/O signals of trip logic
No.

Input Signal

Description
Trip enabling input, it is triggered from binary input or programmable

En
logic etc.
Trip blocking input, it is triggered from binary input or programmable

Blk
logic etc.

Faulty phase selection (phase

The result of fault phase selection

A, phase B, phase C)

If multi-phase is selected, three-phase breakers will be tripped.


Input signal of permitting three-phase tripping

PrepTrp3P

When this signal is valid, three-phase tripping will be adopted for any
kind of faults.

Line tripping element

Breaker tripping element

Initiating BFP element

No.

All operation signals of various line protection tripping elements, such


as distance protection, overcurrent protection, etc.
All protection tripping elements concerned with breaker, such as pole
discrepancy protection, etc.
Tripping element to initiate BFP

Output Signal

Description

On

Tripping logic is enabled.

TrpA

Tripping A-phase circuit breaker

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3

TrpB

Tripping B-phase circuit breaker

TrpC

Tripping C-phase circuit breaker

Trp

Tripping any phase circuit breaker

Trp3P

Tripping three-phase circuit breaker

BFI_A

BFI_B

BFI_ C

10

BFI

11

Trp3P_PSFail

Initiating three-phase tripping due to failure in fault phase selection

12

BlockAR

Blocking auto-reclosing

Protection tripping signal of A-phase configured to initiate BFP, BFI


signal shall be reset immediately after tripping signal drops off.
Protection tripping signal of B-phase configured to initiate BFP, BFI
signal shall be reset immediately after tripping signal drops off.
Protection tripping signal of C-phase configured to initiate BFP, BFI
signal shall be reset immediately after tripping signal drops off.
Protection tripping signal configured to initiate BFP, BFI signal shall be
reset immediately after tripping signal drops off.

3.26.5 Logic
After tripping signal is issued, the tripping pulse will be kept as same as the setting [t_Dwell_Trp] at
least. When the time delay is expired, for phase-segregated tripping, the tripping signal will drop
off immediately if the faulty current of corresponding phase is less than 0.06In (In is secondary
rated current), otherwise the tripping signal will be always kept until the faulty current of
corresponding phase is less than 0.06In. For three-phase tripping, the tripping signal will drop off
immediately if three-phase currents are all less than 0.06In, otherwise the tripping signal will be
always kept until three-phase currents are all less than 0.06In.

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SIG

FPS (phase A)

&

SIG

FPS (phase B)

&

SIG

FPS (phase C)

&

SIG

Line tripping element

SIG

En

SIG

Blk

SIG

Breaker tripping element

SIG

PrepTrp3P

&

>=1

&

>=1

&

>=1

&
&

>=1

>=1
&

EN

SIG

[En_Trp3P]

Trp

SIG

Line tripping element

SIG

FPS (phase A)

&

SIG

FPS (phase B)

&

SIG

FPS (phase C)

&

&

>=1

>=1

>=1
&
200ms
SIG

0ms

Trp3P_PSFail

Line tripping element

&
SIG

SIG

SIG

SIG

SIG

SIG

TrpA

[t_Dwell_Trp]

&

[t_Dwell_Trp]

&

[t_Dwell_Trp]

&

TrpA

Ia<0.06In
TrpB

&
TrpB

Ib<0.06In
TrpC

&
TrpC

Ib<0.06In

SIG

TrpA

SIG

TrpB

SIG

TrpC

>=1
Trp

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SIG

TrpA

SIG

TrpB

SIG

TrpC

&
Trp3P

Figure 3.26-1 Tripping logic

>=1

&
BFI

SIG

Initiating BFP element

&
BFI_A

SIG

TrpA

&
BFI_B
SIG

TrpB

&
BFI_C
SIG

TrpC

Figure 3.26-2 Breaker failure initiation logic

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SIG

Y.ZPx.Op

EN

[Y.ZPx.En_BlkAR]

SIG

Y.ZGx.Op

EN

[Y.ZGx.En_BlkAR]

SIG

50/51Px.Op

EN

[50/51Px.En_BlkAR]

SIG

50/51Gx.Op

EN

50/51Gx.En_BlkAR

SIG

51PVT.Op

SIG

51GVT.Op

SIG

59Pz.Op

SIG

27Pz.Op

SIG

81U.UFx.Op

SIG

81O.OFx.Op

SIG

50BF.Op_t1

SIG

50BF.Op_t2

SIG

49-1.Op

SIG

49-2.Op

SIG

50STB.Op

SIG

62PD.Op

SIG

46BC.Op

SIG

TT.Op

EN

En_MPF_Blk_AR

SIG

Multi-phase fault

EN

En_3PF_Blk_AR

SIG

Three-phase fault

EN

En_PhSF_Blk_AR

SIG

Phase selection failure

SIG

21SOTF.Op

SIG

50GSOTF.Op

SIG

Manual closing signal

&
>=1
>=1
&

&
>=1
&

>=1

>=1

>=1
>=1

>=1
BlockAR

>=1

>=1

>=1

>=1

>=1

&

&

>=1
>=1

&

>=1
&

Figure 3.26-3 Blocking AR logic


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Where:
Y can be 21M or 21Q
x can be 1, 2, 3 or 4
z can be 1 or 2

3.26.6 Settings
Table 3.26-2 Settings of trip logic
No.

Name

Range

Step

Unit

Remark
Enabling/disabling

En_MPF_Blk_AR

auto-reclosing

blocked

when multi-phase fault happens

0 or 1

0: disable
1: enable
Enabling/disabling

En_3PF_Blk_AR

auto-reclosing

blocked

when three-phase fault happens

0 or 1

0: disable
1: enable
Enabling/disabling
3

En_PhSF_Blk_AR

auto-reclosing

blocked

when faulty phase selection fails

0 or 1

0: disable
1: enable
Enabling/disabling three-phase tripping mode
4

En_Trp3P

for any fault conditions

0 or 1

0: disable
1: enable
The dwell time of tripping command, empirical
value is 0.04

t_Dwell_Trp

0.000~10.000

0.001

The tripping contact shall drop off under


conditions of no current or protection tripping
element drop-off.

3.27 VT Circuit Supervision


3.27.1 General Application
The purpose of VT circuit supervision is to detect whether VT circuit is normal. Because some
protection functions, such as distance protection, under-voltage protection and so on, will be
influenced by VT circuit failure, these protection functions should be disabled when VT circuit fails.
VT circuit failure can be caused by many reasons, such as fuse blown due to short-circuit fault,
poor contact of VT circuit, VT maintenance and so on. The device can detect them and issue an
alarm signal to block relevant protection functions. However, the alarm of VT circuit failure should
not be issued when the following cases happen.
1.

Line VT is used as protection VT and the protected line is out of service.

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2.

Only current protection functions are enabled and VT is not connected to the device.

3.27.2 Function Description


VT circuit supervision can detect failure of single-phase, two-phase and three-phase on protection
VT. Under normal condition, the device continuously supervises input voltage from VT, VT circuit
failure signal will be activated if residual voltage exceeds the threshold value or positive-sequence
voltage is lower than the threshold value. If the device is under pickup state due to system fault or
other abnormality, VT circuit supervision will be disabled.
Under normal conditions, the device detect residual voltage greater than 8% of Unn to determine
single-phase or two-phase VT circuit failure, and detect three times positive-sequence voltage less
than Unn to determine three-phase VT circuit failure. Upon detecting abnormality on VT circuit, an
alarm will comes up with the time delay [VTS.t_DPU] and drop off with the time delay [VTS.t_DDO]
after VT circuit restored to normal.
VT (secondary circuit) MCB auxiliary contact as a binary input can be connected to the binary
input circuit of the device. If MCB is open (i.e. [VTS.MCB_VT] is energized), the device will
consider the VT circuit is not in a good condition and issues an alarm without a time delay.
When VT is not connected into the device, the alarm will be not issued if the logic setting
[VTS.En_Out_VT] is set as 1. However, the alarm is still issued if the binary input [VTS.MCB_VT]
is energized, no matter that the logic setting [VTS.En_Out_VT] is set as 1 or 0.
When VT neutral point fails, third harmonic of residual voltage is comparatively large. If third
harmonic amplitude of residual voltage is larger than 0.2Unn and without operation of fault
detector element, VT neutral point failure alarm signal [VTNS.Alm] will be issued with the time
delay [VTS.t_DPU] and drop off with the time delay [VTS.t_DDO] after three phases voltage
restored to normal.

3.27.3 Function Block Diagram


VTS

VTS.En

VTNS

VTNS.En

VTS.Alm

VTS.Blk

VTNS.Alm

VTNS.Blk

VTS.MCB_VT

3.27.4 I/O Signals


Table 3.27-1 I/O signals of VT circuit supervision
No.

Input Signal

VTS.En

VTS.Blk

Description
VT supervision enabling input, it is triggered from binary input or programmable
logic etc.
VT supervision blocking input, it is triggered from binary input or programmable

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logic etc.
VT neutral point supervision enabling input, it is triggered from binary input or

VTNS.En

VTNS.Blk

VTS.MCB_VT

No.

programmable logic etc.


VT neutral point supervision blocking input, it is triggered from binary input or
programmable logic etc.
Binary input for VT MCB auxiliary contact

Output Signal

Description

VTS.Alm

Alarm signal to indicate VT circuit fails

VTNS.Alm

Alarm signal to indicate VT neutral point fails

3.27.5 Logic

&
SIG

FD.Pkp

SIG

79.Inprog

SIG

3U0>0.08Unn

SIG

3U1<Unn

EN

[VTS.En_LineVT]

SIG

52b_3P

EN

[VTS.En_Out_VT]

>=1

>=1
&
>=1

BI

1: open
0: closed

&

[VTS.t_DPU] [VTS.t_DDO]

&
>=1

>=1
&

VTS.Alm

[VTS.MCB_VT]

EN

[VTS.En]

SIG

[VTS.En]

SIG

[VTS.Blk]

&

Figure 3.27-1 Logic of VT circuit supervision

&
SIG

FD.Pkp

SIG

79.Inprog

OTH

U03>0.2Unn

>=1

&

1: open
0: closed

>=1

[VTS.t_DPU]
EN

[VTS.En_Out_VT]

EN

[VTS.En]

SIG

[VTNS.En]

SIG

[VTNS.Blk]

[VTS.t_DDO]

&

VTNS.Alm

&

Figure 3.27-2 Logic of VT neutral point supervision

Unn: rated phase-to-phase voltage


U03: third harmonic amplitude of neutral point residual voltage
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If there is already a VTS alarm before FD operated, VTS will continue to block distance protection,
that is VTS will be latched when FD operates.

3.27.6 Settings
Table 3.27-2 VTS Settings
No.

Name

Range

Step

Unit

Remark

VTS.t_DPU

0.200~100.000

0.001

Pickup time delay of VT circuit supervision

VTS.t_DDO

0.200~100.000

0.001

Dropoff time delay of VT circuit supervision


No voltage used for protection calculation
1: enable

VTS.En_Out_VT

0: disable

0 or 1

In general, when VT is not connected to the


device, this logic setting should be set as
1
Voltage selection for protection calculation

VTS.En_LineVT

from busbar VT or line VT

0 or 1

1: line VT
0: busbar VT
Alarm function of VT circuit supervision

VTS.En

0 or 1

1: enable
0: disable

3.28 CT Circuit Supervision


3.28.1 General Application
The purpose of the CT circuit supervision is to detect any abnormality on CT secondary circuit.

3.28.2 Function Description


Under normal conditions, CT secondary signal is continuously supervised by detecting the
residual current and voltage. If residual current is larger than 10%In whereas residual voltage is
less than 3V, an error in CT circuit is considered, the concerned protection functions are blocked
and an alarm is issued with a time delay of 10s and drop off with a time delay of 10s after CT
circuit is restored to normal condition.

3.28.3 Function Block Diagram


CTS
CTS.En

CTS.Alm

CTS.Blk

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3.28.4 I/O Signals


Table 3.28-1 I/O signals of CT circuit supervision
No.

Input Signal

CTS.En

CTS.Blk

No.
1

Description
CT circuit supervision enabling input, it is triggered from binary input or
programmable logic etc.
CT circuit supervision blocking input, it is triggered from binary input or
programmable logic etc.

Output Signal
CTS.Alm

Description
Alarm signal to indicate CT circuit fails

3.28.5 Logic
SIG

CTS.En

SIG

CTS.Blk

SIG

3I0>0.1In

SIG

3U0<3V

SIG

IA<0.06In

SIG

IB<0.06In

SIG

IC<0.06In

&
&
10s

10s

CTS.Alm

&

>=1

Figure 3.28-1 Logic diagram of CT circuit failure

3.29 Control and Synchrocheck for Manual Closing


3.29.1 General Application
The purpose of control is to open or close primary equipment, including circuit breaker (CB),
disconnector (DS) and earth switch (ES), or to issue outputs for signaling purpose. Synchronism
check and dead check are also provided for the control processes as below:
1. Local manual closing CB
2. Local closing CB by access the menu Local CmdControl
3. Remote closing CB from SCADA (i.e., local HMI system) or control center (CC)
Programmable interlocking logics within a bay and amongst different bays are provided by using
PCS-Explorer.

3.29.2 Function Description


1. Control
High reliability is ensured by adopting the principle of selection before operation (abbreviated
SBO). When the binary input [BI_Maintenance] is energized as 1, remote control from

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SCADA/CC will be disabled, but local control will not be influenced.


The integrated control process is as follow:
1) The control source (SCADA/CC, or local LCD control operation, or manual control operation)
sends control selection command to this device
2) This device sends back the control selection result (success or failure) to the control source
after logic judgment
3) The control source sends control operation command to this device if the control selection
result is success. The control source will send control cancellation command to this device if
the control selection result is failure.
4) This device sends back the control operation result (success or failure) to the control source
after logic judgment.
Logic calculation result of interlocking is input to the remote control module as a criterion of remote
operation. When the enabling parameter of remote open/close interlock is 1, remote control
module determines whether it can be output according to the calculation result of interlocking. If
the current breaker position or programmable part can meet the interlocking condition, remote
control can be output normally, otherwise remote operation is blocked. When the enabling
parameter of remote open/close interlock is 0, interlocking function is disabled and remote
control will be output directly without the judgment of interlocking.
Holding time of each binary output contact can be set by configuring corresponding settings and is
often configured as 250ms. However, for the control circuits without latched relays, the holding
time must be longer to ensure successful control operation.

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SIG

CSWI01.CILO.Disable

SIG

BIinput.CILO.Disable

EN

[CSWI01.En_Cls_Blk]

SIG

CSWI01.CILO.EnCls

SIG

CSWI01.RmtCtrl

SIG

BIinput.RmtCtrl

SIG

CSWI01.Cmd_RmtCtrl

SIG

CSWI01.LocCtrl

SIG

BIinput.LocCtrl

SIG

CSWI01.ManSynCls

SIG

CSWI01.Cmd_LocCtrl

SET

MCBrd.25.En_SynChk

SIG

Sig_Ok_Chk

SET

MCBrd.25.En_LvL_DdB

SET

MCBrd.25.En_DdL_LvB

SET

MCBrd.25.En_DdL_DdB

SIG

Sig_Ok_Chk

SET

MCBrd.25.En_NoChk

SIG

CSWIxx.CILO.Disable

SIG

BIinput.CILO.Disable

EN

[CSWIxx.En_Cls_Blk]

SIG

CSWIxx.CILO.EnCls

SIG

CSWIxx.RmtCtrl

SIG

BIinput.RmtCtrl

SIG

CSWIxx.Cmd_RmtCtrl

SIG

CSWIxx.LocCtrl

SIG

BIinput.LocCtrl

SIG

CSWIxx.Cmd_LocCtrl

>=1

>=1

>=1

&
&

>=1

[CSWI01.t_PW_Cls]

0ms

[CSWI01.Op_Cls]

>=1

&
>=1

>=1
>=1

>=1
>=1

>=1

>=1

&
[CSWIxx.t_PW_Cls]

0ms

[CSWIxx.Op_Cls]

>=1

&
>=1

>=1

&

Figure 3.29-1 Logic diagram of closing primary equipment

Where:
xx=02~10
Only the first closing command CSWI01.Op_Cls controlled by synchrocheck logic can be used
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for CB closing.
After receiving a closing command, this device will continuously check whether the 2 voltages
(Incoming voltage and reference voltage) involved in synchronism check (or dead check) can meet
the criteria. Within the duration of [MCBrd.25.t_Wait_Chk], if the synchronism check (or dead
check) criteria are not met, the signal Sig_Ok_Chk will be set as 0; if the synchronism check (or
dead check) criteria are met, the signal Sig_Ok_Chk will be set as 1.
Access the menu Local CmdControl to issue control command locally, and this signal
CSWIxx.md_LocCtrl will be set as 1.
Remote control commands from SCADA/CC can be transmitted via IEC 60870-5-103 protocol or
IEC 61850 protocol, and this signal CSWIxx.Cmd_RmtCtrl will be set as 1.
SIG

CSWI01.CILO.Disable

SIG

BIinput.CILO.Disable

EN

[CSWI01.En_Opn_Blk]

SIG

CSWI01.CILO.EnOpn

SIG

CSWI01.RmtCtrl

SIG

BIinput.RmtCtrl

SIG

CSWI.Cmd_RmtCtrl

SIG

CSWI01.LocCtrl

SIG

BIinput.LocCtrl

SIG

CSWI01.ManOpn

SIG

CSWI01.Cmd_LocCtrl

SIG

CSWIxx.CILO.Disable

SIG

BIinput.CILO.Disable

EN

[CSWIxx.En_Opn_Blk]

SIG

CSWIxx.CILO.EnOpn

SIG

CSWIxx.RmtCtrl

SIG

BIinput.RmtCtrl

SIG

CSWIxx.Cmd_RmtCtrl

SIG

CSWIxx.LocCtrl

SIG

BIinput.LocCtrl

SIG

CSWIxx.Cmd_LocCtrl

>=1

>=1

&
[CSWI01.t_PW_Opn]

0ms

[CSWI01.Op_Opn]

[CSWIxx.t_PW_Opn]

0ms

[CSWIxx.Op_Opn]

>=1

&
>=1

>=1

&
>=1

>=1

>=1

&

>=1

&
>=1

>=1

&

Figure 3.29-2 Logic diagram of open primary equipment

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Where:
xx=01~10
The control output fulfills signal output circuit, and opens or closes circuit breaker, disconnector
and earth switch according to the control command. Object manipulation strictly performs three
steps: selection, check and excute, and perform output relay check, to ensure that the remote
control can be excuted safely and reliably.
When logic interlock is enabled, the device can receive the programmable interlock logic. The
device can automatically initiate the interlock logic to determine whether to allow control
operations. The device provides corresponding settings ([En_Opnxx_Blk] and [En_Clsxx_Blk]) for
each control object. When they are set as 1, the interlock function of the corresponding control
object is enabled. The interlock logic can be configured by using PCS-Explorer, and downloaded
to the device via the Ethernet port. If the interlock function is enabled, but it is not configured the
interlock logic, the result of the logic output is 0.
The control record is a file which is used to store remote control command records of this device
circularly. If the record number is to 256, the storage area of the control record will be full. If this
device has received a new remote command, this device will delete the oldest remote control
record, and then store the latest remote control record.
There are 10 configuration page corresponding to 10 control outputs in totall respectively. Each
configuration page can finish some signals configuration, including remote control, local control,
disable interlock blocking, and so on.
In order to conveniently configure control output, the same output signals, including
BIinput.RmtCtrl, BIinput.LocCtrl and BIinput.CILO.Disable, are available after processing
binary signals internally, as shown in figure below.

Figure 3.29-3 Configuration page of control output 01 (default configration)

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Figure 3.29-4 Configuration page of control output 02 (default configration)

Control output 03~10 is as same as control output 02.


The configuration rule about remote control and local control to binary outputs is as bellow:
Remot

Local

CSWIxx.

BIinput.

CSWIxx.

BIinput.

RmtCtrl

RmtCtrl

LocCtrl

LocCtrl

Control Mode

Neither Local control nor remote control are permissible.


Only local control is permissible.

Only remote control is permissible.

Only remote control is permissible.

Only local control is permissible.

Neither Local control nor remote control are permissible.

Only local control is permissible.

Only remote control is permissible.

Both Local control and remote control are permissible.

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1

For remote control or local control, they can be configured by either of CSWIxx.RmtCtrl and
BIinput.RmtCtrl, or either of CSWIxx.LocCtrl and BIinput.LocCtrl. X means that it is not
configured.
2. Synchrocheck
Three synchrocheck modes are designed for CB closing: no check mode, dead check mode and
synchronism check mode, if any one of the condition of three synchrocheck modes satisfied, then
synchrocheck signal Sig_Ok_Chk will be asserted.
The synchronism check function measures the conditions across the circuit breaker and compares
them with the corresponding settings. The output is only given if all measured quantities are
simultaneously within their set limits. Compared to the synchronism check for auto-reclosing, an
additional criterion is applied to check the rate of frequency change (df/dt) between both sides of
the CB.
When the following four conditions are all met, the synchronism check is successful.
1) Phase angle difference between incoming voltage and reference voltage is less than the
setting [MCBrd.25.phi_Diff]
2) Frequency difference between incoming voltage and reference voltage is less than
[MCBrd.25.f_Diff]
3) Voltage difference between between incoming voltage and reference voltage is less than
[MCBrd.25.U_Diff]
4) Rate of frequency change between incoming voltage and reference voltage is less than
[MCBrd.25.df/dt]
The dead check function measures the amplitude of line voltage and bus voltage at both sides of
the circuit breaker, and then compare them with the live check setting [MCBrd.25.U_Lv] and the
dead check setting [MCBrd.25.U_Dd]. The dead check is successful when the measured
quantities comply with the criteria.
When this device is set to work in no check mode and receives a closing command, CB will be
closed without synchronism check and dead check.

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3.29.3 Function Block Diagram


CSWI01
CILO.EnOpn

Op_Opn

CILO.EnCls

Op_Cls

RmtCtrl
LocCtrl
CILO.Disable
ManSynCls
ManOpn

CSWIxx
CILO.EnOpn

Op_Opn

CILO.EnCls

Op_Cls

RmtCtrl
LocCtrl
CILO.Disable

BIinput
RmtCtrl

RmtCtrl

LocCtrl

LocCtrl

CILO.Disable

CILO.Disable

xx can be from 02 to 10

3.29.4 I/O Signals


Table 3.29-1 I/O signals of control
No.

Input Signal

Description
From receiving a closing command, this device will continuously check

Sig_Ok_Chk

whether the 2 voltages (Incoming voltage and reference voltage) involved


in synchronism check(or dead check) can meet the criteria.
Within the duration of [MCBrd.25.t_Wait_Chk], if the synchronism

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check(or dead check) criteria are not met, [Sig_Ok_Chk] will be set as 0;
if the synchronism check(or dead check) criteria are met, [Sig_Ok_Chk]
will be set as 1.
2

CSWIxx.CILO.EnOpn

It is the interlock status of No.xx open output of BO module (xx=01~10)

CSWIxx.CILO.EnCls

It is the interlock status of No.xx closing output of BO module (xx=01~10)


Access the menu Local CmdControl to issue control command
locally.

CSWIxx.Cmd_LocCtrl

It is used to select the local control to No.xx controlled object (CB/DS/ES).


When the local control is active, No.xx binary outputs can only be locally
controlled. (xx=01~10)
It is used to select the remote control to No.xx controlled object

CSWIxx.Cmd_RmtCtrl

(CB/DS/ES). When the remote control is active, No.xx binary outputs can
only be remotely controlled by SCADA or control centers. (xx=01~10)
It is used to disable the interlock blocking function for control output. If the

CSWIxx.CILO.Disable

signal CSWIxx.CILO.Disable is 1, No.xx binary outputs of the device


will not be blocked by interlock conditions. (xx=01~10)
It is used to select the remote control to No.xx controlled object

BIinput.RmtCtrl

(CB/DS/ES). When the remote control is active, all binary outputs can only
be remotely controlled by SCADA or control centers.
It is used to select the local control to No.xx controlled object (CB/DS/ES).

BIinput.LocCtrl

When the local control is active, all binary outputs can only be locally
controlled.
It is used to disable the interlock blocking function for control output. If the

BIinput.CILO.Disable

signal BIinput.CILO.Disable is 1, all binary outputs of this device will


not be blocked by interlock conditions.
When

10

CSWI01.ManSynCls

the

condition

of

local

control

is

met

and

the

signal

CSWI01.ManSynCls is 1, the output contact [BO_CtrlCls01] is closed


to execute manually closing the circuit breaker with synschrochcek.
When

11

CSWI01.ManOpn

the

condition

of

local

control

is

met

and

the

signal

CSWI01.ManOpn is 1, the output contact [BO_CtrlOpn01] is closed to


execute manually open the circuit breaker.

No.

Output Signal

Description

CSWIxx.Op_Opn

No.xx command output for open. (xx=01~10)

CSWIxx.Op_Cls

No.xx command output for closing. (xx=01~10)

BIinput.RmtCtrl

In order to be convenient to user configure control output, three same

BIinput.LocCtrl

output signals with input signals are available. The relationship with 10
binary output have been configured inside the device. The user only
assigns a specific binary input to input signal, the relevant function can be

BIinput.CILO.Disable

gained. If some binary output need not be controlled by three signals,


please cancle the configuration by PCS-Explorer, and configure it
independently.

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3.29.5 Settings
Table 3.29-2 Control Settings
No.

Name

Range

Step

Unit

Remark
No.xx holding time of a normal open contact

CSWIxx.t_PW_Opn

0~65535

ms

of remote opening CB, disconnector or for


signaling purpose.
(xx=01, 02.10)
No.xx closing time of a normal open contact

CSWIxx.t_PW_Cls

0~65535

ms

of remote closing CB, disconnector or for


signaling purpose.
(xx=01, 02.10)
These settings are applied to configure the

CSWIxx.t_DPU_DPS

0~60000

ms

debouncing time. DPU is the abbreviation of


Delay Pick Up. (xx=01, 02.10)
Enabling/disabling No.xx open output of the
BO module be controlled by the interlocking

CSWIxx.En_Opn_Blk

logic

0 or 1

0: disable
1: enable
(xx=01, 02.10)
Enabling/disabling No.xx closing output of the
BO module be controlled by the interlocking
5

CSWIxx.En_Cls_Blk

logic

0 or 1

0: disable
1: enable
(xx=01, 02.10)
Table 3.29-3 Synchrocheck Settings
No.

Name

Range

Step

Unit

Remark
Voltage selecting mode of line
0: A-phase voltage
1: B-phase voltage

MCBrd.25.Opt_Source_UL

0~5

2: C-phase voltage
3: AB-phase voltage
4: BC-phase voltage
5: CA-phase voltage
Voltage selecting mode of bus
0: A-phase voltage
1: B-phase voltage

MCBrd.25.Opt_Source_UB

0~5

2: C-phase voltage
3: AB-phase voltage
4: BC-phase voltage
5: CA-phase voltage

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3

MCBrd.25.U_Dd

0.05Un~0.8Un

0.001

Voltage threshold of dead check

MCBrd.25.U_Lv

0.5Un~Un

0.001

Voltage threshold of live check

MCBrd.25.K_Usyn

0.20-5.00

MCBrd.25.phi_Diff

0~ 89

MCBrd.25.phi_Comp

0~359

MCBrd.25.f_Diff

0.02~1.00

0.01

Hz

MCBrd.25.U_Diff

0.02Un~0.8Un

0.01

10

MCBrd.25.En_SynChk

0 or 1

11

MCBrd.25.En_DdL_DdB

0 or 1

12

MCBrd.25.En_DdL_LvB

0 or 1

13

MCBrd.25.En_LvL_DdB

0 or 1

14

MCBrd.25.En_NoChk

0 or 1

Compensation

coefficient

for

synchronism voltage
Deg

Phase

difference

limit

of

synchronism check for AR


Compensation for phase difference
between two synchronous voltages
Frequency

difference

limit

of

synchronism check for AR


Voltage

difference

limit

of

synchronism check for AR


Enable synchronism check
Enable dead line and dead bus
(DLDB) check
Enable dead line and live bus
(DLLB) check
Enable live line and dead bus
(LLDB) check
Enable AR without any check
Threshold of rate of frequency

15

MCBrd.25.df/dt

0.00~3.00

0.01

Hz/s

change between both sides of CB


for synchronism-check.
Circuit breaker closing time. It is the

16

MCBrd.25.t_Close_CB

20~1000

ms

time

from

receiving

closing

command pulse till the CB is


completely closed.
From receiving a closing command,
this device will continuously check
whether between incoming voltage
and reference voltage involved in
synchronism check (or dead check)

17

MCBrd.25.t_Wait_Chk

5~30

0.001

can

meet

the

criteria.

If

the

synchronism check (or dead check)


criteria are not met within the
duration of this time delay, the failure
of

synchronism-check

(or

dead

check) will be confirmed.

3.30 Faulty Phase Selection


3.30.1 General Application
Fault phase selection logic can be implemented by the following methods:

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3 Operation Theory

1.

Detecting the variation of operating voltage

2.

Detecting the phase difference between I0 and I2A

The logic makes the device ideal for single-phase tripping applications.

3.30.2 Function Description


3.30.2.1 Variation of Operating Voltage (Faulty Phase Selection Element 1)
1.

Variation of phase operating voltage

1)

Phase A: UOPA

2)

Phase B: UOPB

3)

Phase C: UOPC

2.

Variation of phase-to-phase operating voltage

1)

Phase AB: UOPAB

2)

Phase BC: UOPBC

3)

Phase CA: UOPCA

UOMAX=Max(UOPA, UOPB, UOPC)


UOMAX=Max(UOPAB, UOPBC, UOPCA)
If UOMAX is several times higher than the variation of operating voltages of other two phases, the
single-phase fault is ensured, otherwise, the multi-phase fault is ensured.
Table 3.30-1 Relation between UOMAX and faulty phase
UOMAX or UOMAX

Fault phase

UOPA

Phase A

UOPB

Phase B

UOPC

Phase C

UOPAB

Phase AB

UOPBC

Phase BC

UOPCA

Phase CA

3.30.2.2 I0 and I2A (Faulty Phase Selection Element 2)


The phase selection algorithm uses the angle relation between I0 and I2A of the device. As shown
in Figure 3.30-1, there are three faulty phase selection regions.

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3 Operation Theory

Region A
60

-60

Region B

Region C

180

Figure 3.30-1 The region of faulty phase selection

Depended on the phase relation between I0 and I2A, the faulty phase can be determined.
1.

-60<Arg(I0/I2A)<60, region A is selected, possible faulty phase is phase A or phase BC.

2.

60<Arg(I0/I2A)<180, region B is selected, possible faulty phase is phase B or phase CA.

3.

180<Arg(I0/I2A)<300, region C is selected, possible faulty phase is phase C or phase AB.

For single-phase earth fault, I0 and I2 of faulty phase are in-phase and its distance element
operates.
For phase to phase to earth fault, I0 and I2 of non-faulty phase are in-phase but its distance
element does not operate.

3.30.3 Function Block Diagram


PhSel
PhSA
PhSB
PhSC
GndFlt

3.30.4 I/O Signals


Table 3.30-2 I/O signals of faulty phase selection
No.

Output Signal

Description

PhSA

Phase-A is selected as faulty phase

PhSB

Phase-B is selected as faulty phase

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3 Operation Theory
3

PhSC

Phase-C is selected as faulty phase

GndFlt

Earth fault

3.31 Fault Location


3.31.1 Application
The main objective of line protection is fast, selective and reliable operation for faults on a
protected line section. Besides this, information on distance to fault is very important for those
involved in operation and maintenance. Reliable information on the fault location greatly
decreases the outage of the protected lines and increases the total availability of a power system.
This fault location function cannot be used for the transmission line with series compensation.

3.31.2 Function Description


3.31.2.1 Fundamental Principle
The fault location is an essential function to various line protection devices, after selecting faulty
phase, it measures and indicates the distance to the fault with high accuracy. Thus, the fault can
be quickly located for repairs. The calculation algorithm considers the effect of load currents,
double-end infeed and additional fault resistance. Both double-end fault location and single-end
fault location are available in line differential relay, but only single-end fault location is provided in
other relays.
The calculation equation is:

[km]
Where:
Dist: The distance of fault location according to the Zcalc (km)
Zcalc: The impedance value calculated from the location of protection device to fault point
Zl: The impedance value of the whole line + mutual impedance
Length: The input length of transmission line (km)
3.31.2.2 Mutual Compensation
When an earth fault occurred on a line of parallel lines arrangement, a distance relay at one end of
the faulty line will tend to underreach whilst the distance relay at the other end will tend to
overreach. Usually the degree of underreach or overreach is acceptable, however, for cases
where precise fault location is required for long lines with high mutual coupling, mutual
compensation is then required to improve the distance measurement. Practically, the mutual effect
between the parallel lines is insignificant to positive and negative sequence and thus the mutual
compensation is only for zero sequence

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3 Operation Theory
A

Ia

ZM
k
C

Ic

ZS

D
(1-k)ZL

kZL

ZL

The principle in the application of mutual compensation is shown as follows with the aid of
following sequence network diagram figure. The diagram indicates a parallel lines arrangement
with an earth fault at location k on line CD.
The equivalent sequence network for an earth fault on a parallel lines arrangement with single
source is shown as below.
Ia1

ZL1

ZS1
kZL1

(1-k)ZL1

Ic1
Ia2

ZL2

ZS2
kZL2

(1-k)ZL2

Ic2
Ia0

ZL0

ZS0
Z0M
kZL0

(1-k)ZL0

Ic0

Figure 3.31-1 Equivalent sequence network

The device at location C without mutual compensation will have voltage URC and current IRC
measured as shown in the expression
URC is the voltage of the device at location C.

If the line is fully transposed, ZL1=ZL2, Then

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3 Operation Theory

The impedance presented to the device is:

For an earth fault,

With the mutual compensation enabled,

(Actual distance of the fault)


The residual current from the parallel line should be added to the device. It should be connected to
terminal 08 and star point of the parallel line CT connected to terminal 07 as shown in the following
figure. Please note the connection diagram and the terminal numbers are for reference only. The
final connection terminals are subject to the device configuration at site.

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3 Operation Theory
A
B
C

P2

S2

P2

S2

P1

S1

P1

S1

02

01

02

01

04

03

04

03

06

05

06

05

08

07

08

07

3.31.3 Function Block Diagram


FL
Fault_Location

FPS_Fault

Fault_Phase

FD.Pkp

Fault_Phase_Curr
Fault_Resid_Curr

3.31.4 I/O Signals


Table 3.31-1 I/O signals of fault location
No.

Input Signal

Description

FPS_Fault

Faulty phase selection

FD.Pkp

The device picks up

No.
1

Output Signal
Fault_Location

Description
The result of fault location

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3 Operation Theory
2

Faulty_Phase

The selected faulty phase

Fault_Phase_Curr

Maximum faulty current

Fault_Resid_Curr

Maximum residual current

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3 Operation Theory

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Date: 2013-12-25

4 Supervision

4 Supervision
Table of Contents
4 Supervision ...................................................................................... 4-a
4.1 Overview .......................................................................................................... 4-1
4.2 Supervision Alarms ......................................................................................... 4-1
4.3 Relay Self-supervision.................................................................................... 4-7
4.3.1 Relay Hardware Monitoring................................................................................................ 4-7
4.3.2 Fault Detector Monitoring ................................................................................................... 4-7
4.3.3 Check Setting..................................................................................................................... 4-7

4.4 AC Input Monitoring ........................................................................................ 4-8


4.4.1 Voltage/current Drift Monitoring and Auto-adjustment ........................................................ 4-8
4.4.2 Sampling Monitoring .......................................................................................................... 4-8

4.5 Secondary Circuit Monitoring ........................................................................ 4-8


4.5.1 Opto-coupler Power Supervision ....................................................................................... 4-8
4.5.2 Circuit Breaker Supervision................................................................................................ 4-8

4.6 GOOSE Alarm .................................................................................................. 4-8

List of Tables
Table 4.2-1 Alarm description ...................................................................................................4-1
Table 4.2-2 Troubleshooting .....................................................................................................4-5

PCS-902 Line Distance Relay

4-a
Date: 2013-09-07

4 Supervision

4-b

PCS-902 Line Distance Relay


Date: 2013-09-07

4 Supervision

4.1 Overview
Protection system is in quiescent state under normal conditions, and it is required to respond
promptly for faults occurred on power system. When the device is in energizing process before the
LED HEALTHY is on, the device need to be checked to ensure no abnormality. Therefore, the
automatic supervision function, which checks the health of the protection system when startup and
during normal operation, plays an important role.
The numerical relay based on the microprocessor operations is suitable for implementing this
automatic supervision function of the protection system.
In case a defect is detected during initialization when DC power supply is provided to the device,
the device will be blocked with indication and alarm of relay out of service. It is suggested a trial
recovery of the device by re-energization. Please contact supplier if the device is still failure.
When a failure is detected by the automatic supervision, it is followed by a LCD message, LED
indication and alarm contact outputs. The failure alarm is also recorded in event recording report
and can be printed If required.

4.2 Supervision Alarms


Hardware circuit and operation status of the device are self-supervised continuously. If any
abnormal condition is detected, information or report will be displayed and a corresponding alarm
will be issued.
A minor abnormality may block a certain number of protections functions while the other functions
can still work. However, if severe hardware failure or abnormality, such as PWR module failure,
DC converter failure and so on, are detected, all protection functions will be blocked and the LED
HEALTHY will be extinguished and blocking output contacts BO_FAIL will be given. The
protective device then can not work normally and maintenance is required to eliminate the failure.
All the alarm signals and the corresponding handling suggestions are listed below.
Note!
If the protective device is blocked or alarm signal is sent during operation, please do find
out its reason with the help of self-diagnostic record. If the reason can not be found at site,
please notify the factory NR. Please do not simply press button TARGET RESET on the
protection panel or re-energize on the device.
Table 4.2-1 Alarm description
No.

Item

Description

Blocking Device

Fail Signals
The device fails.
1

Fail_Device

This signal will be pick up if any fail signal picks up and it

Blocked

will drop off when all fail signals drop off.


2

Fail_Setting_OvRange

Set value of any setting is out of scope.

PCS-902 Line Distance Relay

Blocked

4-1
Date: 2013-09-07

4 Supervision
This signal will pick up instantaneously and will be
latched unless the recommended handling suggestion is
adopted.
3

Fail_BoardConfig

Mismatch between the configuration of plug-in modules


and the designing drawing of an applied-specific project.

Blocked

After config file is updated, settings of the file and


settings saved on the device are not matched.
4

Fail_SettingItem_Chgd

This signal will pick up instantaneously and will be

Blocked

latched unless the recommended handling suggestion is


adopted.
Error is found during checking memory data.
5

Fail_Memory

This signal will pick up instantaneously and will be


latched unless the recommended handling suggestion is

Blocked

adopted.
Error is found during checking settings.
6

Fail_Settings

This signal will pick up instantaneously and will be


latched unless the recommended handling suggestion is

Blocked

adopted.
DSP chip is damaged.
7

Fail_DSP

This signal will pick up instantaneously and will be


latched unless the recommended handling suggestion is

Blocked

adopted.
Communication between two DSP chips is abnormal
8

Fail_DSP_Comm

This signal will pick up instantaneously and will drop off

Blocked

instantaneously.
Software configuation is incorrect.
9

Fail_Config

This signal will pick up instantaneously and will be


latched unless the recommended handling suggestion is

Blocked

adopted.
AC current and voltage samplings are abnormal.
10

Fail_Sample

This signal will pick up with a time delay of 200ms and


will be latched unless the recommended handling

Blocked

suggestion is adopted.
11

MCBrd.Fail_Sample

12

MCBrd.Fail_Settings

For DSP plug-in module for measurement and control in


slot 06, AC current and voltage samplings are abnormal
Error is found during checking the settings of DSP
plug-in module for measurement and control in slot 06.

Blocked

Blocked

Alarm Signals
The device is abnormal.
13

Alm_Device

This signal will be pick up if any alarm signal picks up

Unblocked

and it will drop off when all alarm signals drop off.
14

Alm_Insuf_Memory

15

Alm_CommTest

The memory of MON plug-in module is insufficient.


The device is in the communication test mode.
This signal will pick up instantaneously and will drop off

4-2

Unblocked
Unblocked

PCS-902 Line Distance Relay


Date: 2013-09-07

4 Supervision
instantaneously.
The error is found during MON module checking
16

Alm_Settings_MON

settings of device.
This signal will pick up with a time delay of 10s and will

Unblocked

be latched unless re-powering or rebooting the device.


The error is found during checking the version of
17

Alm_Version

software downloaded to the device.


This signal will pick up instantaneously and will drop off

Unblocked

instantaneously.
The active group set by settings in device and that set
18

Alm_BI_SettingGrp

by binary input are not matched.


This signal will pick up instantaneously and will drop off

Unblocked

instantaneously.
Data frame is abnormal between two DSP modules.
19

Alm_DSP_Frame

This signal will pick up instantaneously and will drop off

Unblocked

instantaneously.
The power supply of BI plug-in module in slot xx is
20

Bxx.Alm_OptoDC

abnormal.
This signal will pick up with a time delay of 10s and will

Unblocked

drop off with a time delay of 10s.


Fault detector element operates for longer than 50s.
21

Alm_Pkp_FD

This signal will pick up with a time delay of 50s and will

Unblocked

drop off with a time delay of 10s.


Neutral current fault detector element operates for
22

Alm_Pkp_I0

longer than 10s.


This signal will pick up with a time delay of 10s and will

Unblocked

drop off with a time delay of 10s.


Protection VT circuit fails.
23

VTS.Alm

This signal will pick up with a time delay [VTS.t_DPU]

Unblocked

and will drop off with a time delay [VTS.t_DDO].


Protection VT circuit of neutral point fails.
24

VTNS.Alm

This signal will pick up with a time delay [VTS.t_DPU]

Unblocked

and will drop off with a time delay [VTS.t_DDO].


CT circuit of corresponding circuit breaker fails.
25

CTS.Alm

This signal will pick up with a time delay of 10s and will

Unblocked

drop off with a time delay of 10s.


The
26

Alm_52b

auxiliary

normally

closed

contact

(52b)

of

corresponding circuit breaker is abnormal.


This signal will pick up with a time delay of 10s and will

Unblocked

drop off with a time delay of 10s.


The device is in maintenance state.
27

BI_Maintenance

This signal will pick up with a time delay of 150ms and

Unblocked

will drop off with a time delay of 150ms.

PCS-902 Line Distance Relay

4-3
Date: 2013-09-07

4 Supervision
28

Alm_TimeSyn

Time synchronization abnormality alarm.

Unblocked

Frequency of the system is higher than 65Hz or lower


29

Alm_Freq

than 45Hz.
This signal will pick up with a time delay of 100ms and

Unblocked

will drop off with a time delay of 10s.

30

Alm_Sparexx
(xx=01~08)

Spare alarm signals


The time delay of pickup and dropoff for these alarm

Unblocked

signals can be set by PCS-Explorer.


Protection Element Alarm Signals
Channel x is abnormal

31

FOx.Alm

This signal will pick up with a time delay of 100ms and

Unblocked

will drop off with a time delay of 1s.


Received ID from the remote end is not as same as the
32

FOx.Alm_ID

setting [FOx.RmtID] of the device in local end


This signal will pick up with a time delay of 100ms and

Unblocked

will drop off with a time delay of 1s.


No valid frame of channel x is received.
33

FOx.Alm_NoValFram

This signal will pick up with a time delay of 100ms and

Unblocked

will drop off with a time delay of 1s.


Rate of error code of channel x is larger than 40 error
34

FOx.Alm_CRC

codes per second.


This signal will pick up instantaneously and will drop off

Unblocked

with a time delay of 10s.


Channelx is out of service due to receive error codes
35

FOx.Alm_Off

after device picking up.


This signal will pick up instantaneously and will drop off

Unblocked

instantaneously.
Optical fibre of channel x is connected wrongly.
36

FOx.Alm_Connect

This signal will pick up with a time delay of 100ms and

Unblocked

will drop off with a time delay of 1s.


37

27P1.Alm

Stage 1 of undervoltage protection alarms.

Unblocked

38

27P2.Alm

Stage 2 of undervoltage protection alarms.

Unblocked

39

59P1.Alm

Stage 1 of overvoltage protection alarms.

Unblocked

40

59P2.Alm

Stage 2 of overvoltage protection alarms.

Unblocked

41

49-1.Alm

42

49-2.Alm

43

46BC.Alm

44

25.Alm_VTS_UB

Stage 1 of thermal overload protection operates to


alarm.
Stage 2 of thermal overload protection operates to
alarm.
Broken-conductor protection operates to alarm.

Unblocked

Unblocked
Unblocked

Synchronism voltage circuit is abnormal (UB)


This signal will pick up with a time delay of 1.25s and will

Unblocked

drop off with a time delay of 10s.


45

25.Alm_VTS_UL

Synchronism voltage circuit is abnormal (UL)

4-4

Unblocked
PCS-902 Line Distance Relay

Date: 2013-09-07

4 Supervision
This signal will pick up with a time delay of 1.25s and will
drop off with a time delay of 10s.
46

79.Fail_Rcls

Auto-reclosing fails.

Unblocked

47

79.Fail_Chk

Synchrocheck for AR fails.

Unblocked

Input signal of receiving transfer trip is energized for


48

TT.Alm

longer than 4s and it will drop off with a time delay of

Unblocked

10s.
Table 4.2-2 Troubleshooting
No.

Item

Handling suggestion
Fail Signals

Fail_Device

The signal is issued with other specific fail signals, and please refer to the
handling suggestion other specific alarm signals.
Please reset setting values according to the range described in the instruction

Fail_Setting_OvRange

manual, then re-power or reboot the device and the device will restore to
normal operation state.
1. Go to the menu InformationBorad Info, check the abnormality
information.

Fail_BoardConfig

2. For the abnormality board, if the board is not used, then remove, and if the
board is used, then check whether the board is installed properly and work
normally.
Please check the settings mentioned in the prompt message on the LCD, and

Fail_SettingItem_Chgd

go to the menu Settings and select Confirm_Settings item to comfirm


settings. Then, the device will restore to normal operation stage.

Fail_Memory

Please inform the manufacture or the agent for repair.

Fail_Settings

Please inform the manufacture or the agent for repair.

Fail_DSP

Fail_DSP_Comm

Fail_Config

Chips are damaged and please inform the manufacture or the agent replacing
the module.
Please inform the manufacture or the agent for repair.
Please inform configuration engineers to check and confirm visualization
functions of the device
1. Please make the device out of service.

10

Fail_Sample

2. Then check if the analog input modules and wiring connectors connected to
those modules are installed at the position.
3. Re-power the device and the device will restore to normal operation state.
1. Please make the device out of service.

11

MCBrd.Fail_Sample

2. Then check if analog input modules and wiring connectors connected to


those modules are installed at the position.
3. Re-power the device and the device will restore to normal operation state.

12

MCBrd.Fail_Settings

Please inform the manufacturer or the agent for repair.


Alarm Signals

13

Alm_Device

14

Alm_Insuf_Memory

The signal is issued with other specific alarm signals, and please refer to the
handling suggestion other specific alarm signals.
Please replace MON plug-in module.

PCS-902 Line Distance Relay

4-5
Date: 2013-09-07

4 Supervision
15

Alm_CommTest

16

Alm_Settings_MON

No special treatment is needed, and disable the communication test function


after the completion of the test.
Please inform the manufacture or the agent for repair.
Users may pay no attention to the alarm signal in the project commissioning
stage, but it is needed to download the latest package file (including correct

17

Alm_Version

version checksum file) provided by R&D engineer to make the alarm signal
disappear. Then users get the correct software version. It is not allowed that
the alarm signal is issued on the device already has been put into service. the
devices having being put into service so that the alarm signal disappears.
Please check the value of setting [Active_Grp] and binary input of indiating

18

Alm_BI_SettingGrp

active group, and make them matched. Then the ALARM LED will be
extinguished and the corresponding alarm message will disappear and the
device will restore to normal operation state.

19

Alm_DSP_Frame

Please inform the manufacture or the agent for repair.


1. check whether the binary input module is connected to the power supply.
2. check whether the voltage of power supply is in the required range.

20

Bxx.Alm_OptoDC

3. After the voltage for binary input module restores to normal range, the
ALARM LED will be extinguished and the corresponding alarm message will
disappear and the device will restore to normal operation state.
Please check secondary values and protection settings. If settings are not set

21

Alm_Pkp_FD

reasonable to make fault detectors pick up, please reset settings, and then
the alarm message will disappear and the device will restore to normal
operation state.
Please check secondary values and protection settings. If settings are not set

22

Alm_Pkp_I0

reasonable to make fault detectors pick up, please reset settings, and then
the alarm message will disappear and the device will restore to normal
operation state.

23

VTS.Alm

24

VTNS.Alm

25

CTS.Alm

26

Alm_52b

Please check the corresponding VT secondary circuit. After the abnormality is


eliminated, the device returns to normal operation state.
Please check the corresponding VT secondary circuit of neutral point. After
the abnormality is eliminated, the device returns to normal operation state.
Please check the corresponding CT secondary circuit. After the abnormality is
eliminated, the device returns to normal operation state.
Please check the auxiliary contact of CB. After the abnormality is eliminated,
the device returns to normal operation state.
After maintenance is finished, please de-energized the binary input

27

BI_Maintenance

[BI_Maintenance] and then the alarm will disappear and the device restore to
normal operation state.
1. check whether the selected clock synchronization mode matches the clock
synchronization source;

28

Alm_TimeSyn
2. check whether the wiring connection between the device and the clock
synchronization source is correct

4-6

PCS-902 Line Distance Relay


Date: 2013-09-07

4 Supervision
3. check whether the setting for selecting clock synchronization (i.e.
[Opt_TimeSync]) is set correctly. If there is no clock synchronization, please
set the setting [Opt_TimeSync] as No TimeSync.
4. After the abnormality is removed, the ALARM LED will be extinguished
and the corresponding alarm message will disappear and the device will
restore to normal operation state.
29
30

Alm_Freq

Adjust the system operating mode

Alm_Sparexx

Find the reason according to specific problem. (These signals are

(xx=01~08)

user-defined.)
Operation Alarm Signals

31

FOx.Alm

Please check the conncetion of optical fibre channel.

32

FOx.Alm_ID

Please check the conncetion of optical fibre channel.

33

FOx.Alm_NoValFram

Please check the conncetion of optical fibre channel.

34

FOx.Alm_CRC

Please check the conncetion of optical fibre channel.

35

FOx.Alm_Off

Please check the conncetion of optical fibre channel.

36

FOx.Alm_Connect

Please check the conncetion of optical fibre channel. (For example, receiving
and sending are inconsistent, or channel 1 and channel 2 are inconsistent)
Please check the corresponding binary input secondary circuit. After the

37

TT.Alm

abnormality is eliminated, ALARM LED will go off automatically and device


returns to normal operation state with a time delay of 10s.

4.3 Relay Self-supervision


4.3.1 Relay Hardware Monitoring
All chips on DSP module are monitored to ensure whether they are damaged or having errors. If
any one of them is detected damaged or having error, the alarm signal [Fail_DSP] is issued with
the device being blocked.

4.3.2 Fault Detector Monitoring


When neutral current fault detector picks up and lasts for longer than 10 seconds, an alarm
[Alm_Pkp_I0] will be issued without the device blocked.
When any fault detector picks up for longer than 50s, an alarm will be issued [Alm_Pkp_FD]
without the device blocked.

4.3.3 Check Setting


This relay has 10 setting groups, only one Setting group could be activiated (is active) at a time.
The settings of active setting group are checked to ensure they are reasonable. If settings are
checked to be unreasonable or out of setting scopes, a corresponding alarm signal will be issued,
and the device is also blocked.

PCS-902 Line Distance Relay

4-7
Date: 2013-09-07

4 Supervision

4.4 AC Input Monitoring


4.4.1 Voltage/current Drift Monitoring and Auto-adjustment
Zero point of voltage and current may drift due to variation of temperature or other environment
factors. The device continually traces the drift and adjust it to normal value automatically.

4.4.2 Sampling Monitoring


AC current and voltage samplings of protection DSP and fault detector DSP are monitored and if
the samples of protection DSP and fault detector DSP are detected to be wrong or inconsistent
between them, the alarm signal [Fail_Sample] will be issued and the device will be blocked.

4.5 Secondary Circuit Monitoring


4.5.1 Opto-coupler Power Supervision
Positive power supply of opto-coupler is continually monitored. If an error or damage has occurred,
an alarm [Bxx.Alm_OptoDC] will be issued.

4.5.2 Circuit Breaker Supervision


If 52b of three phases are energized ,which indicates circuit breaker is open and there is no
current detected in the line, the line will be considered to be out of service. SOTF protection will be
enabled after 50ms.
If 52b of three phases are energized that indicates circuit breaker is open but there is still current
detected in the line (the measured current is greater than a settable threshold value) or
three-phase circuit breaker is in pole disagreement, an alarm signal [Alm_52b] will be issued after
10 seconds.

4.6 GOOSE Alarm


No.

Output Signal

Description
GOOSE alarm signal indicating that there is a network storm occurring on the

GAlm_AStorm_SL

GAlm_BStorm_SL

GAlm_CfgFile_SL

Namexx.GAlm_ADisc_SL_xx

GOOSE alarm signal indicating that network A for Namexx is disconnected.

Namexx.GAlm_BDisc_SL_xx

GOOSE alarm signal indicating that network B for Namexx is disconnected.

Namexx.GAlm_Cfg_SL_xx

network A.
GOOSE alarm signal indicating that there is a network storm occurring on the
network B.
GOOSE alarm signal indicating that there is an error in the GOOSE
configuration file

Between GOOSE control blocks received on network and GOOSE control


blocks defined in GOOSE.txt file are unmatched for Namexx.

These are GOOSE alarm reports. When any alarm message is issued, the LED ALARM is lit without
the device being blocked. After the abnormality is removed, the device will return to normal with the
LED ALARM being distinguished automatically.
4-8

PCS-902 Line Distance Relay


Date: 2013-09-07

4 Supervision
No.

Output Signal

Handling suggestion

GAlm_AStorm_SL

Please check the related switches

GAlm_BStorm_SL

Please check the related switches

GAlm_CfgFile_SL

Please check the GOOSE configuration file (i.e. GOOSE.txt)

Namexx.GAlm_ADisc_SL_xx

Please check the network

Namexx.GAlm_BDisc_SL_xx

Please check the network

Namexx.GAlm_Cfg_SL_xx

Please check the GOOSE configuration file and the network

Namexx is the name defined by the setting [Linkxx], xx=01, 02, 03, , 64

PCS-902 Line Distance Relay

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Date: 2013-09-07

4 Supervision

4-10

PCS-902 Line Distance Relay


Date: 2013-09-07

5 Management

5 Management
Table of Contents
5 Management ..................................................................................... 5-a
5.1 Measurement ................................................................................................... 5-1
5.1.1 Root-Mean-Square Values ................................................................................................. 5-1
5.1.2 Phase Angle ....................................................................................................................... 5-2
5.1.3 Primary Value ..................................................................................................................... 5-2

5.2 Recording ........................................................................................................ 5-4


5.2.1 Overview ............................................................................................................................ 5-4
5.2.2 Event Recording ................................................................................................................ 5-4
5.2.3 Disturbance Recording ...................................................................................................... 5-5
5.2.4 Present Recording ............................................................................................................. 5-6

PCS-902 Line Distance Relay

5-a
Date: 2013-09-07

5 Management

5-b

PCS-902 Line Distance Relay


Date: 2013-09-07

5 Management

5.1 Measurement
PCS-902 performs continuous measurement of the analogue input quantities. The current full
scale of relay is 40 times of rated current, and there is no effect to the performance of IED due to
overflowing of current full scale. The relay samples 24 points per cycle and calculates the RMS
value in each interval and updated the LCD display in every 0.5 second. The measurement data
can be displayed on the LCD of the relay front panel or on the local/remote PC via software tool.
Navigate the menu to view the sampling value through LCD screen.

5.1.1 Root-Mean-Square Values


Access path:
MainMenu Measurements Measurements1
Measurement1 is use to display measured values from protection calculation DSP (displayed in
secondary value)
MainMenu Measurements Measurements2
Measurement2 is used to display measured values from fault detector DSP (displayed in
secondary value)
No.

Symbol

Definition

Resolution

Unit

Ia

The secondary value of phase-A current

0.000

Ib

The secondary value of phase-B current

0.000

Ic

The secondary value of phase-C current

0.000

I1

The secondary value of positive-sequence current

0.000

I2

The secondary value of negative-sequence current

0.000

3I0

The secondary value of calculated residual current

0.000

3I0Adj

0.000

Ua

The secondary value of phase-A protection voltage

0.000

Ub

The secondary value of phase-B protection voltage

0.000

10

Uc

The secondary value of phase-C protection voltage

0.000

11

Uab

The secondary value of phase-AB protection voltage

0.000

12

Ubc

The secondary value of phase-BC protection voltage

0.000

13

Uca

The secondary value of phase-CA protection voltage

0.000

14

Usyn

The secondary value of synchronism voltage

0.000

15

U1

The secondary value of positive-sequence voltage

0.000

16

U2

The secondary value of negative-sequence voltage

0.000

17

3U0

The secondary value of calculated residual voltage

0.000

18

Frequency of protection voltage

0.000

Hz

The secondary value of residual current from parallel


line

PCS-902 Line Distance Relay

5-1
Date: 2013-09-07

5 Management
19

25.f_Syn

20

25.f_Diff

21

25.phi_Diff

22

25.U_Diff

Frequency of synchronism voltage


Frequency difference between protection voltage and
synchronism voltages
Phase angle difference between protection voltage and
synchronism voltages
Voltage difference between protection voltage and
synchronism voltages

0.000

Hz

0.000

Hz

0.000

5.1.2 Phase Angle


Access path:
MainMenu Measurements Measurements1
Measurement1 is use to display measured values from protection calculation DSP (displayed in
secondary value)
MainMenu Measurements Measurements2
Measurement2 is used to display measured values from fault detector DSP (displayed in
secondary value)
No.

Symbol

Ang (Ua-Ub)

Ang (Ub-Uc)

Ang (Uc-Ua)

Ang (Ua-Ia)

Ang (Ub-Ib)

Ang (Uc-Ic)

Ang (Ia-Ib)

Ang (Ib-Ic)

Ang (Ic-Ia)

Definition
Phase angle between phase-A voltage and
phase-B voltage
Phase angle between phase-B voltage and
phase-C voltage
Phase angle between phase-C voltage and
phase-A voltage
Phase angle between phase-A voltage and
phase-A current
Phase angle between phase-B voltage and
phase-B current
Phase angle between phase-C voltage and
phase-C current
Phase angle between phase-A current and
phase-B current
Phase angle between phase-B current and
phase-C current
Phase angle between phase-C current and
phase-A current

Resolution

Unit

Deg

Deg

Deg

Deg

Deg

Deg

Deg

Deg

Deg

5.1.3 Primary Value


Access path:

5-2

PCS-902 Line Distance Relay


Date: 2013-09-07

5 Management

MainMenu Measurements Measurements3


Measurement3 is used to display measured primary values and other calculated quantities
related to the measurement and control.
No.

Symbol

Definition

Resolution

Unit

Ia

The primary value of phase-A current

0.000

Ib

The primary value of phase-A current

0.000

Ic

The primary value of phase-A current

0.000

I1

The primary value of positive-sequence current

0.000

I2

The primary value of negative-sequence current

0.000

3I0

The primary value of calculated residual current

0.000

3I0Adj

The primary value of residual current from parallel line

0.000

Ua

The primary value of phase-A voltage

0.000

kV

Ub

The primary value of phase-B voltage

0.000

kV

10

Uc

The primary value of phase-C voltage

0.000

kV

11

Uab

The primary value of phase-AB voltage

0.000

kV

12

Ubc

The primary value of phase-BC voltage

0.000

kV

13

Uca

The primary value of phase-CA voltage

0.000

kV

14

U1

The primary value of positive-sequence voltage

0.000

kV

15

U2

The primary value of negative-sequence voltage

0.000

kV

16

3U0

The primary value of calculated residual voltage

0.000

kV

17

U_Syn

The primary value of synchronism voltage

0.000

kV

18

Frequency of protection voltage

0.000

Hz

19

f_Syn

Frequency of synchronism voltage

0.000

Hz

20

The primary value of active power

0.000

MW

21

The primary value of reactive power

0.000

MVar

22

The primary value of apparent power

0.000

MVA

23

Cos

The value of power factor

0.000

24

Pa

The primary value of phase-A active power

0.000

MW

25

Pb

The primary value of phase-B active power

0.000

MW

26

Pc

The primary value of phase-C active power

0.000

MW

27

Qa

The primary value of phase-A reactive power

0.000

MVar

28

Qb

The primary value of phase-B reactive power

0.000

MVar

29

Qc

The primary value of phase-C reactive power

0.000

MVar

30

Cosa

The value of phase-A power factor

0.000

31

Cosb

The value of phase-B power factor

0.000

32

Cosc

The value of phase-C power factor

0.000

PCS-902 Line Distance Relay

5-3
Date: 2013-09-07

5 Management
33

f_Diff

34

df/dt

35

phi_Diff

36

U_Diff

37

PHr+_Pri

38

The frequency difference between reference side and

0.000

Hz

0.000

Hz/s

0.00

Deg

0.000

kV

The primary positive active energy

0.000

MWh

PHr-_Pri

The primary negative active energy

0.000

MWh

39

QHr+_Pri

The primary positive reactive energy

0.000

MVAh

40

QHr-_Pri

The primary negative reactive energy

0.000

MVAh

incoming side for manual closing synchrocheck


The rate of frequency change between reference side and
incoming side for manual closing synchrocheck
Phase angle difference between reference side and incoming
side for manual closing synchrocheck
The primary value of voltage difference between reference
side and incoming side for manual closing synchrocheck.

5.2 Recording
5.2.1 Overview
PCS-902 provides the following recording functions:
1.

Event recording

2.

Disturbance recording

3.

Present recording

All the recording information except waveform can be viewed on local LCD or by printing.
Waveform could only be printed or extracted with PCS-Explorer software tool and a waveform
analysis software.

5.2.2 Event Recording


5.2.2.1 Overview
The device can store the latest 1024 disturbance records, 1024 binary events, 1024 supervision
events, 256 control logs and 1024 device logs. All the records are stored in non-volatile memory,
and when the available space is exhausted, the oldest record is automatically overwritten by the
latest one.
5.2.2.2 Disturbance Records
When any protection element operates or drops off, such as fault detector, distance protection etc.,
they will be logged in event records.
5.2.2.3 Supervision Events
The device is under automatic supervision all the time. If there are any failure or abnormal
condition detected, such as, chip damaged, VT circuit failure and so on, it will be logged in event
records.

5-4

PCS-902 Line Distance Relay


Date: 2013-09-07

5 Management

5.2.2.4 Binary Events


When there is a binary input is energized or de-energized, i.e., its state has changed from 0 to 1
or from 1 to 0, it will be logged in event records.
5.2.2.5 Control Logs
When the total number of control command records reaches 256, Control_Logs memory area
will be full. If the device receives a new control command now, the oldest control command record
will be deleted, and then the latest control command record will be stored and displayed.
5.2.2.6 Device Logs
If an operator implements some operations on the device, such as reboot protective device,
modify setting, etc., they will be logged in event records.

5.2.3 Disturbance Recording


5.2.3.1 Application
Disturbance records can be used to have a better understanding of the behavior of the power
network and related primary and secondary equipment during and after a disturbance. Analysis of
the recorded data provides valuable information that can be used to improve existing equipment.
This information can also be used when planning for and designing new installations.
5.2.3.2 Design
A disturbance record consists of fault record and fault waveform. The disturbance record can be
initiated by fault detector element, tripping element, reclosing element or configurable signal
[BI_TrigDFR].
5.2.3.3 Capacity and Information of Disturbance Records
The device can store up to 32 disturbance records with waveform in non-volatile memory. It is
based on first in first out queue that the oldest disturbance record will be overwritten by the latest
one.
For each disturbance record, the following items are included:
1.

Sequence number

Each operation will be recorded with a sequence number in the record and displayed on LCD
screen.
2.

Date and time of fault occurrence

The time resolution is 1ms using the relay internal clock synchronized via clock synchronized
device if connected. The date and time is recorded when a system fault is detected.
3.

Relative operating time

An operating time (not including the operating time of output relays) is recorded in the record.
4.

Faulty phase

PCS-902 Line Distance Relay

5-5
Date: 2013-09-07

5 Management

5.

Fault location

To get accurate result of fault location, the following settings shall be set correctly:
1)

Positive-sequence line reactance [X1L]

2)

Positive-sequence line resistance [R1L]

3)

Zero-sequence line reactance [X0L]

4)

Zero-sequence line resistance [R0L]

5)

Zero-sequence line mutual reactance [X0M]

6)

Zero-sequence line mutual resistance [R0M]

7)

Line positive-sequence sensitive angle [phi1_Reach]

8)

Line zero-sequence sensitive angle [ph0_Reach]

9)

Line length in km [LineLength]

6.

Protection elements

5.2.3.4 Capacity and Information of Fault Waveform


MON module can store 32 pieces of fault waveform oscillogram in non-volatile memory. If a new
fault occurs when 32 fault waveform have been stored, the oldest will be overwritten by the latest
one.
Each fault record consists of all analog and digital quantities related to protection, such as original
current and voltage, differential current, alarm elements, and binary inputs and etc.
Each time recording includes 12-cycle pre-fault waveform, and 250 cycles at least and 500 cycles
at most can be recorded. Each cycle waveform is high-frequency recording at a rate of 1200Hz (24
poingts per cycle).

5.2.4 Present Recording


Present recording is a waveform triggered manually on on the devices LCD or remotely through
PCS-Explorer software. Recording content of present recording is same to that of disturbance
recording.
Each time recording includes 12-cycle waveform before triggering, and 250 cycles at most can be
recorded. Each cycle waveform is high-frequency recording at a rate of 1200Hz (24 poingts per
cycle).

5-6

PCS-902 Line Distance Relay


Date: 2013-09-07

6 Hardware

6 Hardware
Table of Contents
6 Hardware .......................................................................................... 6-a
6.1 Overview .......................................................................................................... 6-1
6.2 Typical Wiring .................................................................................................. 6-4
6.2.1 Conventional CT/VT (For reference only) .......................................................................... 6-4
6.2.2 ECT/EVT (For reference only) ........................................................................................... 6-6
6.2.3 CT Requirement ................................................................................................................. 6-8

6.3 Plug-in Module Description ............................................................................ 6-9


6.3.1 PWR Plug-in Module (Power Supply) ................................................................................ 6-9
6.3.2 MON Plug-in Module (Monitor) ........................................................................................ 6-11
6.3.3 AI Plug-in Module (Analog Input) ..................................................................................... 6-13
6.3.4 DSP Plug-in Module (Logic Process) ............................................................................... 6-23
6.3.5 NET-DSP Plug-in Module (GOOSE and SV) ................................................................... 6-24
6.3.6 CH Plug-in Module (Fibre Optical Channel Interface) ...................................................... 6-25
6.3.7 BI Plug-in Module (Binary Input) ...................................................................................... 6-26
6.3.8 BO Plug-in Module (Binary Output) .................................................................................. 6-31
6.3.9 HMI Module...................................................................................................................... 6-34

List of Figures
Figure 6.1-1 Rear view of fixed module position ....................................................................6-1
Figure 6.1-2 Hardware diagram ................................................................................................6-2
Figure 6.1-3 Front view of PCS-902 ..........................................................................................6-3
Figure 6.1-4 Typical rear view of PCS-902 ...............................................................................6-4
Figure 6.2-1 Typical wiring of PCS-902 (conventional CT/VT) ...............................................6-5
Figure 6.2-2 Typical wiring of PCS-902 (ECT/EVT) .................................................................6-7
Figure 6.3-1 View of PWR plug-in module .............................................................................6-10
Figure 6.3-2 Output contacts of PWR plug-in module ..........................................................6-10
PCS-902 Line Distance Relay

6-a
Date: 2013-09-07

6 Hardware

Figure 6.3-3 View of MON plug-in module .............................................................................6-12


Figure 6.3-4 Connection of communication terminal ...........................................................6-13
Figure 6.3-5 Schematic diagram of CT circuit automatically closed .......................................6-14
Figure 6.3-6 Current connection of AI plug-in module .........................................................6-15
Figure 6.3-7 Voltage connection 1 of AI plug-in module ......................................................6-16
Figure 6.3-8 Voltage connection 2 of AI plug-in module ......................................................6-16
Figure 6.3-9 View of AI plug-in module for one CT group input ..........................................6-17
Figure 6.3-10 Current connection of AI plug-in module .......................................................6-18
Figure 6.3-11 Voltage connection of AI plug-in module........................................................6-19
Figure 6.3-12 View of AI plug-in module for two CT group input ........................................6-19
Figure 6.3-13 Current connection of AI plug-in module .......................................................6-21
Figure 6.3-14 Voltage connection of AI plug-in module .......................................................6-21
Figure 6.3-15 View of AI plug-in module for two CT group input ........................................6-22
Figure 6.3-16 View of DSP plug-in module ............................................................................6-23
Figure 6.3-17 View of NET-DSP plug-in module ....................................................................6-24
Figure 6.3-18 View of CH plug-in module ..............................................................................6-25
Figure 6.3-19 Debouncing technique .....................................................................................6-26
Figure 6.3-20 View of BI plug-in module (NR1503) ...............................................................6-27
Figure 6.3-21 View of BI plug-in module (NR1504) ...............................................................6-28
Figure 6.3-22 View of BO plug-in module (NR1521A) ...........................................................6-31
Figure 6.3-23 View of BO plug-in module (NR1521C) ...........................................................6-32
Figure 6.3-24 View of BO plug-in module (NR1521F) ...........................................................6-33
Figure 6.3-25 View of BO plug-in module (NR1521G) ...........................................................6-34

List of Tables
Table 6.3-1 Terminal definition and description of PWR plug-in module ............................6-10
Table 6.3-2 Terminal definition of AI module .........................................................................6-17
Table 6.3-3 Terminal definition of AI module .........................................................................6-20
Table 6.3-4 Terminal definition of AI module .........................................................................6-22

6-b

PCS-902 Line Distance Relay


Date: 2013-09-07

6 Hardware

6.1 Overview
PCS-902 adopts 32-bit microchip processor CPU produced by FREESCALE as control core for
management and monitoring function, meanwhile, adopts high-speed digital signal processor DSP
for all the protection calculation. 24 points are sampled in every cycle and parallel processing of
sampled data can be realized in each sampling interval to ensure ultrahigh reliability and safety of
the device.

12

13

PWR module

11

BO module

09

BO module

08

BO module

06

BO module

DSP module

05

BI module

CH Module

04

BI module

DSP module

AI module

MON module

PCS-902 is comprised of intelligent plug-in modules, except that few particular plug-in modules
position cannot be changed in the whole device (gray plug-in modules as shown in Figure 6.1-1),
other plug-in modules like AI (analog input) and IO (binary input and binary output) can be flexibly
configured in the remaining slot positions.

15

P1

Slot No.
01

02

03

07

10

14

Figure 6.1-1 Rear view of fixed module position

PCS-902 has 16 slots, PWR plug-in module, MON plug-in module, DSP plug-in module and CH
plug-in module are assigned at fixed slots.
Besides 5 fixed modules are shown in above figure, there are 12 slots can be flexibly configured.
AI plug-in module, BI plug-in module and BO plug-in module can be configured at position
between slot 02, 03 and 06~15. It should be pay attention that AI plug-in module will occupy two
slots.
This device is developed on the basis of our latest software and hardware platform, and the new
platform major characteristics are of high reliability, networking and great capability in
anti-interference. See Figure 6.1-2 for hardware diagram.

PCS-902 Line Distance Relay

6-1
Date: 2013-09-07

A/D

Protection
Calculation
DSP

A/D

Fault
Detector
DSP

Output Relay

Conventional CT/VT

External
Binary Input

6 Hardware

ECVT
Pickup
Relay

ECVT
ETHERNET
LCD
Power
Supply

Uaux

+E
Clock SYN

LED

CPU
RJ45

Keypad
PRINT

Figure 6.1-2 Hardware diagram

The working process of the device is as shown in above figure: current and voltage from
conventional CT/VT are converted into small voltage signal and sent to DSP module after filtered
and A/D conversion for protection calculation and fault detector respectively (ECVT signal is sent
to the device without small signal and A/D convertion). When DSP module completes all the
protection calculation, the result will be recorded in 32-bit CPU on MON module. DSP module
carries out fault detector, protection logic calculation, tripping output, and MON module perfomes
SOE (sequence of event) record, waveform recording, printing, communication between the
device and SAS and communication between HMI and CPU. When fault detector detects a fault
and picks up, positive power supply for output relay is provided.
The items can be flexibly configured depending on the situations like sampling method of the
device (conventional CT/VT or ECT/EVT), and the mode of binary output (conventional binary
output or GOOSE binary output). The configurations for PCS-900 series based on microcomputer
are classified into standard and optional modules.
Table 6.1-1 PCS-902 module configuration
No.

ID

Module description

NR1101/NR1102

Management and monitor module (MON module)

standard

NR1401

Analog input module (AI module )

standard

NR1161

Protection calculation and fault detector module (DSP module)

standard

NR1213

Protection communication channel module (CH module)

option

NR1503/NR1504

Binary input module (BI module)

standard

NR1521

Binary output module (BO module)

standard

NR1301

Power supply module (PWR module)

standard

6-2

Remark

PCS-902 Line Distance Relay


Date: 2013-09-07

6 Hardware
No.

ID
NR1136

Module description

Remark

GOOSE and SV from merging unit by IEC61850-9-2 (NET-DSP


module)
Human machine interface module (HMI module)

option
standard

MON module provides functions like communication with SAS, event record, setting
management etc.

AI module converts AC current and voltage from current transformers and voltage
transformers respectively to small voltage signal.

DSP module performs filtering, sampling, protection calculation and fault detector calculation.

CH module performs information exchange with the remote device through a dedicated
optical fibre channel, multiplex optical fibre channel or PLC channel.

BI module provides binary inputs via opto-couplers with rating voltage among
24V/110V/125V/220V/250V (configurable).

BO module provides output contacts for tripping, and signal output contact for annunciation
signal, remote signal, fault and disturbance signal, operation abnormal signal etc.

PWR module converts DC 250/220/125/110V into various DC voltage levels for modules of
the device.

HMI module is comprised of LCD, keypad, LED indicators and multiplex RJ45 ports for user
as human-machine interface.

NET-DSP module receives and sends GOOSE messages, sampled values (SV) from
merging unit by IEC61850-9-2 protocol.

PCS-902 series is made of a 4U height 19 chassis for flush mounting. Components mounted on
its front include a 320240 dot matrix LCD, a 9 button keypad, 20 LED indicators and a multiplex
RJ45 port. A monolithic micro controller is installed in the equipment for these functions.
Following figures show front and rear views of PCS-902 respectively.

ALARM

11

PCS-902

12
13

14

15

16

17

18

19

10

20

GRP

HEALTHY

ESC

1
2

ENT

Figure 6.1-3 Front view of PCS-902

PCS-902 Line Distance Relay

6-3
Date: 2013-09-07

6 Hardware

20 LED indicators are, from top to bottom, operation (HEALTHY), self-supervision (ALARM),
others are configurable.
For the 9-button keypad, ENT is enter, GRP is group number and ESC is escape.

NR1102

NR1401

NR1161

NR1161

NR1213

NR1504

NR1504

NR1521

NR1521

NR1521

NR1521

NR1301
5V OK

ALM

TX
BO_ALM BO_FAIL

RX
ON
TX
OFF
RX

DANGER
1 BO_COM1
2

BO_FAIL

BO_ALM

BO_COM2

BO_FAIL

BO_ALM

OPTO+

OPTO-

9
10

PWR+

11

PWR-

12

GND

Figure 6.1-4 Typical rear view of PCS-902

6.2 Typical Wiring


6.2.1 Conventional CT/VT (For reference only)

12

13

PWR module

11

NR1521F NR1301

BO module

BO module

06

BO module

05

NR1521A NR1521C NR1521C

BO module

04

NR1504

BI module

NR1161

DSP module

NR1213

CH Module

AI module

NR1161

DSP module

NR1401

MON module

NR1102

15

P1

Slot No.
01

02

03

07

08

09

10

14

The following typical wiring is given based on above hardware configuration

6-4

PCS-902 Line Distance Relay


Date: 2013-09-07

6 Hardware

Power supply supervision

0801

CH-TX

CH-RX

BI_01

or
CH-TX
CH-RX

Fibre Optic

FC/PC Type (Rear)


0201
Ia

0203
Ib

0204
0205
To parallel line

Ic

0206
0207

From parallel line

IM0

0208

0215
Ub

0216
0217

0221
UL2

0222
0223

Power supply for


opto-coupler (24V)

P110

PWR-

P111

OPTO+

P107

OPTO-

P108

BO_ALM

P101

COM

P105

BO_FAIL

P106

BO_ALM

P104

COM

Not used

0815

0816

0821
0822

1101
BO_01

1102
1103

BO_02

1104

BO_11

1121
1122

1201
BO_01

1202
1203

BO_02

1204

BO_11

1221
1222

1301
BO_01

1302
1303

BO_02

1304

BO_FAIL

P103

0814

Power
Supply

P102

BI_13

Signal Binary Output


(option)

PWR+

0809

External DC power
supply

BI_12

Signal Binary Output

UB2

0224

0808

UB1

0220

Not used

BI_18

Synchronism Voltage

0219

0807

BI_07

Controlled by fault
detector element

Uc

0218

BI_06

Ua

0214

Protection Voltage

0213

0802

0202

*BI plug-in module can be independent common terminal

Dedicated Channel
Or
Telecom Equipment

BO_11

1321
1322

1501
B

0102

SGND

0103

BO_CtrlOpn1

0104
0101

SYN-

0102

SGND

0103
0104

Clock SYN

SYN+

1502
1503

BO_CtrlCls1

1504

Signal Binary Output (option)

0101
COM

To the screen of other coaxial


cable with single point earthing

1517
BO_CtrlOpn5

1518
1519

BO_CtrlCls5

1520
1521

0105

TXD

0106

SGND

0107

PRINT

PRINTER

RTS

BO_Ctrl
Multiplex
RJ45 (Front)

1522
P112
0225
Grounding
Bus

Figure 6.2-1 Typical wiring of PCS-902 (conventional CT/VT)

PCS-902 Line Distance Relay

6-5
Date: 2013-09-07

6 Hardware
PCS-902 (conventional CT/VT and conventional binary input and binary output)

Slot No.

01

04

05

08

09

11

12

13

15

P1

Module ID

NR1102

02

NR1401

03

NR1161

NR1213

06

07

NR1504

NR1504

10

NR1521

NR1521

NR1521

14

NR1521

NR1301

MON

AI

DSP

CH

BI

BI

BO

BO

BO

BO

PWR

08

09

11

12

13

PCS-902 (conventional CT/VT and GOOSE binary input and binary output)

Slot No.

01

04

05

06

Module ID

NR1102

02

NR1401

03

NR1161

NR1213

NR1136

07

NR1504

10

14

15

NR1301

P1

MON

AI

DSP

CH

NETDSP

BI

PWR

6.2.2 ECT/EVT (For reference only)

06

07

08

11

12

NR1301

PWR module

05

BO module

04

NR1521A NR1521C

BO module

BI module

NR1503

NET-DSP Module

NR1136

DSP module

NR1161

CH Module

NR1213

DSP module

NR1161

MON module

NR1102

Slot No.
01

02

03

09

10

13

14

15

P1

The following typical wiring is given based on above hardware configuration

6-6

PCS-902 Line Distance Relay


Date: 2013-09-07

6 Hardware

CH-RX

Dedicated Channel
Or
Telecom Equipment

or
CH-TX
CH-RX

Fibre Optic

MU

Phase B

RX

TX

P111

OPTO+

P107

OPTO-

P108

Power
Supply

BO_FAIL

P103

BO_ALM

P101

COM

P105

BO_FAIL

P106

BO_ALM

P104

COM

0102

SGND

0103
0104
0101

SYN-

0102

SGND

0103
0104
0105

TXD

0106

SGND

0107

0804

0805

0806

0821

0822

1101
1102
1103
BO_02

1104

BO_11

1121
1122

1201
BO_01

1202
1203

BO_02

1204

BO_11

1221
1222

1502
1503

BO_CtrlCls1

1504

1517
BO_CtrlOpn5

1518
1519

BO_CtrlCls5

1520
1521

BO_Ctrl

1522
IRIG-B

PRINT

PRINTER

RTS

BO_01

Clock SYN

SYN+

0803

0101

1501

COM

To the screen of other coaxial


cable with single point earthing

0802

BO_CtrlOpn1

Signal Binary Output (option)

P102

PWR-

0801

Power supply for


opto-coupler (24V)

P110

BI_11

Signal Binary Output

External DC power
supply

PWR+

BI_03

Controlled by fault
detector element

Phase C

BI_02

Phase A

FC/PC Type (Rear)

FO interface for SV channel


Up to 8
(LC Type)

SV from
ECT/EVT

BI_01

*BI plug-in module can be common negative


terminal

CH-TX

P112
Multiplex
RJ45 (Front)

0225

Grounding
Bus

Figure 6.2-2 Typical wiring of PCS-902 (ECT/EVT)

PCS-902 ECT/EVT, GOOSE binary input and binary output

Slot No.

01

04

05

06

Module ID

NR1102

02

03

NR1161

NR1213

NR1136

07

NR1504

08

09

10

11

12

13

14

15

NR1301

P1

MON

DSP

CH

NETDSP

BI

PWR

PCS-902 ECT/EVT, conventional binary input and binary output

Slot No.

01

Module ID

02

03

04

05

06

NR1102

NR1161

NR1213

MON

DSP

CH

07

08

09

NR1136

NR1504

NETDSP

BI

11

12

13

NR1504

NR1521

NR1521

BI

BO

BO

PCS-902 Line Distance Relay

10

14

15

P1

NR1521

NR1521

NR1301

BO

BO

PWR

6-7
Date: 2013-09-07

6 Hardware

In the protection system adopting electronic current and voltage transformer (ECT/EVT), the
merging unit will merge the sample data from ECT/EVT, and then send it to the device through
multi-mode optical fibre. DSP module receives the data from merging unit through the optical-fibre
interface to complete the protection calculation and fault detector.
The difference between the hardware platform based on ECT/EVT and the hardware platform
based on conventional CT/VT lies in the receiving module of sampled values only, and the device
receives the sampled value from merging unit through multi-mode optical fibre.

6.2.3 CT Requirement
-Rated primary current Ipn:
According to the rated current or maximum load current of primary apparatus.
-Rated continuous thermal current Icth:
According to the maximum load current.
-Rated short-time thermal current Ith and rated dynamic current Idyn:
According to the maximum fault current.
-Rated secondary current Isn
-Accuracy limit factor Kalf:
Ipn

Rated primary current (amps)

Icth

Rated continuous thermal current (amps)

Ith

Rated short-time thermal current (amps)

Idyn

Rated dynamic current (amps)

Isn

Rated secondary current (amps)

Kalf

Accuracy limit factor ()Kalf=Ipal/Ipn

IPal

Rated accuracy limit primary current (amps)

Performance verification
Esl > Esl
Esl

Rated secondary limiting e.m.f (volts)


Esl = kalfIsn(Rct+Rbn)

Kalf

Accuracy limit factor (Kalf=Ipal/Ipn)

IPal

Rated accuracy limit primary current (amps)

Ipn

Rated primary current (amps)

Isn

Rated secondary current (amps)

Rct

Current transformer secondary winding resistance. (ohms)

Rbn

Rated resistance burden (ohms)


Rbn=Sbn/Isn2

Sbn

Rated burden (VAs)

Esl

Required secondary limiting e.m.f (volts)

6-8

PCS-902 Line Distance Relay


Date: 2013-09-07

6 Hardware
Esl = kIpcf Isn(Rct+Rb)/Ipn
k
Ipcf

stability factor = 2
Protective checking factor current (amps)
Same as the maximum prospective fault current

Isn

Rated secondary current (amps)

Rct

Current transformer secondary winding resistance. (ohms)

Rb

Real resistance burden (ohms)


Rb=Rr+2RL+Rc

Rc

Contact resistance, 0.05-0.1 ohm (ohms)

RL

Resistance of a single lead from relay to current transformer (ohms)

Rr

Impedance of relay phase current input (ohms)

Ipn

Rated primary current (amps)

For example:
1.

Kalf=30, Isn=5A, Rct=1ohm, Sbn=60VA

Esl = kalfIsn(Rct+Rbn) = kalfIsn(Rct+ Sbn/ Isn2)


= 305(1+60/25)=510V
2.

Ipcf=40000A, RL=0.5ohm, Rr=0.1ohm, Rc=0.1ohm, Ipn=2000A

Esl = 2IpcfIsn(Rct+Rb)/Ipn
= 2Ipcf Isn(Rct+(Rr+2RL+Rc))/Ipn
= 2400005(1+(0.1+20.5+0.1))/2000=440V
Thus, Esl > Esl

6.3 Plug-in Module Description


The device consists of PWR plug-in module, MON plug-in module, DSP plug-in module, AI plug-in
module, BI plug-in module, BO plug-in module, CH plug-in module and NET-DSP plug-in module.
Terminal definitions and application of each plug-in module are introduced as follows.

6.3.1 PWR Plug-in Module (Power Supply)


PWR module is a DC/DC converter with electrical insulation between input and output. It has an
input voltage range as described in Chapter 2 Technical Data. The standardized output voltages
are +5V and +24V DC. The tolerances of the output voltages are continuously monitored.
The +5V DC output provides power supply for all the electrical elements that need +5V DC power
supply in this device.
The use of an external miniature circuit breaker is recommended. The miniature circuit breaker
must be in the on position when the device is in operation and in the off position when the device is
in cold reserve.
A 12-pin connector is fixed on PWR module. The terminal definition of the connector is described

PCS-902 Line Distance Relay

6-9
Date: 2013-09-07

6 Hardware

as below.

NR1301
5V OK

ALM

BO_ALM BO_FAIL

ON
OFF

BO_COM1

BO_FAIL

BO_ALM

BO_COM2

BO_FAIL

BO_ALM

OPTO+

OPTO-

9
10 PWR+
11 PWR12 GND

Figure 6.3-1 View of PWR plug-in module

The power switch in the dotted box of above figure maybe is not existed.
01
BO_FAIL
02
BO_ALM
03
04
BO_FAIL
05
BO_ALM
06

Figure 6.3-2 Output contacts of PWR plug-in module

Terminal definition and description is shown as follows:


Table 6.3-1 Terminal definition and description of PWR plug-in module
Terminal No.

Symbol

Description

01

BO_COM1

Common terminal 1

02

BO_FAIL

Device failure output 1 (01-02, NC)

03

BO_ALM

Device abnormality alarm output 1 (01-03, NO)

04

BO_COM2

Common terminal 2

05

BO_FAIL

Device failure output 2 (04-05, NC)

6-10

PCS-902 Line Distance Relay


Date: 2013-09-07

6 Hardware
Terminal No.

Symbol

Description

06

BO_ALM

Device abnormality alarm output 2 (04-06, NO)

07

OPTO+

Positive power supply for BI module (24V)

08

OPTO-

Negative power supply for BI module (24V)

09

Blank

Not used

10

PWR+

Positive input of power supply for the device (250V/220V/125V/110V)

11

PWR-

Negative input of power supply for the device (250V/220V/125V/110V)

12

GND

Grounded connection of the power supply

Note!

The standard rated voltage of PWR module is self-adaptive to 88~300 Vdc. If input voltage
is out of range, an alarm signal (Fail_Device) will be issued. For non-standard rated
voltage power supply module please specify when place order, and check if the rated
voltage of power supply module is the same as the voltage of power source before the
device being put into service.
PWR module provides terminal 12 and grounding screw for device grounding. Terminal 12
shall be connected to grounding screw and then connected to the earth copper bar of
panel via dedicated grounding wire.
Effective grounding is the most important measure for a device to prevent EMI, so effective
grounding must be ensured before the device is put into service.
PCS-902, like almost all electronic relays, contains electrolytic capacitors. These
capacitors are well known to be subject to deterioration over time if voltage is not applied
periodically. Deterioration can be avoided by powering the relays up once a year.

6.3.2 MON Plug-in Module (Monitor)


MON module consists of high-performance built-in processor, FLASH, SRAM, SDRAM, Ethernet
controller and other peripherals. Its functions include management of the complete device, human
machine interface, communication and waveform recording etc.
MON module uses the internal bus to receive the data from other modules of the device. It
communicates with the LCD module by RS-485 bus. This module comprises 100BaseT Ethernet
interfaces, RS-485 communication interfaces that exchange information with above system by
using IEC 61850, PPS/IRIG-B differential time synchronization interface and RS-232 printing
interface.
Modules with various combinations of memory and interface are available as shown in the table
below.

PCS-902 Line Distance Relay

6-11
Date: 2013-09-07

6 Hardware

NR1102D

NR1102I

NR1101E

TX
ETHERNET

ETHERNET

RX
TX
RX
ETHERNET

Figure 6.3-3 View of MON plug-in module


Module ID

Memory

Interface

Terminal No.

4 RJ45 Ethernet

RS-485
NR1102D

128M DDR

128M DDR

Physical Layer

To SCADA
01

SYN+

02

SYN-

To

03

SGND

synchronization

clock

Twisted pair wire

04

RS-232

NR1102I

Usage

05

RTS

06

TXD

07

SGND

To printer

Cable

2 RJ45 Ethernet

To SCADA

Twisted pair wire

2 FO Ethernet

To SCADA

Optical fibre ST

RS-485

01

SYN+

02

SYN-

To

03

SGND

synchronization

clock

Twisted pair wire

04

RS-232

05

RTS

06

TXD

07

SGND

2 RJ45 Ethernet
NR1101E

128M DDR

RS-485

To printer

Cable

To SCADA
01

02

03

SGND

6-12

To SCADA

Twisted pair wire

PCS-902 Line Distance Relay


Date: 2013-09-07

6 Hardware
04

RS-485

05

06

07

SGND

To SCADA

08

RS-485

09

SYN+

10

SYN-

To

SGND

synchronization

11

clock

12

RS-232

13

RTS

14

TXD

15

SGND

To printer

Cable

16

The correct connection is shown in Figure 6.3-4. Generally, the shielded cable with two pairs of
twisted pairs inside shall be applied. One pair of the twisted pairs are respectively used to connect
the + and terminals of difference signal. The other pair of twisted pairs are used to connect
the signal ground of the communication interface. The module reserves a free terminal for all the
communication ports. The free terminal has no connection with any signal of the device, and it is
used to connect the external shields of the cable when connecting multiple devices in series. The
external shield of the cable shall be grounded at one of the ends only.
Twisted pair wire
01

02

SGND

03

COM

Twisted pair wire


SYN+

01

SYN-

02

SGND

03

Clock SYN

To the screen of other coaxial


cable with single point earthing

04

04

Cable
05

TXD

06

SGND

07

PRINT

RTS

Figure 6.3-4 Connection of communication terminal

6.3.3 AI Plug-in Module (Analog Input)


AI module is applicable for power plant or substation with conventional VT and CT. It is assigned to
slot numbers 02 and 03. However, the module is not required if the device is used with ECT/EVT.
For AI module, if the plug is not put in the socket, external CT circuit is closed itself. Just shown as
below.

PCS-902 Line Distance Relay

6-13
Date: 2013-09-07

6 Hardware

Socket

Plug

In

Out

plug is not put in the socket

In

Out

Put the plug in the socket

Figure 6.3-5 Schematic diagram of CT circuit automatically closed

There are two types of AI module with rating 5 A or 1 A. Please declare which kind of AI module is
needed before ordering. Maximum linear range of the current converter is 40In.
1.

One CT group input without synchronism voltage switchover

For one CT group input, three phase currents (Ia, Ib and Ic) and residual current from parallel line
(for mutual compensation) are input to AI module separately. Terminal 01, 03, 05 and 07 are
polarity marks. It is assumed that polarity mark of CT installed on line is at line side.
Three phase voltages (Ua, Ub, and Uc) for protection calculation and one synchronism voltage are
input to AI module. The synchronism voltage could be any phase-to-ground voltage or
phase-to-phase voltage.
If the auto-reclosing is enabled but synchronism check is not required, the synchronism voltage
should be disconnected.

6-14

PCS-902 Line Distance Relay


Date: 2013-09-07

6 Hardware
A
B
C

P2

S2

P2

S2

P1

S1

P1

S1

02

01

02

01

04

03

04

03

06

05

06

05

08

07

08

07

Figure 6.3-6 Current connection of AI plug-in module

In order to accurately locate the fault for parallel lines arrangement, residual current from parallel
line is required to be connected to the device to eliminate the mutual effect between the parallel
lines. Otherwise, residual current from parallel line is not necessary.
Relevant description about parallel line to refer to section Fault Location.

PCS-902 Line Distance Relay

6-15
Date: 2013-09-07

6 Hardware
A
B
C

13

14

15

16

17

18

19

20

Figure 6.3-7 Voltage connection 1 of AI plug-in module


A
B
C

13

14

15

16

17

18

19

20

Figure 6.3-8 Voltage connection 2 of AI plug-in module

6-16

PCS-902 Line Distance Relay


Date: 2013-09-07

6 Hardware
Ia

01

Ian

02

Ib

03

Ibn

04

Ic

05

Icn

06

IM0

07

IM0n

08

NR1401

09

10

11

12

Ua

13

Uan

14

Ub

15

Ubn

16

Uc

17

Ucn

18

Us

19

Usn

20

21

22

23

24

Figure 6.3-9 View of AI plug-in module for one CT group input

Table 6.3-2 lists the terminal number and definition of AI module.


Table 6.3-2 Terminal definition of AI module
Terminal No.

Definition

Definition

01

Ia

The current of A-phase (Polarity mark)

02

Ian

The current of A-phase

03

Ib

The current of B-phase (Polarity mark)

04

Ibn

The current of B-phase

05

Ic

The current of C-phase (Polarity mark)

06

Icn

The current of C-phase

07

IM0

Residual current of parallel line (Polarity mark)

08

IM0n

Residual current of parallel line

09

Reserve

10

Reserve

11

Reserve

12

Reserve

13

Ua

The voltage of A-phase (Polarity mark)

14

Uan

The voltage of A-phase

15

Ub

The voltage of B-phase (Polarity mark)

16

Ubn

The voltage of B-phase

17

Uc

The voltage of C-phase (Polarity mark)

18

Ucn

The voltage of C-phase

19

Us

Synchronism voltage (Polarity mark)

PCS-902 Line Distance Relay

6-17
Date: 2013-09-07

6 Hardware
Terminal No.

2.

Definition

20

Usn

21

Reserve

22

Reserve

23

Reserve

24

Reserve

25

GND

Definition
Synchronism voltage

Ground

Two CT groups input with synchronism voltage switchover

For two circuit breakers configuration with two CT groups input, three phase currents
corresponding to CB1 and CB2 respectively (Ia1, Ib1, Ic1 and Ia2, Ib2, Ic2) are input to AI module.
Terminal 01, 03, 05, 07, 09 and 11 are polarity marks. It is assumed that polarity mark of CT
installed on line is at line side.
Three phase voltages (Ua, Ub, and Uc) are input to AI module. UB1, UB2 and UL2 are the
synchronism voltage from bus VT and line VT used for synchrocheck, it could be any
phase-to-ground voltage or phase-to-phase voltage. The device can automatically switch
synchronism voltage according to auxiliary contact of CB position or DS position.
If the auto-reclosing is enabled but synchronism check is not required, the synchronism voltage
should be disconnected.
P2

P1

P1

P2

S1

S2

A
B

S2

S1

02

01

04

03

06

05

08

07

10

09

12

11

Figure 6.3-10 Current connection of AI plug-in module

6-18

PCS-902 Line Distance Relay


Date: 2013-09-07

6 Hardware
A

13

14

15

16

17

18

19

20

21

22

23

24

Figure 6.3-11 Voltage connection of AI plug-in module

Ia1

01

Ia1n

02

Ib1

03

Ib1n

04

Ic1

05

Ic1n

06

Ia2

07

Ia2n

08

Ib2

09

Ib2n

10

Ic2

11

Ic2n

12

Ua

13

Uan

14

Ub

15

Ubn

16

Uc

17

Ucn

18

UB1

19

UB1n

20

UL2

21

UL2n

22

UB2

23

UB2n

24

NR1401

Figure 6.3-12 View of AI plug-in module for two CT group input

PCS-902 Line Distance Relay

6-19
Date: 2013-09-07

6 Hardware

Table 6.3-3 lists the terminal number and definition of AI module.


Table 6.3-3 Terminal definition of AI module
Terminal No.

3.

Definition

Definition

01

Ia1

The current of A-phase (Polarity mark)

02

Ia1n

The current of A-phase

03

Ib1

The current of B-phase (Polarity mark)

04

Ib1n

The current of B-phase

05

Ic1

The current of C-phase (Polarity mark)

06

Ic1n

The current of C-phase

07

Ia2

The current of A-phase (Polarity mark)

08

Ia2n

The current of A-phase

09

Ib2

The current of B-phase (Polarity mark)

10

Ib2n

The current of B-phase

11

Ic2

The current of C-phase (Polarity mark)

12

Ic2n

The current of C-phase

13

Ua

The voltage of A-phase (Polarity mark)

14

Uan

The voltage of A-phase

15

Ub

The voltage of B-phase (Polarity mark)

16

Ubn

The voltage of B-phase

17

Uc

The voltage of C-phase (Polarity mark)

18

Ucn

The voltage of C-phase

19

UB1

The voltage of bus 1 (Polarity mark)

20

UB1n

The voltage of bus 1

21

UL2

The voltage of line 2 (Polarity mark)

22

UL2n

The voltage of line 2

23

UB2

The voltage of bus 2 (Polarity mark)

24

UB2n

The voltage of bus 2

25

GND

Ground

Two CT groups input without synchronism voltage switchover

For two circuit breakers configuration with two CT groups input, three phase currents
corresponding to CB1 and CB2 respectively (Ia1, Ib1, Ic1 and Ia2, Ib2, Ic2), and residual current
from parallel line (for mutual compensation) are input to AI module. Terminal 01, 03, 05, 07, 09, 11
and 13 are polarity marks. It is assumed that polarity mark of CT installed on line is at line side.
Three phase voltages (Ua, Ub, and Uc) for protection calculation and one synchronism voltage are
input to AI module. The synchronism voltage could be any phase-to-ground voltage or
phase-to-phase voltage.
If the auto-reclosing is enabled but synchronism check is not required, the synchronism voltage
should be disconnected.

6-20

PCS-902 Line Distance Relay


Date: 2013-09-07

6 Hardware
P2

P1

P1

P2

S1

S2

A
B

S2

S1

02

01

04

03

06

05

08

07

10

09

12

11

14

13

To parallel line
From parallel line

Figure 6.3-13 Current connection of AI plug-in module


A

15

16

17

18

19

20

21

22

23

24

Figure 6.3-14 Voltage connection of AI plug-in module

PCS-902 Line Distance Relay

6-21
Date: 2013-09-07

6 Hardware
Ia1

01

Ia1n

02

Ib1

03

Ib1n

04

Ic1

05

Ic1n

06

Ia2

07

Ia2n

08

Ib2

09

Ib2n

10

Ic2

11

Ic2n

12

IM0

13

IM0n

14

Ua

15

Uan

16

Ub

17

Ubn

18

Uc

19

Ucn

20

Us

21

Usn

22

NR1401

23

24

Figure 6.3-15 View of AI plug-in module for two CT group input

Table 6.3-4 lists the terminal number and definition of AI module.


Table 6.3-4 Terminal definition of AI module
Terminal No.

Definition

Definition

01

Ia1

The current of A-phase (Polarity mark)

02

Ia1n

The current of A-phase

03

Ib1

The current of B-phase (Polarity mark)

04

Ib1n

The current of B-phase

05

Ic1

The current of C-phase (Polarity mark)

06

Ic1n

The current of C-phase

07

Ia2

The current of A-phase (Polarity mark)

08

Ia2n

The current of A-phase

09

Ib2

The current of B-phase (Polarity mark)

10

Ib2n

The current of B-phase

11

Ic2

The current of C-phase (Polarity mark)

12

Ic2n

The current of C-phase

13

IM0

Residual current of parallel line (Polarity mark)

14

IM0n

Residual current of parallel line

15

Ua

The voltage of A-phase (Polarity mark)

16

Uan

The voltage of A-phase

17

Ub

The voltage of B-phase (Polarity mark)

18

Ubn

The voltage of B-phase

19

Uc

The voltage of C-phase (Polarity mark)

20

Ucn

The voltage of C-phase

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6 Hardware
Terminal No.

Definition

Definition

21

Us

Synchronism voltage (Polarity mark)

22

Usn

Synchronism voltage

23

Reserve

24

Reserve

25

GND

Ground

6.3.4 DSP Plug-in Module (Logic Process)

NR1161

Figure 6.3-16 View of DSP plug-in module

This device can be equipped with 2 DSP plug-in modules at most and 1 DSP plug-in module at
least. The default DSP plug-in module is necessary, which mainly is responsible for protection
function including fault detector and protection calculation.
The default module consists of high-performance double DSP (digital signal processor),16-digit
high-accuracy ADC that can perform synchronous sampling and manage other peripherals. One
of double DSP is responsible for protection calculation, and can fulfill analog data acquisition,
protection logic calculation and tripping output. The other is responsible for fault detector, and can
fulfill analog data acquisition, fault detector and providing power supply to output relay.
When the module is connected with conventional CT/VT, it can perform the synchronous data
acquisition through AI plug-in module. When the module is connected with ECT/EVT, it can
receive the real-time synchronous sampled value from merging unit through NET-DSP plug-in
module.
The other module is optional and it is not required unless control and manual closing with

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synchronism check are equppied with this device. The default DSP plug-in module is fixed at slot
04 and the option DSP plug-in module is fixed at slot 06.

6.3.5 NET-DSP Plug-in Module (GOOSE and SV)

NR1136A

NR1136C

RX

Figure 6.3-17 View of NET-DSP plug-in module

This module consists of high-performance DSP (digital signal processor), 2~8 100Mbit/s
optical-fibre interface (LC type) and selectable IRIG-B interface (ST type). It supports GOOSE and
SV by IEC 61850-9-2 protocols. It can receive and send GOOSE messages to intelligent control
device, and receive SV from MU (merging unit).
This module supports IEEE1588 network time protocol, E2E and P2P defined in IEEE1588
protocol can be selected. This module supports Ethernet IEEE802.3 time adjustment message
format, UDP time adjustment message format and GMRP.

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6 Hardware

6.3.6 CH Plug-in Module (Fibre Optical Channel Interface)

NR1213

NR1213

NR1213

NR1213

NR1214

TX

TX

TX

TX

RX

RX

RX

RX

TX

TX

RX

RX

NR1214

TX1

TX1

RX1

RX1

TX1

RX1

NR1213A

NR1213A-100

NR1213B

NR1213B-100

NR1214A

NR1214B

Figure 6.3-18 View of CH plug-in module


Type

Wavelength

Application

NR1213A

1310nm

Single-mode, single channel, transmission distance <40 km

NR1213A-100

1550nm

Single-mode, single channel, transmission distance <100 km

NR1213B

1310nm

Single-mode, dual channels, transmission distance <40 km

NR1213B-100

1550nm

Single-mode, dual channels, transmission distance <100 km

NR1214A

830nm

Multi-mode, single channel, transmission distance <2 km

NR1214B

830nm

Multi-mode, dual channels, transmission distance <2 km

PCS-902 series can exchange information with the device at the remote end through a dedicated
optical fibre channel or multiplex channel. The module transmits and receives optical signal using
FC/PC or ST optical connector.
The parameters are shown as follows:
Type1

Type2

Type3

Fiber Optic

Single mode, Rec.G652

Single mode, Rec.G652

Multi mode, Rec.G652

Wavelength

1310nm

1550nm

830nm

Transmission power

-13.03.0 dBm

-5.0 dBm3.0 dBm

-12dBm~-20 dBm

Receiving sensitivity

Min.-37 dBm

Min.-36 dBm

Min.-30 dBm

Transmission distance

Max.40 km

Max.100 km

Max.2 km

Optical overload point

Min.-3 dBm

Min.-3 dBm

Min.-8 dBm

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6 Hardware

Note!

When using dedicated optical fibre channel, if the transmission distance is longer than
50km, the transmitted power may be enchanced to ensure received power larger than
receiving sensitivity. Please notify supplier before ordering and it will be considered as
special project using 1550nm laser diode.
When using multiplex channel, the sending power of the device is fixed.
When using channel multiplexing equipment, the parameters are shown as follows:
1.

Channel type: digital optical fibre or digital microwave.

2.

Interface standard: 2048kbit/s E1

The devices requirements on the channel are shown as follows:


1.

The routine of both direction shall be same to each other, so the time delays of both direction
are the same.

2.

The maximum one-way channel propagation delay shall be less than 15 ms.

6.3.7 BI Plug-in Module (Binary Input)


There are two kinds of BI modules available, NR1503 and NR1504. Up to 3 BI modules can be
equipped with one device. The rated voltage can be selected to be 110V/125V, 220V/250V. The
well-designed debouncing technique is adopted in this device, and the state change of binary input
within Debouncing time will be ignored. As shown in Figure 6.3-19.

Figure 6.3-19 Debouncing technique

Each BI module is with a 22-pin connector for 11 binary inputs (NR1503) or 18 binary inputs
(NR1504).
For NR1503, each binary input has independent negative power input of opto-coupler, and can be
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6 Hardware

configurable. The terminal definition of the connector of BI plug-in module is described as below.
[BI_n] (n=01, 02,,11 can be configured as a specified binary input by PCS-Explorer software.)

NR1503

BI_01

01

Opto01-

02

BI_02

03

Opto02-

04

BI_03

05

Opto03-

06

BI_04

07

Opto04-

08

BI_05

09

Opto05-

10

BI_06

11

Opto06-

12

BI_07

13

Opto07-

14

BI_08

15

Opto08-

16

BI_09

17

Opto09-

18

BI_10

19

Opto10-

20

BI_11

21

Opto11-

22

Figure 6.3-20 View of BI plug-in module (NR1503)

Terminal description for NR 1503 is shown as follows.


Terminal No.

Symbol

Description

01

BI_01

Configurable binary input 1

02

Opto01-

Negative supply of configurable binary input 1

03

BI_02

Configurable binary input 2

04

Opto02-

Negative supply of configurable binary input 2

05

BI_03

Configurable binary input 3

06

Opto03-

Negative supply of configurable binary input 3

07

BI_04

Configurable binary input 4

08

Opto04-

Negative supply of configurable binary input 4

09

BI_05

Configurable binary input 5

10

Opto05-

Negative supply of configurable binary input 5

11

BI_06

Configurable binary input 6

12

Opto06-

Negative supply of configurable binary input 6

13

BI_07

Configurable binary input 7

14

Opto07-

Negative supply of configurable binary input 7

15

BI_08

Configurable binary input 8

16

Opto08-

Negative supply of configurable binary input 8

17

BI_09

Configurable binary input 9

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Terminal No.

Symbol

Description

18

Opto09-

Negative supply of configurable binary input 9

19

BI_10

Configurable binary input 10

20

Opto10-

Negative supply of configurable binary input 10

21

BI_11

Configurable binary input 11

22

Opto11-

Negative supply of configurable binary input 11

For NR1504, all binary inputs share one common negative power input, and is configurable. The
terminal definition of the connector of BI plug-in module is described as below. [BI_n] (n=01,
02,,18 can be configured as a specified binary input by PCS-Explorer software.)

NR1504

Opto+

01

BI_01

02

BI_02

03

BI_03

04

BI_04

05

BI_05

06

BI_06

07
08

BI_07

09

BI_08

10

BI_09

11

BI_10

12

BI_11

13

BI_12

14
15

BI_13

16

BI_14

17

BI_15

18

BI_16

19

BI_17

20

BI_18

21

COM-

22

Figure 6.3-21 View of BI plug-in module (NR1504)

Terminal description for NR1504 is shown as follows.


Terminal No.

Symbol

Description

01

Opto+

Positive supply of power supply of the module

02

BI_01

Configurable binary input 1

03

BI_02

Configurable binary input 2

04

BI_03

Configurable binary input 3

05

BI_04

Configurable binary input 4

06

BI_05

Configurable binary input 5

07

BI_06

Configurable binary input 6

08

Blank

Not used

09

BI_07

Configurable binary input 7

10

BI_08

Configurable binary input 8

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6 Hardware
Terminal No.

Symbol

Description

11

BI_09

Configurable binary input 9

12

BI_10

Configurable binary input 10

13

BI_11

Configurable binary input 11

14

BI_12

Configurable binary input 12

15

Blank

Not used

16

BI_13

Configurable binary input 13

17

BI_14

Configurable binary input 14

18

BI_15

Configurable binary input 15

19

BI_16

Configurable binary input 16

20

BI_17

Configurable binary input 17

21

BI_18

Configurable binary input 18

22

COM-

Common terminal of negative supply of binary inputs

First four binary signals (BI_01, BI_02, BI_03, BI_04) in first BI plug-in module are fixed, they are
[BI_TimeSyn], [BI_Print], [BI_Maintenance] and [BI_RstTarg] respectively.
1.

Binary input: [BI_TimeSyn]

It is used to receive clock synchronization signal from clock synchronization device, the binary
input [BI_TimeSyn] will change from 0 to 1 once pulse signal is received. When the device
adopts Conventional mode as clock synchronization mode (refer to section Communication
Settings), the device can receives PPM (pulse per minute) and PPS (pulse per second). If the
setting [Opt_TimeSyn] is set as other values, this binary input is invalid.
2.

Binary input: [BI_Print]

It is used to manually trigger printing latest report when the equipment is configured as manual
printing mode by logic setting [En_AutoPrint]=0. The printer button is located on the panel usually.
If the equipment is configured as automatic printing mode ([En_AutoPrint]=1), report will be printed
automatically as soon as it is formed.
3.

Binary input: [BI_Maintenance]

It is used to block communication export when this binary input is energized. During device
maintenance or testing, this binary input is then energized not to send reports via communication
port, local display and printing still work as usual. This binary input should be de-energized when
the device is restored back to normal.
The application of the binary input [BI_Maintenance] for digital substation communication adopting
IEC61850 protocol is given as follows.
1)

Processing mechanism for MMS (Manufacturing Message Specification) message

a)

The protection device should send the state of this binary input to client.

b) When this binary input is energized, the bit Test of quality (Q) in the sent message changes
to 1.
c)

When this binary input is energized, the client cannot control the isolator link and circuit

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6 Hardware

breaker, modify settings and switch setting group remotely.


d) According to the value of the bit Test of quality (Q) in the message sent, the client
discriminate whether this message is maintenance message, and then deal with it correspondingly.
If the message is the maintenance message, the content of the message will not be displayed on
real-time message window, audio alarm not issued, but the picture is refreshed so as to ensure
that the state of the picture is in step with the actual state. The maintenance message will be
stored, and can be inquired, in independent window.
2)

Processing mechanism for GOOSE message

a) When this binary input is energized, the bit Test in the GOOSE message sent by the
protection device changes to 1.
b) For the receiving end of GOOSE message, it will compare the value of the bit Test in the
GOOSE message received by it with the state of its own binary input (i..e [BI_Maintenance]), the
message will be thought as invalid unless they are conformable.
3)

Processing mechanism for SV (Sampling Value) message

a) When this binary input of merging unit is energized, the bit Test of quality (Q) of sampling
data in the SV message sent change 1.
b) For the receiving end of SV message, if the value of bit Test of quality (Q) of sampling data
in the SV message received is 1, the relevant protection functions will be disabled, but under
maintenance state, the protection device should calculate and display the magnitude of sampling
data.
c) For duplicated protection function configurations, all merging units of control module
configured to receive sampling should be also duplicated. Both dual protection devices and dual
merging units should be fully independent each other, and one of them is in maintenance state will
not affect the normal operation of the other.
4.

Binary input: [BI_RstTarg]

It is used to reset latching signal relay and LCD displaying. The reset is done by pressing a button
on the panel.

Note!

The rated voltage of binary input is optional: 110V, 125V, 220V or 250V, which must be
specified when placed order. It is necessary to check whether the rated voltage of BI
module complies with site DC supply rating before put the relay in service.
There three binary signals are fixed for measurement functions, they are [BI_Rmt/Loc],
[BI_ManSynCls] and [BI_ManOpen] respectively.
5.

Binary input: [BI_Rmt/Loc]

It is used to select the remote control or the local control.


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6 Hardware

1: the remote control, all the binary outputs can only be remotely controlled by SCADA or control
centers.
0 the local control, each binary output can only be applied to open/close CB/DS/ES locally. Each
binary output can also be applied issue a signal locally.
6.

Binary input: [BI_ManSynCls]

When the device is under local control condition (i.e. [BI_Rmt/Loc] is de-energized), the manual
synchronism check for closing circuit breaker will be initiated if it is energized.
7.

Binary input: [BI_ManOpen]

When the device is under local control condition (i.e. [BI_Rmt/Loc] is de-energized), the manual
control for open circuit breaker will be initiated if it is energized.

6.3.8 BO Plug-in Module (Binary Output)


Four standard binary output modules, NR1521A, NR1521C and NR1521G, and one optional
binary output module, NR1521F, can be selected. The contacts provided by NR1521A, NR1521C,
NR1521G and NR1521F are all normally open (NO) contacts. Output contact can be configured as
a specified tripping output contact and a signal output contact respectively by PCS-Explorer
software according to user requirement.
NR1521A can provide 11 output contacts controlled by fault detector.

BO_01
NR1521A

BO_02

BO_03

BO_04

BO_05

BO_06

BO_07

BO_08

BO_09

BO_10

BO_11

01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
17
18
19
20
21
22

Figure 6.3-22 View of BO plug-in module (NR1521A)

NR1521C can provide 11 output contacts without controlled by fault detector.

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6 Hardware

BO_01
NR1521C

BO_02

BO_03

BO_04

BO_05

BO_06

BO_07

BO_08

BO_09

BO_10

BO_11

01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
17
18
19
20
21
22

Figure 6.3-23 View of BO plug-in module (NR1521C)

BO plug-in module (NR1521F) is dedicatedly for remote/manual open or closing to circuit breaker,
disconnector and earth switch. 5 pairs of binary outputs (one for open and the other for closing)
can be provided by this BO plug-in module configured in slot 15 if measurement and control
function is equipped with the device. Up to 10 pairs of binary outputs can be provided by two BO
plug-in modules that can be configured in slot 14 and 15 respectively. (BO plug-in module
configured in slot 14 is optional if open or closing contacts is not enough)
A normally open contact is presented via terminal 21-22 designated as ROS (i.e. remote operation
signal). Whenever any of binary output contacts for open or closing is closed, ROS contact will
close to issue a signal indicating that this device is undergoing a remote operation.
BO plug-in module (NR1521F) is displayed as shown in the following figure.

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6 Hardware

BO_CtrlOpn01
NR1521F

BO_CtrlCls01

BO_CtrlOpn02

BO_CtrlCls02

BO_CtrlOpn03

BO_CtrlCls03

BO_CtrlOpn04

BO_CtrlCls04

BO_CtrlOpn05

BO_CtrlCls05

BO_Ctrl

01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
17
18
19
20
21
22

Figure 6.3-24 View of BO plug-in module (NR1521F)

NR1521G can provide 11 output contacts without controlled by fault detector. The first four output
contacts are in parallel with instantaneous operating contacts which are recommended to be
configured as fast signaling contacts to send PLC signal.

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6 Hardware

NR1521G

BO_01

BO_02

BO_03

BO_04

BO_05

BO_06

BO_07

BO_08

BO_09

BO_10

BO_11

01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
17
18
19
20
21
22

Figure 6.3-25 View of BO plug-in module (NR1521G)

6.3.9 HMI Module


The display panel consists of liquid crystal display module, keyboard, LED and ARM processor.
The functions of ARM processor include display control of the liquid crystal display module,
keyboard processing, and exchanging data with the CPU through LAN port etc. The liquid crystal
display module is a high-performance grand liquid crystal panel with soft back lighting, which has a
user-friendly interface and an extensive display range.

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7 Settings

7 Settings
Table of Contents
7 Settings ............................................................................................. 7-a
7.1 Communication Settings ................................................................................ 7-1
7.1.1 Setting Description .......................................................................................................... 7-2
7.1.2 Access Path ...................................................................................................................... 7-6

7.2 System Settings .............................................................................................. 7-6


7.2.1 Setting Description ............................................................................................................. 7-6
7.2.2 Access Path ....................................................................................................................... 7-7

7.3 Device Settings ............................................................................................... 7-7


7.3.1 Setting Description ............................................................................................................. 7-7
7.3.2 Access Path ....................................................................................................................... 7-8

7.4 Protection Settings ......................................................................................... 7-8


7.4.1 Setting Description ............................................................................................................. 7-8
7.4.2 Access Path ..................................................................................................................... 7-28

7.5 Logic Link Settings ....................................................................................... 7-28


7.5.1 Setting Description ........................................................................................................... 7-28
7.5.2 Access Path ..................................................................................................................... 7-29

7.6 Measurement and Control Settings ............................................................. 7-29


7.6.1 Setting Description ........................................................................................................... 7-29
7.6.2 Access Path ..................................................................................................................... 7-30

List of Tables
Table 7.2-1 Communication settings ..........................................................................................7-1
Table 7.2-1 System settings ......................................................................................................7-6
Table 7.3-1 Device settings .......................................................................................................7-7

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-09-07

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7 Settings

The device has some setting groups for protection to coordinate with the mode of power system
operation, one of which is assigned to be active. However, communication settings, system
settings, device settings, logic link settings and measurement and control settings are common for
all protection setting groups.
Note!
All current settings in this chapter are secondary current converted from primary current by
CT ratio. Zero-sequence current or voltage setting is configured according to 3I0 or 3U0
and negative sequence current setting according to I2 or U2.

7.1 Communication Settings


Table 7.2-1 Communication settings
No.

Item

Range

IP_LAN1

000.000.000.000~255.255.255.255

Mask_LAN1

000.000.000.000~255.255.255.255

IP_LAN2

000.000.000.000~255.255.255.255

Mask_LAN2

000.000.000.000~255.255.255.255

En_LAN2

0 or 1

IP_LAN3

000.000.000.000~255.255.255.255

Mask_LAN3

000.000.000.000~255.255.255.255

En_LAN3

0 or 1

IP_LAN4

000.000.000.000~255.255.255.255

10

Mask_LAN4

000.000.000.000~255.255.255.255

11

En_LAN4

0 or 1

12

Gateway

000.000.000.000~255.255.255.255

13

En_Broadcast

0 or 1

14

Addr_RS485A

0~255

15

Baud_RS485A

4800,9600,19200,38400,57600,115200 (bps)

16

Protocol_RS485A

0, 1 or 2

17

Addr_RS485B

0~255

18

Baud_RS485B

4800,9600,19200,38400,57600,115200 (bps)

19

Protocol_RS485B

0, 1 or 2

20

Threshold_Measmt

0~100%

21

Period_Measmt

0~65535s

22

Format_Measmt

0, 1

23

Baud_Printer

4800,9600,19200,38400,57600,115200 (bps)

24

En_AutoPrint

0 or 1

25

Opt_TimeSyn

Conventional, SAS, Advanced or NoTImeSyn

26

IP_Server_SNTP

000.000.000.000~255.255.255.255

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7 Settings
No.

Item

Range

27

IP_StandbyServer_SNTP

000.000.000.000~255.255.255.255

28

OffsetHour_UTC

-12~+12 (hrs)

29

OffsetMinute_UTC

0~60 (min)

30

Opt_Display_Status

PriValue, SecValue

31

t_Dly_Net_DNP

0~10000 (ms)

32

Fmt_Setting_DNP

0, 1, 2

7.1.1 Setting Description


1.

IP_LAN1, IP_LAN2, IP_LAN3, IP_LAN4

IP address of Ethernet port 1, Ethernet port 2, Ethernet port 3 and Ethernet port 4
2.

Mask_LAN1, Mask_LAN2, Mask_LAN3, Mask_LAN4

Subnet mask of Ethernet port 1, Ethernet port 2, Ethernet port 3 and Ethernet port 4
3.

En_LAN2, En_LAN3, En_LAN4

Put Ethernet port 2, Ethernet port 3 and Ethernet port 4 in service


They are used for Ethernet communication based on the IEC 60870-5-103 protocol. When the IEC
61850 protocol is applied, the IP address of Ethernet A will be GOOSE source MAC address.
Ethernet port 1 is always in service by default.

4.

Gateway

IP address of Gateway (router)

5.

En_Broadcast

This setting is only used only for IEC 60870-5-103 protocol. If NR network IEC 60870-5-103
protocol is used, the setting must be set as 1.
0: the device does not send UDP messages through network
1: the device sends UDP messages through network
6.

Addr_RS485A, Addr_RS485B

They are the devices communication address used to communicate with the SCADA or RTU via
serial ports (port A and port B).
7.

Baud_RS485A, Baud_RS485B

Baud rate of rear RS-485 serial port A or B


8.

Protocol_RS485A, Protocol_RS485B

Communication protocol of rear RS-485 serial port A or B


0: IEC 60870-5-103 protocol

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7 Settings

1: Modbus Protocol
2: Reserved
Note!
Above table listed all the communication settings, the device delivered to the user maybe
only show some settings of them according to the communication interface configuration.
If only the Ethernet ports are applied, the settings about the serial ports (port A and port B)
are not listed in this submenu. And the settings about the Ethernet ports only listed in this
submenu according to the actual number of Ethernet ports.
The standard arrangement of the Ethernet port is two, at most four (predetermined when
ordering). Set the IP address according to actual arrangement of Ethernet numbers and
the un-useful port/ports need not be configured. If PCS-Explorer configuration tool
auxiliary software is connected with this device through the Ethernet, the IP address of
PCS-Explorer must be set as one of the available IP address of this device.

9.

Threshold_Measmt

Threshold value of sending measurement values to SCADA through IEC 60870-5-103 or


IEC61850 protocol.
Default value: 1%

10. Period_Measmt
The time period for equipment sends measurement data to SCADA through IEC 60870-5-103
protocol.
Default value: 60

11. Format_Measmt
The setting is used to select the format of measurement data sent to SCADA through IEC
60870-5-103 protocol.
0: GDD data type through IEC103 protocol is 12
1: GDD data type through IEC103 protocol is 7, i.e. 754 short real number of IEEE standard
12. Baud_Printer
Baud rate of printer port
13. En_AutoPrint
If automatic print is required for fault report after protection operating, it is set as 1. Otherwise, it
should be set to 0.
14. Opt_TimeSyn
There are four selections for clock synchronization of device shown as follow.

PCS-902 Line Distance Relay

7-3
Date: 2013-12-25
-09-07

7 Settings

Conventional

PPS (RS-485): Pulse per second (PPS) via RS-485 differential level
IRIG-B (RS-485): IRIG-B via RS-485 differential level
PPM (DIN): Pulse per minute (PPM) via the binary input [BI_TimeSyn]
PPS (DIN): Pulse per second (PPS) via the binary input [BI_TimeSyn]

SAS

SNTP (PTP): Unicast (point-to-point) SNTP mode via Ethernet network


SNTP (BC): Broadcast SNTP mode via Ethernet network
Message (IEC103): Clock messages through IEC103 protocol

Advanced

IEEE1588: Clock message via IEEE1588


IRIG-B (Fiber): IRIG-B via optical-fibre interface
PPS (Fiber) PPS: Pulse per second (PPS) via optical-fibre interface

NoTimeSync

When no time synchronization signal is connected to the device, please select this option and the
alarm message [Alm_TimeSyn] will not be issued anymore.
Conventional mode and SAS mode are always be supported by the device, but Advanced
mode is only supported when NET-DSP module is equipped. The alarm signal [Alm_TimeSyn]
may be issued to remind user loss of time synchronization signals.
1)

When SAS is selected, if there is no conventional clock synchronization signal, the device
will not send the alarm signal [Alm_TimeSyn]. When Conventional mode is selected, if there
is no conventional clock synchronization signal, SAS mode will be enabled automatically
with the alarm signal [Alm_TimeSyn] issued simultaneously.

2)

When Advanced mode is selected, if there is no conventional clock synchronization signal


connected to NET-DSP module, SAS mode is enabled automatically with the alarm signal
[Alm_TimeSyn] issued simultaneously.

3)

When NoTimeSyn mode is selected, the device will not send alarm signals without time
synchronization signal. But the device can be still synchronized if receiving time
synchronization signal.
Note!
The clock message via IEC 60870-5-103 protocol is invalid when the device receives the
IRIG-B signal through RCS-485 port.

7-4

PCS-902 Line Distance Relay


Date: 2013-12-25

7 Settings

15. IP_Server_SNTP
It is the address of the SNTP time synchronization server which sends SNTP timing messages to
the relay or BCU.
16. IP_StandbyServer_SNTP
Both [IP_Server_SNTP] and [IP_StandbyServer_SNTP] are inefffective unless SNTP clock
synchronization is valid.
When both [IP_Server_SNTP] and [IP_StandbyServer_SNTP] are set as 000.000.000.000, the
deivce receives broadcast SNTP synchronization message.
When either [IP_Server_SNTP] or [IP_StandbyServer_SNTP] is set as 000.000.000.000, the
deivce adopt the setting whose value is not equal to 000.000.000.000 as SNTP server address
and the deivce receives unicast SNTP synchronization message.
When neither [IP_Server_SNTP] nor [IP_StandbyServer_SNTP] are set as 000.000.000.000, the
deivce adopt the setting [IP_Server_SNTP] as SNTP server address to receive unicast SNTP
synchronization message. If the device does not receive the server responses after 30s, the
deivce adopt the setting [IP_StandbyServer_SNTP] as SNTP server address to receive unicast
SNTP synchronization message. The device will switch between [IP_Server_SNTP] and
[IP_StandbyServer_SNTP] repeatedly if the device always can not receive the server responses
waiting 30s
17. OffsetHour_UTC, OffsetMinute_UTC
If the IEC61850 protocol is adopted in substations, the time tags of communication messages are
required according to UTC (Universal Time Coordinated) time.
The setting [OffsetHour_UTC] is used to set the hour offset of the current time zone to the GMT
(Greenwich Mean Time) zone; for example, if a relay is applied in China, the time zone of China is
east 8th time zone, so this setting is set as 8. The setting [OffsetMinute_UTC] is used to set the
minute offset of the current time zone to the GMT zone.
Time zone
Setting
Time zone
Setting
Time zone
Setting
Time zone
Setting

GMT zone

East 1st

East 2nd

East 3rd

East 4th

East 5th

th

th

East 6

East 7

7
th

East 8
8

st

East/West 12

West 1

12/-12

-1

th

th

East 9
9

nd

West 2
-2

th

th

rd

West 3
-3

th

th

East 10

East 11th

10

11
th

West 4
-4

th

West 5th
-5

th

West 6

West 7

West 8

West 9

West 10

West 11th

-6

-7

-8

-9

-10

-11

18. Opt_Display_Status
This setting is used to set display mode of current and voltage in fault records, primary value or
secondary value. The sampled values of current and voltage are displayed as secondary value by
default. When it is set as primary value, both secondary voltage and secondary current are
converted into primary voltage and primary current according to rated secondary and primary
PCS-902 Line Distance Relay

7-5
Date: 2013-12-25
-09-07

7 Settings

value of VT and CT respectively.


19. t_Dly_Net_DNP
The setting is used to set transmission time delay for transmitting multi-frame messages during
DNP process (the setting is valid only if network DNP3.0 protocol is configured)
20. Format_Setting_DNP
The setting is used to set settings uploading format during DNP process (this setting is valid only if
network or serial port DNP3.0 protocol is configured).
0: not upload settings
1: uploading settings adopts the mode of analog output
2: uploading settings adopts the mode of analog input

7.1.2 Access Path


MainMenuSettingsDevice SetupComm Settings

7.2 System Settings


Table 7.2-1 System settings
No.

Item

Unit

Range

Active_Grp

1~10

Opt_SysFreq

50 or 60

PrimaryEquip_Name

Maximum 12 character

U1n

33~65500

kV

U2n

80~220

I1n

100~65500

I2n

1 or 5

f_High_FreqAlm

50~65

Hz

f_Low_FreqAlm

45~60

Hz

Hz

7.2.1 Setting Description


1.

Active_Grp

The number of active setting group, 10 setting groups can be configured for protection settings,
and only one is active at a time
2.

PrimaryEquip_Name

It is recognized by the device automatically. Such setting is used for printing messages
3.

Opt_SysFreq

It is option of system frequency, and can be set as 50Hz or 60Hz

7-6

PCS-902 Line Distance Relay


Date: 2013-12-25

7 Settings

4.

Un1

Primary rated voltage of VT


5.

Un2

Secondary rated voltage of VT


6.

In1

Primary rated current of CT


7.

In2

Secondary rated current of CT


8.

f_High_FreqAlm

It is frequency upper limit setting.The device will issue an alarm [Alm_Freq], when system
frequency is higher than the setting.
9.

f_Low_FreqAlm

It is frequency lower limit setting.The device will issue an alarm [Alm_Freq], when system
frequency is lower than the setting.

7.2.2 Access Path


MainMenuSettingsSystem Settings

7.3 Device Settings


Table 7.3-1 Device settings
No.

Item

Range

HDR_EncodeMode

GB18030, UTF-8

Opt_Caption_103

0, 1 or 2

Bxx.Un_BinaryInput

24V, 30V, 48V, 110V, 125V, 220V

7.3.1 Setting Description


1.

HDR_EncodeMode

Select encoding format of header (HDR) file COMTRADE recording file


Default value is UTF-8.
2.

Opt_Caption_103

Select the caption language sent to SAS via IEC103 protocol


0: Current language
1: Fixed Chinese
2: Fixed English
PCS-902 Line Distance Relay

7-7
Date: 2013-12-25
-09-07

7 Settings

Default value of [Opt_Caption_103] is 0 (i.e. current language), and please set it to 1 (i.e. Fixed
Chinese) if the SAS is supplied by China Manufacturer.
3.

Bxx.Un_BinaryInput

This setting is used to set voltage level of binary input module. If low-voltage BI module is
equipped, 24V, 30V or 48V can be set according to the actual requirement, and if high-voltage BI
module is equipped, 110V, 125V or 220V can be set according to the actual requirement.
Bxx: this plug-in module is inserted in slot xx.

7.3.2 Access Path


MainMenuSettingsDevice SetupDevice Settings

7.4 Protection Settings


All protection settings are based on secondary ratings of VT and CT.
Unn: rated secondary phase-to-phase voltage
Un: rated secondary phase-to-ground voltage
In: rated secondary current

7.4.1 Setting Description


7.4.1.1 Line Parameters
No.

Item

Remark

Range

X1L

Positive sequence reactance of the line

(0.000~4Unn)/In (ohm)

R1L

Positive sequence resistance of the line

(0.000~4Unn)/In (ohm)

X0L

Zero-sequence reactance of the line

(0.000~4Unn)/In (ohm)

R0L

Zero-sequence resistance of the line

(0.000~4Unn)/In (ohm)

X0M

Line mutual zero-sequence reactance

(0.000~4Unn)/In (ohm)

R0M

Line mutual zero-sequence resistance

(0.000~4Unn)/In (ohm)

LineLength

Total length of the line

0.00~655.35 (km)

phi1_Reach

Phase angle of line positive sequence impedance

30.00~89.00 (Deg)

Real_K0

10

Imag_K0

Resistive

component

of

zero-sequence

of

zero-sequence

compensation coefficient
Imaginary

component

compensation coefficient

-4.000~4.000

-4.000~4.000

7.4.1.2 Fault Detector Settings (FD)


No.

Item

Remark

Range

FD.DPFC.I_Set

Current setting of DPFC current FD element

(0.050~30.000)In (A)

FD.ROC.3I0_Set

Current setting of neutral current FD element

(0.050~30.000)In (A)

7-8

PCS-902 Line Distance Relay


Date: 2013-12-25

7 Settings

7.4.1.3 Auxiliary Element (Aux.E)


No.

Item

AuxE.OCD.t_DDO

AuxE.OCD.En

AuxE.ROC1.3I0_Set

AuxE.ROC1.En

AuxE.ROC2.3I0_Set

AuxE.ROC2.En

AuxE.ROC3.3I0_Set

AuxE.ROC3.En

AuxE.OC1.I_Set

Remark

Range

Extended time delay of current change auxiliary


element
Enable current change auxiliary element

0 or 1

Current setting of stage 1 residual current auxiliary


element
Enable stage 1 residual current auxiliary element
Current setting of stage 2 residual current

0.000~10.000 (s)

auxiliary

element
Enable stage 2 residual current auxiliary element
Current setting of stage 3 residual current auxiliary
element
Enable stage 3 residual current auxiliary element
Current setting of stage 1 phase current auxiliary
element
Enable stage 1 phase current auxiliary element

(0.050~30.000)In
0 or 1
(0.050~30.000)In
0 or 1
(0.050~30.000)In
0 or 1
(0.050~30.000)In

10

AuxE.OC1.En

11

AuxE.OC2.I_Set

12

AuxE.OC2.En

13

AuxE.OC3.I_Set

14

AuxE.OC3.En

Enable stage 3 phase current auxiliary element

0 or 1

15

AuxE.UVD.U_Set

Voltage setting for voltage change auxiliary element

0~Un

16

AuxE.UVD.t_Ext

17

AuxE.UVD.En

18

AuxE.UVG.U_Set

19

AuxE.UVG.En

20

AuxE.UVS.U_Set

21

AuxE.UVS.En

22

AuxE.ROV.3U0_Set

Voltage setting for residual voltage auxiliary element

0~Un

23

AuxE.ROV.En

Enable residual voltage auxiliary element

0 or 1

Current setting of stage 2 phase current auxiliary


element
Enable stage 2 phase current auxiliary element
Current setting of stage 3 phase current auxiliary
element

Extended time delay of voltage change auxiliary


element
Enable voltage change auxiliary element
Voltage setting for phase-to-ground under voltage
auxiliary element
Enable phase-to-ground under voltage auxiliary
element
Voltage setting for phase-to-phase under voltage
auxiliary element
Enable phase-to-phase under voltage auxiliary
element

0 or 1
(0.050~30.000)In
0 or 1
(0.050~30.000)In

0.000~10.000 (s)
0 or 1
0~Un

0 or 1

0~Unn

0 or 1

7.4.1.4 DPFC Distance Protection Settings (21D)


No.

Item

Remark

Range

21D.Z_Set

Impedance setting of DPFC distance protection

(0.000~4Unn)/In (ohm)

21D.En

Enable DPFC distance protection

0 or 1

PCS-902 Line Distance Relay

7-9
Date: 2013-12-25
-09-07

7 Settings

7.4.1.5 Load Encroachment Settings (LoadEnch)


No.

Item

Remark

Range

Angle setting of load trapezoid characteristic, it should


1

LoadEnch.phi_Blinder

be set according to the maximum load area angle 0~45 (Deg)


(Load_Max), Load_Max+5is recommended.
Resistance setting of load trapezoid characteristic, it

LoadEnch.R_Blinder

should be set according to the minimum load


resistance, 70%~90% minimum load resistance is

(0.05~200)/In (ohm)

recommended.
3

LoadEnch.En

Enable load trapezoid characteristic

0 or 1

7.4.1.6 Distance Protection Settings with Mho Characteristic (21M)


No.

Item

21M.ZG.phi_Shift

21M.ZP.phi_Shift

21M.ZG1.Z_Set

21M.ZG1.t_Op

21M.ZG1.En

21M.ZG1.En_BlkAR

21M.ZP1.Z_Set

21M.ZP1.t_Op

21M.ZP1.En

10

21M.ZP1.En_BlkAR

11

21M.ZG2.Z_Set

12

21M.ZG2.t_Op

13

21M.ZG2.t_ShortDly

14

21M.ZG2.En

15

21M.ZG2.En_BlkAR

16

21M.ZP2.Z_Set

Remark

Range

Phase shift of zone 1, 2 of phase-to-ground distance


protection
Phase shift of zone 1, 2 of phase-to-phase distance
protection
Impedance setting of zone 1 of phase-to-ground
distance protection
Time delay of zone 1 of phase-to-ground distance
protection

0, 15 or 30 (Deg)

0, 15 or 30 (Deg)

(0.000~4Unn)/In (ohm)

0.000~10.000 (s)

Enable zone 1 of phase-to-ground distance protection 0 or 1


Enable phase-to-ground zone 1 of distance protection
operation to block AR
Impedance setting of zone 1 of phase-to-phase
distance protection
Time delay of zone 1 of phase-to-phase distance
protection

0 or 1

(0.000~4Unn)/In (ohm)

0.000~10.000 (s)

Enable zone 1 of phase-to-phase distance protection 0 or 1


Enable phase-to-phase zone 1 of distance protection
operation to block AR
Impedance setting of zone 2 of phase-to-ground
distance protection
Time delay of zone 2 of phase-to-ground distance
protection
Short time delay of zone 2 of phase-to-ground
distance protection

0 or 1

(0.000~4Unn)/In (ohm)

0.000~10.000 (s)

0.000~10.000 (s)

Enable zone 2 of phase-to-ground distance protection 0 or 1


Enable phase-to-ground zone 2 of distance protection
operation to block AR
Impedance setting of zone 2 of phase-to-phase
distance protection

7-10

0 or 1

(0.000~4Unn)/In (ohm)

PCS-902 Line Distance Relay


Date: 2013-12-25

7 Settings
Time delay of zone 2 of phase-to-phase distance

17

21M.ZP2.t_Op

18

21M.ZP2.t_ShortDly

19

21M.ZP2.En

20

21M.ZP2.En_BlkAR

21

21M.Z2.En_ShortDly

22

21M.ZG3.Z_Set

23

21M.ZG3.t_Op

24

21M.ZG3.t_ShortDly

25

21M.ZG3.En

26

21M.ZG3.En_BlkAR

27

21M.ZP3.Z_Set

28

21M.ZP3.t_Op

29

21M.ZP3.t_ShortDly

30

21M.ZP3.En

31

21M.ZP3.En_BlkAR

32

21M.Z3.En_ShortDly

33

21M.Z4.Z_Fwd

34

21M.Z4.Z_Rev

35

21M.Z4.t_Op

Time delay of zone 4 of distance protection

0.000~10.000 (s)

36

21M.ZG4.En

Enable zone 4 of phase-to-ground distance element

0 or 1

37

21M.ZG4.En_BlkAR

38

21M.ZP4.En

39

21M.ZP4.En_BlkAR

protection
Short time delay of zone 2 of phase-to-phase distance
protection

0.000~10.000 (s)

0.000~10.000 (s)

Enable zone 2 of phase-to-phase distance protection 0 or 1


Enable phase-to-phase zone 2 of distance protection
operation to block AR

0 or 1

Enable fixed accelerate zone 2 of distance protection 0 or 1


Impedance setting of zone 3 of phase-to-ground
distance protection
Time delay of zone 3 of phase-to-ground distance
protection
Short time delay of zone 3 of phase-to-ground
distance protection

(0.000~4Unn)/In (ohm)

0.000~10.000 (s)

0.000~10.000 (s)

Enable zone 3 of phase-to-ground distance protection 0 or 1


Enable phase-to-ground zone 3 of distance protection
operation to block AR
Impedance setting of zone 3 of phase-to-phase
distance protection
Time delay of zone 3 of phase-to-phase distance
protection
Short time delay of zone 3 of phase-to-phase distance
protection

0 or 1

(0.000~4Unn)/In (ohm)

0.000~10.000 (s)

0.000~10.000 (s)

Enable zone 3 of phase-to-phase distance protection 0 or 1


Enable phase-to-phase zone 3 of distance protection
operation to block AR

0 or 1

Enable fixed accelerate zone 3 of distance protection 0 or 1


Impedance setting of zone 4 of pilot positive distance
protection
Impedance setting of zone 4 of pilot reversal distance
protection

Enable phase-to-ground zone 4 of distance protection


operation to block AR

(0.000~4Unn)/In (ohm)

(0.000~4Unn)/In (ohm)

0 or 1

Enable zone 4 of phase-to-phase distance protection 0 or 1


Enable phase-to-phase zone 4 of distance protection
operation to block AR

0 or 1

7.4.1.7 Distance Protection Settings with Quad Characteristic (21Q)


No.
1

Item
21Q.ZG1.RCA

Remark
Downward offset angle of the reactance line for zone
1 of phase-to-ground distance protection

PCS-902 Line Distance Relay

Range
0~45 (Deg)

7-11
Date: 2013-12-25
-09-07

7 Settings
2

21Q.ZG1.Z_Set

21Q.ZG1.R_Set

21Q.ZG1.t_Op

21Q.ZG1.En

21Q.ZG1.En_BlkAR

21Q.ZP1. RCA

21Q.ZP1.Z_Set

21Q.ZP1.R_Set

10

21Q.ZP1.t_Op

11

21Q.ZP1.En

12

21Q.ZP1.En_BlkAR

13

21Q.ZG2.RCA

14

21Q.ZG2.Z_Set

15

21Q.ZG2.R_Set

16

21Q.ZG2.t_Op

17

21Q.ZG2.t_ShortDly

18

21Q.ZG2.En

19

21Q.ZG2.En_BlkAR

20

21Q.ZP2. RCA

21

21Q.ZP2.Z_Set

22

21Q.ZP2.R_Set

23

21Q.ZP2.t_Op

24

21Q.ZP2.t_ShortDly

Impedance setting of zone 1 of phase-to-ground


distance protection
Resistance setting of zone 1 of phase-to-ground
distance protection
Time delay of zone 1 of phase-to-ground distance
protection

(0.000~4Unn)/In (ohm)

(0.000~4Unn)/In (ohm)

0.000~10.000 (s)

Enable zone 1 of phase-to-ground distance protection 0 or 1


Enable phase-to-ground zone 1 of distance protection
operation to block AR
Downward offset angle of the reactance line for zone
1 of phase-to-phase distance protection
Impedance setting of zone 1 of phase-to-phase
distance protection
Resistance setting of zone 1 of phase-to-phase
distance protection
Time delay of zone 1 of phase-to-phase distance
protection

0 or 1

0~45 (Deg)

(0.000~4Unn)/In (ohm)

(0.000~4Unn)/In (ohm)

0.000~10.000 (s)

Enable zone 1 of phase-to-phase distance protection 0 or 1


Enable phase-to-phase zone 1 of distance protection
operation to block AR
Downward offset angle of the reactance line for zone
2 of phase-to-ground distance protection
Impedance setting of zone 2 of phase-to-ground
distance protection
Resistance setting of zone 2 of phase-to-ground
distance protection
Time delay of zone 2 of phase-to-ground distance
protection
Short time delay of zone 2 of phase-to-ground
distance protection

0 or 1

0~45 (Deg)

(0.000~4Unn)/In (ohm)

(0.000~4Unn)/In (ohm)

0.000~10.000 (s)

0.000~10.000 (s)

Enable zone 2 of phase-to-ground distance protection 0 or 1


Enable phase-to-ground zone 2 of distance protection
operation to block AR
Downward offset angle of the reactance line for zone
2 of phase-to-phase distance protection
Impedance setting of zone 2 of phase-to-phase
distance protection
Resistance setting of zone 2 of phase-to-phase
distance protection
Time delay of zone 2 of phase-to-phase distance
protection
Short time delay of zone 2 of phase-to-phase distance
protection

7-12

0 or 1

0~45 (Deg)

(0.000~4Unn)/In (ohm)

(0.000~4Unn)/In (ohm)

0.000~10.000 (s)

0.000~10.000 (s)

PCS-902 Line Distance Relay


Date: 2013-12-25

7 Settings
25

21Q.ZP2.En

26

21Q.ZP2.En_BlkAR

27

21Q.Z2.En_ShortDly

28

21Q.ZG3.RCA

29

21Q.ZG3.Z_Set

30

21Q.ZG3.R_Set

31

21Q.ZG3.t_Op

32

21Q.ZG3.t_ShortDly

33

21Q.ZG3.En

34

21Q.ZG3.En_BlkAR

35

21Q.ZP3. RCA

36

21Q.ZP3.Z_Set

37

21Q.ZP3.R_Set

38

21Q.ZP3.t_Op

39

21Q.ZP3.t_ShortDly

40

21Q.ZP3.En

41

21Q.ZP3.En_BlkAR

42

21Q.Z3.En_ShortDly

43

21Q.ZG4.RCA

44

21Q.ZG4.Z_Set

45

21Q.ZG4.R_Set

46

21Q.ZG4.t_Op

47

21Q.ZG4.En

48

21Q.ZG4.En_BlkAR

Enable zone 2 of phase-to-phase distance protection 0 or 1


Enable phase-to-phase zone 2 of distance protection
operation to block AR

0 or 1

Enable fixed accelerate zone 2 of distance protection 0 or 1


Downward offset angle of the reactance line for zone
3 of phase-to-ground distance protection
Impedance setting of zone 3 of phase-to-ground
distance protection
Resistance setting of zone 3 of phase-to-ground
distance protection
Time delay of zone 3 of phase-to-ground distance
protection
Short time delay of zone 3 of phase-to-ground
distance protection

0~45 (Deg)

(0.000~4Unn)/In (ohm)

(0.000~4Unn)/In (ohm)

0.000~10.000 (s)

0.000~10.000 (s)

Enable zone 3 of phase-to-ground distance protection 0 or 1


Enable phase-to-ground zone 3 of distance protection
operation to block AR
Downward offset angle of the reactance line for zone
3 of phase-to-phase distance protection
Impedance setting of zone 3 of phase-to-phase
distance element
Resistance setting of zone 3 of phase-to-phase
distance protection
Time delay of zone 3 of phase-to-phase distance
protection
Short time delay of zone 3 of phase-to-phase distance
protection

0 or 1

0~45 (Deg)

(0.000~4Unn)/In (ohm)

(0.000~4Unn)/In (ohm)

0.000~10.000 (s)

0.000~10.000 (s)

Enable zone 3 of phase-to-phase distance protection 0 or 1


Enable phase-to-phase zone 3 of distance protection
operation to block AR

0 or 1

Enable fixed accelerate zone 3 of distance protection 0 or 1


Downward offset angle of the reactance line for zone
4 of phase-to-ground distance protection
Impedance setting of zone 4 of phase-to-ground
distance protection
Resistance setting of zone 4 of phase-to-ground
distance protection
Time delay of zone 4 of phase-to-ground distance
protection

0~45 (Deg)

(0.000~4Unn)/In (ohm)

(0.000~4Unn)/In (ohm)

0.000~10.000 (s)

Enable zone 4 of phase-to-ground distance protection 0 or 1


Enable phase-to-ground zone 4 of distance protection
operation to block AR

PCS-902 Line Distance Relay

0 or 1

7-13
Date: 2013-12-25
-09-07

7 Settings
49

21Q.ZP4. RCA

50

21Q.ZP4.Z_Set

51

21Q.ZP4.R_Set

52

21Q.ZP4.t_Op

53

21Q.ZP4.En

54

21Q.ZP4.En_BlkAR

Downward offset angle of the reactance line for zone


4 of phase-to-phase distance protection
Impedance setting of zone 4 of phase-to-phase
distance protection
Resistance setting of zone 4 of phase-to-phase
distance protection
Time delay of zone 4 of phase-to-phase distance
protection

0~45 (Deg)

(0.000~4Unn)/In (ohm)

(0.000~4Unn)/In (ohm)

0.000~10.000 (s)

Enable zone 4 of phase-to-phase distance protection 0 or 1


Enable phase-to-phase zone 4 of distance protection
operation to block AR

0 or 1

7.4.1.8 Pilot Distance Zone Settings


No.

Item

Remark

Range

21M.Pilot.Z_Set

Impedance setting of pilot distance element

(0.000~4Unn)/In (ohm)

21Q.Pilot.Z_Set

Impedance setting of pilot distance element

(0.000~4Unn)/In (ohm)

21M.Pilot.Z_Rev

Impedance setting of pilot reversal distance element

(0.000~4Unn)/In (ohm)

21Q.Pilot.Z_Rev

Impedance setting of pilot reversal distance element

(0.000~4Unn)/In (ohm)

21Q.Pilot.R_Set

Resistance setting of pilot distance element

(0.000~4Unn)/In (ohm)

21Q.Pilot.R_Rev

Resistance setting of pilot reversal distance element

(0.000~4Unn)/In (ohm)

7.4.1.9 Power Swing Detection Settings (68)


No.
1

Item
68.En

Remark

Range

Enable power swing detection

0 or 1

7.4.1.10 Power Swing Blocking Releasing Settings (PSBR)


No.

Item

21M.Z1.En_PSBR

21Q.Z1.En_PSBR

21M.Z2.En_PSBR

21Q.Z2.En_PSBR

21M.Z3.En_PSBR

21Q.Z3.En_PSBR

21M.Pilot.En_PSBR

Remark

Range

Enable PSBR for zone 1 of distance element (Mho


Characteristic)
Enable PSBR for zone 1 of distance element (Quad
Characteristic)
Enable PSBR for zone 2 of distance element (Mho
Characteristic)
Enable PSBR for zone 2 of distance element (Quad
Characteristic)
Enable PSBR for zone 3 of distance element (Mho
Characteristic)
Enable PSBR for zone 3 of distance element (Quad
Characteristic)
Enable PSBR for pilot distance element (Mho
Characteristic)

7-14

0 or 1

0 or 1

0 or 1

0 or 1

0 or 1

0 or 1

0 or 1

PCS-902 Line Distance Relay


Date: 2013-12-25

7 Settings
8

21Q.Pilot.En_PSBR

21M.I_PSBR

10

21Q.I_PSBR

Enable PSBR for pilot distance element (Quad


Characteristic)
Current setting of PSBR (Mho Characteristic)
Current setting for power swing blocking (Quad
Characteristic)

0 or 1
(0.050~30.000)In (A)
(0.050~30.000)In (A)

7.4.1.11 Distance SOTF Protection Settings (21SOTF)


No.
1

Item

Remark

21SOTF.En

Enable accelerating distance protection to trip

Range
0 or 1

Enable stage 2 of accelerating distance protection


2

21SOTF.Z2.En_ManCls

to trip when manual closing or auto-reclosing onto 0 or 1


an existing fault
Enable stage 3 of accelerating distance protection

21SOTF.Z3.En_ManCls

to trip when manual closing or auto-reclosing onto 0 or 1


an existing fault
Enable stage 4 of accelerating distance protection

21SOTF.Z4.En_ManCls

to trip when manual closing or auto-reclosing onto 0 or 1


an existing fault

21SOTF.Z2.En_3PAR

Enable 3-pole auto-reclosing mode for zone 2

0 or 1

21SOTF.Z3.En_3PAR

Enable 3-pole auto-reclosing mode for zone 3

0 or 1

21SOTF.Z4.En_3PAR

Enable 3-pole auto-reclosing mode for zone 4

0 or 1

21SOTF.Z2.En_PSBR

Enable PSBR for zone 2 of distance element

0 or 1

21SOTF.Z3.En_PSBR

Enable PSBR for zone 3 of distance element

0 or 1

10

21SOTF.Z4.En_PSBR

Enable PSBR for zone 4 of distance element

0 or 1

Enable accelerating distance protection to trip


11

21SOTF.En_PDF

when fault occurs on healthy phase under pole 0 or 1


discrepancy situation
Time delay of accelerating distance protection to

12

21SOTF.t_PDF

trip when fault occurs on healthy phase under pole 0.000~10.000 (s)
discrepancy situation

13

SOTF.Opt_Mode_ManCls

Option of manual SOTF mode

0, 1 or 2

7.4.1.12 Optical Pilot Channel Settings


No.

Item

Remark

Range

FO.LocID

Indentity code of the device at local end

0-65535

FO.RmtID

Indentity code of the device at remote end

0-65535

FO.Protocol

It is used to select protocol type, G.703 or C37.94

G.703 or C37.94

FOx.BaudRate

Baud rate of optical pilot channel x

64 or 2048

FOx.En_IntClock

Option of internal clock or external clock

0 or 1

FOx.En

Enable channel x

0 or 1

PCS-902 Line Distance Relay

7-15
Date: 2013-12-25
-09-07

7 Settings

7.4.1.13 Pilot Distance Protection Settings (85)


No.

Item

Remark

Range

85.Opt_PilotMode

Option of pilot scheme

0~2

85.Opt_Ch_PhSeg

85.En_WI

Enable weak infeed scheme

0 or 1

85.U_UV_WI

Undervoltage setting of weak infeed logic

0~Unn (V)

85.Z.En

Enable pilot distance protection

0 or 1

85.En_Unblocking1

Enable unblocking scheme

0 or 1

85.t_DPU_Blocking1

85.t_DPU_CR1

Time delay pickup for current reversal logic

0.000~1.000 (s)

85.t_DDO_CR1

Time delay dropoff for current reversal logic

0.000~1.000 (s)

10

85.ZX.En

Enable zone extension protection

0 or 1

11

85.t_DPU_ZX

Option of phase-segregated signal scheme or


three-phase signal scheme

Time delay for blocking scheme of pilot distance


protection operation

Pickup time delay for zone extension protection


operation

0 or 1

0.000~1.000 (s)

0.000~10.000 (s)

7.4.1.14 Pilot Directional Earth-fault Protection Settings (85)


No.

Item

85.DEF.En

85.DEF.En_BlkAR

85.DEF_En_IndepCh

85.En_Unblocking2

85.DEF.3I0_Set

85.DEF.t_DPU

Remark

Range

Enable pilot directional earth-fault protection

0 or 1

Enable pilot directional earth-fault protection operate


to block AR
Enable independent pilot channel for pilot directional
earth-fault protection
Enable unblocking scheme for pilot DEF via pilot
channel 2
Current

setting

of

pilot

directional

earth-fault

protection
Time delay of pilot directional earth-fault protection

0 or 1

0 or 1

0 or 1

(0.050~30.000)In (A)
0.001~10.000 (s)

Time delay pickup for current reversal logic when pilot


7

85.t_DPU_CR2

directional earth-fault protection adopts independent 0.000~1.000 (s)


pilot channel 2
Time delay dropoff for current reversal logic when

85.t_DDO_CR2

pilot

directional

earth-fault

protection

adopts 0.000~1.000 (s)

independent pilot channel 2

7.4.1.15 Current Direction Settings


No.

Item

RCA_OC

RCA_ROC

Remark
The

characteristic

angle

Range
of

directional

phase

overcurrent element
The characteristic angle of directional earth fault
element

7-16

30.00~89.00 (Deg)

30.00~89.00 (Deg)

PCS-902 Line Distance Relay


Date: 2013-12-25

7 Settings
The

characteristic

angle

of

directional

RCA_NegOC

Z0_Comp

Zero-sequence compensation impedance setting

(0.000~4Unn)/In (ohm)

Z2_Comp

Negative-sequence compensation impedance setting

(0.000~4Unn)/In (ohm)

negative-sequence overcurrent element

30.00~89.00 (Deg)

7.4.1.16 Phase Overcurrent Protection (50/51P)


No.

Item

50/51P.K_Hm2

50/51P1.I_Set

50/51P1.t_Op

50/51P1.En

50/51P1.En_BlkAR

50/51P1.Opt_Dir

50/51P1.En_Hm2_Blk

50/51P1.Opt_Curve

50/51P1.TMS

10

50/51P1.tmin

11

50/51P1.Alpha

12

50/51P1.C

13

50/51P1.K

14

50/51P2.I_Set

15

50/51P2.t_Op

16

50/51P2.En

17

50/51P2.En_BlkAR

18

50/51P2.Opt_Dir

19

50/51P2.En_Hm2_Blk

Remark
Setting of second harmonic component for blocking
phase overcurrent elements
Current setting for stage 1 of phase overcurrent
protection
Time delay for stage 1 of phase overcurrent
protection
Enable stage 1 of phase overcurrent protection
Enable auto-reclosing blocked when stage 1 of
phase overcurrent protection operates
Direction option for stage 1 of phase overcurrent
protection
Enable second harmonic blocking for stage 1 of
phase overcurrent protection
Option of characteristic curve for stage 1 of phase
overcurrent protection
Time multiplier setting for stage 1 of inverse-time
phase overcurrent protection
Minimum operating time for stage 1 of inverse-time
phase overcurrent protection
Constant for stage 1 of customized inverse-time
characteristic phase overcurrent protection
Constant C for stage 1 of customized inverse-time
characteristic phase overcurrent protection
Constant K for stage 1 of customized inverse-time
characteristic phase overcurrent protection
Current setting for stage 2 of phase overcurrent
protection
Time delay for stage 2 of phase overcurrent
protection
Enable stage 2 of phase overcurrent protection
Enable auto-reclosing blocked when stage 2 of
phase overcurrent protection operates
Direction option for stage 2 of phase overcurrent
protection
Enable second harmonic blocking for stage 2 of
phase overcurrent protection

PCS-902 Line Distance Relay

Range
0.000~1.000

(0.050~30.000)In (A)

0.000~20.000 (s)
0 or 1
0 or 1

0, 1 or 2

0 or 1

0~13

0.010~200.000

0.000~20.000 (s)

0.010~5.000

0.000~200.000

0.050~20.000

(0.050~30.000)In (A)

0.000~20.000 (s)
0 or 1
0 or 1

0, 1 or 2

0 or 1

7-17
Date: 2013-12-25
-09-07

7 Settings
20

50/51P2.Opt_Curve

21

50/51P2.TMS

22

50/51P2.tmin

23

50/51P3.I_Set

24

50/51P3.t_Op

25

50/51P3.En

26

50/51P3.En_BlkAR

27

50/51P3.Opt_Dir

28

50/51P3.En_Hm2_Blk

29

50/51P3.Opt_Curve

30

50/51P3.TMS

31

50/51P3.tmin

32

50/51P4.I_Set

33

50/51P4.t_Op

34

50/51P4.En

35

50/51P4.En_BlkAR

36

50/51P4.Opt_Dir

37

50/51P4.En_Hm2_Blk

38

50/51P4.Opt_Curve

39

50/51P4.TMS

40

50/51P4.tmin

Option of characteristic curve for stage 2 of phase


overcurrent protection
Time multiplier setting for stage 2 of inverse-time
phase overcurrent protection.
Minimum operating time for stage 2 of inverse-time
phase overcurrent protection
Current setting for stage 3 of phase overcurrent
protection
Time delay for stage 3 of phase overcurrent
protection
Enable stage 3 of phase overcurrent protection

phase overcurrent protection operates


Direction option for stage 3 of phase overcurrent
protection
Enable second harmonic blocking for stage 3 of
phase overcurrent protection
Option of characteristic curve for stage 3 of phase
overcurrent protection
Time multiplier setting for stage 3 of inverse-time
phase overcurrent protection.
Minimum operating time for stage 3 of inverse-time
phase overcurrent protection
Current setting for stage 4 of phase overcurrent
protection
Time delay for stage 4 of phase overcurrent
protection
Enable stage 4 of phase overcurrent protection

0.000~20.000 (s)

(0.050~30.000)In (A)

0.000~20.000 (s)

0 or 1

0, 1 or 2

0 or 1

0~12

0.010~200.000

0.000~20.000 (s)

(0.050~30.000)In (A)

0.000~20.000 (s)
0 or 1

Enable auto-reclosing blocked when stage 4 of


phase overcurrent protection operates
Direction option for stage 4 of phase overcurrent
protection
Enable second harmonic blocking for stage 4 of
phase overcurrent protection
Option of characteristic curve for stage 4 of phase
overcurrent protection
Time multiplier setting for stage 4 of inverse-time
phase overcurrent protection.
Minimum operating time for stage 4 of inverse-time

7-18

0.010~200.000

0 or 1

Enable auto-reclosing blocked when stage 3 of

phase overcurrent protection

0~12

0 or 1

0, 1 or 2

0 or 1

0~12

0.010~200.000

0.010~20.000 (s)

PCS-902 Line Distance Relay


Date: 2013-12-25

7 Settings

7.4.1.17 Direction Earth Fault Protection Settings (50/51G)


No.

Item

Remark
Setting of second harmonic component for blocking

Range

50/51G.K_Hm2

50/51G1.3I0_Set

Current setting for stage 1 of earth fault protection

(0.050~30.000)In (A)

50/51G1.t_Op

Time delay for stage 1 of earth fault protection

0.000~20.000 (s)

50/51G1.En

Enable stage 1 of earth fault protection

0 or 1

50/51G1.En_BlkAR

50/51G1.Opt_Dir

50/51G1.En_Hm2_Blk

50/51G1.En_Abnor_Blk

50/51G1.En_CTS_Blk

earth fault elements

Enable auto-reclosing blocked when stage 1 of


earth fault protection operates
Direction option for stage 1 of earth fault protection
Enable second harmonic blocking for stage 1 of
earth fault protection
Enable blocking for stage 1 of earth fault protection
under abnormal conditions
Enable blocking for stage 1 of earth fault protection
under CT failure conditions
Option of characteristic curve for stage 1 of earth

0.000~1.000

0 or 1
0, 1 or 2
0 or 1

0 or 1

0 or 1

10

50/51G1.Opt_Curve

11

50/51G1.TMS

12

50/51G1.tmin

13

50/51G1.Alpha

14

50/51G1.C

15

50/51G1.K

16

50/51G2.3I0_Set

Current setting for stage 2 of earth fault protection

(0.050~30.000)In (A)

17

50/51G2.t_Op

Time delay for stage 2 of earth fault protection

0.000~20.000 (s)

18

50/51G2.En

Enable stage 2 of earth fault protection

0 or 1

19

50/51G2.En_BlkAR

20

50/51G2.Opt_Dir

21

50/51G2.En_Hm2_Blk

22

50/51G2.En_Abnor_Blk

23

50/51G2.En_CTS_Blk

24

50/51G2.Opt_Curve

fault protection
Time multiplier setting for stage 1 of inverse-time
earth fault protection
Minimum operating time for stage 1 of inverse-time
earth fault protection
Constant for stage 1 of customized inverse-time
characteristic earth fault protection
Constant C for stage 1 of customized inverse-time
characteristic earth fault protection
Constant K for stage 1 of customized inverse-time
characteristic earth fault protection

Enable auto-reclosing blocked when stage 2 of


earth fault protection operates
Direction option for stage 2 of earth fault protection
Enable second harmonic blocking for stage 2 of
earth fault protection
Enable blocking for stage 2 of earth fault protection
under abnormal conditions
Enable blocking for stage 2 of earth faultv protection
under CT failure conditions
Option of characteristic curve for stage 2 of earth
fault protection

PCS-902 Line Distance Relay

0~13

0.010~200.000

0.050~20.000 (t)

0.010~5.000

0.000~20.000

0.050~20.000

0 or 1
0, 1 or 2
0 or 1

0 or 1

0 or 1

0~12

7-19
Date: 2013-12-25
-09-07

7 Settings
Time multiplier setting for stage 2 of inverse-time

25

50/51G2.TMS

26

50/51G2.tmin

27

50/51G3.3I0_Set

Current setting for stage 3 of earth fault protection

(0.050~30.000)In (A)

28

50/51G3.t_Op

Time delay for stage 3 of earth fault protection

0.000~20.000 (s)

29

50/51G3.En

Enable stage 3 of earth fault protection

0, 1 or 2

30

50/51G3.En_BlkAR

31

50/51G3.Opt_Dir

32

50/51G3.En_Hm2_Blk

33

50/51G3.En_Abnor_Blk

34

50/51G3.En_CTS_Blk

35

50/51G3.Opt_Curve

36

50/51G3.TMS

37

50/51G3.tmin

38

50/51G4.3I0_Set

Current setting for stage 4 of earth fault protection

(0.050~30.000)In (A)

39

50/51G4.t_Op

Time delay for stage 4 of earth fault protection

0.000~20.000 (s)

40

50/51G4.En

Enable stage 4 of earth fault protection

0, 1 or 2

41

50/51G4.En_BlkAR

42

50/51G4.Opt_Dir

43

50/51G4.En_Hm2_Blk

44

50/51G4.En_Abnor_Blk

45

50/51G4.En_CTS_Blk

46

50/51G4.Opt_Curve

47

50/51G4.TMS

48

50/51G4.tmin

earth fault protection


Minimum operating time for stage 2 of inverse-time
earth fault protection

Enable auto-reclosing blocked when stage 3 of


earth fault protection operates
Direction option for stage 3 of earth fault protection
Enable second harmonic blocking for stage 3 of
earth fault protection
Enable blocking for stage 3 of earth fault protection
under abnormal conditions
Enable blocking for stage 3 of earth fault protection
under CT failure conditions
Option of characteristic curve for stage 3 of earth
fault protection
Time multiplier setting for stage 3 of inverse-time
earth fault protection
Minimum operating time for stage 3 of inverse-time
earth fault protection

Enable auto-reclosing blocked when stage 4 of


earth fault protection operates
Direction option for stage 4 of earth fault protection
Enable second harmonic blocking for stage 4 of
earth fault protection
Enable blocking for stage 4 of earth fault protection
under abnormal conditions
Enable blocking for stage 4 of earth fault protection
under CT failure conditions
Option of characteristic curve for stage 4 of earth
fault protection
Time multiplier setting for stage 4 of inverse-time
earth fault protection
Minimum operating time for stage 4 of inverse-time
earth fault protection

7-20

0.010~200.000

0.050~20.000 (s)

0 or 1
0 or 1
0 or 1

0 or 1

0 or 1

0~12

0.010~200.000

0.050~20.000 (s)

0 or 1
0 or 1
0 or 1

0 or 1

0 or 1

0~12

0.010~200.000

0.050~20.000 (s)

PCS-902 Line Distance Relay


Date: 2013-12-25

7 Settings

7.4.1.18 Overcurrent Protection Settings for VT Circuit Failure (50PVT/50GVT)


No.

Item

50PVT.I_Set

50PVT.t_Op

50PVT.En

50GVT.3I0_Set

50GVT.t_Op

50GVT.En

Remark
Current setting of phase overcurrent protection
when VT circuit failure
Time delay of phase overcurrent protection when
VT circuit failure
Enable phase overcurrent protection when VT
circuit failure
Current setting of ground overcurrent protection
when VT circuit failure
Time delay of ground overcurrent protection when
VT circuit failure
Enable ground overcurrent protection when VT
circuit failure

Range
(0.050~30.000)In (A)

0.000~10.000 (s)

0 or 1

(0.050~30.000)In (A)

0.000~10.000 (s)

0 or 1

7.4.1.19 Residual Current SOTF Protection Settings (50GSOTF)


No.

Item

Remark

Range

50GSOTF.3I0_Set

Current setting of residual current SOTF protection

(0.050~30.000)In (A)

50GSOTF.En_3I0

Enable residual current SOTF protection

0 or 1

7.4.1.20 Overvoltage Protection Settings (59P)


No.

Item

Remark

Range

59P1.U_Set

Voltage setting for stage 1 of overvoltage protection

Un~2Unn (V)

59P1.t_Op

Time delay for stage 1 of overvoltage protection

0.000~30.000 (s)

59P1.En

Enable stage 1 of overvoltage protection

0 or 1

59P1.Opt_1P/3P

Option of 1-out-of-3 mode or 3-out-of-3 mode

0 or 1

59P1.Opt_Up/Upp

Option of phase-to-phase voltage or phase voltage

0 or 1

59P1.En_Alm

59P1.En_52b_TT

59P1.En_TT

59P1.Opt_Curve

Enable stage 1 of overvoltage protection for alarm


purpose
Enable transfer trip controlled by CB open position for
stage 1 of overvoltage protection
Enable stage 1 of overvoltage protection operate to
initiate transfer trip
Option of characteristic curve for stage 1 of overvoltage
protection
Time multiplier setting for stage 1 of inverse-time

0 or 1

0 or 1

0 or 1

0~13

10

59P1.TMS

11

59P1.tmin

12

59P2.U_Set

Voltage setting for stage 2 of overvoltage protection

Un~2Unn (V)

13

59P2.t_Op

Time delay for stage 2 of overvoltage protection

0.000~30.000 (s)

14

59P2.En

Enable stage 2 of overvoltage protection

0 or 1

overvoltage protection
Minimum delay for stage 1 of inverse-time overvoltage
protection

PCS-902 Line Distance Relay

0.010~200.000

0.050~20.000 (s)

7-21
Date: 2013-12-25
-09-07

7 Settings
15

59P2.Opt_1P/3P

Option of 1-out-of-3 mode or 3-out-of-3 mode

0 or 1

16

59P2.Opt_Up/Upp

Option of phase-to-phase voltage or phase voltage

0 or 1

17

59P2.En_Alm

18

59P2.En_52b_TT

19

59P2.En_TT

20

59P2.Opt_Curve

21

59P2.TMS

22

59P2.tmin

Enable stage 2 of overvoltage protection for alarm


purpose
Enable transfer trip controlled by CB open position for
stage 2 of overvoltage protection
Enable stage 2 of overvoltage protection operate to
initiate transfer trip
Option of characteristic curve for stage 2 of overvoltage
protection
Time multiplier setting for stage 2 of inverse-time
overvoltage protection
Minimum delay for stage 2 of inverse-time overvoltage
protection

0 or 1

0 or 1

0 or 1

0~12

0.010~200.000

0.050~20.000 (s)

7.4.1.21 Undervoltage Protection Settings (27P)


No.

Item

Remark

Range

27P1.U_Set

Voltage setting for stage 1 of undervoltage protection

0~Unn (V)

27P1.t_Op

Time delay for stage 1 of undervoltage protection

0.000~30.000 (s)

27P1.En

Enable stage 1 of undervoltage protection

0 or 1

27P1.Opt_1P/3P

Option of 1-out-of-3 mode or 3-out-of-3 mode

0 or 1

27P1.Opt_Up/Upp

27P1.En_Alm

27P1.Opt_Curve

27P1.TMS

27P1.tmin

Option of voltage criterion adopting phase-to-phase


voltage or phase voltage
Enable stage 1 of undervoltage protection operate to
alarm
Option

of

characteristic

curve

for

stage

of

undervoltage protection
Time multiplier setting for stage 1 of inverse-time
undervoltage protection
Minimum delay for stage 1 of inverse-time undervoltage
protection

0 or 1

0 or 1

0~13

0.010~200.000

0.050~20.000 (s)

10

27P2.U_Set

Voltage setting for stage 2 of undervoltage protection

0~Unn (V)

11

27P2.t_Op

Time delay for stage 2 of undervoltage protection

0.000~30.000 (s)

12

27P2.En

Enable stage 2 of undervoltage protection

0 or 1

13

27P2.Opt_1P/3P

Option of 1-out-of-3 mode or 3-out-of-3 mode

0 or 1

14

27P2.Opt_Up/Upp

15

27P2.En_Alm

16

27P2.Opt_Curve

17

27P2.TMS

Option of voltage criterion adopting phase-to-phase


voltage or phase voltage
Enable stage 2 of undervoltage protection operate to
alarm
Option

of

characteristic

curve

for

stage

of

undervoltage protection
Time multiplier setting for stage 2 of inverse-time
undervoltage protection

7-22

0 or 1

0 or 1

0~12

0.010~200.000

PCS-902 Line Distance Relay


Date: 2013-12-25

7 Settings
18

27P2.tmin

Minimum delay for stage 2 of inverse-time undervoltage


protection

0.050~20.000 (s)

7.4.1.22 Frequency Protection Settings (81U and 81O)


No.

Item

Remark

Range

81U.f_Pkp

Frequency pickup setting for underfrequency protection 45.000~60.000 (Hz)

81U.df/dt_Blk

81U.UF1.f_Set

81U.UF1.t_Op

Time delay for stage 1 of underfrequency protection

0.050~30.000 (s)

81U.UF1.En

Enable stage 1 of underfrequency protection

0 or 1

81U.UF1.En_df/dt_Blk

81U.UF2.f_Set

81U.UF2.t_Op

Time delay for stage 2 of underfrequency protection

0.050~30.000 (s)

81U.UF2.En

Enable stage 2 of underfrequency protection

0 or 1

Rate of frequency change for blocking underfrequency


protection
Frequency setting for stage 1 of underfrequency
protection

Enable rate of frequency change to block stage 1 of


underfrequency protection
Frequency setting for stage 2 of underfrequency
protection

Enable rate of frequency change to block stage 2 of

0.200~20.000 (Hz/s)

45.000~60.000 (Hz)

0 or 1

45.000~60.000 (Hz)

10

81U.UF2.En_df/dt_Blk

11

81U.UF3.f_Set

12

81U.UF3.t_Op

Time delay for stage 3 of underfrequency protection

0.050~30.000 (s)

13

81U.UF3.En

Enable stage 3 of underfrequency protection

0 or 1

14

81U.UF3.En_df/dt_Blk

15

81U.UF4.f_Set

16

81U.UF4.t_Op

Time delay for stage 4 of underfrequency protection

0.050~30.000 (s)

17

81U.UF4.En

Enable stage 4 of underfrequency protection

0 or 1

18

81U.UF4.En_df/dt_Blk

19

81O.f_Pkp

20

81O.OF1.f_Set

21

81O.OF1.t_Op

Time delay for stage 1 of overfrequency protection

0.050~20.000 (s)

22

81O.OF1.En

Enable stage 1 of overfrequency protection

0 or 1

23

81O.OF2.f_Set

24

81O.OF2.t_Op

Time delay for stage 2 of overfrequency protection

0.050~20.000 (s)

25

81O.OF2.En

Enable stage 2 of overfrequency protection

0 or 1

26

81O.OF3.f_Set

underfrequency protection
Frequency setting for stage 3 of underfrequency
protection

Enable rate of frequency change to block stage 3 of


underfrequency protection
Frequency setting for stage 4 of underfrequency
protection

Enable rate of frequency change to block stage 4 of


underfrequency protection
Frequency pickup setting for overfrequency protection
Frequency setting for stage 1 of overfrequency
protection

Frequency setting for stage 2 of overfrequency


protection

Frequency setting for stage 3 of overfrequency


protection

PCS-902 Line Distance Relay

0 or 1

45.000~60.000 (Hz)

0 or 1

45.000~60.000 (Hz)

0 or 1
50.000~65.000 (Hz)
50.000~65.000 (Hz)

50.000~65.000 (Hz)

50.000~65.000 (Hz)

7-23
Date: 2013-12-25
-09-07

7 Settings
27

81O.OF3.t_Op

Time delay for stage 3 of overfrequency protection

0.050~20.000 (s)

28

81O.OF3.En

Enable stage 3 of overfrequency protection

0 or 1

29

81O.OF4.f_Set

30

81O.OF4.t_Op

Time delay for stage 4 of overfrequency protection

0.050~20.000 (s)

31

81O.OF4.En

Enable stage 4 of overfrequency protection

0 or 1

Frequency setting for stage 4 of overfrequency


protection

50.000~65.000 (Hz)

7.4.1.23 Breaker Failure Protection Settings (50BF)


No.

Item

Remark

Range

50BF.I_Set

Current setting of phase current criterion for BFP

(0.050~30.000 )In (A)

50BF.3I0_Set

Current setting of zero-sequence current criterion


(0.050~30.000 )In (A)
for BFP

50BF.I2_Set

Current setting of negative-sequence current


(0.050~30.000 )In (A)
criterion for BFP

50BF.t_ReTrp

Time delay of re-tripping for BFP

0.000~10.000 (s)

50BF.t1_Op

Time delay of stage 1 for BFP

0.000~10.000 (s)

50BF.t2_Op

Time delay of stage 2 for BFP

0.000~10.000 (s)

50BF.En

Enable breaker failure protection

0 or 1

50BF.En_ReTrp

Enable re-trip function for BFP

0 or 1

50BF.En_3I0_1P

Enable zero-sequence current criterion for BFP


0 or 1
initiated by single-phase tripping contact

10

50BF.En_3I0_3P

Enable zero-sequence current criterion for BFP


0 or 1
initiated by three-phase tripping contact

11

50BF.En_I2_3P

Enable negative-sequence current criterion for BFP


0 or 1
initiated by three-phase tripping contact

12

50BF.En_CB_Ctrl

Enable breaker failure protection can be initiated by


0 or 1
normally closed contact of circuit breaker

7.4.1.24 Thermal Overload Protection (49)


No.

Item

Remark

Range

49-1.K

The factor setting for stage 1 of thermal overload


protection which is associated to the thermal state 1.000~3.000
formula

49-2.K

The factor setting for stage 2 of thermal overload


protection which is associated to the thermal state 1.000~3.000
formula

49.Ib_Set

The reference current setting of the thermal


(0.050~30.000 )In (A)
overload protection

49.Tau

The time constant setting of the IDMT overload


0.100~100.000 (min)
protection

49-1.En_Alm

Enable stage 1 of thermal overload protection for


0 or 1
alarm purpose

49-1.En_Trp

Enable stage 1 of thermal overload protection for


0 or 1
trip purpose

49-2.En_Alm

Enable stage 2 of thermal overload protection for


0 or 1
alarm purpose

7-24

PCS-902 Line Distance Relay


Date: 2013-12-25

7 Settings
8

49-2.En_Trp

Enable stage 2 of thermal overload protection for


0 or 1
trip purpose

7.4.1.25 Stub Overcurrent Protection (50STB)


No.

Name

Remark

Range

50STB.I_Set

Current setting of stub overcurrent protection

(0.050~30.000)In (A)

50STB.t_Op

Time delay of stub overcurrent protection

0.000~10.000 (s)

50STB.En

Enable stub overcurrent protection

0 or 1

7.4.1.26 Dead Zone Protection (50DZ)


No.

Name

Remark

Range

50DZ.I_Set

Current setting of dead zone protection

(0.050~30.000)In (A)

50DZ.t_Op

Time delay of dead zone protection

0.000~10.000 (s)

50DZ.En

Enable dead zone protection

0 or 1

7.4.1.27 Pole Discrepancy Protection Settings (62PD)


No.

Item

Remark

Range

62PD.3I0_Set

Current setting of residual


pole discrepancy protection

current criterion for

62PD.I2_Set

Current setting of negative-sequence current


(0.050~30.000 )In (A)
criterion for pole discrepancy protection

62PD.t_Op

Time delay of pole discrepancy protection

0.000~600.000 (s)

62PD.En

Enable pole discrepancy protection

0 or 1

62PD.En_3I0/I2_Ctrl

Enable
residual
current
criterion
negative-sequence current criterion for
discrepancy protection

(0.050~30.000 )In (A)

and
pole 0 or 1

7.4.1.28 Broken Conductor Protection (46BC)


No.

Item

Remark

Range

46BC.I2/I1_Set

Ratio setting (negative-sequence current to


positive-sequence current) of broken conductor
protection

0.20~1.00

46BC.t_Op

Time delay of broken conductor protection

0.000~600.000 (s)

46BC.I_Min

Minimum operation current of broken conductor


protection

(0.050~30.000)In (A)

46BC.En_Trp

Enable broken conductor protection to operate to


trip

0 or 1

46BC.En_Alm

Enable broken conductor protection to operate to


alarm

0 or 1

7.4.1.29 Synchrocheck Settings (25)


No.

Item

Remark

Range

25.Opt_Source_UL

Voltage selecting mode of line

0~5

25.Opt_Source_UB

Voltage selecting mode of bus

0~5

25.U_Dd

Voltage threshold of dead check

0.05Un~0.8Un (V)

PCS-902 Line Distance Relay

7-25
Date: 2013-12-25
-09-07

7 Settings
4

25.U_Lv

Voltage threshold of live check

0.5Un~Un (V)

25.K_Usyn

Compensation coefficient for synchronism voltage

0.20-5.00

25.phi_Diff

Phase difference limit of synchronism check for AR

0~ 89 (Deg)

25.phi_Comp

25.f_Diff

25.U_Diff

Voltage difference limit of synchronism check for AR 0.02Un~0.8Un (V)

10

25.t_DdChk

Time delay to confirm dead check condition

11

25.t_SynChk

Time delay to confirm synchronism check condition 0.010~25.000 (s)

12

25.En_fDiffChk

Enable frequency difference check

0 or 1

13

25.En_SynChk

Enable synchronism check

0 or 1

14

25.En_DdL_DdB

Enable dead line and dead bus (DLDB) check

0 or 1

15

25.En_DdL_LvB

Enable dead line and live bus (DLLB) check

0 or 1

16

25.En_LvL_DdB

Enable live line and dead bus (LLDB) check

0 or 1

17

25.En_NoChk

Enable AR without any check

0 or 1

Compensation for phase difference between two


synchronous voltages
Frequency difference limit of synchronism check for
AR

0~359 (Deg)

0.02~1.00 (Hz)

0.010~25.000 (s)

7.4.1.30 Auto-reclosing Settings (79)


No.

Item

Remark

Range

79.N_Rcls

Maximum number of reclosing attempts

1~4

79.t_Dd_1PS1

Dead time of first shot 1-pole reclosing

0.000~600.000 (s)

79.t_Dd_3PS1

Dead time of first shot 3-pole reclosing

0.000~600.000 (s)

79.t_Dd_3PS2

Dead time of second shot 3-pole reclosing

0.000~600.000 (s)

79.t_Dd_3PS3

Dead time of third shot 3-pole reclosing

0.000~600.000 (s)

79.t_Dd_3PS4

Dead time of fourth shot 3-pole reclosing

0.000~600.000 (s)

79.t_CBClsd

Time delay of circuit breaker in closed position


before reclosing

0.000~600.000 (s)

Time delay to wait for CB healthy, and begin to


8

79.t_CBReady

timing when the input signal [79.CB_Healthy] is


de-energized and if it is not energized within this

0.000~600.000 (s)

time delay, AR will be blocked.


9

79.t_Wait_Chk

Maximum wait time for synchronism check

0.000~600.000 (s)

Time delay allow for CB status change to conform

10

79.t_Fail

11

79.t_PW_AR

Pulse width of AR closing signal

0.000~600.000 (s)

12

79.t_Reclaim

Reclaim time of AR

0.000~600.000 (s)

13

79.t_PersistTrp

reclosing successful

Time delay of excessive trip signal to block


auto-reclosing

7-26

0.000~600.000 (s)

0.000~600.000 (s)

PCS-902 Line Distance Relay


Date: 2013-12-25

7 Settings
Drop-off time delay of blocking AR, when blocking
14

79.t_DDO_BlkAR

signal for AR disappears, AR blocking condition 0.000~600.000 (s)


drops off after this time delay

15

79.t_AddDly

16

79.t_WaitMaster

Additional time delay for auto-reclosing


Maximum wait time for reclosing permissive signal
from master AR

0.000~600.000 (s)
0.000~600.000 (s)

Time delay of discriminating another fault, and begin


to times after 1-pole AR initiated, 3-pole AR will be
17

79.t_SecFault

initiated if another fault happens during this time 0.000~600.000 (s)


delay. AR will be blocked if another fault happens
after that.
Enable auto-reclosing blocked when a fault occurs

18

79.En_PDF_Blk

19

79.En_AddDly

20

79.En_CutPulse

21

79.En_FailCheck

22

79.En

23

79.En_ExtCtrl

24

79.En_CBInit

25

79.Opt_Priority

Option of AR priority

None, High or Low

26

79.SetOpt

Control option of AR mode

0 or 1

27

79.En_1PAR

Enable 1-pole AR mode

0 or 1

28

79.En_3PAR

Enable 3-pole AR mode

0 or 1

29

79.En_1P/3PAR

Enable 1/3-pole AR mode

0 or 1

under pole disagreement condition


Enable auto-reclosing with an additional dead time
delay
Enable adjust the length of reclosing pulse
Enable confirm whether AR is successful by
checking CB state
Enable auto-reclosing

0 or 1

0 or 1
0 or 1
0 or 1
0 or 1

Enable AR by external input signal besides logic


setting [79.En]
Enable AR be initiated by open state of circuit
breaker

0 or 1

0 or 1

7.4.1.31 Transfer Trip Settings (TT)


No.

Item

Remark

Range

TT.t_Op

Time delay of transfer trip

0.000~600.000 (s)

TT.En_FD_Ctrl

Enable transfer trip controlled by local fault detector

0 or 1

7.4.1.32 Tripping Logic Settings


No.

Item

En_MPF_Blk_AR

En_3PF_Blk_AR

En_PhSF_Blk_AR

Remark
Enable auto-reclosing blocked when multi-phase fault
happens
Enable auto-reclosing blocked when three-phase fault
happens
Enable auto-reclosing blocked when selection of faulty
phase fails

PCS-902 Line Distance Relay

Range
0 or 1

0 or 1

0 or 1

7-27
Date: 2013-12-25
-09-07

7 Settings
Enable three-phase tripping mode for any fault

En_Trp3P

t_Dwell_Trp

conditions
The dwell time of tripping command, empirical value is
0.04

0 or 1

0.000~10.000 (s)

7.4.1.33 VTS Settings (VTS)


No.

Item

Remark

Range

VTS.t_DPU

Pickup time delay of VT circuit supervision

0.200~100.000

VTS.t_DDO

Dropoff time delay of VT circuit supervision

0.200~100.000

VTS.En_Out_VT

VT is not connected to the protection device

0 or 1

If three-phase voltage used for protection measurement


4

VTS.En_LineVT

comes from line side (for example, 3/2 breaker), it


should be set as 1. If three-phase voltage comes from

0 or 1

busbar side, it should be set as 0.


5

VTS.En

Enable alarm function of VT circuit supervision

0 or 1

7.4.2 Access Path


MainMenuSettingsProt Settings

7.5 Logic Link Settings


The logic link settings are used to determine whether the relevant function of this device is
enabled or disabled. If this device supports the logic link function, it will have a corresponding
submenu in the submenu Logic Links for the logic link settings.
Each logic link settings is an AND condition of enabling the relevant function with the
corresponding binary input and logic setting. Through SAS or RTU, logic link settings can be set
as 1 or 0; and it means that the relevant function can be in service or out of service through
remote command. It provides convenience for operation management.

7.5.1 Setting Description


7.5.1.1 Spare Link Settings
The spare link settings are used for future application. It can be defined according to project
specification through the configuration tool, PCS-Explorer.
No.

Item

Remark

Range

Link_01

Spare link setting 01

0 or 1

Link_02

Spare link setting 02

0 or 1

Link_03

Spare link setting 03

0 or 1

Link_04

Spare link setting 04

0 or 1

Link_05

Spare link setting 05

0 or 1

Link_06

Spare link setting 06

0 or 1

Link_07

Spare link setting 07

0 or 1

Link_08

Spare link setting 08

0 or 1

7-28

PCS-902 Line Distance Relay


Date: 2013-12-25

7 Settings

7.5.2 Access Path


MainMenuSettingsLogic Links

7.6 Measurement and Control Settings


7.6.1 Setting Description
7.6.1.1 Synchronism Settings
No.

Item

Remark

Range

MCBrd.25.Opt_Source_UL

Voltage selecting mode of line

0~5

MCBrd.25.Opt_Source_UB

Voltage selecting mode of bus

0~5

MCBrd.25.U_Dd

Voltage threshold of dead check

1.000~100.000 (V)

MCBrd.25.U_Lv

Voltage threshold of live check

1.000~100.000 (V)

MCBrd.25.K_Usyn

Compensation coefficient for synchronism voltage

0.20-5.00

MCBrd.25.phi_Diff

Phase difference limit of synchronism check for AR

0.10~ 180.00 (Deg)

MCBrd.25.phi_Comp

MCBrd.25.f_Diff

MCBrd.25.U_Diff

Voltage difference limit of synchronism check for AR 1.000~100.000 (V)

10

MCBrd.25.En_SynChk

Enable synchronism check

0 or 1

11

MCBrd.25.En_DdL_DdB

Enable dead line and dead bus (DLDB) check

0 or 1

12

MCBrd.25.En_DdL_LvB

Enable dead line and live bus (DLLB) check

0 or 1

13

MCBrd.25.En_LvL_DdB

Enable live line and dead bus (LLDB) check

0 or 1

14

MCBrd.25.En_NoChk

Enable AR without any check

0 or 1

15

MCBrd.25.df/dt

Compensation for phase difference between two


synchronous voltages
Frequency difference limit of synchronism check for
AR

Threshold of rate of frequency change between both


sides of CB for synchronism-check.

0~360 (Deg)

0.00~3.00 (Hz)

0.10~5.00 (Hz/s)

Circuit breaker closing time. It is the time from


16

MCBrd.25.t_Close_CB

receiving closing command pulse till the CB is 0~1000 (ms)


completely closed.
From receiving a closing command, this device will
continuously check whether between incoming
voltage

17

MCBrd.25.t_Wait_Chk

and

reference

voltage

involved

in

synchronism check (or dead check) can meet the


criteria. If the synchronism check (or dead check)

5.000~30.000 (s)

criteria are not met within the duration of this time


delay, the failure of synchronism-check (or dead
check) will be confirmed.

7.6.1.2 Dual Point Binary Input Settings


Thses settings are applied to configure the status change confirmation time for No.xx double point
binary inputs. Up to 10 virtual double point binary inputs are provided in this device.

PCS-902 Line Distance Relay

7-29
Date: 2013-12-25
-09-07

7 Settings

If a double point binary input changes from normal status to invalid status, i.e.: double point error
occurs, [CSWIxx.t_DPU_DPS] will be applied as the debouncing time for No.xx double point
binary input.
No.

Name

Remark

Range

These settings are applied to configure the debouncing


1

time. DPU is the abbreviation of Delay Pick Up.

CSWIxx.t_DPU_DPS

0~60000 (ms)

(xx=01, 02.10)

7.6.1.3 Control Settings


No.

Name

Remark

Range

No.xx holding time of a normal open contact of remote


1

CSWIxx.t_PW_Opn

opening CB, disconnector or for signaling purpose.

0~60000 (ms)

(xx=01, 02.10)
No.xx closing time of a normal open contact of remote
2

CSWIxx.t_PW_Cls

closing CB, disconnector or for signaling purpose.

0~60000 (ms)

(xx=01, 02.10)

7.6.1.4 Interlock Settings


No.

Name

Remark

Range

Enable No.xx open output of the BO module be controlled


1

CSWIxx.En_Opn_Blk

by the interlocking logic

0 or 1

(xx=01, 02.10)
Enable No.xx closing output of the BO module be
2

CSWIxx.En_Cls_Blk

controlled by the interlocking logic

0 or 1

(xx=01, 02.10)

7.6.2 Access Path


MainMenuSettingsBCU Settings

7-30

PCS-902 Line Distance Relay


Date: 2013-12-25

8 Human Machine Interface

8 Human Machine Interface


Table of Contents
8 Human Machine Interface ............................................................... 8-a
8.1 Overview .......................................................................................................... 8-1
8.1.1 Keypad Operation .............................................................................................................. 8-2
8.1.2 LED Indications .................................................................................................................. 8-3
8.1.3 Front Communication Port ................................................................................................. 8-3
8.1.4 Ethernet Port Setup ........................................................................................................... 8-4

8.2 Menu Tree ........................................................................................................ 8-5


8.2.1 Overview ............................................................................................................................ 8-5
8.2.2 Main Menus ....................................................................................................................... 8-6
8.2.3 Sub Menus ......................................................................................................................... 8-7

8.3 LCD Display ................................................................................................... 8-27


8.3.1 Overview .......................................................................................................................... 8-27
8.3.2 Normal Display................................................................................................................. 8-27
8.3.3 Display Disturbance Records ........................................................................................... 8-28
8.3.4 Display Supervision Event ............................................................................................... 8-30
8.3.5 Display IO Events ............................................................................................................ 8-31
8.3.6 Display Device Logs ........................................................................................................ 8-31

8.4 Keypad Operation ......................................................................................... 8-32


8.4.1 View Device Measurements ............................................................................................. 8-32
8.4.2 View Device Status .......................................................................................................... 8-33
8.4.3 View Device Records ....................................................................................................... 8-33
8.4.4 Print Device Records ....................................................................................................... 8-33
8.4.5 View Device Setting ......................................................................................................... 8-34
8.4.6 Modify Device Setting ...................................................................................................... 8-35
8.4.7 Copy Device Setting ........................................................................................................ 8-38

PCS-902 Line Distance Relay

8-a
Date: 2013-12-25

8 Human Machine Interface

8.4.8 Switch Setting Group ....................................................................................................... 8-38


8.4.9 Delete Device Records .................................................................................................... 8-39
8.4.10 Remote Control .............................................................................................................. 8-40
8.4.11 Modify Device Clock ....................................................................................................... 8-43
8.4.12 View Module Information................................................................................................ 8-44
8.4.13 Check Software Version ................................................................................................. 8-44
8.4.14 Communication Test....................................................................................................... 8-44
8.4.15 Select Language ............................................................................................................ 8-45

List of Figures
Figure 8.1-1 Front panel ............................................................................................................8-1
Figure 8.1-2 Keypad buttons ....................................................................................................8-2
Figure 8.1-3 LED indications ....................................................................................................8-3
Figure 8.1-4 Corresponding cable of the RJ45 port in the front panel ..................................8-4
Figure 8.1-5 Rear view and terminal definition of NR1102C...................................................8-5
Figure 8.2-1 Menu tree ..............................................................................................................8-7

List of Tables
Table 8.1-1 Definition of the 8-core cable ................................................................................8-4
Table 8.3-1 Tripping report messages....................................................................................8-30
Table 8.3-2 User operating event list......................................................................................8-32

8-b

PCS-902 Line Distance Relay


Date: 2013-12-25

8 Human Machine Interface

The operator can access the protective device from the front panel. Local communication with the
protective device is possible using a computer via a multiplex RJ45 port on the front panel.
Furthermore, remote communication is also possible using a PC with the substation automation
system via rear RS485 port or rear Ethernet port. The operator is able to check the protective
device status at any time.
This chapter describes human machine interface (HMI), and give operator an instruction about
how to display or print event report, setting and so on through HMI menu tree and display metering
value, including r.m.s. current, voltage and frequency etc. through LCD. Procedures to change
active setting group or a settable parameter value through keypad is also described in details.

Note!

About three measurements in menu Measurements, please refer to the following


description:
Measurements1 is use to display measured values from protection calculation DSP
(displayed in secondary value)
Measurements2 is used to display measured values from fault detector DSP
(displayed in secondary value)
Measurements3 is used to display measured primary values and other calculated
quantities

8.1 Overview
The human-machine interface consists of a human-machine interface (HMI) module which allows
a communication to be as simple as possible for the user. The HMI module helps to draw your
attention to something that has occurred which may activate a LED or a report displayed on the
LCD. Operator can locate the data of interest by navigating the keypad.

HEALTHY

11

13

14

15

16

17

18

19

10

20

GRP

PCS-902

12

ALARM

ESC

1
2

ENT

4
3

Figure 8.1-1 Front panel

The function of HMI module:


PCS-902 Line Distance Relay

8-1
Date: 2013-12-25

8 Human Machine Interface


No.

Item

Description
A 320240 dot matrix backlight LCD display is visible in dim lighting

LCD

conditions. The corresponding messages are displayed when there is


operation implemented.
20 status indication LEDs, 2 LEDs are fixed as the signals of HEALTHY

LED

(green) and ALARM (yellow), 18 LEDs are configurable with selectable


color among green, yellow and red.

Keypad

Navigation keypad and command keys for full access to device

Communication port

a multiplex RJ45 port for local communication with a PC

Logo

Type and designation and manufacturer of device

GR
P

8.1.1 Keypad Operation

ENT

ESC

Figure 8.1-2 Keypad buttons

1.

2.

3.

ESC:

Cancel the operation

Quit the current menu

ENT:

Execute the operation

Confirm the interface

GRP

4.

5.

6.

Activate the switching interface of setting group

leftward and rightward direction keys ( and ):

Move the cursor horizontally

Enter the next menu or return to the previous menu

upward and downward direction keys ( and )

Move the cursor vertically

Select command menu within the same level of menu

plus and minus sign keys ( and )

Modify the value

8-2

PCS-902 Line Distance Relay


Date: 2013-12-25

8 Human Machine Interface

Modify and display the message number

Page up/down

8.1.2 LED Indications


HEALTHY
ALARM

Figure 8.1-3 LED indications

A brief explanation has been made as bellow.


LED

Display
Off

HEALTHY
Steady Green
Off

Description
When the equipment is out of service or any hardware error is defected during
self-check.
Lit when the equipment is in service and ready for operation.
When equipment in normal operating condition.

ALARM
Steady Yellow

Lit when VT circuit failure, CT circuit failure or other abnormal alarm is issued.

Note!

HEALTHY LED can only be turned on by energizing the device and no abnormality
detected.
ALARM LED is turned on when abnormalities of device occurs like above mentioned
and can be turned off after abnormalities are removed except alarm report [CTS.Alm]
which can only be reset only when the failure is removed and the device is rebooted or
re-energized.
Other LED indicators with no labels are configurable and user can configure them to be lit
by signals of operation element, alarm element and binary output contact according to
requirement through PCS-Explorer software, but as drawn in figure, 2 LEDs are fixed as
the signals of HEALTHY (green) and ALARM (yellow), 18 LEDs are configurable with
selectable color among green, yellow and red.

8.1.3 Front Communication Port


There is a multiplex RJ45 port on the front panel. This port can be used as an RS-232 serial port
PCS-902 Line Distance Relay

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as well as a twisted-pair ethernet port. As shown in the following figure, a customized cable is
applied for debugging via this multiplex RJ45 port.

Figure 8.1-4 Corresponding cable of the RJ45 port in the front panel

In the above figure and the following table:


P1: To connect the multiplex RJ45 port. An 8-core cable is applied here.
P2: To connect the twisted-pair ethernet port of the computer.
P3: To connect the RS-232 serial port of the computer.
The definition of the 8-core cable in the above figure is introduced in the following table.
Table 8.1-1 Definition of the 8-core cable
Terminal
No.

Core color

Function

Device side

Computer side

(Left)

(Right)

Orange

TX+ of the ethernet port

P1-1

P2-1

Orange & white

TX- of the ethernet port

P1-2

P2-2

Green & white

RX+ of the ethernet port

P1-3

P2-3

Blue

TXD of the RS-232 serial port

P1-4

P3-2

Brown & white

RXD of the RS-232 serial port

P1-5

P3-3

Green

RX- for the ethernet port

P1-6

P2-6

Blue & white

The ground connection of the RS-232 port.

P1-7

P3-5

8.1.4 Ethernet Port Setup


MON plug-in module is equipped with two or four 100Base-TX Ethernet interface, take NR1102C
as an example, as shown in Figure 8.1-5. Its rear view and the definition of terminals.
The Ethernet port can be used to communication with PC via auxiliary software (PCS-Explorer)
after connecting the protection device with PC, so as to fulfill on-line function (please refer to the
instruction manual of PCS-Explorer). At first, the connection between the protection device and PC
must be established. Through setting the IP address and subnet mask of corresponding Ethernet
interface in the menu SettingsDevice SetupComm Settings, it should be ensured that the
protection device and PC are in the same network segment. For example, setting the IP address
and subnet mask of network A. (using network A to connect with PC)

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PC: IP address is set as 198.87.96.102, subnet mask is set as 255.255.255.0


The IP address and subnet mask of protection device should be [IP_LAN1]= 198.87.96.XXX,
[Mask_LAN1]=255.255.255.0, [En_LAN1]=1. (XXX can be any value from 0 to 255 except 102)
If the logic setting [En_LAN1] is non-available, it means that network A is always enabled.

NR1102C

ETHERNET

Network A

Network B

SYN+
SYNSGND
GND
RTS
TXD
SGND

Figure 8.1-5 Rear view and terminal definition of NR1102C

Note!
If using other Ethernet port, for example, Ethernet B, the logic setting [En_LAN2] must be
set as 1.

8.2 Menu Tree


8.2.1 Overview
Press of any running interface and enter the main menu. Select different submenu by and
. Enter the selected submenu by pressing ENT or . Press and return to the previous
menu. Press ESC back to main menu directly. For sake of entering the command menu again, a
command menu will be recorded in the quick menu after its execution. Five latest command
menus can be recorded in the quick menu. When five command menus are recorded, the latest
command menu will cover the earliest one, adopting the first in first out principle. It is arranged
from top to bottom and in accordance with the execution order of command menus.
Press to enter the main menu with the interface as shown in the following diagram:

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MainMenu

Language
Clock
Quick Menu

For the first powered device, there is no record in quick menu. Press to enter the main menu
with the interface as shown in the following diagram:

Measurements
Status
Records
Settings
Print
Local Cmd
Information
Test
Clock
Language

The descriptions about menu are based on the maximized configuration, for a specific project, if
some function is not available, the corresponding submenu will hidden.

8.2.2 Main Menus


The menu of PCS-902 is organized into main menu and submenus, much like a PC directory
structure. The menu of PCS-902 is divided into 10 sections:

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Main Menu

Measurements

Status

Records

Settings

Print

Local Cmd

Information

Test

Clock

Language

Figure 8.2-1 Menu tree

Under main interface, press to enter main menu, and select submenu by pressing ,
and ENT. The command menu adopts a tree shaped content structure. The above diagram
provides the integral structure and all main menus (first-level menus) under menu tree of the
device.

8.2.3 Sub Menus


8.2.3.1 Measurements
Main Menu

Measurements

Measurements1
Measurements2
Measurements3

This menu is used to display real-time measured values, including AC voltage, AC current, phase
angle and calculated quantities. These data can help users to acquaint the devices status. This
menu comprises following submenus. Please refer to section Measurement about the detailed
measured values.

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No.

Item

Measurements1

Measurements2

Measurements3

Function description
Display measured values from protection calculation DSP (Displayed in
secondary value)
Display measured values from fault detector DSP (Displayed in
secondary value)
Display measured primary values and other calculated quantities

8.2.3.2 Status
Main Menu

Status

Inputs
Outputs
Superv State

This menu is used to display real time input signals, output signals and alarm signals of the device.
These data can help users to acquaint the devices status. This menu comprises following
submenus. Please respectively refer to section Signal List about the detailed introduction of input
signals and output signals, and section Supervision Alarms about the detailed introduction of
alarm signals.
No.

Item

Function description

Inputs

Display all input signal states

Outputs

Display all output signal states

Superv State

Display supervision alarm states

The submenu Inputs comprises the following command menus.


Main Menu

Status

Inputs

Contact Inputs
GOOSE Inputs
Prot Ch Inputs

No.
1

Item
Contact Inputs

Function description
Display states of binary inputs derived from opto-isolated channels

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2

GOOSE Inputs

Display states of GOOSE binary inputs.

Prot Ch Inputs

Display states of binary inputs received from protection channel.

The submenu Outputs comprises the following command menus.


Main Menu

Status

Outputs

Contact Outputs
GOOSE Outputs
Interlock Status
Prot Ch Outputs

No.

Item

Function description

Contact Outputs

Display states of contact binary outputs

GOOSE Outputs

Display states of GOOSE binary outputs

Interlock Status

Display states of interlock result of each remote control.

Prot Ch Outputs

Display states of channel outputs

The submenu Superv State comprises the following command menus.


Main Menu

Status

Superv State

Prot Superv
FD Superv
GOOSE Superv
SV Superv

No.

Item

Function description

Prot Superv

Display states of self-supervision signals from protection calculation DSP

FD Superv

Display states of self-supervision signals from fault detector DSP

GOOSE Superv

Display states of GOOSE self-supervision signals

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4

SV Superv

Display states of SV self-supervision signals

8.2.3.3 Records
Main Menu

Records

Disturb Records
Superv Events
IO Events
Device Logs
Control Logs
Clear Records

This menu is used to display all kinds of records, including the disturbance records, supervision
events, binary events and device logs, so that the operator can load to view and use as the
reference of analyzing accidents and repairing the device. All records are stored in non-volatile
memory, it can still record them even if it loses its power.
This menu comprises the following submenus.
No.

Item

Function description

Disturb Records

Display disturbance records of the device

Superv Events

Display supervision events of the device

IO Events

Display binary events of the device

Device Logs

Display device logs of the device

Control Logs

Display control logs of the device

Clear Records

Clear all records.

8.2.3.4 Settings
Main Menu

Settings

System Settings
Prot Settings
BCU Settings
Logic Links
Device Setup

This menu is used to check the device setup, system parameters, protection settings and logic

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links settings, as well as modifying any of the above setting items. Moreover, it can also execute
the setting copy between different setting groups.
This menu comprises the following submenus.
No.

Item

Function description

System Settings

Check or modify the system parameters

Prot Settings

Check or modify the protection settings

BCU Settings

Check or modify the measurement and control settings

Logic Links

Device Setup

Check or modify the logic links settings, including function links, SV links,
GOOSE links and spare links
Check or modify the device setup

The submenu Prot Settings includes the following command menus.

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Main Menu

Settings

Prot Settings

Line Settings
FD Settings
AuxE Settings
Direction Settings
Pilot Scheme Settings
Rmt CommCh Settings
DPFC Dist Settings
LoadEnch Settings
Mho Dist Settings
Quad Dist Settings
ROC Settings
SOTF Settings
OC Settings
VTF OC Settings
BRC Settings
BFP Settings
Deadzone Settings
OV Settings
UV Settings
ThOvld Settings
PD Settings
Stub Settings
FreqProt Settings
MiscProt Settings
VTS/CTS Settings
Trip Logic Settings
AR/Syn Settings
Copy Settings

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No.

Item

Function description

Line Settings

Check or modify line parameters

FD Settings

Check or modify fault detector element settings

AuxE Settings

Check or modify auxiliary element settings

Direction Settings

Check or modify direction control element settings

Pilot Scheme Settings

Rmt CommCh Settings

Check or modify optical pilot channel settings

DPFC Dist Settings

Check or modify DPFC distance protection settings

LoadEnch Settings

Check or modify load encroachment settings

Mho Dist Settings

Check or modify distance protection with mho characteristic settings

10

Quad Dist Settings

Check or modify distance protection with Quad characteristic settings

11

ROC Settings

Check or modify directional earth-fault protection settings

12

SOTF Settings

Check or modify SOTF distance and overcurrent protection settings

13

OC Settings

Check or modify phase overcurrent protection settings

14

VTF OC Settings

Check or modify overcurrent protection settings for VT circuit failure

15

BRC Settings

Check or modify broken conductor protection settings

16

BFP Settings

Check or modify breaker failure protection settings

17

Deadzone Settings

Check or modify dead zone settings

18

OV Settings

Check or modify overvoltage protection settings

19

UV Settings

Check or modify undervoltage protection settings

20

ThOvld Settings

Check or modify thermal overload protection settings

21

PD Settings

Check or modify pole discrepancy protection settings

22

Stub Settings

Check or modify stub overcurrent protection settings

23

FreqProt Settings

Check or modify frequency protection settings

24

MiscProt Settings

Check or modify miscellaneous settings

25

VTS/CTS Settings

Check or modify VT circuit supervision and CT circuit supervision settings

26

Trip Logic Settings

Check or modify trippling logic settings

27

AR/Syn Settings

Check or modify synchronism check and auto-reclosing settings

28

Copy Settings

Copy setting between different setting groups

Check or modify pilot distance protection and pilot directional earth-fault


protection settings

The submenu BCU Settings includes the following command menus.

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Main Menu

Settings

BCU Settings

Syn Settings
BI Settings
Control Settings
Interlock Settings

No.

Item

Function description

Syn Settings

Check or modify manual sysnchronism check settings

BI Settings

Check or modify binary input settings

Control Settings

Check or modify control settings

Interlock Settings

Check or modify interlock settings

The submenu Logic Links comprises the following command menus.


Main Menu

Settings

Logic Links

Function Links
GOOSE Links
SV Links
Spare Links

No.

Item

Function description

Function Links

Check or modify function links settings

GOOSE Links

Check or modify GOOSE links settings

SV Links

Check or modify SV links settings

Spare Links

Check or modify spare links settings (used for programmable logic)

The submenu GOOSE Links includes the following command menus.

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Main Menu

Settings

Logic Links

GOOSE Links

GOOSE Send Links


GOOSE Recv Links

No.

Item

Function description

GOOSE Send Links

Check or modify GOOSE sending links settings

GOOSE Recv Links

Check or modify GOOSE receiving links settings

The submenu Device Setup comprises the following command menus.


Main Menu

Settings

Device Setup

Device Settings
Comm Settings
Label Settings

No.

Item

Function description

Device Settings

Check or modify the device settings.

Comm Settings

Check or modify the communication settings.

Label Settings

Check or modify the label settings of each protection element.

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8.2.3.5 Print
Main Menu

Print

Device Info
Settings
Disturb Records
Superv Events
IO Events
Prot Ch Superv
Prot Ch Statistics
Device Status
Waveforms
IEC103 Info
Cancel Print

This menu is used to print device description, settings, all kinds of records, waveforms, information
related with IEC60870-5-103 protocol, channel state and channel statistic.
This menu comprises the following submenus.
No.
1

Item
Device Info

Function description
Print the description information of the device, including software
version.
Print device setup, system parameters, protection settings and logic

Settings

links settings. It can print by different classifications as well as printing all


settings of the device. Besides, it can also print the latest modified
settings.

Disturb Records

Print the disturbance records

Superv Events

Print the supervision events

IO Events

Print the binary events


Print the self-check information of optical fibre channel, which is made of

Prot Ch Superv

some hexadecimal characters and used to developer analyze channel


state

Prot Ch Statistics

Device Status

Print the statistic report of optical fibre channel, which is formed A.M.
9:00 every day
Print the current state of the device, including the sampled value of
voltage and current, the state of binary inputs, setting and so on

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9

Waveforms

Print the recorded waveforms

10

IEC103 Info

Print 103 Protocol information, including function type (FUN),


information serial number (INF), general classification service group
number, and channel number (ACC)
11

Cancel Print

Cancel the print command

The submenu Settings comprises the following submenus.


Main Menu

Print

Settings

System Settings
Prot Settings
BCU Settings
Logic Links
Device Setup
All Settings
Latest Chgd Settings

No.

Item

Function description

System Settings

Print the system parameters

Prot Settings

Print the protection settings

BCU Settings

Print the measurement and control settings

Logic Links

Print the logic links settings

Device Setup

Print the settings related to device setup

All Settings

Latest Chgd Settings

Print all settings including device setup, system parameters, protection


settings and logic links settings
Print the setting latest modified

The submenu Prot Settings comprises the following command menus.

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Main Menu

Print

Settings

Prot Settings

Line Settings
FD Settings
AuxE Settings
Direction Settings
Pilot Scheme Settings
Rmt CommCh Settings
DPFC Dist Settings
LoadEnch Settings
Mho Dist Settings
Quad Dist Settings
ROC Settings
SOTF Settings
OC Settings
VTF OC Settings
BRC Settings
BFP Settings
Deadzone Settings
OV Settings
UV Settings
ThOvld Settings
PD Settings
Stub Settings
FreqProt Settings
MiscProt Settings
VTS/CTS Settings
Trip Logic Settings
AR/Syn Settings
All Settings

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No.

Item

Function description

Line Settings

Print line parameters

FD Settings

Print fault detector element settings

AuxE Settings

Print auxiliary element settings

Direction Settings

Print direction control element settings

Pilot Scheme Settings

Rmt CommCh Settings

Print optical pilot channel settings

DPFC Dist Settings

Print y DPFC distance protection settings

LoadEnch Settings

Print load encroachment settings

Mho Dist Settings

Print distance protection with mho characteristic settings

10

Quad Dist Settings

Print distance protection with Quad characteristic settings

11

ROC Settings

Print directional earth-fault protection settings

12

SOTF Settings

Print SOTF distance and overcurrent protection settings

13

OC Settings

Print phase overcurrent protection settings

14

VTF OC Settings

Print overcurrent protection settings for VT circuit failure

15

BRC Settings

Print broken conductor protection settings

16

BFP Settings

Print breaker failure protection settings

17

Deadzone Settings

Print dead zone settings

18

OV Settings

Print overvoltage protection settings

19

UV Settings

Print undervoltage protection settings

20

ThOvld Settings

Print thermal overload protection settings

21

PD Settings

Print pole discrepancy protection settings

22

Stub Settings

Print stub overcurrent protection settings

23

FreqProt Settings

Print frequency protection settings

24

MiscProt Settings

Print miscellaneous settings

25

VTS/CTS Settings

Print VT circuit supervision and CT circuit supervision settings

26

Trip Logic Settings

Print trippling logic settings

27

AR/Syn Settings

Print synchronism check and auto-reclosing settings

28

All Settings

Print all settings included in Prot Settings submenu

Print pilot distance protection and pilot directional earth-fault protection


settings

The submenu BCU Settings includes the following command menus.

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Main Menu

Print

Settings

BCU Settings

Syn Settings
BI Settings
Control Settings
Interlock Settings
All Settings

No.

Item

Function description

Syn Settings

Print manual sysnchronism check settings

BI Settings

Print binary input settings

Control Settings

Print control settings

Interlock Settings

Print interlock settings

All Settings

Print all settings included in BCU Settings submenu

The submenu Logic Links comprises the following command menus.


Main Menu

Print

Settings

Logic Links

Function Links
GOOSE Links
SV Links
Spare Links
All Settings

No.
1

Item
Function Links

Function description
Print function links settings

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2

GOOSE Links

Print GOOSE links settings

SV Links

Print SV links settings

Spare Links

Print spare links settings (used for programmable logic)

All Settings

Print all settings included in Logic Links submenu

The submenu GOOSE Links comprises the following command menus.


Main Menu

Print

Settings

Logic Links

GOOSE Links

GOOSE Send Links


GOOSE Recv Links

No.

Item

Function description

GOOSE Send Links

Print GOOSE sending links settings

GOOSE Recv Links

Print GOOSE receiving links settings

The submenu Device Setup comprises the following command menus.


Main Menu

Print

Settings

Device Setup

Device Settings
Comm Settings
Label Settings
All Settings

No.

Item

Function description

Device Settings

Print the device settings.

Comm Settings

Print the communication settings.

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3

Label Settings

Print the label settings of each protection element.

All Settings

Print all settings included in Device Setup submenu

The submenu Prot Ch Superv comprises the following command menus.


Main Menu

Print

Prot Ch Superv

Channel 1
Channel 2

No.

Item

Channel 1

Channel 2

Function description
Print the self-check information of optical fibre channel 1, which is made of some
hexadecimal characters and used to developer analyze channel state
Print the self-check information of optical fibre channel 2, which is made of some
hexadecimal characters and used to developer analyze channel state

The submenu Prot Ch Statistics includes the following command menus.


Main Menu

Print

Prot Ch Statistics

Channel 1
Channel 2

No.

Item

Channel 1

Channel 2

Function description
Print the statistic report of optical fibre channel 1, which is formed A.M. 9:00 every
day
Print the statistic report of optical fibre channel 2, which is formed A.M. 9:00 every
day

The submenu Waveforms includes the following command menus.

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Main Menu

Print

Waveforms

Wave

No.
1

Item

Function description

Wave

Print the recorded current and voltage waveforms

8.2.3.6 Local Cmd


Main Menu

Local Cmd

Reset Target
Trig Oscillograph
Control
Download
Clear Counter
Clear AR Counter
Clear Energy Counter

This menu is used to reset the tripping relay with latch, indicator LED, LCD display, and as same
as the reset function of binary inputs. This menu provides a method of manually recording the
current waveform data of the device under normal condition for printing and uploading SAS.
Besides, it can send out the request of program download, clear statistic information about
GOOSE, SV, AR, FO channel and energy.
This menu comprises the following submenus.
No.

Item

Function description

Reset Target

Reset the local signal, indicator LED, LCD display and so on

Trig Oscillograph

Trigger waveform recording

Control

Manually operating to trip, close output or for signaling purpose

Download

Send out the request of downloading program

Clear Counter

Clear GOOSE, SV and FO channel statistic data

Clear AR Counter

Clear AR statistic data

Clear Energy Counter

Clear all energy metering values (i.e., PHr+_Pri, PHr-_Pri, Qr+_Pri,

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QHr-_Pri)

8.2.3.7 Information
Main Menu

Information

Version Info
Board Info

In this menu, LCD can display software information of all kinds of intelligent plug-in modules,
which consists of version, creating time of software, CRC codes and management sequence
number. Besides, plug-in module information can also be viewed.
This menu comprises the following command menus.
No.

Item

Function description
Display software information of DSP module, MON module and HMI module,

Version Info

which consists of version, creating time of software, CRC codes and


management sequence number.

Board Info

Monitor the current working state of each intelligent module.

8.2.3.8 Test
Main Menu

Test

Prot Ch Counter
GOOSE Comm Counter
SV Comm Counter
Device Test
AR Counter

This menu is mainly used for developers to debug the program and for engineers to maintain the
device. It can be used to fulfill the communication test function. It is also used to generate all kinds
of reports or events to transmit to the SAS without any external input, so as to debug the
communication on site. Besides, it can also display statistic information about GOOSE, SV, AR
and FO channel.
This menu comprises the following submenus.

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No.

Item

Function description

Prot Ch Counter

Check communication statistics data of protection FO channel

GOOSE Counter

Check communication statistics data of GOOSE

SV Counter

Check communication statistics data of SV (Sampled Values)


Automatically generate all kinds of reports or events to transmit to SCADA,

including disturbance records, self-supervision events and binary events. It can

Device Test

realize the report uploading by different classification, as well as the uploading


of all kinds of reports

AR Counter

Check AR counters

The submenu Prot Ch Counter comprises the following command menus.


Main Menu

Test

Prot Ch Counter

Ch1 Counter
Ch2 Counter

No.

Item

Function description

Ch1 Counter

Check communication statistic information of channel 1

Ch2 Counter

Check communication statistic information of channel 2

The submenu Device Test comprises the following submenus.


Main Menu

Test

Device Test

Disturb Events
Superv Events
IO Events

No.

Item

Disturb Events

Superv Events

Function description
View the relevant information about disturbance records (only used for
debugging persons)
View the relevant information about supervision events (only used for

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debugging persons)
3

View the relevant information about binary events (only used for debugging

IO Events

persons)

Users can respectively execute the test automatically or manually by selecting commands All
Test or Select Test.
The submenu Disturb Events comprises the following command menus.
Main Menu

Test

Device Test

Disturb Events

All Test
Select Test

No.

Item

Description

All Test

Ordinal test of all protection elements

Select Test

Selective test of corresponding classification

The submenu Superv Events comprises the following command menus.


Main Menu

Test

Device Test

Superv Events

All Test
Select Test

No.

Item

Description

All Test

Ordinal test of all self-supervisions

Select Test

Selective test of corresponding classification

The submenu IO Events comprises the following command menus.

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Main Menu

Test

Device Test

IO Events

All Test
Select Test

No.

Item

Description

All Test

Ordinal test of change of all binary inputs

Select Test

Selective test of corresponding classification

8.2.3.9 Clock
The current time of internal clock can be viewed here. The time is displayed in the form
YY-MM-DD and hh:mm:ss. All values are presented with digits and can be modified.
8.2.3.10 Language
This menu is mainly used to set LCD display language.

8.3 LCD Display


8.3.1 Overview
There are some kinds of LCD display, SLD (single line diagram) display, disturbance records,
supervison events, IO events, control logs and device logs. Disturbance records and supervison
events will not disappear until them are acknowledged by pressing the RESET button in the
protection panel (i.e. energizing the binary input [BI_RstTarg]). If any event is detected, the
corresponding event display will pop up automatically, and user can keep pressing ENT and then
press ESC to switch between normal display and event display. IO events will be displayed for 5s
and then it will return to the previous display interface automatically. Device logs will not pop up
and can only be viewed by navigating the corresponding menu.

8.3.2 Normal Display


After the device is powered and entered into the initiating interface, it takes tens of seconds to
complete the initialization of the device. During the initialization of the device, the HEALTHY
indicator lamp of the device goes out.
The device can display single line diagram (SLD) and primary operation information, it can support
wiring configuration function. LCD configuration file can be downloaded via the network. Remote
control operation through single line diagram is also supported.

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Under normal condition, LCD will display the following interface. LCD adopts white color as its
backlight that is activated if once there is any keyboard operation, moreover, the backlight will be
extinguished automatically if no keyboard operation is detected for a duration.

2010-06-08 10:10:00
Ia

0.00A

Ib

0.00A

Ic

0.00A

3I0

0.00A

Ua

0.02V

Ub

0.00V

Uc

0.00V

3U0

0.02V

U_Syn

0.00V

50.00Hz
Addr 24343

Group 01

The content displayed on the screen contains: the current date and time of the device (with a
format of yyyy-mm-dd hh:mm:ss:), the active setting group number, three-phase current sampling
value, residual current sampling value, three-phase voltage sampling value, residual voltage
sampling value, the synchronism voltage sampling value, line frequency and the address relevant
to IP address of Ethernet A. If all the sampling values of the voltage and the current cant be fully
displayed within one screen, they will be scrolling-displayed automatically from the top to the
bottom.
If IP address of Ethernet A is xxx.xxx.a.b, the displayed address equals to (a256+b). For
example, If IP address of Ethernet A is 198.087.095.023, the displayed address will be 95
256+23=24343.
If the device has detected any abnormal state, itll display the self-check alarm information.
S indicates that device clock is synchronized. If S disappears, it means that device clock is not
synchronized.

8.3.3 Display Disturbance Records


This device can store up to 32 groups of disturbance records with fault waveform. Each group
consists of disturbance records of operation elements and corresponding fault detector elements.
Up to 1024 disturbance records can be stored in this device. If there is protection element
operation, LCD will automatically display the latest group of disturbance records, and two kinds of
LCD display interfaces will be available depending on whether there are supervision events or not.
For the situation that the disturbance records and the supervision events coexist, the upper half
part is the disturbance record, and the lower half part is the supervision event. The following items
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are listed in the upper half part: record No., record name, generation time of the disturbance
record. If there is protection element operation, faulty phase and relative operation time (with
reference to the corresponding fault detector element) will be displayed. If the disturbance records
can not be displayed in one page, they will be displayed in several pages alternately.
If there is no supervision event, disturbance records will be displayed as shown in the following
figure.

2013-01-15 13:22:23:669

NO.001
0000ms

Disturb

FD.DPFC.Pkp

0024ms

AB

21Q.Z1.Op

If the device has the supervision event, the display interface will show the disturbance record and
the supervision event at the same time.

2013-01-15 13:22:23:669

NO.001
0000ms

Disturb

FD.DPFC.Pkp

0024ms

AB

21Q.Z1.Op

Superv Events
Alm_Device

NO.001

shows the SOE No. of the disturbance record.

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2013-01-15 13:22:23:669

shows the time of the disturbance record, the format is


yyyy-mm-dd hh:mm:ss:fff.

Disturb

shows the title of the disturbance record.

0000ms FD.DPFC.Pkp

shows fault detector element and its operation time (set as


0000ms fixedly).

0024ms

shows operation element and its relative operation time (with


reference to the corresponding fault detector element).

AB

21Q.Z1.Op

All the protection elements have been listed in chapter Operation Theory, and please refer to
each protection element for details. The reports related to oscillography function are showed in the
following table.
Table 8.3-1 Tripping report messages
No.

Message

Description

TrigDFR_Man

Oscillography function is triggered manually.

TrigDFR_Rmt

Oscillography function is triggered remotely.


Oscillography function is triggered by binary input [BI_TrigDFR]. The

TrigDFR_BI

binary input [BI_TrigDFR] is configurable, and it can be designated to


internal signal or external input.

8.3.4 Display Supervision Event


This device can store 1024 pieces of supervision events. During the running of the device, the
supervision event of hardware self-check errors or system running abnormity will be displayed
immediately.

Superv Events

Alm_Device
Alm_Version

indicates that device clock is synchronized. If S disappears, it


means that device clock is not synchronized.

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Superv Events

shows the title of the supervision events.

Alm_Device

shows the contents of supervision events.

Alm_Version

8.3.5 Display IO Events


This device can store 1024 pieces of binary events. During the running of the device, the binary
input will be displayed once its state has changed, i.e. from 0 to 1 or from 1 to 0.

NO.001

2013-01-15 13:31:23:669

BI_Maintenance

IO Chg
0

NO.001

shows the No. of the binary event.

2013-01-15 13:31:23:669

shows date and time when the report occurred, the format is
yyyy-mm-dd hh:mm:ss:fff.

IO Chg

shows the title of the binary event.

BI_Maintenance

01

shows the state change of binary input, including binary input


name, original state and final state.

8.3.6 Display Device Logs


This device can store 1024 pieces of device logs. Please refer to section 8.4.3 for LCD operation

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4. Device Logs NO.4


2008-11-28 10:18:47:569ms
Reboot

Device Logs NO. 4

shows the title and the number of the device log

2008-11-28 10:18:47:569

shows date and time when the report occurred, the format is
yearmonth-date and hour:minute:second:millisecond

Reboot

shows the manipulation content of the device log

User operating information listed below may be displayed.


Table 8.3-2 User operating event list
No.

Message

Description

Reboot

The device has been reboot.

Settings_Chg

The devices settings have been changed.

ActiveGrp_Chgd

Active setting group has been changed.

Report_Cleared

All reports have been deleted. (Device logs can not be deleted)

Waveform_Cleared

All waveforms have been deleted.

Process_Exit

A process has exited.

Counter_Cleared

Clear counter

It will be displayed on LCD before disturbance records and supervision events are confirmed. Only
pressing both ENT and ESC at the same time can switch among disturbance records,
supervision events and the normal running state of the device to display it. IO events will be
displayed for 5s and then it will return to the previous display interface automatically.

8.4 Keypad Operation


8.4.1 View Device Measurements
The operation is as follows:
1.

Press the to enter the main menu;

2.

Press the or to move the cursor to the Measurements menu, and then press

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the ENT or to enter the menu;


3.

Press the or to move the cursor to any command menu, and then press the
ENT to enter the menu;

4.

Press the or to page up/down (if all information cannot be displayed in one
display screen, one screen can display 14 lines of information at most);

5.

Press the or to select pervious or next command menu;

6.

Press the ENT or ESC to exit this menu (returning to the Measurements menu);

8.4.2 View Device Status


The operation is as follows:
1.

Press the key to enter the main menu.

2.

Press the key or to move the cursor to the Status menu, and then press the
ENT or to enter the menu.

3.

Press the key or to move the cursor to any command menu item, and then press
the key ENT to enter the submenu.

4.

Press the or to page up/down (if all information cannot be displayed in one
display screen, one screen can display 14 lines of information at most).

5.

Press the key or to select pervious or next command menu.

6.

Press the key ENT or ESC to exit this menu (returning to the Status menu).

8.4.3 View Device Records


The operation is as follows:
1.

Press the to enter the main menu;

2.

Press the or to move the cursor to the Records menu, and then press the
ENT or to enter the menu;

3.

Press the or to move the cursor to any command menu, and then press the
ENT to enter the menu;

4.

Press the or to page up/down;

5.

Press the or to select pervious or next record;

6.

Press the or to select pervious or next command menu;

7.

Press the ENT or ESC to exit this menu (returning to the Records menu);

8.4.4 Print Device Records


The operation is as follows:
1.

Press the to enter the main menu;

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2.

Press the or to move the cursor to the Print menu, and then press the ENT or
to enter the menu;

3.

Press the or to move the cursor to any command menu, and then press the
ENT to enter the menu;

Selecting the Disturb Records, and then press the or to select pervious
or next record. After pressing the key ENT, the LCD will display Start Printing... ,
and then automatically exit this menu (returning to the menu Print). If the printer
doesnt complete its current print task and re-start it for printing, and the LCD will
display Printer Busy. Press the key ESC to exit this menu (returning to the
menu Print).

Selecting the command menu Superv Events or IO Events, and then press the
key or to move the cursor. Press the or to select the starting and
ending numbers of printing message. After pressing the key ENT, the LCD will
display Start Printing, and then automatically exit this menu (returning to the
menu Print). Press the key ESC to exit this menu (returning to the menu Print).

4.

If selecting the command menu Device Info, Device Status or IEC103 Info, press
the key ENT, the LCD will display Start printing.., and then automatically exit this menu
(returning to the menu Print).

5.

If selecting the Settings, press the key ENT or to enter the next level of menu.

6.

After entering the submenu Settings, press the key or to move the cursor, and
then press the key ENT to print the corresponding default value. If selecting any item to
printing:
Press the key or to select the setting group to be printed. After pressing the key
ENT, the LCD will display Start Printing, and then automatically exit this menu
(returning to the menu Settings). Press the key ESC to exit this menu (returning to the
menu Settings).

7.

After entering the submenu Waveforms, press the or to select the waveform
item to be printed and press ENT to enter. If there is no any waveform data, the LCD will
display No Waveform Data! (Before executing the command menu Waveforms, it is
necessary to execute the command menu Trig Oscillograph in the menu Local Cmd,
otherwise the LCD will display No Waveform Data!). With waveform data existing:

Press the key or to select pervious or next record. After pressing the key ENT, the LCD
will display Start Printing, and then automatically exit this menu (returning to the menu
Waveforms). If the printer does not complete its current print task and re-start it for printing, and
the LCD will display Printer Busy. Press the key ESC to exit this menu (returning to the menu
Waveforms).

8.4.5 View Device Setting


The operation is as follows:

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1.

Press the to enter the main menu;

2.

Press the or to move the cursor to the Settings menu, and then press the
ENT or to enter the menu;

3.

Press the or to move the cursor to any command menu, and then press the
ENT to enter the menu;

4.

Press the or to move the cursor;

5.

Press the + or - to page up/down;

6.

Press the or to select pervious or next command menu;

7.

Press the ESC to exit this menu (returning to the menu Settings).
Note!
If the displayed information exceeds 14 lines, the scroll bar will appear on the right side of
the LCD to indicate the quantity of all displayed information of the command menu and the
relative location of information where the current cursor points at.

8.4.6 Modify Device Setting


The operation is as follows:
1.

Press the to enter the main menu;

2.

Press the or to move the cursor to the Settings menu, and then press the
ENT or to enter the menu;

3.

Press the or to move the cursor to any command menu, and then press the
ENT to enter the menu;

4.

Press the or to move the cursor;

5.

Press the + or - to page up/down;

6.

Press the or to select pervious or next command menu;

7.

Press the ESC to exit this menu (returning to the menu Settings );

8.

If selecting the command menu System Settings, move the cursor to the setting item
to be modified, and then press the ENT;

Press the or to modify the value (if the modified value is of multi-bit, press the or
to move the cursor to the digit bit, and then press the or to modify the value), press the
ESC to cancel the modification and return to the displayed interface of the command menu
System Settings. Press the ENT to automatically exit this menu (returning to the displayed
interface of the command menu System Settings).
Move the cursor to continue modifying other setting items. After all setting values are modified,
press the , or ESC, and the LCD will display Save or Not?. Directly press the ESC or

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press the or to move the cursor. Select the Cancel, and then press the ENT to
automatically exit this menu (returning to the displayed interface of the command menu System
Settings).
Press the or to move the cursor. Select No and press the ENT, all modified setting item
will restore to its original value, exit this menu (returning to the menu Settings).
Press the or to move the cursor to select Yes, and then press the ENT, the LCD will
display password input interface.

Password:

____

Input a 4-bit password (, , and ). If the password is incorrect, continue inputting it,
and then press the ESC to exit the password input interface and return to the displayed interface
of the command menu System Settings. If the password is correct, LCD will display Save
Setting Now, and then exit this menu (returning to the displayed interface of the command
menu System Settings), with all modified setting items as modified values.
Note!
For different setting items, their displayed interfaces are different but their modification
methods are the same. The following is ditto.
9.

If selecting the submenu Prot Settings, and press ENT to enter. After selecting
different command menu, the LCD will display the following interface: (take FD
Settings as an example)

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Line Settings

Please Select Group for Config


Active Group:

01

Selected Group:

02

Press the or to modify the value, and then press the ENT to enter it. Move the cursor to
the setting item to be modified, press the ENT to enter.
Take the setting [FD.DPFC.I_Set] as an example is selected to modify, then press the ENT to
enter and the LCD will display the following interface. is shown the or to modify the value
and then press the ENT to confirm.

FD.DPFC.I_Set

Current Value

0.200

Modified Value

0.202

Min Value

0.050

Max Value

30.000

Note!
After modifying protection settings in current active setting group or system parameters of
the device, the HEALTHY LED indicator the device will be lit off, and the MON module
will check the new settings. If the abnormality is detected during the setting check,
corresponding alarm signals will be issued. Moreover, if the critical error is detected, the
device will be blocked.

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8.4.7 Copy Device Setting


The operation is as follows:
1.

Press the to enter the main menu;

2.

Press the or to move the cursor to the Settings menu, and then press the
ENT or to enter the menu;

3.

Press the or to move the cursor to the command menu Copy Settings, and
then press the ENT to enter the menu.

Copy Settings
Active Group:

01

Copy To Group:

02

Press the or to modify the value. Press the ESC, and return to the menu Settings.
Press the ENT, the LCD will display the interface for password input, if the password is incorrect,
continue inputting it, press the ESC to exit the password input interface and return to the menu
Settings. If the password is correct, the LCD will display copy setting OK!, and exit this menu
(returning to the menu Settings).

8.4.8 Switch Setting Group


The operation is as follows:
1.

Exit the main menu;

2.

Press the GRP

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Change Active Group

Active Group:

01

Change To Group:

02

Press the or to modify the value, and then press the ESC to exit this menu (returning to
the main menu). After pressing the ENT, the LCD will display the password input interface. If the
password is incorrect, continue inputting it, and then press the ESC to exit the password input
interface and return to its original state. If the password is correct, the HEALTHY indicator lamp
of the protection device will go out, and the protection device will re-check the protection setting. If
the check doesnt pass, the protection device will be blocked. If the check is successful, the LCD
will return to its original state.

8.4.9 Delete Device Records


The operation is as follows:
1.

Exit the main menu;

2.

Press the , , , and ENT; Press the ESC to exit this menu (returning to
the original state). Press the ENT to carry out the deletion.

Press <ENT> To Clear


Press <ESC> To Exit

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Note!
The operation of deleting device message will delete all messages saved by the protection
device, including disturbance records, supervision events, binary events, but not including
device logs. Furthermore, the message is irrecoverable after deletion, so the application of
the function shall be cautious.

8.4.10 Remote Control


Control operation method is introduced as below:
1.

Press the key to enter the main menu.

2.

Press the key or to move the cursor to the command menu Local Cmd, and
then press the key ENT to enter submenus. Press the key or to move the
cursor to the command menu Control, and then press the key ENT to enter and the
following display will be shown on LCD.

Password:
000

Input a 3-bit password (111). If the password is incorrect, continue inputting it, and then press the
ESC to exit the password input interface and return to the displayed interface of the command
menu Control. If the password is correct, it will go to the following step.
3.

Press the key or to move the cursor to the control object and press the key
ENT to select control object.

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Control

4.

1.

Step1: select Control Object


CSWI01

2.

CSWI02

3.

CSWI03

4.

CSWI04

5.

CSWI05

6.

CSWI06

7.

CSWI07

8.

CSWI08

9.

CSWI09

10.

CSWI10

Press the key or to select control command press the key ENT to the next step.

Three control commands are optional:


1) Open (Step down): Remote open
2) Close (Step up): Remote close
3) Stop: Reserved
CSWI01
Step2: select Control Command
Open(Lower)

Close(Raise)

NoCheck

SynchroCheck

LoopCheck

EF Line Selection

InterlockChk

InterlockNotChk

Select

Execute

(Stop)
DeadCheck

Cancel

Result

5.

Press the key or to select synchronism check mode and press the key ENT to
the next step.

Five synchronism check modes are optional:


1) NoCheck: Without any check
2) SynchroCheck: Synchronism-check mode

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3) DeadCheck: Dead check mode


4) LoopCheck: Reserved
5) EF Line Selection: Reserved
CSWI01
Step3: select Execution Condition
Open(Lower)

Close(Raise)

NoCheck

SynchroCheck

LoopCheck

EF Line Selection

InterlockChk

InterlockNotChk

Select

Execute

(Stop)
DeadCheck

Cancel

Result

6.

Press the key or to select interlock mode and press the key ENT to next step.

Two interlock check modes are optional:


1) InterlockChk: Check interlocking criteria
2) InterlockNotChk: Not check interlocking criteria
CSWI01
Step4: select Interlock Condition
Open(Lower)

Close(Raise)

NoCheck

SynchroCheck

LoopCheck

EF Line Selection

InterlockChk

InterLockNotChk

Select

Execute

(Stop)
DeadCheck

Cancel

Result

7.

Press the key or to select control type and press the key ENT.

As shown in the following figure, operation results will be shown after Result at the bottom of the
LCD.

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Three synchronism control types are optional:


1) Select: Select control object
2) Execute: Execute control operation
3) Cancel: Cancel control operation
CSWI01
Step5: select Control Type
Open(Lower)

Close(Raise)

NoCheck

SynchroCheck

LoopCheck

EF Line Selection

InterlockChk

InterLockNotChk

Select

Execute

(Stop)
DeadCheck

Cancel

Result

Note!
Exectue operation must be operated after Select operation.

8.4.11 Modify Device Clock


The operation is as follows:
1.

Press the to enter the main menu;

2.

Press the or to move the cursor to the Clock menu, and then press the ENT
to enter clock display

3.

Press the or to move the cursor to the date or time to be modified;

4.

Press the + or - to modify value, and then press the ENT to save the modification
and return to the main menu;

5.

Press the ESC to cancel the modification and return to the main menu.

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Clock
Year:

2008

Month:

11

Day:

28

Hour:

20

Minute:

59

Second:

14

8.4.12 View Module Information


The operation is as follows:
1.

Press the to enter the main menu;

2.

Press the or to move the cursor to the Information menu, and then press the
ENT or to enter the menu;

3.

Press the or to move the cursor to the command menu Board Info, and then
press the ENT to enter the menu;

4.

Press the or to move the scroll bar;

5.

Press the ENT or ESC to exit this menu (returning to the Information menu).

8.4.13 Check Software Version


The operation is as follows:
1.

Press the to enter the main menu.

2.

Press the or to move the cursor to the Information menu, and then press the
ENT to enter the submenu.

3.

Press the key or to move the cursor to the command menu Version Info, and
then press the key ENT to display the software version.

4.

Press the ESC to return to the main menu.

8.4.14 Communication Test


The operation is as follows:
1.

Press the key to enter the main menu.

2.

Press the key or to move the cursor to the Test menu, and then press the key
ENT or to enter the menu.

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3.

Press the key or to move the cursor to the submenu Device Test, and then
press the key ENT to enter the submenu,to select test item. If Disturb Events
Superv Events or IO Events is selected, two options All Test and Select Test are
provided.

4.

Press the key or to move the cursor to select the corresponding command menu
All Test or Select Test. If selecting the All Test, press the ENT, and the device will
successively carry out all operation element message test one by one.

5.

If Select Test is selected, press the key ENT. Press the or to page up/down,
and then press the key or to move the scroll bar. Move the cursor to select the
corresponding protection element. Press the key ENT to execute the communication
test of this protection element, the substation automatic system (SAS) will receive the
corresponding message.
Note!
If no input operation is carried out within 60s, exit the communication transmission and
return to the Test menu, at this moment, the LCD will display Communication Test
Timeout and Exiting....

Press the key ESC to exit this menu (returning to the menu Test, at this moment, the LCD will
display Communication Test Exiting.

8.4.15 Select Language


The operation is as follows:
1.

Press the key to enter the main menu.

2.

Press the key or to move the cursor to the command menu Language, and
then press the key ENT to enter the menu and the following display will be shown on
LCD.

Please Select Language:


1

English

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3.

Press the key or to move the cursor to the language user preferred and press
the key ENT to execute language switching. After language switching is finished, LCD
will return to the menu Language, and the display language is changed. Otherwise,
press the key ESC to cancel language switching and return to the menu Language.
Note!
LCD interface provided in this chapter is only a reference and available for explaining
specific definition of LCD. The displayed interface of the actual device may be some
different from it, so you shall be subject to the actual protection device.

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9 Configurable Function
Table of Contents
9 Configurable Function..................................................................... 9-a
9.1 Overview .......................................................................................................... 9-1
9.2 Introduction on PCS-Explorer Software ........................................................ 9-1
9.3 Signal List ........................................................................................................ 9-1
9.3.1 Input Signal ........................................................................................................................ 9-2
9.3.2 Output Signal ................................................................................................................... 9-10

List of Tables
Table 9.3-1 Input signals ...........................................................................................................9-2
Table 9.3-2 Output signals ......................................................................................................9-10

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9 Configurable Function

9.1 Overview
By adoption of PCS-Explorer software, it is able to make device configuration, function
configuration, LCD configuration, binary input and binary output configuration, LED indicator
configuration and programming logic for PCS-902.

9.2 Introduction on PCS-Explorer Software


PCS-Explorer software is developed in order to meet customers demand on functions of UAPC
platform device such as device configuration and programmable design. It selects substation as
the core of data management and the device as fundamental unit, supporting one substation to
govern many devices. The software provides on-line and off-line functions: on-line mode: Ethernet
connected with the device supporting IEC60870-5-103 and capable of uploading and downloading
configuration files through Ethernet net; off-line mode: off-line setting configuration. In addition, it
also supports programmable logic to meet customers demand.
After function configuration is finished, disabled protection function will be hidden in the device and
in setting configuration list of PCS-Explorer Software. The user can select to show or hide some
setting by this way, and modify the setting value.
Please refer to the instruction manual PCS-Explorer Auxiliary Software for details.
Overall functions:

Programmable logic (off-line function)

Device configuration (off-line function)

Function configuration (off-line function)

LCD configuration (off-line function)

LED indicators configuration (off-line function)

Binary signals configuration (off-line function)

Setting configuration (off-line & on-line function)

Real-time display of analogue and digital quantity of device (on-line function)

Display of sequence of report (SOE) (on-line function)

Analysis of waveform (off-line & on-line function)

File downloading/uploading (on-line function)

9.3 Signal List


If an input signal or output signal is gray in PCS-Explorer, it means that the input signal or output
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9 Configurable Function

signal is not configurable. Otherwise, it is configurable signal.

9.3.1 Input Signal


All input signals of this device are listed in the following table.
Table 9.3-1 Input signals
No.

Item

Description
Circuit breaker position supervision

52b_PhA

Normally closed auxiliary contact of phase A of corresponding circuit breaker

52b_PhB

Normally closed auxiliary contact of phase B of corresponding circuit breaker

52b_PhC

Normally closed auxiliary contact of phase C of corresponding circuit breaker

ManCls

External manual closing binary input, it is only applied to SOTF logic

52b

Normally closed contact of three-phase of circuit breaker

52a

Normally open contact of three-phase of circuit breaker


Control circuit failure (normally closed contact and normally open contact of

TCCS.Input

three-phase circuit breaker are all de-energized due to DC power loss of


control circuit)
Auxiliary element

AuxE.OCD.En

AuxE.OCD.Blk

10

AuxE.ROC1.En

11

AuxE.ROC1.Blk

12

AuxE.ROC2.En

13

AuxE.ROC2.Blk

14

AuxE.ROC3.En

15

AuxE.ROC3.Blk

16

AuxE.OC1.En

17

AuxE.OC1.Blk

18

AuxE.OC2.En

19

AuxE.OC2.Blk

20

AuxE.OC3.En

Current change auxiliary element enabling input, it is triggered from binary


input or programmable logic etc.
Current change auxiliary element blocking input, it is triggered from binary
input or programmable logic etc.
Stage 1 of residual current auxiliary element enabling input, it is triggered from
binary input or programmable logic etc.
Stage 1 of residual current auxiliary element blocking input, it is triggered from
binary input or programmable logic etc.
Stage 2 of residual current auxiliary element enabling input, it is triggered from
binary input or programmable logic etc.
Stage 2 of residual current auxiliary element blocking input, it is triggered from
binary input or programmable logic etc.
Stage 3 of residual current auxiliary element enabling input, it is triggered from
binary input or programmable logic etc.
Stage 3 of residual current auxiliary element blocking input, it is triggered from
binary input or programmable logic etc.
Stage 1 of phase current auxiliary element enabling input, it is triggered from
binary input or programmable logic etc.
Stage 1 of phase current auxiliary element blocking input, it is triggered from
binary input or programmable logic etc.
Stage 2 of phase current auxiliary element enabling input, it is triggered from
binary input or programmable logic etc.
Stage 2 of phase current auxiliary element blocking input, it is triggered from
binary input or programmable logic etc.
Stage 3 of phase current auxiliary element enabling input, it is triggered from

9-2

PCS-902 Line Distance Relay


Date: 2013-12-25

9 Configurable Function
No.

Item

Description
binary input or programmable logic etc.

21

AuxE.OC3.Blk

22

AuxE.UVD.En

23

AuxE.UVD.Blk

24

AuxE.UVG.En

25

AuxE.UVG.Blk

26

AuxE.UVS.En

27

AuxE.UVS.Blk

28

AuxE.ROV.En

29

AuxE.ROV.Blk

Stage 3 of phase current auxiliary element blocking input, it is triggered from


binary input or programmable logic etc.
Voltage change auxiliary element enabling input, it is triggered from binary
input or programmable logic etc.
Voltage change auxiliary element blocking input, it is triggered from binary
input or programmable logic etc.
Phase-to-ground under voltage auxiliary element enabling input, it is triggered
from binary input or programmable logic etc.
Phase-to-ground under voltage auxiliary element blocking input, it is triggered
from binary input or programmable logic etc.
Phase-to-phase under voltage auxiliary element enabling input, it is triggered
from binary input or programmable logic etc.
Phase-to-phase under voltage auxiliary element blocking input, it is triggered
from binary input or programmable logic etc.
Residual voltage auxiliary element enabling input, it is triggered from binary
input or programmable logic etc.
Residual voltage auxiliary element blocking input, it is triggered from binary
input or programmable logic etc.
Distance protection
DPFC distance protection enabling input, it is triggered from binary input or

30

21D.En

31

21D.Blk

32

LoadEnch.En

33

LoadEnch.Blk

34

21M.En

35

21M.Blk

36

21M.ZGx.En

37

21M.ZGx.Blk

38

21M.ZPx.En

39

21M.ZPx.Blk

40

21M.Zx.En_ShortDly

Enable accelerating zone x of distance protection (x=2, 3)

41

21M.Zx.Blk_ShortDly

Accelerating zone x of distance protection is disabled (x=2, 3)

programmable logic etc.


DPFC distance protection blocking input, it is triggered from binary input or
programmable logic etc.
Load trapezoid characteristic enabling input, it is triggered from binary input or
programmable logic etc.
Load trapezoid characteristic blocking input, it is triggered from binary input or
programmable logic etc.
Distance protection enabling input, it is triggered from binary input or
programmable logic etc.
Distance protection blocking input, it is triggered from binary input or
programmable logic etc.
Zone x of phase-to-ground distance protection enabling input, default value is
1 (x=1, 2, 3, 4)
Zone x of phase-to-ground distance protection blocking input, default value is
0 (x=1, 2, 3, 4)
Zone x of phase-to-phase distance protection enabling input, default value is
1 (x=1, 2, 3, 4)
Zone x of phase-to-phase distance protection blocking input, default value is
0 (x=1, 2, 3, 4)

PCS-902 Line Distance Relay

9-3
Date: 2013-12-25

9 Configurable Function
No.

Item

Description

42

21M.Z1.En_Instant

Enable zone 1 of distance protection operates without time delay

43

21Q.En

44

21Q.Blk

45

21Q.ZGx.En

46

21Q.ZGx.Blk

47

21Q.ZPx.En

48

21Q.ZPx.Blk

49

21Q.Zx.En_ShortDly

Enable accelerating zone x of distance protection (x=2, 3)

50

21Q.Zx.Blk_ShortDly

Accelerating zone x of distance protection is disabled (x=2, 3)

51

21Q.Z1.En_Instant

Enable zone 1 of distance protection operates without time delay

52

68.En

53

68.Blk

54

21M.En_PSBR

Enabling power swing blocking releasing (Mho characteristic)

55

21Q.En_PSBR

Enabling power swing blocking releasing (Quad characteristic)

56

21M.Blk_PSBR

Blocking power swing blocking releasing (Mho characteristic)

57

21Q.Blk_PSBR

Blocking power swing blocking releasing (Quad characteristic)

58

21SOTF.En

59

21SOTF.Blk

Distance protection enabling input, it is triggered from binary input or


programmable logic etc.
Distance protection blocking input, it is triggered from binary input or
programmable logic etc.
Zone x of phase-to-ground distance protection enabling input, default value is
1 (x=1, 2, 3, 4)
Zone x of phase-to-ground distance protection blocking input, default value is
0 (x=1, 2, 3, 4)
Zone x of phase-to-phase distance protection enabling input, default value is
1 (x=1, 2, 3, 4)
Zone x of phase-to-phase distance protection blocking input, default value is
0 (x=1, 2, 3, 4)

Power swing detection enabling input, it is triggered from binary input or


programmable logic etc.
Power swing detection blocking input, it is triggered from binary input or
programmable logic etc.

Distance SOTF protection enabling input, it is triggered from binary input or


programmable logic etc.
Distance SOTF protection blocking input, it is triggered from binary input or
programmable logic etc.
Optical pilot channel

60

FOx.En

Enabling channel x

61

FOx.Send1

Sending signal 1 of channel x

62

FOx.Send2

Sending signal 2 of channel x

63

FOx.Send3

Sending signal 3 of channel x

64

FOx.Send4

Sending signal 4 of channel x

65

FOx.Send5

Sending signal 5 of channel x

66

FOx.Send6

Sending signal 6 of channel x

67

FOx.Send7

Sending signal 7 of channel x

68

FOx.Send8

Sending signal 8 of channel x


Sending signal 9 of channel x (it is configured fixedly as sending permissive

69

FOx.Send9

signal 1 or sending A-phase permissive signal (only for phase-segregated


command scheme))

70

FOx.Send10

Sending signal 10 of channel x (it is configured fixedly as sending B-phase

9-4

PCS-902 Line Distance Relay


Date: 2013-12-25

9 Configurable Function
No.

Item

Description
permissive signal (only for phase-segregated command scheme))

71

FOx.Send11

Sending signal 11 of channel x (it is configured fixedly as sending C-phase


permissive signal (only for phase-segregated command scheme))
Sending signal 12 of channel x (it is configured fixedly as sending permissive

72

FOx.Send12

signal 1 when pilot directional earth-fault protection sharing pilot channel 1


with pilot distance protection, or sending permissive signal 2 only for pilot
directional earth-fault protection adopting independent pilot channel 2)

Pilot distance protection and pilot directional earth-fault protection


Pilot distance protection enabling input 1, it is triggered from binary input or

73

85.Z.En1

74

85.Z.En2

75

85.Z.Blk

76

85.Abnor_Ch1

Input signal of indicating that pilot channel 1 is abnormal

77

85.Abnor_Ch2

Input signal of indicating that pilot channel 2 is abnormal

programmable logic etc.


Pilot distance protection enabling input 2, it is triggered from binary input or
programmable logic etc.
Pilot distance protection blocking input, it is triggered from binary input or
programmable logic etc.

Input signal of receiving permissive signal via channel No.1, or input signal of
78

85.Recv1

receiving permissive signal of A-phase via channel No.1 (only for


phase-segregated command scheme)

79

85.Recv2

Input signal of receiving permissive signal via channel 2

80

85.RecvB

81

85.RecvC

82

85.ExTrp

Input signal of initiating sending permissive signal from external tripping signal

83

85.Unblocking1

Unblocking signal 1

84

85.Unblocking2

Unblocking signal 2

85

85.ZX.En1

86

85.ZX.En2

87

85.ZX.Blk1

88

85.ZX.Blk2

89

85.DEF.En1

90

85.DEF.En2

91

85.DEF.Blk

Input signal of receiving permissive signal of B-phase via channel No.1 (only
for phase-segregated command scheme)
Input signal of receiving permissive signal of C-phase via channel No.1 (only
for phase-segregated command scheme)

Zone Extension enabling input 1, it is triggered from binary input or


programmable logic etc.
Zone Extension enabling input 2, it is triggered from binary input or
programmable logic etc.
Zone Extension blocking input 1, it is triggered from binary input or
programmable logic etc.
Zone Extension blocking input 2, it is triggered from binary input or
programmable logic etc.
Pilot directional earth-fault protection enabling input 1, it is triggered from
binary input or programmable logic etc.
Pilot directional earth-fault protection enabling input 2, it is triggered from
binary input or programmable logic etc.
Pilot directional earth-fault protection blocking input, it is triggered from binary
input or programmable logic etc.
Phase overcurrent protection

PCS-902 Line Distance Relay

9-5
Date: 2013-12-25

9 Configurable Function
No.

Item

92

50/51Px.En1

93

50/51Px.En2

94

50/51Px.Blk

Description
Stage x of phase overcurrent protection enabling input 1, it is triggered from
binary input or programmable logic etc.
Stage x of phase overcurrent protection enabling input 2, it is triggered from
binary input or programmable logic etc.
Stage x of phase overcurrent protection blocking input, it is triggered from
binary input or programmable logic etc.
Earth fault protection

95

50/51Gx.En1

96

50/51Gx.En2

97

50/51Gx.Blk

Stage x of earth fault protection enabling input 1, it is triggered from binary


input or programmable logic etc.
Stage x of earth fault protection enabling input 2, it is triggered from binary
input or programmable logic etc.
Stage x of earth fault protection blocking input, it is triggered from binary input
or programmable logic etc.
Overcurrent protection for VT circuit failure

98

50PVT.En1

99

50PVT.En2

100

50PVT.Blk

101

50GVT.En1

102

50GVT.En2

103

50GVT.Blk

Phase overcurrent protection for VT circuit failure enabling input 1, it is


triggered from binary input or programmable logic etc.
Phase overcurrent protection for VT circuit failure enabling input 2, it is
triggered from binary input or programmable logic etc.
Phase overcurrent protection for VT circuit failure blocking input, it is triggered
from binary input or programmable logic etc.
Ground overcurrent protection for VT circuit failure enabling input 1, it is
triggered from binary input or programmable logic etc.
Ground overcurrent protection for VT circuit failure enabling input 2, it is
triggered from binary input or programmable logic etc.
Ground overcurrent protection for VT circuit failure blocking input, it is
triggered from binary input or programmable logic etc.
Residual SOTF protection

104

50GSOTF.En1

105

50GSOTF.En2

106

50GSOTF.Blk

Residual current SOTF protection enabling input 1, it is triggered from binary


input or programmable logic etc.
Residual current SOTF protection enabling input 2, it is triggered from binary
input or programmable logic etc.
Residual current SOTF protection blocking input, it is triggered from binary
input or programmable logic etc.
Voltage protection

107

59Px.En1

108

59Px.En2

109

59Px.Blk

110

27Px.En1

Stage x of overvoltage protection enabling input 1, it is triggered from binary


input or programmable logic etc.
Stage x of overvoltage protection enabling input 2, it is triggered from binary
input or programmable logic etc.
Stage x of overvoltage protection blocking input, it is triggered from binary
input or programmable logic etc.
Stage x of undervoltage protection enabling input 1, it is triggered from binary
input or programmable logic etc.

9-6

PCS-902 Line Distance Relay


Date: 2013-12-25

9 Configurable Function
No.

Item

111

27Px.En2

112

27Px.Blk

Description
Stage x of undervoltage protection enabling input 2, it is triggered from binary
input or programmable logic etc.
Stage x of undervoltage protection blocking input, it is triggered from binary
input or programmable logic etc.
Frequency protection

113

81U.En1

114

81U.En2

115

81U.Blk

116

81O.En1

117

81O.En2

118

81O.Blk

Underfrequency protection enabling input 1, it is triggered from binary input or


programmable logic etc.
Underfrequency protection enabling input 2, it is triggered from binary input or
programmable logic etc.
Underfrequency protection blocking input, it is triggered from binary input or
programmable logic etc.
Overfrequency protection enabling input 1, it is triggered from binary input or
programmable logic etc.
Overfrequency protection enabling input 2, it is triggered from binary input or
programmable logic etc.
Overfrequency protection blocking input, it is triggered from binary input or
programmable logic etc.
Breaker failure protection

119

50BF.ExTrp3P_L

Input signal of three-phase tripping contact from line protection

120

50BF.ExTrp3P_GT

121

50BF.ExTrpA

Input signal of phase-A tripping contact from external device

122

50BF.ExTrpB

Input signal of phase-B tripping contact from external device

123

50BF.ExTrpC

Input signal of phase-C tripping contact from external device

Input signal of three-phase tripping contact from generator or transformer


protection

Input signal of three-phase tripping contact from external device. Once it is


124

50BF.ExTrp_WOI

energized, normally closed auxiliary contact of circuit breaker is chosen in


addition to breaker failure current check to trigger breaker failure timers.

125

50BF.En

Input signal of enabling breaker failure protection


Breaker failure protection blocking input, such as function blocking binary

126

50BF.Blk

input.
When the input is 1, breaker failure protection is reset and time delay is
cleared.
Thermal overload protection

127

49.Clr_Cmd

128

49.En

129

49.Blk

Input signal of clear thermal accumulation value


Thermal overload protection enabling input, it is triggered from binary input or
programmable logic etc.
Thermal overload protection blocking input, it is triggered from binary input or
programmable logic etc.
Stub overcurrent protection

130

50STB.En1

131

50STB.En2

Stub overcurrent protection enabling input 1, it is triggered from binary input or


programmable logic etc.
Stub overcurrent protection enabling input 2, it is triggered from binary input or

PCS-902 Line Distance Relay

9-7
Date: 2013-12-25

9 Configurable Function
No.

Item

Description
programmable logic etc.

132

50STB.Blk

133

50STB.89b_DS

Stub overcurrent protection blocking input, it is triggered from binary input or


programmable logic etc.
Normally closed auxiliary contact of line disconnector
Dead zone protection

134

50DZ.En1

Dead zone protection enabling input 1, it can be binary inputs or logic link.

135

50DZ.En2

Dead zone protection enabling input 2, it can be binary inputs or logic link.

136

50DZ.Blk

137

50DZ.Init

Dead zone protection blocking input, such as function blocking binary input.
When the input is 1, dead zone protection is reset and time delay is cleared.
Initiation signal input of the dead zone protection.
Pole discrepancy protection

138

62PD.En1

139

62PD.En2

140

62PD.Blk

Pole discrepancy protection enabling input 1, it is triggered from binary input


or programmable logic etc.
Pole discrepancy protection enabling input 2, it is triggered from binary input
or programmable logic etc.
Pole discrepancy protection blocking input, it is triggered from binary input or
programmable logic etc.
Broken conductor protection

141

46BC.En1

142

46BC.En2

143

46BC.Blk

Enable broken conductor protection input 1, it is triggered from binary input or


programmable logic etc.
Enable broken conductor protection input 2, it is triggered from binary input or
programmable logic etc.
Broken conductor protection blocking input, it is triggered from binary input or
programmable logic etc.
Synchrocheck function

144

25.Blk_Chk

Input signal of blocking synchrocheck function for AR.

145

25.Blk_SynChk

146

25.Blk_DdChk

147

25.Start_Chk

148

25.Blk_VTS_UB

VT circuit supervision (UB) is blocked

149

25.Blk_VTS_UL

VT circuit supervision (UL) is blocked

150

25.MCB_VT_UB

Binary input for VT MCB auxiliary contact (UB)

151

25.MCB_VT_UL

Binary input for VT MCB auxiliary contact (UL)

Input signal of blocking synchronism check for AR. If the value is 1, the
output of synchronism check is 0.
Input signal of blocking dead charge check for AR.
Input signal of starting synchronism check, usually it was starting signal of AR
from auto-reclosing module.

Auto-reclosing
Binary input for enabling AR. If the logic setting [79.En_ExtCtrl]=1, enabling

152

79.En

153

79.Blk

154

79.Sel_1PAR

Input signal for selecting 1-pole AR mode of corresponding circuit breaker

155

79.Sel_3PAR

Input signal for selecting 3-pole AR mode of corresponding circuit breaker

AR will be controlled by the external signal via binary input


Binary input for disabling AR. If the logic setting [79.En_ExtCtrl]=1, disabling
AR will be controlled by the external input

9-8

PCS-902 Line Distance Relay


Date: 2013-12-25

9 Configurable Function
No.

Item

Description

156

79.Sel_1P/3PAR

Input signal for selecting 1/3-pole AR mode of corresponding circuit breaker

157

79.Trp

Input signal of single-phase tripping from line protection to initiate AR

158

79.Trp3P

Input signal of three-phase tripping from line protection to initiate AR

159

79.TrpA

Input signal of A-phase tripping from line protection to initiate AR

160

79.TrpB

Input signal of B-phase tripping from line protection to initiate AR

161

79.TrpC

Input signal of C-phase tripping from line protection to initiate AR

162

79.Lockout

Input signal of blocking reclosing, usually it is connected with the operating


signals of definite-time protection, transformer protection and busbar
differential protection, etc.
163

79.PLC_Lost

Input signal of indicating the alarm signal that signal channel is lost

164

79.WaitMaster

165

79.CB_Healthy

166

79.Clr_Counter

Clear the reclosing counter

167

79.Ok_Chk

Synchrocheck condition of AR is met

Input signal of waiting for reclosing permissive signal from master AR (when
reclosing multiple circuit breakers)
The input for indicating whether circuit breaker has enough energy to perform
the close function

Transfer trip
168

TT.Init

169

TT.En

170

TT.Blk

Input signal of initiating transfer trip after receiving transfer trip


Transfer trip enabling input, it is triggered from binary input or programmable
logic etc.
Transfer trip blocking input, it is triggered from binary input or programmable
logic etc.
VT circuit supervision

171

VTS.En

172

VTS.Blk

173

VTNS.En

174

VTNS.Blk

175

VTS.MCB_VT

VT supervision enabling input, it is triggered from binary input or


programmable logic etc.
VT supervision blocking input, it is triggered from binary input or
programmable logic etc.
VT neutral point supervision enabling input, it is triggered from binary input or
programmable logic etc.
VT neutral point supervision blocking input, it is triggered from binary input or
programmable logic etc.
Binary input for VT MCB auxiliary contact
CT circuit supervision

176

CTS.En

177

CTS.Blk

CT circuit supervision enabling input, it is triggered from binary input or


programmable logic etc.
CT circuit supervision blocking input, it is triggered from binary input or
programmable logic etc.
Control and Synchrocheck for Manual Closing

178

CSWIxx.CILO.EnOpn

It is the interlock status of No.xx open output of BO module (xx=01~10)

179

CSWIxx.CILO.EnCls

It is the interlock status of No.xx closing output of BO module (xx=01~10)

180

Sig_Ok_Chk

From receiving a closing command, this device will continuously check


whether the 2 voltages (Incoming voltage and reference voltage) involved in

PCS-902 Line Distance Relay

9-9
Date: 2013-12-25

9 Configurable Function
No.

Item

Description
synchronism check(or dead check) can meet the criteria.
Within the duration of [MCBrd.25.t_Wait_Chk], if the synchronism check(or
dead check) criteria are not met, [Sig_Ok_Chk] will be set as 0; if the
synchronism check(or dead check) criteria are met, [Sig_Ok_Chk] will be set
as 1.
Access the menu Local CmdControl to issue control command locally.

181

CSWIxx.Cmd_LocCtrl

It is used to select the local control to No.xx controlled object (CB/DS/ES).


When the local control is active, No.xx binary outputs can only be locally
controlled.
It is used to select the remote control to No.xx controlled object (CB/DS/ES).

182

CSWIxx.Cmd_RmtCtrl

When the remote control is active, No.xx binary outputs can only be remotely
controlled by SCADA or control centers.
It is used to disable the interlock blocking function for control output. If the

183

CSWIxx.CILO.Disable

signal CSWIxx.CILO.Disable is 1, No.xx binary outputs of the device will


not be blocked by interlock conditions.
It is used to select the remote control to No.xx controlled object (CB/DS/ES).

184

BIinput.RmtCtrl

When the remote control is active, all binary outputs can only be remotely
controlled by SCADA or control centers.
It is used to select the local control to No.xx controlled object (CB/DS/ES).

185

BIinput.LocCtrl

When the local control is active, all binary outputs can only be locally
controlled.
It is used to disable the interlock blocking function for control output. If the

186

BIinput.CILO.Disable

signal BIinput.CILO.Disable is 1, all binary outputs of this device will not be


blocked by interlock conditions.
When

187

CSWI01.ManSynCls

the

condition

of

local

control

is

met

and

the

signal

CSWI01.ManSynCls is 1, the output contact [BO_CtrlCls01] is closed to


execute manually closing the circuit breaker with synschrochcek.
When the condition of local control is met and the signal CSWI01.ManOpn is

188

CSWI01.ManOpn

1, the output contact [BO_CtrlOpn01] is closed to execute manually open the


circuit breaker.

9.3.2 Output Signal


All output signals of this device have been listed in the following table.
Table 9.3-2 Output signals
No.

Signal

Description
Circuit breaker position supervision

Alm_52b

CB position is abnormal

TCCS.Alm

Control circuit of circuit breaker is abnormal


Fault detector

FD.Pkp

The device picks up

FD.DPFC.Pkp

DPFC current fault detector element operates.

FD.ROC.Pkp

Residual current fault detector element operates.

9-10

PCS-902 Line Distance Relay


Date: 2013-12-25

9 Configurable Function
No.

Signal

Description
Auxiliary element

AuxE.St

Any auxiliary element of the device operates

AuxE.OCD.St_Ext

Current change auxiliary element operates (7s delayed drop off)

AuxE.OCD.On

Current change auxiliary element is enabled

AuxE.ROC1.St

Stage 1 of residual current auxiliary element operates

10

AuxE.ROC1.On

Stage 1 of residual current auxiliary element is enabled

11

AuxE.ROC2.St

Stage 2 of residual current auxiliary element operates

12

AuxE.ROC2.On

Stage 2 of residual current auxiliary element is enabled

13

AuxE.ROC3.St

Stage 3 of residual current auxiliary element operates

14

AuxE.ROC3.On

Stage 3 of residual current auxiliary element is enabled

15

AuxE.OC1.St

Stage 1 of phase current auxiliary element operates

16

AuxE.OC1.StA

Stage 1 of phase current auxiliary element operates (phase A)

17

AuxE.OC1.StB

Stage 1 of phase current auxiliary element operates (phase B)

18

AuxE.OC1.StC

Stage 1 of phase current auxiliary element operates (phase C)

19

AuxE.OC1.On

Stage 1 of phase current auxiliary element is enabled

20

AuxE.OC2.St

Stage 2 of phase current auxiliary element operates.

21

AuxE.OC2.StA

Stage 2 of phase current auxiliary element operates (phase A)

22

AuxE.OC2.StB

Stage 2 of phase current auxiliary element operates (phase B)

23

AuxE.OC2.StC

Stage 2 of phase current auxiliary element operates (phase C)

24

AuxE.OC2.On

Stage 2 of phase current auxiliary element is enabled

25

AuxE.OC3.St

Stage 3 of phase current auxiliary element operates

26

AuxE.OC3.StA

Stage 1 of phase current auxiliary element operates (phase A)

27

AuxE.OC3.StB

Stage 1 of phase current auxiliary element operates (phase B)

28

AuxE.OC3.StC

Stage 1 of phase current auxiliary element operates (phase C)

29

AuxE.OC3.On

Stage 3 of phase current auxiliary element is enabled

30

AuxE.UVD.St

Voltage change auxiliary element operates.

31

AuxE.UVD.St_Ext

Voltage change auxiliary element operates (7s delayed drop off)

32

AuxE.UVD.On

Voltage change auxiliary element is enabled

33

AuxE.UVG.St

Phase-to-ground under voltage auxiliary element operates.

34

AuxE.UVG.StA

Phase-to-ground under voltage auxiliary element operates (phase A)

35

AuxE.UVG.StB

Phase-to-ground under voltage auxiliary element operates (phase B)

36

AuxE.UVG.StC

Phase-to-ground under voltage auxiliary element operates (phase C)

37

AuxE.UVG.On

Phase-to-ground under voltage auxiliary element is enabled

38

AuxE.UVS.St

Phase-to-phase under voltage auxiliary element operates.

39

AuxE.UVS.StAB

Phase-to-phase under voltage auxiliary element operates (phase AB)

40

AuxE.UVS.StBC

Phase-to-phase under voltage auxiliary element operates (phase BC)

41

AuxE.UVS.StCA

Phase-to-phase under voltage auxiliary element operates (phase CA)

42

AuxE.UVS.On

Phase-to-phase under voltage auxiliary element is enabled

43

AuxE.ROV.St

Residual voltage auxiliary element operates

44

AuxE.ROV.On

Residual voltage auxiliary element is enabled


Distance protection

45

21D.Op

DPFC distance protection operates

PCS-902 Line Distance Relay

9-11
Date: 2013-12-25

9 Configurable Function
No.

Signal

Description

46

21D.On

DPFC distance protection is enabled.

47

LoadEnch.St

Measured impedance into the load area

48

21M.Z1.On

Zone 1 of distance protection is enabled

49

21M.Z2.On

Zone 2 of distance protection is enabled

50

21M.Z3.On

Zone 3 of distance protection is enabled

51

21M.Z4.On

zone 4 of distance protection is enabled

52

21M.Z1.Op

Zone 1 of distance protection operates

53

21M.Z2.Op

Zone 2 of distance protection operates

54

21M.Z3.Op

Zone 3 of distance protection operates

55

21M.Z4.Op

zone 4 of distance protection operates

56

21Q.Z1.On

Zone 1 of distance protection is enabled

57

21Q.Z2.On

Zone 2 of distance protection is enabled

58

21Q.Z3.On

Zone 3 of distance protection is enabled

59

21Q.Z4.On

zone 4 of distance protection is enabled

60

21Q.Z1.Op

Zone 1 of distance protection operates

61

21Q.Z2.Op

Zone 2 of distance protection operates

62

21Q.Z3.Op

Zone 3 of distance protection operates

63

21Q.Z4.Op

zone 4 of distance protection operates

64

68.St

Power swing detection takes into effect.

65

21M.Z1.Rls_PSBR

PSBR operates to release zone 1 (Mho characteristic)

66

21Q.Z1.Rls_PSBR

PSBR operates to release zone 1 (Quad characteristic)

67

21M.Z2.Rls_PSBR

PSBR operates to release zone 2 (Mho characteristic)

68

21Q.Z2.Rls_PSBR

PSBR operates to release zone 2 (Quad characteristic)

69

21M.Z3.Rls_PSBR

PSBR operates to release zone 3 (Mho characteristic)

70

21Q.Z3.Rls_PSBR

PSBR operates to release zone 3 (Quad characteristic)

71

21M.Pilot.Rls_PSBR

72

21Q.Pilot.Rls_PSBR

73

21SOTF.Op

74

21SOTF.Op_PDF

75

21SOTF.On

PSBR

operates

to

release

pilot

to

release

pilot

distance

protection

(Mho

characteristic)
PSBR

operates

distance

protection

(Quad

characteristic)
Accelerate distance protection to trip when manual closing or
auto-reclosing to fault
Accelerate distance protection to trip when another fault happening
under pole discrepancy conditions
Accelerate distance protection is enabled.
Optical pilot channel

76

FOx.On

Channel x is enabled.

77

FOx.Recv1

Receiving signal 1 of channel x

78

FOx.Recv2

Receiving signal 2 of channel x

79

FOx.Recv3

Receiving signal 3 of channel x

80

FOx.Recv4

Receiving signal 4 of channel x

81

FOx.Recv5

Receiving signal 5 of channel x

82

FOx.Recv6

Receiving signal 6 of channel x

9-12

PCS-902 Line Distance Relay


Date: 2013-12-25

9 Configurable Function
No.

Signal

Description

83

FOx.Recv7

Receiving signal 7 of channel x

84

FOx.Recv8

Receiving signal 8 of channel x


Receiving signal 9 of channel x (it is configured fixedly as receiving

85

permissive signal via channel No.1, or receiving permissive signal of

FOx.Recv9

A-phase via channel No.1 (only for phase-segregated command


scheme))
Receiving signal 10 of channel x (it is configured fixedly as receiving

86

FOx.Recv10

permissive

signal

of

B-phase

via

channel

No.1

(only

for

phase-segregated command scheme))


Receiving signal 11 of channel x (it is configured fixedly as receiving
87

FOx.Recv11

permissive

signal

of

C-phase

via

channel

No.1

(only

for

phase-segregated command scheme))


Receiving signal 12 of channel x (it is configured fixedly as receiving
permissive signal 1 when pilot directional earth-fault protection sharing
88

FOx.Recv12

pilot channel 1 with pilot distance protection, or receiving permissive


signal 2 only for pilot directional earth-fault protection adopting
independent pilot channel 2)

89

FOx.Alm

Channel x is abnormal

90

FOx.Alm_ID

Received ID from the remote end is not as same as the setting


[FO.RmtID] of the device in local end

Pilot distance protection and pilot directional earth-fault protection


91

85.Z.On

Pilot distance protection is enabled.

92

85.ZX.On

Zone extension protection is enabled.

93

85.Op_Z

Pilot distance protection operates.

94

85.Send1

95

85.SendB

96

85.SendC

97

85.Op_ZX

Zone extension protection operates.

98

85.ZX_St

Zone extension protection starts

99

85.DEF.On

Pilot directional earth-fault protection is enabled.

100

85.Op_DEF

Pilot directional earth-fault protection operates.

101

85.DEF_BlkAR

Pilot directional earth-fault protection operates to block AR.

Output signal of sending permissive signal 1 or sending A-phase


permissive signal (only for phase-segregated command scheme)
Output signal of sending B-phase permissive signal (only for
phase-segregated command scheme)
Output signal of sending C-phase permissive signal (only for
phase-segregated command scheme)

Output signal of sending permissive signal 1 when pilot directional


102

85.Send1

earth-fault protection sharing pilot channel 1 with pilot distance


protection

103

85.Send2

Output signal of sending permissive signal 2 only for pilot directional


earth-fault protection adopting independent pilot channel 2
Current direction

104

FwdDir_ROC

The forward direction of zero-sequence power

PCS-902 Line Distance Relay

9-13
Date: 2013-12-25

9 Configurable Function
No.

Signal

Description

105

RevDir_ROC

The reverse direction of zero-sequence power

106

FwdDir_NegOC

The forward direction of negative-sequence power

107

RevDir_NegOC

The reverse direction of negative-sequence power

108

FwdDir_A

The forward direction of phase-A current

109

FwdDir_B

The forward direction of phase-B current

110

FwdDir_C

The forward direction of phase-C current

111

RevDir_A

The reverse direction of phase-A current

112

RevDir_B

The reverse direction of phase-B current

113

RevDir_C

The reverse direction of phase-C current

114

FwdDir_AB

The forward direction of phase-AB current

115

FwdDir_BC

The forward direction of phase-BC current

116

FwdDir_CA

The forward direction of phase-CA current

117

RevDir_AB

The reverse direction of phase-AB current

118

RevDir_BC

The reverse direction of phase-BC current

119

RevDir_CA

The reverse direction of phase-CA current


Phase overcurrent protection

120

50/51Px.On

Stage x of phase overcurrent protection is enabled.

121

50/51Px.Op

Stage x of phase overcurrent protection operates.

122

50/51Px.St

Stage x of phase overcurrent protection starts.

123

50/51Px.StA

Stage x of phase overcurrent protection starts (A-Phase).

124

50/51Px.StB

Stage x of phase overcurrent protection starts (B-Phase).

125

50/51Px.StC

Stage x of phase overcurrent protection starts (C-Phase).


Earth fault protection

126

50/51Gx.On

Stage x of earth fault protection is enabled.

127

50/51Gx.Op

Stage x of earth fault protection operates.

128

50/51Gx.St

Stage x of earth fault protection starts.


Overcurrent protection for VT circuit failure

129

50PVT.On

Phase overcurrent protection for VT circuit failure is enabled.

130

50PVT.Op

Phase overcurrent protection for VT circuit failure operates.

131

50PVT.St

Phase overcurrent protection for VT circuit failure starts.

132

50PVT.StA

Phase overcurrent protection for VT circuit failure starts (A-Phase).

133

50PVT.StB

Phase overcurrent protection for VT circuit failure starts (B-Phase).

134

50PVT.StC

Phase overcurrent protection for VT circuit failure starts (C-Phase).

135

50GVT.On

Ground overcurrent protection for VT circuit failure is enabled.

136

50GVT.Op

Ground overcurrent protection for VT circuit failure operates.

137

50GVT.St

Ground overcurrent protection for VT circuit failure starts.


Residual SOTF protection

138

50GSOTF.On

Residual current SOTF protection is enabled.

139

50GSOTF.Op

Residual current SOTF protection operates.

140

50GSOTF.St

Residual current SOTF protection starts.


Voltage protection

141

59Px.On

Stage x of overvoltage protection is enabled.

9-14

PCS-902 Line Distance Relay


Date: 2013-12-25

9 Configurable Function
No.

Signal

Description

142

59Px.Op

Stage x of overvoltage protection operates.

143

59Px.St

Stage x of overvoltage protection starts.

144

59Px.St1

Stage x of overvoltage protection starts (A or AB).

145

59Px.St2

Stage x of overvoltage protection starts (B or BC).

146

59Px.St3

Stage x of overvoltage protection starts (C or CA).

147

59Px.Op_InitTT

Stage x of overvoltage protection operates to initiate transfer trip.

148

59Px.Alm

Stage x of overvoltage protection alarms.

149

27Px.On

Stage x of undervoltage protection is enabled.

150

27Px.Op

Stage x of undervoltage protection operates.

151

27Px.Alm

Stage x of undervoltage protection alarms.

152

27Px.St

Stage x of undervoltage protection starts.

153

27Px.St1

Stage x of undervoltage protection starts (A or AB).

154

27Px.St2

Stage x of undervoltage protection starts (B or BC).

155

27Px.St3

Stage x of undervoltage protection starts (C or CA).


Frequency protection

156

81O.OFx.On

Stage x of overfrequency protection is enabled (x=1, 2, 3 or 4).

157

81O.OFx.Op

Stage x of overfrequency protection operates (x=1, 2, 3 or 4).

158

81O.St

Overfrequency protection starts.

159

81U.UFx.On

Stage x of underfrequency protection is enabled (x=1, 2, 3 or 4).

160

81U.UFx.Op

Stage x of underfrequency protection operates (x=1, 2, 3 or 4).

161

81U.St

Underfrequency protection starts.


Breaker failure protection

162

50BF.On

Breaker failure protection is enabled

163

50BF.Op_ReTrpA

Breaker failure protection operates to re-trip phase-A circuit breaker

164

50BF.Op_ReTrpB

Breaker failure protection operates to re-trip phase-B circuit breaker

165

50BF.Op_ReTrpC

Breaker failure protection operates to re-trip phase-C circuit breaker

166

50BF.Op_ReTrp3P

167

50BF.Op_t1

Stage 1 of breaker failure protection operates

168

50BF.Op_t2

Stage 2 of breaker failure protection operates

Breaker failure protection operates to re-trip three-phase circuit


breaker

Thermal overload protection


169

49.On

Thermal overload protection is enabled.

170

49.St

Thermal overload protection starts.

171

49-1.Op

Stage 1 of thermal overload protection operates to trip.

172

49-2.Op

Stage 2 of thermal overload protection operates to trip.

173

49-1.Alm

Stage 1 of thermal overload protection operates to alarm.

174

49-2.Alm

Stage 2 of thermal overload protection operates to alarm.


Stub overcurrent protection

175

50STB.On

Stub overcurrent protection is enabled.

176

50STB.Op

Stub overcurrent protection operates.

177

50STB.St

Stub overcurrent protection starts.

178

50STB.StA

Phase A of stub overcurrent protection starts.

PCS-902 Line Distance Relay

9-15
Date: 2013-12-25

9 Configurable Function
No.

Signal

Description

179

50STB.StB

Phase B of stub overcurrent protection starts.

180

50STB.StC

Phase C of stub overcurrent protection starts.


Dead zone protection

181

50DZ.On

Dead zone protection is enabled.

182

50DZ.St

Dead zone protection starts.

183

50DZ.Op

Dead zone protection operates.


Pole discrepancy protection

184

62PD.On

Pole discrepancy protection is enabled.

185

62PD.Op

Pole discrepancy protection operates to trip

186

62PD.St

Pole discrepancy protection starts


Broken conductor protection

187

46BC.On

Broken-conductor protection is enabled.

188

46BC.St

Broken-conductor protection starts

189

46BC.Op

Broken-conductor protection operates to trip.

190

46BC.Alm

Broken-conductor protection operates to alarm.


Synchrocheck function
To indicate that frequency difference condition for synchronism check

191

25.Ok_fDiffChk

of AR is met, frequency difference between UB and UL is smaller than


[25.f_Diff].
To indicate that voltage difference condition for synchronism check of

192

25.Ok_UDiffChk

AR is met, voltage difference between UB and UL is smaller than


[25.U_Diff]
To indicate phase difference condition for synchronism check of AR is

193

25.Ok_phiDiffChk

met, phase difference between UB and UL is smaller than


[25.phi_Diff].

194

25.Ok_DdL_DdB

Dead line and dead bus condition is met

195

25.Ok_DdL_LvB

Dead line and live bus condition is met

196

25.Ok_LvL_DdB

Live line and dead bus condition is met

197

25.Chk_LvL

Line voltage is greater than the voltage setting [25.U_Lv]

198

25.Chk_DdL

Line voltage is smaller than the voltage setting [25.U_Dd]

199

25.Chk_LvB

Bus voltage is greater than the voltage setting [25.U_Lv]

200

25.Chk_DdB

Bus voltage is smaller than the voltage setting [25.U_Dd]

201

25.Ok_DdChk

To indicate that dead charge check condition of AR is met

202

25.Ok_SynChk

To indicate that synchronism check condition of AR is met

203

25.Ok_Chk

To indicate that synchrocheck condition of AR is met

204

25.Alm_VTS_UB

Synchronism voltage circuit is abnormal (UB)

205

25.Alm_VTS_UL

Reference voltage circuit is abnormal (UL)


Auto-reclosing

206

79.On

Automatic reclosure is enabled

207

79.Off

Automatic reclosure is disabled

208

79.Close

Output of auto-reclosing signal

209

79.Ready

Automatic reclosure have been ready for reclosing cycle

9-16

PCS-902 Line Distance Relay


Date: 2013-12-25

9 Configurable Function
No.

Signal

Description

210

79.AR_Blkd

Automatic reclosure is blocked

211

79.Active

Automatic reclosing logic is actived

212

79.Inprog

Automatic reclosing cycle is in progress

213

79.Inprog_1P

The first 1-pole AR cycle is in progress

214

79.Inprog_3P

3-pole AR cycle is in progress

215

79.Inprog_3PS1

First 3-pole AR cycle is in progress

216

79.Inprog_3PS2

Second 3-pole AR cycle is in progress

217

79.Inprog_3PS3

Third 3-pole AR cycle is in progress

218

79.Inprog_3PS4

Fourth 3-pole AR cycle is in progress

219

79.WaitToSlave

220

79.Perm_Trp1P

221

79.Perm_Trp3P

222

79.Rcls_Status

223

79.Fail_Rcls

Auto-reclosing fails

224

79.Succ_Rcls

Auto-reclosing is successful

225

79.Fail_Chk

Synchrocheck for AR fails

226

79.Mode_1PAR

Output of 1-pole AR mode

227

79.Mode_3PAR

Output of 3-pole AR mode

228

79.Mode_1/3PAR

Output of 1/3-pole AR mode

Waiting signal of automatic reclosing which will be sent to slave (when


reclosing multiple circuit breakers)
Single-phase circuit breaker will be tripped once protection device
operates
Three-phase circuit breaker will be tripped once protection device
operates
Automatic reclosure status (0: AR is ready, 1: AR is in progress, 2: AR
is successful)

Transfer trip
229

TT.Alm

Input signal of receiving transfer trip is abnormal

230

TT.Op

Transfer trip operates

231

TT.On

Transfer trip is enabled


Trip logic

232

On

Tripping logic is enabled.

233

TrpA

Tripping A-phase circuit breaker

234

TrpB

Tripping B-phase circuit breaker

235

TrpC

Tripping C-phase circuit breaker

236

Trp

Tripping any phase circuit breaker

237

Trp3P

Tripping three-phase circuit breaker

238

BFI_A

239

BFI_B

240

BFI_C

241

BFI

Protection tripping signal of A-phase configured to initiate BFP, BFI


signal shall be reset immediately after tripping signal drops off.
Protection tripping signal of B-phase configured to initiate BFP, BFI
signal shall be reset immediately after tripping signal drops off.
Protection tripping signal of C-phase configured to initiate BFP, BFI
signal shall be reset immediately after tripping signal drops off.
Protection tripping signal configured to initiate BFP, BFI signal shall be
reset immediately after tripping signal drops off.

PCS-902 Line Distance Relay

9-17
Date: 2013-12-25

9 Configurable Function
No.

Signal

Description

242

Trp3P_PSFail

Initiating three-phase tripping due to failure in fault phase selection

243

BlockAR

Blocking auto-reclosing
VT circuit supervision

244

VTS.Alm

Alarm signal to indicate VT circuit fails

245

VTNS.Alm

Alarm signal to indicate VT neutral point fails


CT circuit supervision

246

CTS.Alm

Alarm signal to indicate CT circuit fails


Control and Synchrocheck for Manual Closing

247

CSWIxx.Op_Opn

No.xx command output for open. (xx=01~10)

248

CSWIxx.Op_Cls

No.xx command output for closing. (xx=01~10)

249

BIinput.RmtCtrl

In order to be convenient to user configure control output, three same

250

BIinput.LocCtrl

output signals with input signals are available. The relationship with 10
binary output have been configured inside the device. The user only
assigns a specific binary input to input signal, the relevant function can

251

BIinput.CILO.Disable

be gained. If some binary output need not be controlled by three


signals, please cancle the configuration by PCS-Explorer, and
configure it independently.
Faulty phase selection

252

PhSA

Phase-A is selected as faulty phase

253

PhSB

Phase-B is selected as faulty phase

254

PhSC

Phase-C is selected as faulty phase

255

GndFlt

Earth fault

9-18

PCS-902 Line Distance Relay


Date: 2013-12-25

10 Communication

10 Communication
Table of Contents
10 Communication ............................................................................ 10-a
10.1 Overview ...................................................................................................... 10-1
10.2 Rear Communication Port Information ..................................................... 10-1
10.2.1 RS-485 Interface ............................................................................................................ 10-1
10.2.2 Ethernet Interface .......................................................................................................... 10-3
10.2.3 IEC60870-5-103 Communication ................................................................................... 10-4

10.3 IEC60870-5-103 Interface over Serial Port ................................................ 10-4


10.3.1 Physical Connection and Link Layer .............................................................................. 10-5
10.3.2 Initialization .................................................................................................................... 10-5
10.3.3 Time Synchronization ..................................................................................................... 10-5
10.3.4 Spontaneous Events ...................................................................................................... 10-5
10.3.5 General Interrogation ..................................................................................................... 10-5
10.3.6 General Service ............................................................................................................. 10-6
10.3.7 Disturbance Records ..................................................................................................... 10-6

10.4 Messages Description for IEC61850 Protocol .......................................... 10-6


10.4.1 Overview ........................................................................................................................ 10-6
10.4.2 Communication Profiles ................................................................................................. 10-7
10.4.3 MMS Communication Network Deployment................................................................... 10-8
10.4.4 Server Data Organization............................................................................................. 10-11
10.4.5 Server Features and Configuration .............................................................................. 10-13
10.4.6 ACSI Conformance ...................................................................................................... 10-15
10.4.7 Logical Nodes .............................................................................................................. 10-19

10.5 DNP3.0 Interface ....................................................................................... 10-21


10.5.1 Overview ...................................................................................................................... 10-21
10.5.2 Link Layer Functions .................................................................................................... 10-21

PCS-902 Line Distance Relay

10-a
Date: 2013-09-16

10 Communication

10.5.3 Transport Functions ..................................................................................................... 10-21


10.5.4 Application Layer Functions ......................................................................................... 10-22

List of Figures
Figure 10.2-1 EIA RS-485 bus connection arrangements.....................................................10-2
Figure 10.2-2 Ethernet communication cable .......................................................................10-3
Figure 10.2-3 Ethernet communication structure .................................................................10-4
Figure 10.4-1 Dual-net full duplex mode sharing the RCB block instance .........................10-8
Figure 10.4-2 Dual-net hot-standby mode sharing the same RCB instance .......................10-9
Figure 10.4-3 Dual-net full duplex mode with 2 independent RCB instances ..................10-10

10-b

PCS-902 Line Distance Relay


Date: 2013-09-16

10 Communication

10.1 Overview
This section outlines the remote communications interfaces of NR Relays. The protective device
supports a choice of three protocols via the rear communication interface (RS-485 or Ethernet),
selected via the model number by setting. The protocol provided by the protective device is
indicated in the menu SettingsDevice SetupComm Settings.
The rear EIA RS-485 interface is isolated and is suitable for permanent connection of whichever
protocol is selected. The advantage of this type of connection is that up to 32 protective devices
can be daisy chained together using a simple twisted pair electrical connection.
It should be noted that the descriptions contained within this section do not aim to fully detail the
protocol itself. The relevant documentation for the protocol should be referred to for this
information. This section serves to describe the specific implementation of the protocol in the relay.

10.2 Rear Communication Port Information


10.2.1 RS-485 Interface
This protective device provides two rear RS-485 communication ports, and each port has three
terminals in the 12-terminal screw connector located on the back of the relay and each port has a
ground terminal for the earth shield of the communication cable. The rear ports provide RS-485
serial data communication and are intended for use with a permanently wired connection to a
remote control center.
10.2.1.1 EIA RS-485 Standardized Bus
The EIA RS-485 two-wire connection provides a half-duplex fully isolated serial connection to the
product. The connection is polarized and whilst the products connection diagrams indicate the
polarization of the connection terminals it should be borne in mind that there is no agreed
definition of which terminal is which. If the master is unable to communicate with the product, and
the communication parameters match, then it is possible that the two-wire connection is reversed.
10.2.1.2 Bus Termination
The EIA RS-485 bus must have 120 (Ohm) Watt terminating resistors fitted at either end
across the signal wires (refer to Figure 10.2-1). Some devices may be able to provide the bus
terminating resistors by different connection or configuration arrangements, in which case
separate external components will not be required. However, this product does not provide such a
facility, so if it is located at the bus terminus then an external termination resistor will be required.

PCS-902 Line Distance Relay

10-1
Date: 2013-09-16

Master

EIA RS-485

10 Communication

120 Ohm

120 Ohm

Slave

Slave

Slave

Figure 10.2-1 EIA RS-485 bus connection arrangements

10.2.1.3 Bus Connections & Topologies


The EIA RS-485 standard requires that each device is directly connected to the physical cable that
is the communications bus. Stubs and tees are expressly forbidden, such as star topologies. Loop
bus topologies are not part of the EIA RS-485 standard and are forbidden by it also.
Two-core screened cable is recommended. The specification of the cable will be dependent on the
application, although a multi-strand 0.5mm2 per core is normally adequate. Total cable length must
not exceed 500m. The screen must be continuous and connected to ground at one end, normally
at the master connection point; it is important to avoid circulating currents, especially when the
cable runs between buildings, for both safety and noise reasons.
This product does not provide a signal ground connection. If a signal ground connection is present
in the bus cable then it must be ignored, although it must have continuity for the benefit of other
devices connected to the bus. At no stage must the signal ground be connected to the cables
screen or to the products chassis. This is for both safety and noise reasons.
10.2.1.4 Biasing
It may also be necessary to bias the signal wires to prevent jabber. Jabber occurs when the signal
level has an indeterminate state because the bus is not being actively driven. This can occur when
all the slaves are in receive mode and the master is slow to turn from receive mode to transmit
mode. This may be because the master purposefully waits in receive mode, or even in a high
impedance state, until it has something to transmit. Jabber causes the receiving device(s) to miss
the first bits of the first character in the packet, which results in the slave rejecting the message
and consequentially not responding. Symptoms of these are poor response times (due to retries),
increasing message error counters, erratic communications, and even a complete failure to
communicate.
Biasing requires that the signal lines be weakly pulled to a defined voltage level of about 1V. There
should only be one bias point on the bus, which is best situated at the master connection point.
The DC source used for the bias must be clean; otherwise noise will be injected. Note that some
devices may (optionally) be able to provide the bus bias, in which case external components will
not be required.

10-2

PCS-902 Line Distance Relay


Date: 2013-09-16

10 Communication

Note!
It is extremely important that the 120 termination resistors are fitted. Failure to do so will
result in an excessive bias voltage that may damage the devices connected to the bus.
As the field voltage is much higher than that required, NR cannot assume responsibility for
any damage that may occur to a device connected to the network as a result of incorrect
application of this voltage.
Ensure that the field voltage is not being used for other purposes (i.e. powering logic inputs)
as this may cause noise to be passed to the communication network.

10.2.2 Ethernet Interface


This protective device can provide four rear Ethernet interfaces (optional) and they are unattached
each other. Parameters of each Ethernet port can be configured in the menu SettingsDevice
SetupComm Settings.
10.2.2.1 Ethernet Standardized Communication Cable
It is recommended to use twisted screened eight-core cable as the communication cable. A picture
is shown bellow.

Figure 10.2-2 Ethernet communication cable

10.2.2.2 Connections and Topologies


Each equipment is connected with an exchanger via communication cable, and thereby it forms a
star structure network. Dual-network is recommended in order to increase reliability. SCADA is
also connected to the exchanger and will play a role of master station, so the every equipment
which has been connected to the exchanger will play a role of slave unit.

PCS-902 Line Distance Relay

10-3
Date: 2013-09-16

10 Communication

SCADA

Switch: Net A

Switch: Net B

Figure 10.2-3 Ethernet communication structure

10.2.3 IEC60870-5-103 Communication


The IEC specification IEC60870-5-103: Telecontrol Equipment and Systems, Part 5: Transmission
Protocols Section 103 defines the use of standards IEC60870-5-1 to IEC60870-5-5 to perform
communication with protective device. The standard configuration for the IEC60870-5-103
protocol is to use a twisted pair EIA RS-485 connection over distances up to 500m. It also supports
to use an Ethernet connection. The relay operates as a slave in the system, responding to
commands from a master station.
To use the rear port with IEC60870-5-103 communication, the relevant settings to the protective
device must be configured.

10.3 IEC60870-5-103 Interface over Serial Port


The IEC60870-5-103 interface over serial port (RS-485) is a master/slave interface with the
protective device as the slave device. It is properly developed by NR.
The protective device conforms to compatibility level 3.
The following IEC60870-5-103 facilities are supported by this interface:

Initialization (reset)

Time synchronization

Event record extraction

General interrogation

General commands

Disturbance records

10-4

PCS-902 Line Distance Relay


Date: 2013-09-16

10 Communication

10.3.1 Physical Connection and Link Layer


Two EIA RS-485 standardized ports are available for IEC60870-5-103 in this protective device.
The transmission speed is optional: 4800 bit/s, 9600 bit/s, 19200 bit/s or 38400 bit/s.
The link layer strictly abides by the rules defined in the IEC60870-5-103.

10.3.2 Initialization
Whenever the protective device has been powered up, or if the communication parameters have
been changed, a reset command is required to initialize the communications. The protective
device will respond to either of the two reset commands (Reset CU or Reset FCB), the difference
is that the Reset CU will clear any unsent messages in the transmit buffer.
The protective device will respond to the reset command with an identification message ASDU 5,
the COT (Cause Of Transmission) of this response will be either Reset CU or Reset FCB
depending on the nature of the reset command.

10.3.3 Time Synchronization


The protective device time and date can be set using the time synchronization feature of the
IEC60870-5-103 protocol. The protective device will correct for the transmission delay as specified
in IEC60870-5-103. If the time synchronization message is sent as a send/confirm message then
the protective device will respond with a confirmation. Whether the time-synchronization message
is sent as a send confirmation or a broadcast (send/no reply) message, a time synchronization
class 1 event will be generated/produced.
If the protective device clock is synchronized using the IRIG-B input then it will not be possible to
set the protective device time using the IEC60870-5-103 interface. An attempt to set the time via
the interface will cause the protective device to create an event with the current date and time
taken from the IRIG-B synchronized internal clock.

10.3.4 Spontaneous Events


Events are categorized using the following information:

Type identification (TYP)

Function type (FUN)

Information number (INF)

Messages sent to substation automation system are grouped according to IEC60870-5-103


protocol. Operating elements are sent by ASDU2 (time-tagged message with relative time), and
status of binary signal and alarm element are sent by ASDU1 (time-tagged message). The cause
of transmission (COT) of these responses is 1.
All spontaneous events can be gained by printing, implementing submenu IEC103 Info in the
menu Print.

10.3.5 General Interrogation


The GI can be used to read the status of the relay, the function numbers, and information numbers
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that will be returned during the GI cycle. The GI cycle strictly abides by the rules defined in the
IEC60870-5-103.
Refer the IEC60870-5-103 standard can get the enough details about general interrogation.

10.3.6 General Service


The generic functions can be used to read the setting and protection measurement of the
protective device, and modify the setting. Two supported type identifications are ASDU 21 and
ASDU 10. For more details about generic functions, see the IEC60870-5-103 standard.
All general classification service group numbers can be gained by printing, implementing submenu
IEC103 Info in the menu Print.

10.3.7 Disturbance Records


This protective device can store up to 32 disturbance records in its memory. A pickup of the fault
detector or an operation of the relay can make the protective device store the disturbance records.
The disturbance records are stored in uncompressed format and can be extracted using the
standard mechanisms described in IEC60870-5-103.
All channel numbers (ACC) of disturbance data can be gained by printing, implementing submenu
IEC103 Info in the menu Print.

10.4 Messages Description for IEC61850 Protocol


10.4.1 Overview
The IEC 61850 standard is the result of years of work by electric utilities and vendors of electronic
equipment to produce standardized communications systems. IEC 61850 is a series of standards
describing client/server and peer-to-peer communications, substation design and configuration,
testing, environmental and project standards. The complete set includes:

IEC 61850-1: Introduction and overview

IEC 61850-2: Glossary

IEC 61850-3: General requirements

IEC 61850-4: System and project management

IEC 61850-5: Communications and requirements for functions and device models

IEC 61850-6: Configuration description language for communication in electrical substations


related to IEDs

IEC 61850-7-1: Basic communication structure for substation and feeder equipment
Principles and models

IEC 61850-7-2: Basic communication structure for substation and feeder equipment - Abstract
communication service interface (ACSI)

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IEC 61850-7-3: Basic communication structure for substation and feeder equipment
Common data classes

IEC 61850-7-4: Basic communication structure for substation and feeder equipment
Compatible logical node classes and data classes

IEC 61850-8-1: Specific Communication Service Mapping (SCSM) Mappings to MMS (ISO
9506-1 and ISO 9506-2) and to ISO/IEC 8802-3
IEC 61850-9-1: Specific Communication Service Mapping (SCSM) Sampled values over
serial unidirectional multidrop point to point link
IEC 61850-9-2: Specific Communication Service Mapping (SCSM) Sampled values over
ISO/IEC 8802-3
IEC 61850-10: Conformance testing

These documents can be obtained from the IEC (http://www.iec.ch). It is strongly recommended
that all those involved with any IEC 61850 implementation obtain this document set.

10.4.2 Communication Profiles


The PCS-900 series relay supports IEC 61850 server services over TCP/IP communication
protocol stacks. The TCP/IP profile requires the PCS-900 series to have an IP address to establish
communications. These addresses are located in the menu SettingsDevice SetupComm
Settings.
1.

MMS protocol

IEC 61850 specifies the use of the Manufacturing Message Specification (MMS) at the upper
(application) layer for transfer of real-time data. This protocol has been in existence for a number
of years and provides a set of services suitable for the transfer of data within a substation LAN
environment. IEC 61850-7-2 abstract services and objects are mapped to actual MMS protocol
services in IEC61850-8-1.
2.

Client/server

This is a connection-oriented type of communication. The connection is initiated by the client, and
communication activity is controlled by the client. IEC61850 clients are often substation computers
running HMI programs or SOE logging software. Servers are usually substation equipment such
as protection relays, meters, RTUs, transformer, tap changers, or bay controllers.
3.

Peer-to-peer

This is a non-connection-oriented, high speed type of communication usually between substation


equipment, such as protection relays, intelligent terminal. GOOSE is the method of peer-to-peer
communication.
4.

Substation configuration language (SCL)

A substation configuration language is a number of files used to describe IED configurations and
communication systems according to IEC 61850-5 and IEC 61850-7. Each configured device has

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an IED Capability Description (ICD) file and a Configured IED Description (CID) file. The
substation single line information is stored in a System Specification Description (SSD) file. The
entire substation configuration is stored in a Substation Configuration Description (SCD) file. The
SCD file is the combination of the individual ICD files and the SSD file, moreover, add
communication system parameters (MMS, GOOSE, control block, SV control block) and the
connection relationship of GOOSE and SV to SCD file.

10.4.3 MMS Communication Network Deployment


In order to enhance the stability and reliability of SAS, dual-MMS Ethernet is widely adopted. This
section is applied to introduce the details of dual-MMS Ethernet technology. Generally,
single-MMS Ethernet is recommended to be adopted in the SAS of 110kV and lower voltage levels,
while dual-MMS Ethernet is recommended to be adopted in the SAS of voltage levels above
110kV.
Client-server mode is adopted: clients (SCADA, control center and etc.) communicate with the
IEDs via MMS communication network, and the IEDs operate as the servers. IEDs are connected
to clients passively, and they can interact with the clients according to the configuration and the
issued command of the clients.
Three modes for dual-MMS Ethernet (abbreviated as dual-net) are provided as below.
Note!
Hereinafter, the normal operation status of net means the physical link and TCP link are
both ok. The abnormal operation status of net means physical link or TCP link is broken.
10.4.3.1 Dual-net Full Duplex Mode Sharing the Same RCB Instance

Client

Client

Net A

Net B

Net A

Net B

Report Instance 1
RptEna = true

Report Instance 1
RptEna = true

Report Control Block

Report Control Block

IED (Server)

IED (Server)

Normal operation status

Abnormal operation status

TCP Link

MMS Link

Figure 10.4-1 Dual-net full duplex mode sharing the RCB block instance

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Net A and Net B share the same report control block (abbreviated as RCB) enabled by the client.
IED sends undifferentiated date through dual-net to the clients. If one net is physically
disconnected, the flag of RCB instance (i.e.: RptEna in above figure) is still true. Only when
both Net A and Net B are disconnected, the flag of the RCB instance will automatically change to
false.
In normal operation status of this mode, IED provides the same MMS service for Net A and Net B.
If one net is physically disconnected (i.e.: Abnormal operation status in above figure), the
working mode will switch to single-net mode seamlessly and immediately. Network communication
supervision is unnecessary here, and Buffered Report Control Block (abbreviated as BRCB) need
not to be used. On the other net, date alternation works normally. Therefore, MMS service can
interact normally without interruption. This mode ensures no data loss during one net is in
abnormal operation status.
In this mode, one report will be transmitted twice via dual nets for the same report instance, so the
client needs to distinguish whether two reports are same according to corresponding EntryIDs.
10.4.3.2 Dual-net Hot-standby Mode Sharing the Same RCB Instance

Client

Net A

Client

Net B

Net A

Net B

Report Instance 1
RptEna = true

Report Instance 1
RptEna = true

Report Control Block

Report Control Block

IED (Server)

IED (Server)

Normal operation status

Abnormal operation status

TCP Link

Main MMS Link

Standby MMS Link

Figure 10.4-2 Dual-net hot-standby mode sharing the same RCB instance

In this mode, the MMS service is provided on main MMS link, no MMS service interacts on the
standby MMS link. The definitions of two links are as follows:

Main MMS Link: Physically connected, TCP level connected, MMS report service available.

Standby MMS Link: Physically connected, TCP level connected, MMS report service not
available.

If the main net fails to operate (i.e.: Abnormal operation status in the above figure), the IED will
set RptEna to false. Meanwhile the client will detect the failure by heartbeat message or
keep-alive, it will automatically enable the RCB instance by setting RptEna back to true
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through standby MMS link. By the buffer function of BRCB, the IED can provide uninterrupted
MMS service on the standby net. However, the differences of BRCB standards among different
manufacturers may cause data loss. Moreover, if duration of net switch is too long, the data loss is
positively as the capacity of BRCBs buffer function is limited.
Note!
The first mode and second mode, Net A IED host address and Net B IED host address
must be the same.
For example, if the subnet mask is 255.255.0.0, network prefix of Net A is 198.120.0.0,
network prefix of Net B is 198.121.0.0, Net A IP address of the IED is 198.120.1.2, and
then Net B IP address of the IED must be configured as 198.121.1.2, i.e., Net A IED host
address =1x256+2=258, Net B IED host address =1x256+2=258, Net A IED host address
equals to Net B IED host address.
10.4.3.3 Dual-net Full Duplex Mode with 2 Independent RCB Instances

Client

Net A

Client

Net B

Report Instance 1
RptEna = true

Report Instance 2
RptEna = true

Net A

Net B

Report Instance 1
RptEna = true

Report Instance 2
RptEna = true

Report Control Block

Report Control Block

IED (Server)

IED (Server)

Normal operation status

Abnormal operation status

TCP Link

MMS Link

Figure 10.4-3 Dual-net full duplex mode with 2 independent RCB instances

In this mode, IED provides 2 report instances for each RCB, Net A and Net B work independently
from each other, failures of any net will not affect the other net at all. Tow report instances are
required for each client. Therefore, the IED may be unable to provide enough report instances if
there are too many clients.
Net A and Net B send the same report separately when they operates normally, To ensure no
repeated data is saved into database, massive calculation is required for the client.
Moreover, accurate clock synchronization of the IED is required to distinguish whether 2 reports
are the same report according to the timestamps. Clock synchronization error of the IED may lead
to report loss/redundancy.

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As a conclusion, for the second mode, its difficult to realize seamless switchover between dual
nets, however, for the third mode, the IED may be unable to provide enough report instances if too
many clients are applied on site. Considering client treatment and IED implementation, the first
mode (Dual-net full duplex mode sharing the same report instance) is recommended for MMS
communication network deployment.

10.4.4 Server Data Organization


IEC61850 defines an object-oriented approach to data and services. An IEC61850 physical device
can contain one or more logical device(s) (for proxy). Each logical device can contain many logical
nodes. Each logical node can contain many data objects. Each data object is composed of data
attributes and data attribute components. Services are available at each level for performing
various functions, such as reading, writing, control commands, and reporting.
Each IED represents one IEC61850 physical device. The physical device contains one or more
logical device(s), and the logical device contains many logical nodes. The logical node LPHD
contains information about the IED physical device. The logical node LLN0 contains common
information about the IED logical device.
10.4.4.1 Digital Status Values
The GGIO logical node is available in the PCS-900 series relays to provide access to digital status
points (including general I/O inputs and warnings) and associated timestamps and quality flags.
The data content must be configured before the data can be used. GGIO provides digital status
points for access by clients. It is intended that clients use GGIO in order to access digital status
values from the PCS-900 series relays. Clients can utilize the IEC61850 buffered reporting
features available from GGIO in order to build sequence of events (SOE) logs and HMI display
screens. Buffered reporting should generally be used for SOE logs since the buffering capability
reduces the chances of missing data state changes. All needed status data objects are transmitted
to HMI clients via buffered reporting, and the corresponding buffered reporting control block
(BRCB) is defined in LLN0.
10.4.4.2 Analog Values
Most of analog measured values are available through the MMXU logical nodes, and metering
values in MMTR, the else in MMXN, MSQI and so on. Each MMXU logical node provides data
from a IED current/voltage source. There is one MMXU available for each configurable source.
MMXU1 provides data from CT/VT source 1(usually for protection purpose), and MMXU2 provides
data from CT/VT source 2 (usually for monitor and display purpose). All these analog data objects
are transmitted to HMI clients via unbuffered reporting periodically, and the corresponding
unbuffered reporting control block (URCB) is defined in LLN0. MMXUx logical nodes provide the
following data for each source:

MMXU.MX.Hz: frequency

MMXU.MX.PPV.phsAB: phase AB voltage magnitude and angle

MMXU.MX.PPV.phsBC: phase BC voltage magnitude and angle

MMXU.MX.PPV.phsCA: Phase CA voltage magnitude and angle

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MMXU.MX.PhV.phsA: phase AG voltage magnitude and angle

MMXU.MX.PhV.phsB: phase BG voltage magnitude and angle

MMXU.MX.PhV.phsC: phase CG voltage magnitude and angle

MMXU.MX.A.phsA: phase A current magnitude and angle

MMXU.MX.A.phsB: phase B current magnitude and angle

MMXU.MX.A.phsC: phase C current magnitude and angle

10.4.4.3 Protection Logical Nodes


The following list describes the protection elements for PCS-902 series relays. The specified relay
will contain a subset of protection elements from this list.

PDIS: Phase-to-phase distance, phase-to-ground distance and SOTF distance

PTUC: Undercurrent

PTOC: Phase overcurrent, zero-sequence overcurrent and overcurrent when VT circuit failure

PTTR: Thermal overload

PTUV: Undervoltage

PTOV: Overvoltage and auxiliary overvoltage

PTOF: Overfrequency

PTUF: Underfrequency

PPDP: Pole discrepancy

PSCH: Protection scheme

RBRF:Breaker failure

RPSB: Power swing detection/blocking

RREC: Automatic reclosing

RSYN: Synchronism-check

RFLO: Fault location

The protection elements listed above contain start (pickup) and operate flags, instead of any
element has its own start (pickup) flag separately, all the elements share a common start (pickup)
flags PTRC.ST.Str.general. The operate flag for PTOC1 is PTOC1.ST.Op.general. For
PCS-902 series relays protection elements, these flags take their values from related module for
the corresponding element. Similar to digital status values, the protection trip information is
reported via BRCB, and BRCB also locates in LLN0.
10.4.4.4 LLN0 and Other Logical Nodes
Logical node LLN0 is essential for an IEC61850 based IED. This LN shall be used to address
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common issues for Logical Devices. Most of the public services, the common settings, control
values and some device oriented data objects are available here. The public services may be
BRCB, URCB and GSE control blocks and similar global defines for the whole device; the
common settings include all the setting items of communication settings, system settings and
some of the protection setting items, which can be configured to two or more protection elements
(logical nodes). In LLN0, the item Loc is a device control object, this Do item indicates the local
operation for complete logical device, when it is true, all the remote control commands to the IED
will be blocked and those commands make effective until the item Loc is changed to false. In
PCS-900 series relays, besides the logical nodes we describe above, there are some other logical
nodes below in the IEDs:

MMXU: This LN shall be used to acquire values from CTs and VTs and calculate measurands
such as r.m.s. values for current and voltage or power flows out of the acquired voltage and
current samples. These values are normally used for operational purposes such as power
flow supervision and management, screen displays, state estimation, etc. The requested
accuracy for these functions has to be provided.

LPHD: Physical device information, the logical node to model common issues for physical
device.

PTRC: Protection trip conditioning, it shall be used to connect the operate outputs of one or
more protection functions to a common trip to be transmitted to XCBR. In addition or
alternatively, any combination of operate outputs of protection functions may be combined to
a new operate of PTRC.
RDRE: Disturbance recorder function. It triggers the fault wave recorder and its output refers
to the IEEE Standard Format for Transient Data Exchange (COMTRADE) for Power System
(IEC 60255-24). All enabled channels are included in the recording, independently of the
trigger mode.

10.4.5 Server Features and Configuration


10.4.5.1 Buffered/unbuffered Reporting
IEC61850 buffered and unbuffered reporting control blocks locate in LLN0, they can be configured
to transmit information of protection trip information (in the Protection logical nodes), binary status
values (in GGIO) and analog measured/calculated values (in MMXU, MMTR and MSQI). The
reporting control blocks can be configured in CID files, and then be sent to the IED via an
IEC61850 client. The following items can be configured.

TrgOps: Trigger options.

The following bits are supported by the PCS-900 series relays:


Bit 1: Data-change
Bit 4: Integrity
Bit 5: General interrogation

OptFlds: Option Fields.

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The following bits are supported by the PCS-900 series relays:


Bit 1: Sequence-number
Bit 2: Report-time-stamp
Bit 3: Reason-for-inclusion
Bit 4: Data-set-name
Bit 5: Data-reference
Bit 7: EntryID (for buffered reports only)
Bit 8: Conf-revision
Bit 9: Segmentation

IntgPd: Integrity period.

10.4.5.2 File Transfer


MMS file services are supported to allow transfer of oscillography, event record or other files from
a PCS-900 series relay.
10.4.5.3 Timestamps
The Universal Time Coordinated(UTC for short) timestamp associated with all IEC61850 data
items represents the lastest change time of either the value or quality flags of the data item.
10.4.5.4 Logical Node Name Prefixes
IEC61850 specifies that each logical node can have a name with a total length of 11 characters.
The name is composed of:

A five or six-character name prefix.

A four-character standard name (for example, MMXU, GGIO, PIOC, etc.).

A one or two-character instantiation index.

Complete names are of the form xxxxxxPTOC1, where the xxxxxx character string is configurable.
Details regarding the logical node naming rules are given in IEC61850 parts 6 and 7-2. It is
recommended that a consistent naming convention be used for an entire substation project.
10.4.5.5 GOOSE Services
IEC61850 specifies the type of broadcast data transfer services: Generic Object Oriented
Substation Events (GOOSE). IEC61850 GOOSE services provide virtual LAN (VLAN) support,
Ethernet priority tagging, and Ether-type Application ID configuration. The support for VLANs and
priority tagging allows for the optimization of Ethernet network traffic. GOOSE messages can be
given a higher priority than standard Ethernet traffic, and they can be separated onto specific
VLANs. Devices that transmit GOOSE messages also function as servers. Each GOOSE
publisher contains a GOOSE control block to configure and control the transmission.

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The GOOSE transmission (including subscribing and publishing) is controlled by GOOSE logic link
settings in device.
The PCS-900 series relays support IEC61850 Generic Object Oriented Substation Event (GOOSE)
communication. All GOOSE messages contain IEC61850 data collected into a dataset. It is this
dataset that is transferred using GOOSE message services. The GOOSE related dataset is
configured in the CID file and it is recommended that the fixed GOOSE be used for
implementations that require GOOSE data transfer between PCS-900 series relays.
IEC61850 GOOSE messaging contains a number of configurable parameters, all of which must be
correct to achieve the successful transfer of data. It is critical that the configured datasets at the
transmission and reception devices are an exact match in terms of data structure, and that the
GOOSE addresses and name strings match exactly.

10.4.6 ACSI Conformance


10.4.6.1 ACSI Basic Conformance Statement
Services

Client

Server

PCS-900 Series

B11

Server side (of Two-party Application-Association)

C1

B12

Client side (of Two-party Application-Association)

C1

Client-Server Roles

SCSMS Supported
B21

SCSM: IEC 61850-8-1 used

B22

SCSM: IEC 61850-9-1 used

B23

SCSM: IEC 61850-9-2 used

B24

SCSM: other

Generic Substation Event Model (GSE)


B31

Publisher side

B32

Subscriber side

Transmission Of Sampled Value Model (SVC)


B41

Publisher side

B42

Subscriber side

Where:
C1: Shall be "M" if support for LOGICAL-DEVICE model has been declared
O: Optional
M: Mandatory
Y:

Supported by PCS-900 series relays

N:

Currently not supported by PCS-900 series relays

10.4.6.2 ACSI Models Conformance Statement


Services
M1

Logical device

Client

Server

PCS-900 Series

C2

C2

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M2

Logical node

C3

C3

M3

Data

C4

C4

M4

Data set

C5

C5

M5

Substitution

M6

Setting group control

M7

Buffered report control

M7-1

sequence-number

M7-2

report-time-stamp

M7-3

reason-for-inclusion

M7-4

data-set-name

M7-5

data-reference

M7-6

buffer-overflow

M7-7

entryID

M7-8

BufTm

M7-9

IntgPd

M7-10

GI

M8

Unbuffered report control

M8-1

sequence-number

M8-2

report-time-stamp

M8-3

reason-for-inclusion

M8-4

data-set-name

M8-5

data-reference

M8-6

BufTm

M8-7

IntgPd

M9

Log control

M9-1

IntgPd

M10

Log

M12

GOOSE

M13

GSSE

M14

Multicast SVC

M15

Unicast SVC

M16

Time

M17

File transfer

Reporting

Logging

GSE

Where:
C2: Shall be "M" if support for LOGICAL-NODE model has been declared
C3: Shall be "M" if support for DATA model has been declared
C4: Shall be "M" if support for DATA-SET, Substitution, Report, Log Control, or Time models has
been declared
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C5: Shall be "M" if support for Report, GSE, or SMV models has been declared
M: Mandatory
Y:

Supported by PCS-900 series relays

N:

Currently not supported by PCS-900 series relays

10.4.6.3 ACSI Services Conformance Statement


Services

Server/Publisher

PCS-902

Server
S1

ServerDirectory

Application association
S2

Associate

S3

Abort

S4

Release

Logical device
S5

LogicalDeviceDirectory

Logical node
S6

LogicalNodeDirectory

S7

GetAllDataValues

S8

GetDataValues

S9

SetDataValues

S10

GetDataDirectory

S11

GetDataDefinition

S12

GetDataSetValues

S13

SetDataSetValues

S14

CreateDataSet

S15

DeleteDataSet

S16

GetDataSetDirectory

Data

Data set

Substitution
S17

SetDataValues

Setting group control


S18

SelectActiveSG

M/O

S19

SelectEditSG

M/O

S20

SetSGValuess

M/O

S21

ConfirmEditSGValues

M/O

S22

GetSGValues

M/O

S23

GetSGCBValues

M/O

Reporting
Buffered report control block
S24

Report

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S24-1

data-change

S24-2

qchg-change

S24-3

data-update

S25

GetBRCBValues

S26

SetBRCBValues

Unbuffered report control block


S27

Report

S27-1

data-change

S27-2

qchg-change

S27-3

data-update

S28

GetURCBValues

S29

SetURCBValues

Logging
Log control block
S30

GetLCBValues

S31

SetLCBValues

S32

QueryLogByTime

S33

QueryLogAfter

S34

GetLogStatusValues

Log

Generic substation event model (GSE)


GOOSE control block
S35

SendGOOSEMessage

S36

GetGoReference

S37

GetGOOSEElementNumber

S38

GetGoCBValues

S39

SetGoCBValuess

S51

Select

S52

SelectWithValue

S53

Cancel

S54

Operate

S55

Command-Termination

S56

TimeActivated-Operate

Control

File transfer
S57

GetFile

M/O

S58

SetFile

S59

DeleteFile

S60

GetFileAttributeValues

M/O

Time
SNTP

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10.4.7 Logical Nodes


10.4.7.1 Logical Nodes Table
The PCS-902 series relays support IEC61850 logical nodes as indicated in the following table.
Note that the actual instantiation of each logical node is determined by the product order code.
Nodes

PCS-902 Series

L: System Logical Nodes


LPHD: Physical device information

YES

LLN0: Logical node zero

YES

P: Logical Nodes For Protection Functions


PDIF: Differential

PDIR: Direction comparison

PDIS: Distance

YES

PDOP: Directional overpower

PDUP: Directional underpower

PFRC: Rate of change of frequency

PHAR: Harmonic restraint

PHIZ: Ground detector

PIOC: Instantaneous overcurrent

PMRI: Motor restart inhibition

PMSS: Motor starting time supervision

POPF: Over power factor

PPAM: Phase angle measuring

PSCH: Protection scheme

YES

PSDE: Sensitive directional earth fault

PTEF: Transient earth fault

PTOC: Time overcurrent

YES

PTOF: Overfrequency

YES

PTOV: Overvoltage

YES

PTRC: Protection trip conditioning

YES

PTTR: Thermal overload

YES

PTUC: Undercurrent
PPDP: Pole discrepancy

YES

PTUV: Undervoltage

YES

PUPF: Underpower factor


PTUF: Underfrequency

YES

PVOC: Voltage controlled time overcurrent

PVPH: Volts per Hz

PZSU: Zero speed or underspeed

R: Logical Nodes For Protection Related Functions


RDRE: Disturbance recorder function

YES

RADR: Disturbance recorder channel analogue

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RBDR: Disturbance recorder channel binary

RDRS: Disturbance record handling

RBRF: Breaker failure

YES

RDIR: Directional element


RFLO: Fault locator

YES

RPSB: Power swing detection/blocking

YES

RREC: Autoreclosing

YES

RSYN: Synchronism-check or synchronizing

YES

C: Logical Nodes For Control


CALH: Alarm handling

CCGR: Cooling group control

CILO: Interlocking

CPOW: Point-on-wave switching

CSWI: Switch controller

G: Logical Nodes For Generic References


GAPC: Generic automatic process control

YES

GGIO: Generic process I/O

YES

GSAL: Generic security application


I: Logical Nodes For Interfacing And Archiving
IARC: Archiving

IHMI: Human machine interface

ITCI: Telecontrol interface

ITMI: Telemonitoring interface

A: Logical Nodes For Automatic Control


ANCR: Neutral current regulator

ARCO: Reactive power control

ATCC: Automatic tap changer controller

AVCO: Voltage control

M: Logical Nodes For Metering And Measurement


MDIF: Differential measurements

MHAI: Harmonics or interharmonics

MHAN: Non phase related harmonics or interharmonic

MMTR: Metering

MMXN: Non phase related measurement

MMXU: Measurement

YES

MSQI: Sequence and imbalance

MSTA: Metering statistics

S: Logical Nodes For Sensors And Monitoring


SARC: Monitoring and diagnostics for arcs

SIMG: Insulation medium supervision (gas)

SIML: Insulation medium supervision (liquid)

SPDC: Monitoring and diagnostics for partial discharges

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10 Communication
X: Logical Nodes For Switchgear
TCTR: Current transformer

YES

TVTR: Voltage transformer

YES

Y: Logical Nodes For Power Transformers


YEFN: Earth fault neutralizer (Peterson coil)

YLTC: Tap changer

YPSH: Power shunt

YPTR: Power transformer

Z: Logical Nodes For Further Power System Equipment


ZAXN: Auxiliary network

ZBAT: Battery

ZBSH: Bushing

ZCAB: Power cable

ZCAP: Capacitor bank

ZCON: Converter

ZGEN: Generator

ZGIL: Gas insulated line

ZLIN: Power overhead line

ZMOT: Motor

ZREA: Reactor

ZRRC: Rotating reactive component

ZSAR: Surge arrestor

ZTCF: Thyristor controlled frequency converter

ZTRC: Thyristor controlled reactive component

10.5 DNP3.0 Interface


10.5.1 Overview
The descriptions given here are intended to accompany this relay. The DNP3.0 protocol is not
described here; please refer to the DNP3.0 protocol standard for the details about the DNP3.0
implementation. This manual only specifies which objects, variations and qualifiers are supported
in this relay, and also specifies what data is available from this relay via DNP3.0.
The relay operates as a DNP3.0 slave and supports subset level 2 of the protocol, plus some of
the features from level 3. The DNP3.0 communication uses the Ethernet ports at the rear side of
this relay. The Ethernet ports are optional: electrical or optical.

10.5.2 Link Layer Functions


Please see the DNP3.0 protocol standard for the details about the linker layer functions.

10.5.3 Transport Functions


Please see the DNP3.0 protocol standard for the details about the transport functions.

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10 Communication

10.5.4 Application Layer Functions


10.5.4.1 Time Synchronization
1.

2.

3.

Time delay measurement


Master/Slave

Function Code

Object

Variation

Qualifier

Master

0x17

Slave

0x81

0x34

0x02

0x07

Master/Slave

Function Code

Object

Variation

Qualifier

Master

0x01

0x34

0x00, 0x01

0x07-

Slave

0x81

0x32

0x01

0x07

Read time of device

Write time of device


Master/Slave

Function Code

Object

Variation

Qualifier

Master

0x02

0x32

0x01

0x00, 0x01, 0x07, 0x08

Slave

0x81

10.5.4.2 Supported Writing Functions


1.

Write time of device


See Section 10.5.4.1 for the details.

2.

Reset the CU (Reset IIN bit7)


Master/Slave

Function Code

Object

Variation

Qualifier

Master

0x02

0x50

0x01

0x00, 0x01

Slave

0x81

10.5.4.3 Supported Reading Functions


1.

2.

Supported qualifiers
Master Qualifier

0x00

0x01

0x06

0x07

0x08

Slave Qualifier

0x00

0x01

0x01

0x07

0x08

Supported objects and variations

Object 1, Binary inputs


Master Variation

0x00

0x01

0x02

Slave Variation

0x02

0x01

0x02

The protection operation signals, alarm signals and binary input state change signals are
transported respectively according to the variation sequence in above table.

Object 2, SOE
Master Variation

0x00

0x01

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0x02

0x03

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10 Communication
0x02

Slave Variation

0x01

0x02

0x03

If the master qualifier is 0x07, the slave responsive qualifier is 0x27; and if the master
qualifier is 0x01, 0x06 or 0x08, the slave responsive qualifier is 0x28.

Object 30, Analog inputs


Master Variation

0x00

0x01

0x02

0x03

0x04

Slave Variation

0x01

0x01

0x02

0x03

0x04

The measurement values are transported firstly, and then the measurement values are
transported.

Object 40, Analog outputs


Master Variation

0x00

0x01

0x02

Slave Variation

0x01

0x01

0x02

The protection settings are transported in this object.

Object 50, Time Synchronization


See Section 10.5.4.1 for the details.

3.

Class 0 data request


The master adopts the Object 60 for the Class 0 data request and the variation is 0x01.
The slave responds with the above mentioned Object 1, Object 30 and Object 40 (see
Supported objects and variations in Section 10.5.4.3).

4.

Class 1 data request


The master adopts the Object 60 for the Class 1 data request and the variation is 0x02.
The slave responds with the above mentioned Object 2 (see Supported objects and
variations in Section 10.5.4.3).

5.

Multiple object request


The master adopts the Object 60 for the multiple object request and the variation is 0x01,
0x02, 0x03 and 0x04.
The slave responds with the above mentioned Object 1, Object 2, Object 30 and Object
40 (see Supported objects and variations in Section 10.5.4.3).

10.5.4.4 Remote Control Functions


The function code 0x03 and 0x04 are supported in this relay. The function code 0x03 is for the
remote control with selection; and the function code 0x04 is for the remote control with execution.
The selection operation must be executed before the execution operation, and the single point
control object can be supported to this relay.
Master Qualifier

0x17

0x27

PCS-902 Line Distance Relay

0x18

0x28

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10 Communication
Slave Qualifier

0x17

0x27

0x18

0x28

The Object 12 is for the remote control functions.


Master Variation

0x01

Slave Variation

0x01

Control Code

0x01: closing
0x10: tripping

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11 Installation

11 Installation
Table of Contents
11 Installation .................................................................................... 11-a
11.1 Overview ....................................................................................................... 11-1
11.2 Safety Information ........................................................................................ 11-1
11.3 Checking Shipment ...................................................................................... 11-2
11.4 Material and Tools Required........................................................................ 11-2
11.5 Device Location and Ambient Conditions.................................................. 11-2
11.6 Mechanical Installation ................................................................................ 11-3
11.7 Electrical Installation and Wiring ................................................................ 11-4
11.7.1 Grounding Guidelines .................................................................................................... 11-4
11.7.2 Cubicle Grounding ......................................................................................................... 11-4
11.7.3 Ground Connection on the Device ................................................................................. 11-5
11.7.4 Grounding Strips and their Installation............................................................................ 11-6
11.7.5 Guidelines for Wiring ...................................................................................................... 11-6
11.7.6 Wiring for Electrical Cables ............................................................................................ 11-7

List of Figures
Figure 11.6-1 Dimensions and panel cut-out of PCS-902 ..................................................... 11-3
Figure 11.6-3 Demonstration of plugging a board into its corresponding slot .................. 11-4
Figure 11.7-1 Cubicle grounding system ............................................................................... 11-5
Figure 11.7-2 Ground terminal of this relay ........................................................................... 11-6
Figure 11.7-3 Ground strip and termination .......................................................................... 11-6
Figure 11.7-4 Glancing demo about the wiring for electrical cables ................................... 11-7

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11 Installation

11.1 Overview
The device must be shipped, stored and installed with the greatest care.
Choose the place of installation such that the communication interface and the controls on the
front of the device are easily accessible.
Air must circulate freely around the equipment. Observe all the requirements regarding place of
installation and ambient conditions given in this instruction manual.
Take care that the external wiring is properly brought into the equipment and terminated correctly
and pay special attention to grounding. Strictly observe the corresponding guidelines contained in
this section.

11.2 Safety Information


Modules and units may only be replaced by correspondingly trained personnel. Always observe
the basic precautions to avoid damage due to electrostatic discharge when handling the
equipment.
In certain cases, the settings have to be configured according to the demands of the engineering
configuration after replacement. It is therefore assumed that the personnel who replace modules
and units are familiar with the use of the operator program on the service PC.
DANGER!
Only insert or withdraw the PWR module while the power supply is switched off. To this end,
disconnect the power supply cable that connects with the PWR module.
WARNING!
Only insert or withdraw other modules while the power supply is switched off.
WARNING!
The modules may only be inserted in the slots designated in Section 6.2. Components can
be damaged or destroyed by inserting boards in the wrong slots.
DANGER!
Improper handling of the equipment can cause damage or an incorrect response of the
equipment itself or the primary plant.
WARNING!
Industry packs and ribbon cables may only be replaced or the positions of jumpers be
changed on a workbench appropriately designed for working on electronic equipment. The
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11 Installation

modules, bus backplanes are sensitive to electrostatic discharge when not in the unit's
housing.
The basic precautions to guard against electrostatic discharge are as follows:

Should boards have to be removed from this relay installed in a grounded cubicle in an HV
switchgear installation, please discharge yourself by touching station ground (the cubicle)
beforehand.

Only hold electronic boards at the edges, taking care not to touch the components.

Only works on boards that have been removed from the cubicle on a workbench designed for
electronic equipment and wear a grounded wristband. Do not wear a grounded wristband,
however, while inserting or withdrawing units.

Always store and ship the electronic boards in their original packing. Place electronic parts in
electrostatic screened packing materials.

11.3 Checking Shipment


Check that the consignment is complete immediately upon receipt. Notify the nearest NR
Company or agent, should departures from the delivery note, the shipping papers or the order be
found.
Visually inspect all the material when unpacking it. When there is evidence of transport damage,
lodge a claim immediately in writing with the last carrier and notify the nearest NR Company or
agent.
If the equipment is not going to be installed immediately, store all the parts in their original packing
in a clean dry place at a moderate temperature. The humidity at a maximum temperature and the
permissible storage temperature range in dry air are listed in Chapter Technical Data.

11.4 Material and Tools Required


The necessary mounting kits will be provided, including screws, pincers and assembly
instructions.
A suitable drill and spanners are required to secure the cubicles to the floor using the plugs
provided (if this relay is mounted in cubicles).

11.5 Device Location and Ambient Conditions


The place of installation should permit easy access especially to front of the device, i.e. to the
human machine interface of the equipment.
There should also be free access at the rear of the equipment for additions and replacement of
electronic boards.
Since every piece of technical equipment can be damaged or destroyed by inadmissible ambient
conditions, such as:

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11 Installation

1.

The location should not be exposed to excessive air pollution (dust, aggressive substances).

2.

Severe vibration, extreme changes of temperature, high levels of humidity, surge voltages of
high amplitude and short rise time and strong induced magnetic fields should be avoided as
far as possible.

3.

Air must not be allowed to circulate freely around the equipment.

The equipment can in principle be mounted in any attitude, but it is normally mounted vertically
(visibility of markings).
WARNING!
Excessively high temperature can appreciably reduce the operating life of this relay.

11.6 Mechanical Installation


The device adopts IEC standard chassis and is rack with modular structure. It uses an integral
faceplate and plug terminal block on backboard for external connections. PCS-902 series is IEC
4U high, and Figure 11.6-1 shows its dimensions and panel cut-out.

Figure 11.6-1 Dimensions and panel cut-out of PCS-902

Note!
It is necessary to leave enough space top and bottom of the cut-out in the cubicle for heat
emission of this relay.
The safety instructions must be abided by when installing the boards, please see Section 11.2 for
the details.
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11 Installation

Following figure shows the installation way of a module being plugged into a corresponding slot.

Figure 11.6-2 Demonstration of plugging a board into its corresponding slot

In the case of equipment supplied in cubicles, place the cubicles on the foundations that have
been prepared. Take care while doing so not to jam or otherwise damage any of the cables that
have already been installed. Secure the cubicles to the foundations.

11.7 Electrical Installation and Wiring


11.7.1 Grounding Guidelines
Switching operations in HV installations generate transient over voltages on control signal cables.
There is also a background of electromagnetic RF fields in electrical installations that can induce
spurious currents in the devices themselves or the leads connected to them.
All these influences can influence the operation of electronic apparatus.
On the other hand, electronic apparatus can transmit interference that can disrupt the operation of
other apparatus.
In order to minimize these influences as far as possible, certain standards have to be observed
with respect to grounding, wiring and screening.
Note!
All these precautions can only be effective if the station ground is of good quality.

11.7.2 Cubicle Grounding


The cubicle must be designed and fitted out such that the impedance for RF interference of the
ground path from the electronic device to the cubicle ground terminal is as low as possible.
Metal accessories such as side plates, blanking plates etc., must be effectively connected
surface-to-surface to the grounded frame to ensure a low-impedance path to ground for RF
interference. The contact surfaces must not only conduct well, they must also be non-corroding.
Note!
If the above conditions are not fulfilled, there is a possibility of the cubicle or parts of it
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11 Installation

forming a resonant circuit at certain frequencies that would amplify the transmission of
interference by the devices installed and also reduce their immunity to induced interference.
Movable parts of the cubicle such as doors (front and back) or hinged equipment frames must be
effectively grounded to the frame by three braided copper strips (see Figure 11.7-1).
The metal parts of the cubicle housing and the ground rail are interconnected electrically
conducting and corrosion proof. The contact surfaces shall be as large as possible.
Note!
For metallic connections please observe the voltage difference of both materials according
to the electrochemical code.
The cubicle ground rail must be effectively connected to the station ground rail by a grounding strip
(braided copper).

Door or hinged
equipment frame

Cubicle ground
rail close to floor

Braided
copper strip
Station
ground
Conducting
connection

Figure 11.7-1 Cubicle grounding system

11.7.3 Ground Connection on the Device


There is a ground terminal on the rear panel, and the ground braided copper strip can be
connected with it. Take care that the grounding strip is always as short as possible. The main thing
is that the device is only grounded at one point. Grounding loops from unit to unit are not allowed.
There are some ground terminals on some connectors of this relay, and the sign is GND. All the
ground terminals are connected in the cabinet of this relay. So, the ground terminal on the rear
panel (see Figure 11.7-2) is the only ground terminal of this device.

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11 Installation

Figure 11.7-2 Ground terminal of this relay

11.7.4 Grounding Strips and their Installation


High frequency currents are produced by interference in the ground connections and because of
skin effect at these frequencies, only the surface region of the grounding strips is of consequence.
The grounding strips must therefore be of (preferably tinned) braided copper and not round copper
conductors, as the cross-section of round copper would have to be too large.
Proper terminations must be fitted to both ends (press/pinch fit and tinned) with a hole for bolting
them firmly to the items to be connected.
The surfaces to which the grounding strips are bolted must be electrically conducting and
non-corroding.
The following figure shows the ground strip and termination.
Press/pinch fit
cable terminal

Braided
copper strip

Terminal bolt
Contact surface

Figure 11.7-3 Ground strip and termination

11.7.5 Guidelines for Wiring


There are several types of cables that are used in the connection of this relay: braided copper
cable, serial communication cable etc. Recommendation of each cable:

Grounding: braided copper cable, 2.5mm2 ~ 6.0mm2

Power supply, binary inputs & outputs: brained copper cable, 1.0mm2 ~ 2.5mm2

AC voltage inputs: brained copper cable, 1.0mm2 ~ 2.5mm2

AC current inputs: brained copper cable, 1.5mm2 ~ 4.0mm2

Serial communication: 4-core shielded braided cable

Ethernet communication: 4-pair screened twisted category 5E cable

11-6

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11 Installation

11.7.6 Wiring for Electrical Cables


A female connector is used for connecting the wires with it, and then a female connector plugs into
a corresponding male connector that is in the front of one board. See Chapter Hardware for
further details about the pin defines of these connectors.
The following figure shows the glancing demo about the wiring for the electrical cables.

Tighten

01

02

03

04

05

06

07

08

09

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

01

Figure 11.7-4 Glancing demo about the wiring for electrical cables

DANGER!
Never allow the current transformer (CT) secondary circuit connected to this equipment to
be opened while the primary system is live. Opening the CT circuit will produce a
dangerously high voltage.

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12 Commissioning

12 Commissioning
Table of Contents
12 Commissioning ............................................................................ 12-a
12.1 Overview ...................................................................................................... 12-1
12.2 Safety Instructions ...................................................................................... 12-1
12.3 Commission Tools ...................................................................................... 12-2
12.4 Setting Familiarization ................................................................................ 12-2
12.5 Product Checks ........................................................................................... 12-3
12.5.1 With the Relay De-energized ......................................................................................... 12-3
12.5.2 With the Relay Energized............................................................................................... 12-5
12.5.3 Print Fault Report ........................................................................................................... 12-8
12.5.4 On-load Checks ............................................................................................................. 12-8

12.6 Final Checks ................................................................................................ 12-9

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12 Commissioning

12.1 Overview
This relay is fully numerical in their design, implementing all protection and non-protection
functions in software. The relay employs a high degree of self-checking and in the unlikely event of
a failure, will give an alarm. As a result of this, the commissioning test does not need to be as
extensive as with non-numeric electronic or electro-mechanical relays.
To commission numerical relays, it is only necessary to verify that the hardware is functioning
correctly and the application-specific software settings have been applied to the relay.
Blank commissioning test and setting records are provided at the end of this manual for
completion as required.
Before carrying out any work on the equipment, the user should be familiar with the contents of the
safety and technical data sections and the ratings on the equipments rating label.

12.2 Safety Instructions


WARNING!
Hazardous voltages are present in this electrical equipment during operation.
Non-observance of the safety rules