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OptiX OSN 3500 II Intelligent Optical Transmission System

V100R009

Hardware Description

Issue

02

Date

2009-07-30

Huawei Proprietary and Confidential


Copyright Huawei Technologies Co., Ltd.

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Huawei Proprietary and Confidential


Copyright Huawei Technologies Co., Ltd.

OptiX OSN 3500 II Intelligent Optical Transmission System


Hardware Description

Contents

Contents
About This Document.....................................................................................................................1
1 Equipment Structure.................................................................................................................1-1
2 Cabinet.........................................................................................................................................2-1
2.1 Types of Cabinets............................................................................................................................................2-2
2.2 Configuration of the Cabinet...........................................................................................................................2-3
2.2.1 Indicators................................................................................................................................................2-3
2.2.2 DC PDU.................................................................................................................................................2-4
2.2.3 Other Configurations..............................................................................................................................2-5
2.3 Technical Specifications.................................................................................................................................2-5

3 Subrack.........................................................................................................................................3-1
3.1 Slot Access Capacity.......................................................................................................................................3-2
3.2 Structure..........................................................................................................................................................3-3
3.3 Slot Allocation.................................................................................................................................................3-4
3.4 Technical Specifications.................................................................................................................................3-6

4 Board List and Classification...................................................................................................4-1


4.1 Appearances and Dimensions of the Boards...................................................................................................4-2
4.2 Bar Codes of the Boards..................................................................................................................................4-3
4.3 Classification of the Boards............................................................................................................................4-4

5 SDH Boards.................................................................................................................................5-1
5.1 SL1..................................................................................................................................................................5-4
5.1.1 Version Description................................................................................................................................5-4
5.1.2 Functions and Features...........................................................................................................................5-5
5.1.3 Working Principle and Signal Flow.......................................................................................................5-6
5.1.4 Front Panel.............................................................................................................................................5-8
5.1.5 Valid Slots............................................................................................................................................5-10
5.1.6 Feature Code........................................................................................................................................5-10
5.1.7 Parameter Settings................................................................................................................................5-10
5.1.8 Technical Specifications......................................................................................................................5-11
5.2 SL1A.............................................................................................................................................................5-12
5.2.1 Version Description..............................................................................................................................5-13
5.2.2 Functions and Features.........................................................................................................................5-13
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Contents

OptiX OSN 3500 II Intelligent Optical Transmission System


Hardware Description
5.2.3 Working Principle and Signal Flow.....................................................................................................5-14
5.2.4 Front Panel...........................................................................................................................................5-16
5.2.5 Valid Slots............................................................................................................................................5-18
5.2.6 Feature Code........................................................................................................................................5-18
5.2.7 Parameter Settings................................................................................................................................5-18
5.2.8 Technical Specifications......................................................................................................................5-18

5.3 SLQ1.............................................................................................................................................................5-20
5.3.1 Version Description..............................................................................................................................5-20
5.3.2 Functions and Features.........................................................................................................................5-21
5.3.3 Working Principle and Signal Flow.....................................................................................................5-22
5.3.4 Front Panel...........................................................................................................................................5-24
5.3.5 Valid Slots............................................................................................................................................5-26
5.3.6 Feature Code........................................................................................................................................5-26
5.3.7 Parameter Settings................................................................................................................................5-26
5.3.8 Technical Specifications......................................................................................................................5-27
5.4 SLQ1A..........................................................................................................................................................5-28
5.4.1 Version Description..............................................................................................................................5-28
5.4.2 Functions and Features.........................................................................................................................5-29
5.4.3 Working Principle and Signal Flow.....................................................................................................5-30
5.4.4 Front Panel...........................................................................................................................................5-32
5.4.5 Valid Slots............................................................................................................................................5-34
5.4.6 Feature Code........................................................................................................................................5-34
5.4.7 Parameter Settings................................................................................................................................5-34
5.4.8 Technical Specifications......................................................................................................................5-35
5.5 SLO1.............................................................................................................................................................5-36
5.5.1 Version Description..............................................................................................................................5-36
5.5.2 Functions and Features.........................................................................................................................5-37
5.5.3 Working Principle and Signal Flow.....................................................................................................5-38
5.5.4 Front Panel...........................................................................................................................................5-40
5.5.5 Valid Slots............................................................................................................................................5-42
5.5.6 Feature Code........................................................................................................................................5-42
5.5.7 Parameter Settings................................................................................................................................5-43
5.5.8 Technical Specifications......................................................................................................................5-43
5.6 SLT1..............................................................................................................................................................5-44
5.6.1 Version Description..............................................................................................................................5-45
5.6.2 Functions and Features.........................................................................................................................5-45
5.6.3 Working Principle and Signal Flow.....................................................................................................5-46
5.6.4 Front Panel...........................................................................................................................................5-48
5.6.5 Valid Slots............................................................................................................................................5-50
5.6.6 Parameter Settings................................................................................................................................5-50
5.6.7 Technical Specifications......................................................................................................................5-50
5.7 SLH1B...........................................................................................................................................................5-51
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Hardware Description

Contents

5.7.1 Version Description..............................................................................................................................5-52


5.7.2 Functions and Features.........................................................................................................................5-52
5.7.3 Working Principle and Signal Flow.....................................................................................................5-53
5.7.4 Front Panel...........................................................................................................................................5-56
5.7.5 Valid Slots............................................................................................................................................5-57
5.7.6 Board Protection...................................................................................................................................5-58
5.7.7 Parameter Settings................................................................................................................................5-60
5.7.8 Technical Specifications......................................................................................................................5-60
5.8 SEP1..............................................................................................................................................................5-61
5.8.1 Version Description..............................................................................................................................5-61
5.8.2 Functions and Features.........................................................................................................................5-61
5.8.3 Working Principle and Signal Flow.....................................................................................................5-63
5.8.4 Front Panel...........................................................................................................................................5-67
5.8.5 Valid Slots............................................................................................................................................5-69
5.8.6 Board Protection...................................................................................................................................5-69
5.8.7 Parameter Settings................................................................................................................................5-71
5.8.8 Technical Specifications......................................................................................................................5-72
5.9 SL4................................................................................................................................................................5-72
5.9.1 Version Description..............................................................................................................................5-73
5.9.2 Functions and Features.........................................................................................................................5-73
5.9.3 Working Principle and Signal Flow.....................................................................................................5-75
5.9.4 Front Panel...........................................................................................................................................5-77
5.9.5 Valid Slots............................................................................................................................................5-78
5.9.6 Feature Code........................................................................................................................................5-78
5.9.7 Parameter Settings................................................................................................................................5-79
5.9.8 Technical Specifications......................................................................................................................5-79
5.10 SL4A...........................................................................................................................................................5-80
5.10.1 Version Description............................................................................................................................5-81
5.10.2 Functions and Features.......................................................................................................................5-81
5.10.3 Working Principle and Signal Flow...................................................................................................5-82
5.10.4 Front Panel.........................................................................................................................................5-84
5.10.5 Valid Slots..........................................................................................................................................5-86
5.10.6 Feature Code......................................................................................................................................5-86
5.10.7 Parameter Settings..............................................................................................................................5-86
5.10.8 Technical Specifications....................................................................................................................5-87
5.11 SLD4...........................................................................................................................................................5-88
5.11.1 Version Description............................................................................................................................5-88
5.11.2 Functions and Features.......................................................................................................................5-89
5.11.3 Working Principle and Signal Flow...................................................................................................5-90
5.11.4 Front Panel.........................................................................................................................................5-92
5.11.5 Valid Slots..........................................................................................................................................5-94
5.11.6 Feature Code......................................................................................................................................5-94
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iii

Contents

OptiX OSN 3500 II Intelligent Optical Transmission System


Hardware Description
5.11.7 Parameter Settings..............................................................................................................................5-94
5.11.8 Technical Specifications....................................................................................................................5-95

5.12 SLD4A........................................................................................................................................................5-96
5.12.1 Version Description............................................................................................................................5-97
5.12.2 Functions and Features.......................................................................................................................5-97
5.12.3 Working Principle and Signal Flow...................................................................................................5-98
5.12.4 Front Panel.......................................................................................................................................5-100
5.12.5 Valid Slots........................................................................................................................................5-102
5.12.6 Feature Code....................................................................................................................................5-102
5.12.7 Parameter Settings............................................................................................................................5-102
5.12.8 Technical Specifications..................................................................................................................5-103
5.13 SLQ4.........................................................................................................................................................5-104
5.13.1 Version Description..........................................................................................................................5-104
5.13.2 Functions and Features.....................................................................................................................5-105
5.13.3 Working Principle and Signal Flow.................................................................................................5-106
5.13.4 Front Panel.......................................................................................................................................5-108
5.13.5 Valid Slots........................................................................................................................................5-110
5.13.6 Feature Code....................................................................................................................................5-110
5.13.7 Parameter Settings............................................................................................................................5-110
5.13.8 Technical Specifications..................................................................................................................5-111
5.14 SLQ4A......................................................................................................................................................5-112
5.14.1 Version Description..........................................................................................................................5-112
5.14.2 Functions and Features.....................................................................................................................5-113
5.14.3 Working Principle and Signal Flow.................................................................................................5-114
5.14.4 Front Panel.......................................................................................................................................5-116
5.14.5 Valid Slots........................................................................................................................................5-118
5.14.6 Feature Code....................................................................................................................................5-118
5.14.7 Parameter Settings............................................................................................................................5-118
5.14.8 Technical Specifications..................................................................................................................5-119
5.15 SL16..........................................................................................................................................................5-120
5.15.1 Version Description..........................................................................................................................5-120
5.15.2 Functions and Features.....................................................................................................................5-121
5.15.3 Working Principle and Signal Flow.................................................................................................5-123
5.15.4 Front Panel.......................................................................................................................................5-125
5.15.5 Valid Slots........................................................................................................................................5-127
5.15.6 Feature Code....................................................................................................................................5-127
5.15.7 Parameter Settings............................................................................................................................5-127
5.15.8 Technical Specifications..................................................................................................................5-128
5.16 SL16A.......................................................................................................................................................5-130
5.16.1 Version Description..........................................................................................................................5-130
5.16.2 Functions and Features.....................................................................................................................5-131
5.16.3 Working Principle and Signal Flow.................................................................................................5-133
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OptiX OSN 3500 II Intelligent Optical Transmission System


Hardware Description

Contents

5.16.4 Front Panel.......................................................................................................................................5-135


5.16.5 Valid Slots........................................................................................................................................5-136
5.16.6 Feature Code....................................................................................................................................5-136
5.16.7 Parameter Settings............................................................................................................................5-136
5.16.8 Technical Specifications..................................................................................................................5-137
5.17 SLD16.......................................................................................................................................................5-138
5.17.1 Version Description..........................................................................................................................5-139
5.17.2 Functions and Features.....................................................................................................................5-139
5.17.3 Working Principle and Signal Flow.................................................................................................5-140
5.17.4 Front Panel.......................................................................................................................................5-142
5.17.5 Valid Slots........................................................................................................................................5-144
5.17.6 Feature Code....................................................................................................................................5-144
5.17.7 Parameter Settings............................................................................................................................5-144
5.17.8 Technical Specifications..................................................................................................................5-145
5.18 SLQ16.......................................................................................................................................................5-146
5.18.1 Version Description..........................................................................................................................5-147
5.18.2 Functions and Features.....................................................................................................................5-147
5.18.3 Working Principle and Signal Flow.................................................................................................5-149
5.18.4 Front Panel.......................................................................................................................................5-151
5.18.5 Valid Slots........................................................................................................................................5-153
5.18.6 Feature Code....................................................................................................................................5-153
5.18.7 Parameter Settings............................................................................................................................5-154
5.18.8 Technical Specifications..................................................................................................................5-154
5.19 SF16..........................................................................................................................................................5-155
5.19.1 Version Description..........................................................................................................................5-155
5.19.2 Functions and Features.....................................................................................................................5-156
5.19.3 Working Principle and Signal Flow.................................................................................................5-157
5.19.4 Front Panel.......................................................................................................................................5-159
5.19.5 Valid Slots........................................................................................................................................5-161
5.19.6 Parameter Settings............................................................................................................................5-161
5.19.7 Technical Specifications..................................................................................................................5-161
5.20 SL64..........................................................................................................................................................5-163
5.20.1 Version Description..........................................................................................................................5-164
5.20.2 Functions and Features.....................................................................................................................5-164
5.20.3 Working Principle and Signal Flow.................................................................................................5-165
5.20.4 Front Panel.......................................................................................................................................5-167
5.20.5 Valid Slots........................................................................................................................................5-169
5.20.6 Feature Code....................................................................................................................................5-169
5.20.7 Parameter Settings............................................................................................................................5-170
5.20.8 Technical Specifications..................................................................................................................5-170
5.21 SF64..........................................................................................................................................................5-172
5.21.1 Version Description..........................................................................................................................5-173
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Contents

OptiX OSN 3500 II Intelligent Optical Transmission System


Hardware Description
5.21.2 Functions and Features.....................................................................................................................5-173
5.21.3 Working Principle and Signal Flow.................................................................................................5-174
5.21.4 Front Panel.......................................................................................................................................5-175
5.21.5 Valid Slots........................................................................................................................................5-177
5.21.6 Parameter Settings............................................................................................................................5-177
5.21.7 Technical Specifications..................................................................................................................5-177

5.22 SF64A........................................................................................................................................................5-179
5.22.1 Version Description..........................................................................................................................5-179
5.22.2 Functions and Features.....................................................................................................................5-179
5.22.3 Working Principle and Signal Flow.................................................................................................5-181
5.22.4 Front Panel.......................................................................................................................................5-182
5.22.5 Valid Slots........................................................................................................................................5-184
5.22.6 Parameter Settings............................................................................................................................5-184
5.22.7 Technical Specifications..................................................................................................................5-184
5.23 SLQ41.......................................................................................................................................................5-186
5.23.1 Version Description..........................................................................................................................5-187
5.23.2 Functions and Features.....................................................................................................................5-187
5.23.3 Working Principle and Signal Flow.................................................................................................5-188
5.23.4 Front Panel.......................................................................................................................................5-190
5.23.5 Valid Slots........................................................................................................................................5-192
5.23.6 Feature Code....................................................................................................................................5-192
5.23.7 Parameter Settings............................................................................................................................5-192
5.23.8 Technical Specifications..................................................................................................................5-193

6 PDH Boards.................................................................................................................................6-1
6.1 PQ1..................................................................................................................................................................6-3
6.1.1 Version Description................................................................................................................................6-3
6.1.2 Functions and Features...........................................................................................................................6-4
6.1.3 Working Principle and Signal Flow.......................................................................................................6-5
6.1.4 Front Panel............................................................................................................................................. 6-7
6.1.5 Valid Slots..............................................................................................................................................6-9
6.1.6 Feature Code........................................................................................................................................6-10
6.1.7 Board Protection...................................................................................................................................6-10
6.1.8 Parameter Settings................................................................................................................................6-12
6.1.9 Technical Specifications......................................................................................................................6-12
6.2 PO1................................................................................................................................................................6-13
6.2.1 Version Description..............................................................................................................................6-13
6.2.2 Functions and Features.........................................................................................................................6-13
6.2.3 Working Principle and Signal Flow.....................................................................................................6-14
6.2.4 Front Panel...........................................................................................................................................6-17
6.2.5 Valid Slots............................................................................................................................................6-18
6.2.6 Feature Code........................................................................................................................................6-19
6.2.7 Parameter Settings................................................................................................................................6-19
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OptiX OSN 3500 II Intelligent Optical Transmission System


Hardware Description

Contents

6.2.8 Technical Specifications......................................................................................................................6-20


6.3 PQM..............................................................................................................................................................6-20
6.3.1 Version Description..............................................................................................................................6-21
6.3.2 Functions and Features.........................................................................................................................6-21
6.3.3 Working Principle and Signal Flow.....................................................................................................6-21
6.3.4 Front Panel...........................................................................................................................................6-24
6.3.5 Valid Slots............................................................................................................................................6-25
6.3.6 Board Protection...................................................................................................................................6-26
6.3.7 Parameter Settings................................................................................................................................6-28
6.3.8 Technical Specifications......................................................................................................................6-28
6.4 PL3................................................................................................................................................................6-29
6.4.1 Version Description..............................................................................................................................6-29
6.4.2 Functions and Features.........................................................................................................................6-30
6.4.3 Working Principle and Signal Flow.....................................................................................................6-31
6.4.4 Front Panel...........................................................................................................................................6-33
6.4.5 Valid Slots............................................................................................................................................6-34
6.4.6 Board Protection...................................................................................................................................6-34
6.4.7 Parameter Settings................................................................................................................................6-37
6.4.8 Technical Specifications......................................................................................................................6-37
6.5 PL3A.............................................................................................................................................................6-37
6.5.1 Version Description..............................................................................................................................6-38
6.5.2 Functions and Features.........................................................................................................................6-38
6.5.3 Working Principle and Signal Flow.....................................................................................................6-39
6.5.4 Front Panel...........................................................................................................................................6-42
6.5.5 Valid Slots............................................................................................................................................6-43
6.5.6 Parameter Settings................................................................................................................................6-43
6.5.7 Technical Specifications......................................................................................................................6-43
6.6 PD3................................................................................................................................................................6-44
6.6.1 Version Description..............................................................................................................................6-44
6.6.2 Functions and Features.........................................................................................................................6-45
6.6.3 Working Principle and Signal Flow.....................................................................................................6-46
6.6.4 Front Panel...........................................................................................................................................6-48
6.6.5 Valid Slots............................................................................................................................................6-50
6.6.6 Board Protection...................................................................................................................................6-50
6.6.7 Parameter Settings................................................................................................................................6-52
6.6.8 Technical Specifications......................................................................................................................6-53
6.7 PQ3................................................................................................................................................................6-53
6.7.1 Version Description..............................................................................................................................6-54
6.7.2 Functions and Features.........................................................................................................................6-54
6.7.3 Working Principle and Signal Flow.....................................................................................................6-55
6.7.4 Front Panel...........................................................................................................................................6-57
6.7.5 Valid Slots............................................................................................................................................6-58
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Contents

OptiX OSN 3500 II Intelligent Optical Transmission System


Hardware Description
6.7.6 Board Protection...................................................................................................................................6-58
6.7.7 Parameter Settings................................................................................................................................6-61
6.7.8 Technical Specifications......................................................................................................................6-61

6.8 DX1...............................................................................................................................................................6-61
6.8.1 Version Description..............................................................................................................................6-62
6.8.2 Functions and Features.........................................................................................................................6-62
6.8.3 Working Principle and Signal Flow.....................................................................................................6-63
6.8.4 Front Panel...........................................................................................................................................6-64
6.8.5 Valid Slots............................................................................................................................................6-66
6.8.6 Feature Code........................................................................................................................................6-66
6.8.7 Board Protection...................................................................................................................................6-67
6.8.8 Parameter Settings................................................................................................................................6-68
6.8.9 Technical Specifications......................................................................................................................6-69
6.9 DXA..............................................................................................................................................................6-69
6.9.1 Version Description..............................................................................................................................6-70
6.9.2 Functions and Features.........................................................................................................................6-70
6.9.3 Working Principle and Signal Flow.....................................................................................................6-70
6.9.4 Front Panel...........................................................................................................................................6-71
6.9.5 Valid Slots............................................................................................................................................6-73
6.9.6 Parameter Settings................................................................................................................................6-73
6.9.7 Technical Specifications......................................................................................................................6-73
6.10 SPQ4............................................................................................................................................................6-73
6.10.1 Version Description............................................................................................................................6-74
6.10.2 Functions and Features.......................................................................................................................6-74
6.10.3 Working Principle and Signal Flow...................................................................................................6-75
6.10.4 Front Panel.........................................................................................................................................6-79
6.10.5 Valid Slots..........................................................................................................................................6-81
6.10.6 Board Protection.................................................................................................................................6-81
6.10.7 Parameter Settings..............................................................................................................................6-83
6.10.8 Technical Specifications....................................................................................................................6-84

7 Data Boards.................................................................................................................................7-1
7.1 EFT8................................................................................................................................................................7-3
7.1.1 Version Description................................................................................................................................7-3
7.1.2 Functions and Features...........................................................................................................................7-3
7.1.3 Working Principle and Signal Flow.......................................................................................................7-5
7.1.4 Front Panel.............................................................................................................................................7-7
7.1.5 Valid Slots............................................................................................................................................7-10
7.1.6 Parameter Settings................................................................................................................................7-10
7.1.7 Technical Specifications......................................................................................................................7-10
7.2 EFT8A...........................................................................................................................................................7-14
7.2.1 Version Description..............................................................................................................................7-14
7.2.2 Functions and Features.........................................................................................................................7-14
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Hardware Description

Contents

7.2.3 Working Principle and Signal Flow.....................................................................................................7-16


7.2.4 Front Panel...........................................................................................................................................7-18
7.2.5 Valid Slots............................................................................................................................................7-20
7.2.6 Parameter Settings................................................................................................................................7-20
7.2.7 Technical Specifications......................................................................................................................7-20
7.3 EGT2.............................................................................................................................................................7-24
7.3.1 Version Description..............................................................................................................................7-25
7.3.2 Functions and Features.........................................................................................................................7-25
7.3.3 Working Principle and Signal Flow.....................................................................................................7-26
7.3.4 Front Panel...........................................................................................................................................7-28
7.3.5 Valid Slots............................................................................................................................................7-31
7.3.6 Feature Code........................................................................................................................................7-32
7.3.7 Parameter Settings................................................................................................................................7-32
7.3.8 Technical Specifications......................................................................................................................7-32
7.4 EFS0..............................................................................................................................................................7-37
7.4.1 Version Description..............................................................................................................................7-37
7.4.2 Functions and Features.........................................................................................................................7-38
7.4.3 Working Principle and Signal Flow.....................................................................................................7-41
7.4.4 Front Panel...........................................................................................................................................7-44
7.4.5 Valid Slots............................................................................................................................................7-45
7.4.6 Board Protection...................................................................................................................................7-46
7.4.7 Parameter Settings................................................................................................................................7-47
7.4.8 Technical Specifications......................................................................................................................7-47
7.5 EFS0A...........................................................................................................................................................7-51
7.5.1 Version Description..............................................................................................................................7-52
7.5.2 Functions and Features.........................................................................................................................7-52
7.5.3 Working Principle and Signal Flow.....................................................................................................7-55
7.5.4 Front Panel...........................................................................................................................................7-57
7.5.5 Valid Slots............................................................................................................................................7-59
7.5.6 Board Protection...................................................................................................................................7-59
7.5.7 Parameter Settings................................................................................................................................7-60
7.5.8 Technical Specifications......................................................................................................................7-61
7.6 EFS4..............................................................................................................................................................7-65
7.6.1 Version Description..............................................................................................................................7-66
7.6.2 Functions and Features.........................................................................................................................7-66
7.6.3 Working Principle and Signal Flow.....................................................................................................7-69
7.6.4 Front Panel...........................................................................................................................................7-71
7.6.5 Valid Slots............................................................................................................................................7-73
7.6.6 Parameter Settings................................................................................................................................7-74
7.6.7 Technical Specifications......................................................................................................................7-74
7.7 EGS2.............................................................................................................................................................7-78
7.7.1 Version Description..............................................................................................................................7-79
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Contents

OptiX OSN 3500 II Intelligent Optical Transmission System


Hardware Description
7.7.2 Functions and Features.........................................................................................................................7-79
7.7.3 Working Principle and Signal Flow.....................................................................................................7-81
7.7.4 Front Panel...........................................................................................................................................7-84
7.7.5 Valid Slots............................................................................................................................................7-87
7.7.6 Feature Code........................................................................................................................................7-87
7.7.7 Parameter Settings................................................................................................................................7-87
7.7.8 Technical Specifications......................................................................................................................7-87

7.8 EMS2.............................................................................................................................................................7-92
7.8.1 Version Description..............................................................................................................................7-93
7.8.2 Functions and Features.........................................................................................................................7-93
7.8.3 Working Principle and Signal Flow.....................................................................................................7-96
7.8.4 Front Panel...........................................................................................................................................7-98
7.8.5 Valid Slots..........................................................................................................................................7-102
7.8.6 Feature Code......................................................................................................................................7-102
7.8.7 Parameter Settings..............................................................................................................................7-103
7.8.8 Technical Specifications....................................................................................................................7-103
7.9 EMS4...........................................................................................................................................................7-104
7.9.1 Version Description............................................................................................................................7-104
7.9.2 Functions and Features.......................................................................................................................7-104
7.9.3 Working Principle and Signal Flow...................................................................................................7-107
7.9.4 Front Panel.........................................................................................................................................7-110
7.9.5 Valid Slots..........................................................................................................................................7-113
7.9.6 Feature Code......................................................................................................................................7-113
7.9.7 Board Protection.................................................................................................................................7-114
7.9.8 Parameter Settings..............................................................................................................................7-117
7.9.9 Technical Specifications....................................................................................................................7-117
7.10 EGS4.........................................................................................................................................................7-126
7.10.1 Version Description..........................................................................................................................7-127
7.10.2 Functions and Features.....................................................................................................................7-127
7.10.3 Working Principle and Signal Flow.................................................................................................7-130
7.10.4 Front Panel.......................................................................................................................................7-133
7.10.5 Valid Slots........................................................................................................................................7-136
7.10.6 Feature Code....................................................................................................................................7-136
7.10.7 Board Protection...............................................................................................................................7-136
7.10.8 Parameter Settings............................................................................................................................7-140
7.10.9 Technical Specifications..................................................................................................................7-140
7.11 EGR2.........................................................................................................................................................7-149
7.11.1 Version Description..........................................................................................................................7-150
7.11.2 Functions and Features.....................................................................................................................7-150
7.11.3 Working Principle and Signal Flow.................................................................................................7-153
7.11.4 Front Panel.......................................................................................................................................7-155
7.11.5 Valid Slots........................................................................................................................................7-157
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Contents

7.11.6 Feature Code....................................................................................................................................7-157


7.11.7 Parameter Settings............................................................................................................................7-157
7.11.8 Technical Specifications..................................................................................................................7-158
7.12 EMR0........................................................................................................................................................7-162
7.12.1 Version Description..........................................................................................................................7-163
7.12.2 Functions and Features.....................................................................................................................7-163
7.12.3 Working Principle and Signal Flow.................................................................................................7-166
7.12.4 Front Panel.......................................................................................................................................7-168
7.12.5 Valid Slots........................................................................................................................................7-170
7.12.6 Feature Code....................................................................................................................................7-171
7.12.7 Parameter Settings............................................................................................................................7-171
7.12.8 Technical Specifications..................................................................................................................7-172
7.13 EAS2.........................................................................................................................................................7-180
7.13.1 Version Description..........................................................................................................................7-180
7.13.2 Functions and Features.....................................................................................................................7-180
7.13.3 Working Principle and Signal Flow.................................................................................................7-182
7.13.4 Front Panel.......................................................................................................................................7-184
7.13.5 Valid Slots........................................................................................................................................7-185
7.13.6 Parameter Settings............................................................................................................................7-185
7.13.7 Technical Specifications..................................................................................................................7-185
7.14 ADL4.........................................................................................................................................................7-188
7.14.1 Version Description..........................................................................................................................7-189
7.14.2 Functions and Features.....................................................................................................................7-189
7.14.3 Working Principle and Signal Flow.................................................................................................7-190
7.14.4 Front Panel.......................................................................................................................................7-192
7.14.5 Valid Slots........................................................................................................................................7-194
7.14.6 Feature Code....................................................................................................................................7-194
7.14.7 Parameter Settings............................................................................................................................7-194
7.14.8 Technical Specifications..................................................................................................................7-195
7.15 ADQ1........................................................................................................................................................7-196
7.15.1 Version Description..........................................................................................................................7-196
7.15.2 Functions and Features.....................................................................................................................7-196
7.15.3 Working Principle and Signal Flow.................................................................................................7-198
7.15.4 Front Panel.......................................................................................................................................7-199
7.15.5 Valid Slots........................................................................................................................................7-201
7.15.6 Feature Code....................................................................................................................................7-201
7.15.7 Parameter Settings............................................................................................................................7-201
7.15.8 Technical Specifications..................................................................................................................7-202
7.16 IDL4..........................................................................................................................................................7-203
7.16.1 Version Description..........................................................................................................................7-203
7.16.2 Functions and Features.....................................................................................................................7-203
7.16.3 Working Principle and Signal Flow.................................................................................................7-205
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Hardware Description
7.16.4 Front Panel.......................................................................................................................................7-207
7.16.5 Valid Slots........................................................................................................................................7-209
7.16.6 Feature Code....................................................................................................................................7-209
7.16.7 Board Protection...............................................................................................................................7-209
7.16.8 Parameter Settings............................................................................................................................7-209
7.16.9 Technical Specifications..................................................................................................................7-210

7.17 IDL4A.......................................................................................................................................................7-211
7.17.1 Version Description..........................................................................................................................7-211
7.17.2 Functions and Features.....................................................................................................................7-211
7.17.3 Working Principle and Signal Flow.................................................................................................7-213
7.17.4 Front Panel.......................................................................................................................................7-215
7.17.5 Valid Slots........................................................................................................................................7-217
7.17.6 Feature Code....................................................................................................................................7-217
7.17.7 Board Protection...............................................................................................................................7-217
7.17.8 Parameter Settings............................................................................................................................7-217
7.17.9 Technical Specifications..................................................................................................................7-218
7.18 IDQ1..........................................................................................................................................................7-219
7.18.1 Version Description..........................................................................................................................7-219
7.18.2 Functions and Features.....................................................................................................................7-219
7.18.3 Working Principle and Signal Flow.................................................................................................7-221
7.18.4 Front Panel.......................................................................................................................................7-223
7.18.5 Valid Slots........................................................................................................................................7-225
7.18.6 Feature Code....................................................................................................................................7-225
7.18.7 Board Protection...............................................................................................................................7-225
7.18.8 Parameter Settings............................................................................................................................7-225
7.18.9 Technical Specifications..................................................................................................................7-226
7.19 IDQ1A.......................................................................................................................................................7-227
7.19.1 Version Description..........................................................................................................................7-227
7.19.2 Functions and Features.....................................................................................................................7-227
7.19.3 Working Principle and Signal Flow.................................................................................................7-229
7.19.4 Front Panel.......................................................................................................................................7-231
7.19.5 Valid Slots........................................................................................................................................7-233
7.19.6 Feature Code....................................................................................................................................7-233
7.19.7 Board Protection...............................................................................................................................7-233
7.19.8 Parameter Settings............................................................................................................................7-233
7.19.9 Technical Specifications..................................................................................................................7-234

8 Interface Boards and Switching and Bridging Boards........................................................8-1


8.1 D12B...............................................................................................................................................................8-3
8.1.1 Version Description................................................................................................................................8-3
8.1.2 Functions and Features...........................................................................................................................8-3
8.1.3 Working Principle and Signal Flow.......................................................................................................8-3
8.1.4 Front Panel.............................................................................................................................................8-4
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Contents

8.1.5 Valid Slots..............................................................................................................................................8-6


8.1.6 Technical Specifications........................................................................................................................8-6
8.2 D12S................................................................................................................................................................8-7
8.2.1 Version Description................................................................................................................................8-8
8.2.2 Functions and Features...........................................................................................................................8-8
8.2.3 Working Principle and Signal Flow.......................................................................................................8-8
8.2.4 Front Panel.............................................................................................................................................8-9
8.2.5 Valid Slots............................................................................................................................................8-11
8.2.6 Technical Specifications......................................................................................................................8-11
8.3 D75S..............................................................................................................................................................8-12
8.3.1 Version Description..............................................................................................................................8-13
8.3.2 Functions and Features.........................................................................................................................8-13
8.3.3 Working Principle and Signal Flow.....................................................................................................8-13
8.3.4 Front Panel...........................................................................................................................................8-14
8.3.5 Valid Slots............................................................................................................................................8-16
8.3.6 Technical Specifications......................................................................................................................8-16
8.4 D34S..............................................................................................................................................................8-17
8.4.1 Version Description..............................................................................................................................8-18
8.4.2 Functions and Features.........................................................................................................................8-18
8.4.3 Working Principle and Signal Flow.....................................................................................................8-18
8.4.4 Front Panel...........................................................................................................................................8-19
8.4.5 Valid Slots............................................................................................................................................8-20
8.4.6 Technical Specifications......................................................................................................................8-20
8.5 C34S..............................................................................................................................................................8-21
8.5.1 Version Description..............................................................................................................................8-21
8.5.2 Functions and Features.........................................................................................................................8-21
8.5.3 Working Principle and Signal Flow.....................................................................................................8-21
8.5.4 Front Panel...........................................................................................................................................8-22
8.5.5 Valid Slots............................................................................................................................................8-24
8.5.6 Technical Specifications......................................................................................................................8-24
8.6 EU04..............................................................................................................................................................8-25
8.6.1 Version Description..............................................................................................................................8-25
8.6.2 Functions and Features.........................................................................................................................8-25
8.6.3 Working Principle and Signal Flow.....................................................................................................8-26
8.6.4 Front Panel...........................................................................................................................................8-26
8.6.5 Valid Slots............................................................................................................................................8-28
8.6.6 Technical Specifications......................................................................................................................8-28
8.7 EU08..............................................................................................................................................................8-29
8.7.1 Version Description..............................................................................................................................8-29
8.7.2 Functions and Features.........................................................................................................................8-29
8.7.3 Working Principle and Signal Flow.....................................................................................................8-29
8.7.4 Front Panel...........................................................................................................................................8-30
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Hardware Description
8.7.5 Valid Slots............................................................................................................................................8-32
8.7.6 Technical Specifications...................................................................................................................... 8-33

8.8 OU08.............................................................................................................................................................8-33
8.8.1 Version Description..............................................................................................................................8-34
8.8.2 Functions and Features.........................................................................................................................8-34
8.8.3 Working Principle and Signal Flow.....................................................................................................8-35
8.8.4 Front Panel........................................................................................................................................... 8-35
8.8.5 Valid Slots............................................................................................................................................8-38
8.8.6 Technical Specifications...................................................................................................................... 8-39
8.9 MU04............................................................................................................................................................ 8-40
8.9.1 Version Description..............................................................................................................................8-40
8.9.2 Functions and Features.........................................................................................................................8-40
8.9.3 Working Principle and Signal Flow.....................................................................................................8-40
8.9.4 Front Panel........................................................................................................................................... 8-41
8.9.5 Valid Slots............................................................................................................................................8-43
8.9.6 Technical Specifications...................................................................................................................... 8-43
8.10 TSB4............................................................................................................................................................8-44
8.10.1 Version Description............................................................................................................................8-44
8.10.2 Functions and Features.......................................................................................................................8-44
8.10.3 Working Principle and Signal Flow...................................................................................................8-45
8.10.4 Front Panel......................................................................................................................................... 8-45
8.10.5 Valid Slots..........................................................................................................................................8-46
8.10.6 Technical Specifications.................................................................................................................... 8-47
8.11 TSB8............................................................................................................................................................8-48
8.11.1 Version Description............................................................................................................................8-48
8.11.2 Functions and Features.......................................................................................................................8-48
8.11.3 Working Principle and Signal Flow...................................................................................................8-49
8.11.4 Front Panel......................................................................................................................................... 8-49
8.11.5 Valid Slots..........................................................................................................................................8-50
8.11.6 Technical Specifications.................................................................................................................... 8-53
8.12 EFF8............................................................................................................................................................8-54
8.12.1 Version Description............................................................................................................................8-54
8.12.2 Functions and Features.......................................................................................................................8-54
8.12.3 Working Principle and Signal Flow...................................................................................................8-54
8.12.4 Front Panel......................................................................................................................................... 8-55
8.12.5 Valid Slots..........................................................................................................................................8-57
8.12.6 Technical Specifications.................................................................................................................... 8-58
8.13 EFF8A.........................................................................................................................................................8-59
8.13.1 Version Description............................................................................................................................8-59
8.13.2 Functions and Features.......................................................................................................................8-60
8.13.3 Working Principle and Signal Flow...................................................................................................8-60
8.13.4 Front Panel......................................................................................................................................... 8-60
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Contents

8.13.5 Valid Slots..........................................................................................................................................8-62


8.13.6 Technical Specifications....................................................................................................................8-62
8.14 ETF8............................................................................................................................................................8-63
8.14.1 Version Description............................................................................................................................8-64
8.14.2 Functions and Features.......................................................................................................................8-64
8.14.3 Working Principle and Signal Flow...................................................................................................8-64
8.14.4 Front Panel.........................................................................................................................................8-65
8.14.5 Valid Slots..........................................................................................................................................8-66
8.14.6 Technical Specifications....................................................................................................................8-67
8.15 ETF8A.........................................................................................................................................................8-68
8.15.1 Version Description............................................................................................................................8-68
8.15.2 Functions and Features.......................................................................................................................8-69
8.15.3 Working Principle and Signal Flow...................................................................................................8-69
8.15.4 Front Panel.........................................................................................................................................8-69
8.15.5 Valid Slots..........................................................................................................................................8-71
8.15.6 Technical Specifications....................................................................................................................8-71
8.16 ETS8............................................................................................................................................................8-72
8.16.1 Version Description............................................................................................................................8-73
8.16.2 Functions and Features.......................................................................................................................8-73
8.16.3 Working Principle and Signal Flow...................................................................................................8-73
8.16.4 Front Panel.........................................................................................................................................8-74
8.16.5 Valid Slots..........................................................................................................................................8-75
8.16.6 Technical Specifications....................................................................................................................8-76
8.17 DM12..........................................................................................................................................................8-77
8.17.1 Version Description............................................................................................................................8-77
8.17.2 Functions and Features.......................................................................................................................8-78
8.17.3 Working Principle and Signal Flow...................................................................................................8-78
8.17.4 Front Panel.........................................................................................................................................8-78
8.17.5 Valid Slots..........................................................................................................................................8-81
8.17.6 Technical Specifications....................................................................................................................8-82

9 Cross-Connect Boards and System Control Boards.............................................................9-1


9.1 CXLLN............................................................................................................................................................9-2
9.1.1 Version Description................................................................................................................................9-2
9.1.2 Functions and Features...........................................................................................................................9-3
9.1.3 Working Principle and Signal Flow.......................................................................................................9-7
9.1.4 Jumpers and DIP Switches.....................................................................................................................9-9
9.1.5 Front Panel...........................................................................................................................................9-12
9.1.6 Valid Slots............................................................................................................................................9-14
9.1.7 Feature Code........................................................................................................................................9-14
9.1.8 Parameter Settings................................................................................................................................9-14
9.1.9 Technical Specifications......................................................................................................................9-15
9.2 CXLQ41........................................................................................................................................................9-19
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9.2.1 Version Description..............................................................................................................................9-19
9.2.2 Functions and Features.........................................................................................................................9-20
9.2.3 Working Principle and Signal Flow.....................................................................................................9-24
9.2.4 Jumpers and DIP Switches...................................................................................................................9-26
9.2.5 Front Panel........................................................................................................................................... 9-29
9.2.6 Valid Slots............................................................................................................................................9-31
9.2.7 Feature Code........................................................................................................................................ 9-31
9.2.8 Parameter Settings................................................................................................................................9-31
9.2.9 Technical Specifications...................................................................................................................... 9-32

9.3 CXS...............................................................................................................................................................9-35
9.3.1 Version Description..............................................................................................................................9-35
9.3.2 Functions and Features.........................................................................................................................9-36
9.3.3 Working Principle and Signal Flow.....................................................................................................9-37
9.3.4 Jumpers and DIP Switches...................................................................................................................9-39
9.3.5 Front Panel........................................................................................................................................... 9-41
9.3.6 Valid Slots............................................................................................................................................9-43
9.3.7 Parameter Settings................................................................................................................................9-43
9.3.8 Technical Specifications...................................................................................................................... 9-44

10 Auxiliary Boards.....................................................................................................................10-1
10.1 EOW............................................................................................................................................................10-2
10.1.1 Version Description............................................................................................................................10-2
10.1.2 Functions and Features.......................................................................................................................10-2
10.1.3 Working Principle and Signal Flow...................................................................................................10-3
10.1.4 Front Panel......................................................................................................................................... 10-4
10.1.5 Valid Slots..........................................................................................................................................10-6
10.1.6 Technical Specifications.................................................................................................................... 10-6
10.2 AUX............................................................................................................................................................10-7
10.2.1 Version Description............................................................................................................................10-7
10.2.2 Functions and Features.......................................................................................................................10-7
10.2.3 Working Principle and Signal Flow...................................................................................................10-9
10.2.4 Jumpers.............................................................................................................................................10-10
10.2.5 Front Panel.......................................................................................................................................10-11
10.2.6 Valid Slots........................................................................................................................................10-14
10.2.7 Technical Specifications..................................................................................................................10-14
10.3 SEI.............................................................................................................................................................10-14
10.3.1 Version Description..........................................................................................................................10-15
10.3.2 Functions and Features.....................................................................................................................10-15
10.3.3 Working Principle and Signal Flow.................................................................................................10-15
10.3.4 Front Panel.......................................................................................................................................10-16
10.3.5 Valid Slots........................................................................................................................................10-23
10.3.6 Technical Specifications..................................................................................................................10-23
10.4 FAN/FANB...............................................................................................................................................10-23
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Contents

10.4.1 Version Description..........................................................................................................................10-24


10.4.2 Functions and Features.....................................................................................................................10-24
10.4.3 Working Principle and Signal Flow.................................................................................................10-25
10.4.4 Front Panel.......................................................................................................................................10-26
10.4.5 Valid Slots........................................................................................................................................10-26
10.4.6 Technical Specifications..................................................................................................................10-26
10.5 FANA........................................................................................................................................................10-27
10.5.1 Version Description..........................................................................................................................10-27
10.5.2 Function and Feature........................................................................................................................10-28
10.5.3 Working Principle and Signal Flow.................................................................................................10-28
10.5.4 Front Panel.......................................................................................................................................10-29
10.5.5 Valid Slots........................................................................................................................................10-30
10.5.6 Technical Specifications..................................................................................................................10-30

11 WDM Boards...........................................................................................................................11-1
11.1 CMR2..........................................................................................................................................................11-2
11.1.1 Version Description............................................................................................................................11-2
11.1.2 Functions and Features.......................................................................................................................11-2
11.1.3 Working Principle and Signal Flow...................................................................................................11-3
11.1.4 Front Panel.........................................................................................................................................11-4
11.1.5 Valid Slots..........................................................................................................................................11-5
11.1.6 Feature Code......................................................................................................................................11-5
11.1.7 Technical Specifications....................................................................................................................11-6
11.2 CMR4..........................................................................................................................................................11-7
11.2.1 Version Description............................................................................................................................11-8
11.2.2 Functions and Features.......................................................................................................................11-8
11.2.3 Working Principle and Signal Flow...................................................................................................11-8
11.2.4 Front Panel.......................................................................................................................................11-10
11.2.5 Valid Slots........................................................................................................................................11-11
11.2.6 Feature Code....................................................................................................................................11-11
11.2.7 Technical Specifications..................................................................................................................11-12
11.3 MR2...........................................................................................................................................................11-13
11.3.1 Version Description..........................................................................................................................11-14
11.3.2 Functions and Features.....................................................................................................................11-14
11.3.3 Working Principle and Signal Flow.................................................................................................11-14
11.3.4 Front Panel.......................................................................................................................................11-16
11.3.5 Valid Slots........................................................................................................................................11-17
11.3.6 Feature Code....................................................................................................................................11-17
11.3.7 Technical Specifications..................................................................................................................11-18
11.4 MR2A........................................................................................................................................................11-19
11.4.1 Version Description..........................................................................................................................11-19
11.4.2 Functions and Features.....................................................................................................................11-20
11.4.3 Working Principle and Signal Flow.................................................................................................11-21
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Hardware Description
11.4.4 Front Panel.......................................................................................................................................11-22
11.4.5 Valid Slots........................................................................................................................................11-23
11.4.6 Technical Specifications..................................................................................................................11-23

11.5 MR2C........................................................................................................................................................11-24
11.5.1 Version Description..........................................................................................................................11-24
11.5.2 Functions and Features.....................................................................................................................11-25
11.5.3 Working Principle and Signal Flow.................................................................................................11-26
11.5.4 Front Panel.......................................................................................................................................11-27
11.5.5 Valid Slots........................................................................................................................................11-29
11.5.6 Technical Specifications..................................................................................................................11-29
11.6 MR4...........................................................................................................................................................11-30
11.6.1 Version Description..........................................................................................................................11-30
11.6.2 Functions and Features.....................................................................................................................11-30
11.6.3 Working Principle and Signal Flow.................................................................................................11-31
11.6.4 Front Panel.......................................................................................................................................11-32
11.6.5 Valid Slots........................................................................................................................................11-34
11.6.6 Feature Code....................................................................................................................................11-34
11.6.7 Technical Specifications..................................................................................................................11-35
11.7 LWX..........................................................................................................................................................11-36
11.7.1 Version Description..........................................................................................................................11-36
11.7.2 Functions and Features.....................................................................................................................11-36
11.7.3 Working Principle and Signal Flow.................................................................................................11-37
11.7.4 Front Panel.......................................................................................................................................11-39
11.7.5 Valid Slots........................................................................................................................................11-41
11.7.6 Feature Code....................................................................................................................................11-41
11.7.7 Parameter Settings............................................................................................................................11-41
11.7.8 Technical Specifications..................................................................................................................11-42
11.8 FIB.............................................................................................................................................................11-45
11.8.1 Version Description..........................................................................................................................11-45
11.8.2 Functions and Features.....................................................................................................................11-45
11.8.3 Working Principle and Signal Flow.................................................................................................11-46
11.8.4 Front Panel.......................................................................................................................................11-46
11.8.5 Valid Slots........................................................................................................................................11-48
11.8.6 Technical Specifications..................................................................................................................11-48

12 Microwave Boards..................................................................................................................12-1
12.1 IFSD1..........................................................................................................................................................12-2
12.1.1 Version Description............................................................................................................................12-2
12.1.2 Functions and Features.......................................................................................................................12-2
12.1.3 Working Principle and Signal Flow...................................................................................................12-4
12.1.4 Front Panel.........................................................................................................................................12-5
12.1.5 Valid Slots..........................................................................................................................................12-8
12.1.6 Parameter Settings..............................................................................................................................12-8
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Contents

12.1.7 Technical Specifications..................................................................................................................12-10


12.2 RPWR........................................................................................................................................................12-11
12.2.1 Version Description..........................................................................................................................12-12
12.2.2 Functions and Features.....................................................................................................................12-12
12.2.3 Working Principle and Signal Flow.................................................................................................12-12
12.2.4 Front Panel.......................................................................................................................................12-13
12.2.5 Valid Slots........................................................................................................................................12-15
12.2.6 Technical Specifications..................................................................................................................12-15

13 Optical Amplifier Boards and Dispersion Compensation Boards...............................13-1


13.1 BA2............................................................................................................................................................. 13-2
13.1.1 Version Description............................................................................................................................13-2
13.1.2 Functions and Features.......................................................................................................................13-2
13.1.3 Working Principle and Signal Flow...................................................................................................13-3
13.1.4 Front Panel......................................................................................................................................... 13-5
13.1.5 Valid Slots..........................................................................................................................................13-8
13.1.6 Feature Code...................................................................................................................................... 13-8
13.1.7 Technical Specifications.................................................................................................................... 13-9
13.2 BPA...........................................................................................................................................................13-10
13.2.1 Version Description..........................................................................................................................13-10
13.2.2 Functions and Features.....................................................................................................................13-11
13.2.3 Working Principle and Signal Flow.................................................................................................13-12
13.2.4 Front Panel.......................................................................................................................................13-13
13.2.5 Valid Slots........................................................................................................................................13-15
13.2.6 Feature Code....................................................................................................................................13-15
13.2.7 Technical Specifications..................................................................................................................13-15
13.3 COA..........................................................................................................................................................13-16
13.3.1 Version Description..........................................................................................................................13-17
13.3.2 Functions and Features.....................................................................................................................13-18
13.3.3 Working Principle and Signal Flow.................................................................................................13-20
13.3.4 Front Panel.......................................................................................................................................13-22
13.3.5 Valid Slots........................................................................................................................................13-26
13.3.6 Feature Code....................................................................................................................................13-27
13.3.7 Technical Specifications..................................................................................................................13-27
13.4 RPC01.......................................................................................................................................................13-28
13.4.1 Version Description..........................................................................................................................13-29
13.4.2 Functions and Features.....................................................................................................................13-29
13.4.3 Working Principle and Signal Flow.................................................................................................13-29
13.4.4 Front Panel.......................................................................................................................................13-31
13.4.5 Valid Slots........................................................................................................................................13-32
13.4.6 Jumpers and DIP Switches...............................................................................................................13-32
13.4.7 Feature Code....................................................................................................................................13-33
13.4.8 Parameter Settings............................................................................................................................13-33
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Hardware Description
13.4.9 Technical Specifications..................................................................................................................13-34

13.5 RPC02.......................................................................................................................................................13-35
13.5.1 Version Description..........................................................................................................................13-35
13.5.2 Functions and Features.....................................................................................................................13-35
13.5.3 Working Principle and Signal Flow.................................................................................................13-36
13.5.4 Front Panel.......................................................................................................................................13-38
13.5.5 Valid Slots........................................................................................................................................13-39
13.5.6 Jumpers and DIP Switches...............................................................................................................13-39
13.5.7 Feature Code....................................................................................................................................13-40
13.5.8 Parameter Settings............................................................................................................................13-40
13.5.9 Technical Specifications..................................................................................................................13-41
13.6 OBU1........................................................................................................................................................13-42
13.6.1 Version Description..........................................................................................................................13-42
13.6.2 Functions and Features.....................................................................................................................13-42
13.6.3 Working Principle and Signal Flow.................................................................................................13-43
13.6.4 Front Panel.......................................................................................................................................13-45
13.6.5 Valid Slots........................................................................................................................................13-46
13.6.6 Feature Code....................................................................................................................................13-46
13.6.7 Parameter Settings............................................................................................................................13-47
13.6.8 Technical Specifications..................................................................................................................13-47
13.7 DCU..........................................................................................................................................................13-48
13.7.1 Version Description..........................................................................................................................13-49
13.7.2 Functions and Features.....................................................................................................................13-49
13.7.3 Working Principle and Signal Flow.................................................................................................13-51
13.7.4 Front Panel.......................................................................................................................................13-51
13.7.5 Valid Slots........................................................................................................................................13-54
13.7.6 Feature Code....................................................................................................................................13-54
13.7.7 Technical Specifications..................................................................................................................13-55

14 Power Boards...........................................................................................................................14-1
14.1 UPM............................................................................................................................................................14-2
14.1.1 Version Description............................................................................................................................14-2
14.1.2 Functions and Features.......................................................................................................................14-2
14.1.3 Working Principle and Signal Flow...................................................................................................14-3
14.1.4 Front Panel.........................................................................................................................................14-4
14.1.5 Valid Slots..........................................................................................................................................14-6
14.1.6 Technical Specifications....................................................................................................................14-6
14.2 PIU..............................................................................................................................................................14-7
14.2.1 Version Description............................................................................................................................14-8
14.2.2 Functions and Features.......................................................................................................................14-8
14.2.3 Working Principle and Signal Flow...................................................................................................14-8
14.2.4 Front Panel.........................................................................................................................................14-9
14.2.5 Valid Slots........................................................................................................................................14-11
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Contents

14.2.6 Technical Specifications..................................................................................................................14-11

15 Cables.......................................................................................................................................15-1
15.1 Fiber Jumper................................................................................................................................................15-2
15.1.1 Categories of the Fiber Jumpers.........................................................................................................15-2
15.1.2 Connector...........................................................................................................................................15-2
15.2 Power Cable and Grounding Cable.............................................................................................................15-5
15.2.1 Power Cable of the Cabinet................................................................................................................15-5
15.2.2 Grounding Cable of the Cabinet Door............................................................................................... 15-7
15.2.3 Subrack Power Cable.........................................................................................................................15-8
15.2.4 COA Power Cable..............................................................................................................................15-9
15.3 Alarm Cable..............................................................................................................................................15-11
15.3.1 Cabinet Indicator Cable....................................................................................................................15-11
15.3.2 Indicator Cascading Cable Between Subracks or Alarm Cascading Cable Between the OptiX OSN
Equipment...................................................................................................................................................15-13
15.3.3 Alarm Cascading Cable Between the OptiX OSN Equipment and the Other Huawei Transmission
Equipment...................................................................................................................................................15-14
15.3.4 Alarm Input/Output Cable................................................................................................................15-16
15.4 Management Cable....................................................................................................................................15-17
15.4.1 OAM Serial Port Cable....................................................................................................................15-18
15.4.2 Serial 1 to 4/F1/F&f Serial Port Cable.............................................................................................15-19
15.4.3 RS-232/RS-422 Serial Port Cable....................................................................................................15-21
15.4.4 Ordinary Telephone Line.................................................................................................................15-22
15.4.5 COA Cascading Cable.....................................................................................................................15-23
15.4.6 Straight Through Cable....................................................................................................................15-25
15.4.7 Crossover Cable...............................................................................................................................15-26
15.5 Signal Cable..............................................................................................................................................15-27
15.5.1 75-ohm 8xE1 Cable..........................................................................................................................15-28
15.5.2 120-ohm 8xE1 Cable........................................................................................................................15-30
15.5.3 120-ohm 21xE1 Cable......................................................................................................................15-32
15.5.4 E3/T3/STM-1 Cable.........................................................................................................................15-35
15.5.5 Framed E1 Cable..............................................................................................................................15-37
15.5.6 Nx64 kbit/s Cable.............................................................................................................................15-37
15.6 Clock Cable...............................................................................................................................................15-55
15.6.1 Clock Cable......................................................................................................................................15-56
15.6.2 One-Channel Clock Transit Cable and Two-Channel Clock Transit Cable....................................15-57

A Indicators...................................................................................................................................A-1
A.1 Indicators on the Cabinet...............................................................................................................................A-2
A.2 Alarm Indicators on the Boards.....................................................................................................................A-2

B Labels..........................................................................................................................................B-1
B.1 Safety Labels..................................................................................................................................................B-2
B.1.1 Label Description..................................................................................................................................B-2
B.1.2 Label Position.......................................................................................................................................B-3
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B.2 Optical Module Labels...................................................................................................................................B-5


B.3 Engineering Labels........................................................................................................................................B-7

C Power Consumption and Weight of Each Board................................................................C-1


D Compatibility of Board Versions with the Products........................................................D-1
E Loopback Capability of the Boards.......................................................................................E-1
F Parameter Settings.....................................................................................................................F-1
F.1 SDH Processing Boards..................................................................................................................................F-2
F.2 PDH Boards....................................................................................................................................................F-3
F.3 Data Boards.....................................................................................................................................................F-5
F.3.1 SDH Parameters.....................................................................................................................................F-5
F.3.2 Ethernet Parameters...............................................................................................................................F-6
F.3.3 ATM Parameters....................................................................................................................................F-8
F.4 WDM Boards..................................................................................................................................................F-8
F.5 Optical Amplifier Boards..............................................................................................................................F-15
F.6 Cross-Connect and Timing Units.................................................................................................................F-21

G Glossary.....................................................................................................................................G-1
H Acronyms and Abbreviations...............................................................................................H-1

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Figures

Figures
Figure 1-1 Appearance of the OptiX OSN 3500 II that is installed in the ETSI cabinet.....................................1-2
Figure 1-2 Appearance of the OptiX OSN 3500 II subrack that is installed with boards....................................1-3
Figure 2-1 Appearance of the N63E cabinet........................................................................................................2-2
Figure 2-2 ETSI cabinet.......................................................................................................................................2-3
Figure 2-3 Appearance of the DC PDU...............................................................................................................2-5
Figure 3-1 Access capacity of each slot when using the Q5CXL series boards..................................................3-2
Figure 3-2 Access capacity of each slot when using the Q6CXL series boards..................................................3-2
Figure 3-3 Access capacity of each slot when using the Q5CXS series boards...................................................3-3
Figure 3-4 Structure of the OptiX OSN 3500 II subrack.....................................................................................3-4
Figure 3-5 Slot layout of the OptiX OSN 3500 II subrack..................................................................................3-5
Figure 4-1 Bar code of a board.............................................................................................................................4-4
Figure 5-1 Functional block diagram of the SL1.................................................................................................5-7
Figure 5-2 Front panel of the SL1........................................................................................................................5-9
Figure 5-3 Functional block diagram of the SL1A............................................................................................5-14
Figure 5-4 Front panel of the SL1A...................................................................................................................5-17
Figure 5-5 Functional block diagram of the SLQ1............................................................................................5-23
Figure 5-6 Front panel of the SLQ1...................................................................................................................5-25
Figure 5-7 Functional block diagram of the SLQ1A.........................................................................................5-30
Figure 5-8 Front panel of the SLQ1A................................................................................................................5-33
Figure 5-9 Functional block diagram of the SLO1............................................................................................5-39
Figure 5-10 Front panel of the SLO1.................................................................................................................5-41
Figure 5-11 Functional block diagram of the SLT1...........................................................................................5-46
Figure 5-12 Front panel of the SLT1..................................................................................................................5-49
Figure 5-13 Functional block diagram of the SLH1B when the SLH1B works with the EU08........................5-54
Figure 5-14 Functional block diagram of the SLH1B when the SLH1B works with the OU08.......................5-55
Figure 5-15 Front panel of the SLH1B..............................................................................................................5-57
Figure 5-16 1:3 TPS protection provided by the SLH1B...................................................................................5-58
Figure 5-17 Slot configuration for the two 1:3 TPS protection groups of the SLH1B......................................5-59
Figure 5-18 Functional block diagram of the SEP1...........................................................................................5-64
Figure 5-19 Functional block diagram of the SEP when the SEP works with the EU08..................................5-65
Figure 5-20 Functional block diagram of the SEP when the SEP works with the OU08..................................5-66
Figure 5-21 Front panel of the SEP1..................................................................................................................5-68
Figure 5-22 TPS protection provided by the SEP1............................................................................................5-70
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Figures

Figure 5-23 Slot configuration for two 1:3 TPS protection groups of the SEP1...............................................5-71
Figure 5-24 Functional block diagram of the SL4.............................................................................................5-75
Figure 5-25 Front panel of the SL4....................................................................................................................5-77
Figure 5-26 Functional block diagram of the SL4A..........................................................................................5-83
Figure 5-27 Front panel of the SL4A.................................................................................................................5-85
Figure 5-28 Functional block diagram of the SLD4..........................................................................................5-91
Figure 5-29 Front panel of the SLD4.................................................................................................................5-93
Figure 5-30 Functional block diagram of the SLD4A.......................................................................................5-99
Figure 5-31 Front panel of the SLD4A............................................................................................................5-101
Figure 5-32 Functional block diagram of the SLQ4........................................................................................ 5-107
Figure 5-33 Front panel of the SLQ4...............................................................................................................5-109
Figure 5-34 Functional block diagram of the SLQ4A..................................................................................... 5-114
Figure 5-35 Front panel of the SLQ4A............................................................................................................5-117
Figure 5-36 Functional block diagram of the SL16.........................................................................................5-123
Figure 5-37 Front panel of the SL16................................................................................................................5-126
Figure 5-38 Functional block diagram of the N1SL16A/N2SL16A/N3SL16A.............................................. 5-133
Figure 5-39 Front panel of the SL16A.............................................................................................................5-135
Figure 5-40 Functional block diagram of the SLD16...................................................................................... 5-141
Figure 5-41 Front panel of the SLD16.............................................................................................................5-143
Figure 5-42 Functional block diagram of the SLQ16...................................................................................... 5-149
Figure 5-43 Front panel of the N1SLQ16........................................................................................................5-151
Figure 5-44 Front panel of the N2SLQ16........................................................................................................5-152
Figure 5-45 Functional block diagram of the SF16......................................................................................... 5-157
Figure 5-46 Front panel of the SF16................................................................................................................5-160
Figure 5-47 Functional block diagram of the N1SL64.................................................................................... 5-165
Figure 5-48 Appearance of the front panel of the SL64...................................................................................5-168
Figure 5-49 Functional block diagram of the SF64......................................................................................... 5-174
Figure 5-50 Front panel of the SF64................................................................................................................5-176
Figure 5-51 Functional block diagram of the SF64A.......................................................................................5-181
Figure 5-52 Front panel of the SF64A............................................................................................................. 5-183
Figure 5-53 Functional block diagram of the SLQ41...................................................................................... 5-189
Figure 5-54 Front panel of the SLQ41.............................................................................................................5-191
Figure 6-1 Functional block diagram of the PQ1.................................................................................................6-5
Figure 6-2 Functional block diagram of the E1 mapping/demapping module.....................................................6-6
Figure 6-3 Front panel of the PQ1........................................................................................................................6-8
Figure 6-4 TPS protection provided by the PQ1................................................................................................6-11
Figure 6-5 Slot configuration for the 1:10 TPS protection of the PQ1..............................................................6-12
Figure 6-6 Functional block diagram of the PO1...............................................................................................6-15
Figure 6-7 Functional block diagram of the E1 mapping/demapping module...................................................6-15
Figure 6-8 Front panel of the PO1......................................................................................................................6-17
Figure 6-9 Functional block diagram of the PQM.............................................................................................6-22
Figure 6-10 Functional block diagram of the E1/T1 mapping/demapping module...........................................6-22
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Figures

Figure 6-11 Front panel of the PQM..................................................................................................................6-24


Figure 6-12 TPS protection provided by the PQM............................................................................................6-27
Figure 6-13 Slot configuration for the 1:10 TPS protection of the PQM...........................................................6-28
Figure 6-14 Functional block diagram of the PL3.............................................................................................6-31
Figure 6-15 Functional block diagram of the E3/T3 mapping/demapping module...........................................6-31
Figure 6-16 Front panel of the PL3....................................................................................................................6-33
Figure 6-17 TPS protection provided by the PL3..............................................................................................6-35
Figure 6-18 Slot configuration for the two 1:3 TPS protection groups of the PL3............................................6-36
Figure 6-19 Functional block diagram of the PL3A..........................................................................................6-40
Figure 6-20 Functional block diagram of the E3/T3 mapping/demapping module...........................................6-40
Figure 6-21 Front panel of the PL3A.................................................................................................................6-42
Figure 6-22 Functional block diagram of the PD3.............................................................................................6-46
Figure 6-23 Functional block diagram of the E3/T3 mapping/demapping module...........................................6-47
Figure 6-24 Front panel of the PD3....................................................................................................................6-49
Figure 6-25 TPS protection provided by the PD3..............................................................................................6-51
Figure 6-26 Slot configuration for the two 1:3 TPS protection groups of the PD3...........................................6-52
Figure 6-27 Functional block diagram of the PQ3.............................................................................................6-55
Figure 6-28 Functional block diagram of the E3/T3 mapping/demapping module...........................................6-55
Figure 6-29 Front panel of the PQ3....................................................................................................................6-57
Figure 6-30 TPS protection provided by the PQ3..............................................................................................6-59
Figure 6-31 Slot configuration for the two 1:3 TPS protection groups of the PQ3...........................................6-60
Figure 6-32 Functional block diagram of the DX1............................................................................................6-63
Figure 6-33 Front panel of the DX1...................................................................................................................6-65
Figure 6-34 TPS protection provided by the DX1.............................................................................................6-67
Figure 6-35 Slot configuration for the 1:8 TPS protection of the DX1.............................................................6-68
Figure 6-36 Functional block diagram of the DXA...........................................................................................6-70
Figure 6-37 Front panel of the DXA..................................................................................................................6-72
Figure 6-38 Functional block diagram of the SPQ4...........................................................................................6-76
Figure 6-39 Functional block diagram of the 140M mapping/demapping module............................................6-76
Figure 6-40 Functional block diagram of the SDH overhead processing module.............................................6-77
Figure 6-41 Front panel of the SPQ4.................................................................................................................6-80
Figure 6-42 TPS protection provided by the SPQ4............................................................................................6-82
Figure 6-43 Slot configuration for the two 1:3 TPS protection groups of the SPQ4.........................................6-83
Figure 7-1 Functional block diagram of the EFT8...............................................................................................7-6
Figure 7-2 Front panel of the EFT8......................................................................................................................7-8
Figure 7-3 Connection for testing the throughput specifications, packet loss ratio in the case of overloading, and
latency specifications..........................................................................................................................................7-10
Figure 7-4 Connection for testing the back-to-back specifications....................................................................7-11
Figure 7-5 Functional block diagram of the EFT8A..........................................................................................7-16
Figure 7-6 Front panel of the EFT8A.................................................................................................................7-18
Figure 7-7 Connection for testing the throughput specifications, packet loss ratio in the case of overloading, and
latency specifications..........................................................................................................................................7-21
Figure 7-8 Connection for testing the back-to-back specifications....................................................................7-21
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Figures

Figure 7-9 Functional block diagram of the EGT2............................................................................................7-27


Figure 7-10 Front panel of the N1EGT2/N2EGT2 that is installed with the GE optical interface....................7-29
Figure 7-11 Front panel of the N2EGT2 that is installed with the GE electrical interface................................7-30
Figure 7-12 Connection for testing the throughput specifications, packet loss ratio in the case of overloading, and
latency specifications..........................................................................................................................................7-33
Figure 7-13 Connection for testing the back-to-back specifications..................................................................7-34
Figure 7-14 Functional block diagram of the EFS0...........................................................................................7-42
Figure 7-15 Front panel of the EFS0..................................................................................................................7-44
Figure 7-16 Slot configuration for the 1:1 TPS protection for the EFS0...........................................................7-46
Figure 7-17 Connection for testing the throughput specifications, packet loss ratio in the case of overloading,
latency specifications, and back-to-back specifications......................................................................................7-47
Figure 7-18 Functional block diagram of the EFS0A........................................................................................7-55
Figure 7-19 Front panel of the EFS0A...............................................................................................................7-58
Figure 7-20 Slot configuration for the 1:1 TPS protection for the EFS0A........................................................7-60
Figure 7-21 Connection for testing the throughput specifications, packet loss ratio in the case of overloading,
latency specifications, and back-to-back specifications......................................................................................7-61
Figure 7-22 Functional block diagram of the EFS4...........................................................................................7-69
Figure 7-23 Front panel of the EFS4..................................................................................................................7-72
Figure 7-24 Connection for testing the throughput specifications, packet loss ratio in the case of overloading,
latency specifications, and back-to-back specifications......................................................................................7-74
Figure 7-25 Functional block diagram of the EGS2..........................................................................................7-82
Figure 7-26 Front panel of the N2EGS2/N3EGS2 that is installed with the GE optical interface....................7-84
Figure 7-27 Front panel of the N3EGS2 that is installed with the GE electrical interface................................7-85
Figure 7-28 Connection for testing the throughput specifications, packet loss ratio in the case of overloading,
latency specifications, and back-to-back specifications......................................................................................7-88
Figure 7-29 Functional block diagram of the EMS2..........................................................................................7-96
Figure 7-30 Front panel of the EMS2 that is installed with the GE optical interface........................................7-99
Figure 7-31 Front panel of the EMS2 that is installed with the GE electrical interface.................................. 7-100
Figure 7-32 Functional block diagram of the EMS4........................................................................................7-108
Figure 7-33 Front panel of the EMS4 that is installed with the GE optical interface......................................7-110
Figure 7-34 Front panel of the EMS4 that is installed with the GE electrical interface.................................. 7-111
Figure 7-35 Normal working of the EMS4......................................................................................................7-114
Figure 7-36 Principle of the BPS protection for the EMS4............................................................................. 7-115
Figure 7-37 Principle of the PPS protection for the EMS4..............................................................................7-116
Figure 7-38 Connection for testing the throughput specifications, packet loss ratio in the case of overloading, and
latency specifications........................................................................................................................................ 7-118
Figure 7-39 Connection for testing the back-to-back specifications................................................................7-118
Figure 7-40 Functional block diagram of the EGS4........................................................................................ 7-131
Figure 7-41 Front panel of the N1EGS4/N3EGS4/N4EGS4 that is installed with the optical interface.........7-133
Figure 7-42 front panel of the N1EGS4/N4EGS4 that is installed with the GE electrical interface............... 7-134
Figure 7-43 Normal working of the EGS4.......................................................................................................7-137
Figure 7-44 Principle of the BPS protection for the EGS4..............................................................................7-138
Figure 7-45 Principle of the PPS protection for the EGS4...............................................................................7-139

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Figures

Figure 7-46 Connection for testing the throughput specifications, packet loss ratio in the case of overloading, and
latency specifications........................................................................................................................................ 7-141
Figure 7-47 Connection for testing the back-to-back specifications................................................................7-141
Figure 7-48 Functional block diagram of the EGR2........................................................................................7-153
Figure 7-49 Front panel of the EGR2...............................................................................................................7-156
Figure 7-50 Connection for testing the throughput specifications, packet loss ratio in the case of overloading,
latency specifications, and back-to-back specifications....................................................................................7-159
Figure 7-51 Functional block diagram of the EMR0.......................................................................................7-166
Figure 7-52 Front panel of the EMR0..............................................................................................................7-169
Figure 7-53 Connection for testing the throughput specifications, packet loss ratio in the case of overloading,
latency specifications, and back-to-back specifications....................................................................................7-173
Figure 7-54 Functional block diagram of the EAS2........................................................................................7-183
Figure 7-55 Front panel of the EAS2...............................................................................................................7-184
Figure 7-56 Connection for testing the throughput specifications, packet loss ratio in the case of overloading,
latency specifications, and back-to-back specifications....................................................................................7-186
Figure 7-57 Functional block diagram of the ADL4........................................................................................7-191
Figure 7-58 Front panel of the ADL4..............................................................................................................7-193
Figure 7-59 Functional block diagram of the ADQ1.......................................................................................7-198
Figure 7-60 Front panel of the ADQ1..............................................................................................................7-200
Figure 7-61 Functional block diagram of the IDL4.........................................................................................7-205
Figure 7-62 Front panel of the IDL4................................................................................................................7-208
Figure 7-63 Functional block diagram of the IDL4A......................................................................................7-214
Figure 7-64 Front panel of the IDL4A.............................................................................................................7-216
Figure 7-65 Functional block diagram of the IDQ1.........................................................................................7-221
Figure 7-66 Front panel of the IDQ1................................................................................................................7-224
Figure 7-67 Functional block diagram of the IDQ1A......................................................................................7-230
Figure 7-68 Front panel of the IDQ1A.............................................................................................................7-232
Figure 8-1 Functional block diagram of the D12B..............................................................................................8-3
Figure 8-2 Front panel of the D12B.....................................................................................................................8-4
Figure 8-3 Functional block diagram of the D12S...............................................................................................8-8
Figure 8-4 Front panel of the D12S......................................................................................................................8-9
Figure 8-5 Functional block diagram of the D75S.............................................................................................8-13
Figure 8-6 Front panel of the D75S....................................................................................................................8-14
Figure 8-7 Functional block diagram of the D34S.............................................................................................8-18
Figure 8-8 Front panel of the D34S....................................................................................................................8-19
Figure 8-9 Functional block diagram of the C34S.............................................................................................8-21
Figure 8-10 Front panel of the C34S..................................................................................................................8-23
Figure 8-11 Functional block diagram of the EU04...........................................................................................8-26
Figure 8-12 Front panel of the EU04.................................................................................................................8-27
Figure 8-13 Functional block diagram of the EU08...........................................................................................8-30
Figure 8-14 Front panel of the EU08.................................................................................................................8-31
Figure 8-15 Functional block diagram of the OU08..........................................................................................8-35
Figure 8-16 Front panel of the N1OU08............................................................................................................8-36
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Figures

Figure 8-17 Front panel of the N2OU08............................................................................................................8-37


Figure 8-18 Functional block diagram of the MU04.........................................................................................8-41
Figure 8-19 Front panel of the MU04................................................................................................................8-42
Figure 8-20 Functional block diagram of the TSB4...........................................................................................8-45
Figure 8-21 Front panel of the TSB4.................................................................................................................8-46
Figure 8-22 Functional block diagram of the TSB8...........................................................................................8-49
Figure 8-23 Front panel of the TSB8.................................................................................................................8-50
Figure 8-24 Functional block diagram of the EFF8...........................................................................................8-55
Figure 8-25 Front panel of the EFF8..................................................................................................................8-56
Figure 8-26 Functional block diagram of the EFF8A........................................................................................8-60
Figure 8-27 Front panel of the EFF8A...............................................................................................................8-61
Figure 8-28 Functional block diagram of the ETF8...........................................................................................8-64
Figure 8-29 Front panel of the ETF8..................................................................................................................8-65
Figure 8-30 Functional block diagram of the ETF8A........................................................................................8-69
Figure 8-31 Front panel of the ETF8A...............................................................................................................8-70
Figure 8-32 Functional block diagram of the ETS8...........................................................................................8-73
Figure 8-33 Front panel of the ETS8..................................................................................................................8-74
Figure 8-34 Functional block diagram of the DM12.........................................................................................8-78
Figure 8-35 Front panel of the DM12................................................................................................................8-79
Figure 9-1 Functional block diagram of the Q5CXLLN/Q6CXLLN..................................................................9-7
Figure 9-2 Positions of the jumpers and DIP switch of the Q5CXLLN............................................................9-10
Figure 9-3 Positions of the jumpers and DIP switch of the Q6CXLLN............................................................9-11
Figure 9-4 Front panel of the CXLLN...............................................................................................................9-13
Figure 9-5 Functional block diagram of the Q5CXLQ41/Q6CXLQ41.............................................................9-24
Figure 9-6 Positions of the jumpers and DIP switch of the Q5CXLQ41...........................................................9-27
Figure 9-7 Positions of the jumper and DIP switch of the Q6CXLQ41............................................................9-28
Figure 9-8 Front panel of the CXLQ41..............................................................................................................9-30
Figure 9-9 Functional block diagram of the CXS..............................................................................................9-38
Figure 9-10 Positions of the jumpers and DIP switch of the CXS.....................................................................9-40
Figure 9-11 Front panel of the CXS...................................................................................................................9-42
Figure 10-1 Functional block diagram of the EOW...........................................................................................10-3
Figure 10-2 Positions of the orderwire bytes in the SDH frame........................................................................10-4
Figure 10-3 Front panel of the EOW..................................................................................................................10-5
Figure 10-4 Functional block diagram of the AUX...........................................................................................10-9
Figure 10-5 Positions of the J1 and J6 on the AUX.........................................................................................10-10
Figure 10-6 Front panel of the AUX................................................................................................................10-11
Figure 10-7 Connections for alarm input, alarm cascading, and alarm output................................................10-13
Figure 10-8 Connections of cabinet alarm indicators.......................................................................................10-14
Figure 10-9 Functional block diagram of the SEI............................................................................................10-16
Figure 10-10 Front panel of the SEI.................................................................................................................10-17
Figure 10-11 Connections for alarm input, alarm cascading, and alarm output..............................................10-23
Figure 10-12 Functional block diagram of the XE1FAN.................................................................................10-25
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Figures

Figure 10-13 Functional block diagram of the XE3FAN.................................................................................10-25


Figure 10-14 Modular fan tray assembly.........................................................................................................10-26
Figure 10-15 Functional block diagram of the TE2FANA..............................................................................10-29
Figure 10-16 Modular fan tray assembly.........................................................................................................10-29
Figure 11-1 Functional block diagram of the CMR2.........................................................................................11-3
Figure 11-2 Front panel of the CMR2................................................................................................................11-4
Figure 11-3 Functional block diagram of the CMR4.........................................................................................11-9
Figure 11-4 Front panel of the CMR4..............................................................................................................11-10
Figure 11-5 Functional block diagram of the MR2..........................................................................................11-15
Figure 11-6 Front panel of the MR2................................................................................................................ 11-16
Figure 11-7 One MR2A board working as a two-channel add/drop OTM station.......................................... 11-20
Figure 11-8 Two MR2A boards being cascaded to work as a four-channel add/drop OTM station...............11-20
Figure 11-9 MR2A and LWX working as a two-channel add/drop OADM station........................................11-21
Figure 11-10 Functional block diagram of the MR2A.....................................................................................11-21
Figure 11-11 Front panel of the MR2A............................................................................................................11-22
Figure 11-12 One MR2C board working as a two-channel add/drop OTM station.........................................11-25
Figure 11-13 Two MR2C boards being cascaded to work as a four-channel add/drop OTM station............. 11-26
Figure 11-14 MR2C and LWX working as a two-channel add/drop OADM station......................................11-26
Figure 11-15 Functional block diagram of the MR2C.....................................................................................11-26
Figure 11-16 Front panel of the MR2C............................................................................................................11-28
Figure 11-17 Functional block diagram of the MR4........................................................................................11-31
Figure 11-18 Front panel of the MR4.............................................................................................................. 11-33
Figure 11-19 Functional block diagram of the LWX.......................................................................................11-38
Figure 11-20 Front panel of the LWX..............................................................................................................11-40
Figure 11-21 Position of the FIB in an optical transmission system................................................................11-45
Figure 11-22 Functional block diagram of the FIB..........................................................................................11-46
Figure 11-23 Front panel of the FIB................................................................................................................ 11-47
Figure 12-1 Functional block diagram of the IFSD1.........................................................................................12-4
Figure 12-2 Front panel of the IFSD1................................................................................................................12-6
Figure 12-3 Functional block diagram of the RPWR.......................................................................................12-13
Figure 12-4 Front panel of the RPWR............................................................................................................. 12-14
Figure 13-1 Position of the BA in the optical transmission system...................................................................13-2
Figure 13-2 Functional block diagram of the BA2............................................................................................13-4
Figure 13-3 Front panel of the one-interface BA2.............................................................................................13-6
Figure 13-4 Front panel of the two-interface BA2.............................................................................................13-7
Figure 13-5 Positions of the BA and PA in the optical transmission system...................................................13-11
Figure 13-6 Functional block diagram of the N1BPA.....................................................................................13-12
Figure 13-7 Functional block diagram of the N2BPA.....................................................................................13-13
Figure 13-8 Front panel of the BPA.................................................................................................................13-14
Figure 13-9 Appearance of the 61COA/N1COA (PA)....................................................................................13-18
Figure 13-10 Appearance of the 62COA..........................................................................................................13-19
Figure 13-11 Application of the 62COA..........................................................................................................13-20
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Figures

Figure 13-12 Functional block diagram of the 61COA/N1COA.....................................................................13-21


Figure 13-13 Front panel of the 61COA/N1COA............................................................................................13-22
Figure 13-14 Front panel of the 62COA..........................................................................................................13-23
Figure 13-15 SC/PC fiber connector................................................................................................................13-23
Figure 13-16 LSH flange and fiber connector..................................................................................................13-24
Figure 13-17 Position of the 61COA in the cabinet.........................................................................................13-26
Figure 13-18 Functional block diagram of the RPC01 (backward pump).......................................................13-30
Figure 13-19 Front panel of the RPC01...........................................................................................................13-31
Figure 13-20 Jumpers of the RPC01................................................................................................................13-32
Figure 13-21 Functional block diagram of the RPC02 (forward pump)..........................................................13-37
Figure 13-22 Front panel of the RPC02...........................................................................................................13-38
Figure 13-23 Jumpers of the RPC02................................................................................................................13-39
Figure 13-24 Functional block diagram of the OBU1.....................................................................................13-44
Figure 13-25 Front panel of the OBU1............................................................................................................13-45
Figure 13-26 Position of the DCU in the optical transmission system............................................................13-50
Figure 13-27 Functional block diagram of the DCU.......................................................................................13-51
Figure 13-28 Front panel of the one-interface DCU........................................................................................13-52
Figure 13-29 Front panel of the two-interface DCU........................................................................................13-53
Figure 14-1 Appearance of the power box.........................................................................................................14-2
Figure 14-2 Front panel of the UPM..................................................................................................................14-4
Figure 14-3 Functional block diagram of the PIU.............................................................................................14-9
Figure 14-4 Front panel of the PIU..................................................................................................................14-10
Figure 15-1 Appearance of the LC/PC fiber connector......................................................................................15-3
Figure 15-2 Appearance of the SC/PC fiber connector......................................................................................15-4
Figure 15-3 Appearance of the FC/PC fiber connector......................................................................................15-4
Figure 15-4 Appearance of the LSH/APC fiber connector................................................................................15-4
Figure 15-5 Structure of the 48 V/BGND power cable of the cabinet.............................................................15-5
Figure 15-6 Structure of the PGND power cable of the cabinet (JG2)..............................................................15-6
Figure 15-7 Structure of the PGND power cable of the cabinet (OT)...............................................................15-6
Figure 15-8 Structure of the grounding cable of the cabinet door.....................................................................15-7
Figure 15-9 Structure of the subrack power cable..............................................................................................15-8
Figure 15-10 Structure of the COA power cable..............................................................................................15-10
Figure 15-11 Structure of the cabinet indicator cable......................................................................................15-12
Figure 15-12 Structure of the indicator cascading cable between subracks or the alarm cascading cable between
the OptiX OSN equipment................................................................................................................................15-13
Figure 15-13 Structure of the alarm cascading cable between the OptiX OSN equipment and the other Huawei
transmission equipment.....................................................................................................................................15-15
Figure 15-14 Structure of the alarm input/output cable...................................................................................15-16
Figure 15-15 Structure of the OAM serial port cable.......................................................................................15-18
Figure 15-16 Structure of the serial 14/F1/F&f serial port cable...................................................................15-20
Figure 15-17 Structure of the RS-232/RS-422 serial port cable......................................................................15-21
Figure 15-18 Structure of the ordinary telephone line.....................................................................................15-23
Figure 15-19 Structure of the COA cascading cable........................................................................................15-24
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Figures

Figure 15-20 Structure of the straight through cable........................................................................................15-25


Figure 15-21 Structure of the crossover cable..................................................................................................15-26
Figure 15-22 Structure of the 75-ohm 8xE1 cable...........................................................................................15-28
Figure 15-23 Structure of the 120-ohm 8xE1 cable.........................................................................................15-31
Figure 15-24 Structure of the 120-ohm 21xE1 cable.......................................................................................15-33
Figure 15-25 Structure of the E3/T3/STM-1 cable..........................................................................................15-36
Figure 15-26 Structure of the V.35 DCE cable................................................................................................15-39
Figure 15-27 Structure of the V.35 DTE cable................................................................................................ 15-41
Figure 15-28 Structure of the V.24 DCE cable................................................................................................15-42
Figure 15-29 Structure of the V.24 DTE cable................................................................................................ 15-44
Figure 15-30 Structure of the X.21 DCE cable................................................................................................15-45
Figure 15-31 Structure of the X.21 DTE cable................................................................................................ 15-47
Figure 15-32 Structure of the RS-449 DCE cable............................................................................................15-48
Figure 15-33 Structure of the RS-449 DTE cable............................................................................................15-50
Figure 15-34 Structure of the RS-530 DCE cable............................................................................................15-52
Figure 15-35 Structure of the RS-530 DTE cable............................................................................................15-54
Figure 15-36 Structure of the 75-ohm clock cable...........................................................................................15-56
Figure 15-37 Structure of the 120-ohm clock cable.........................................................................................15-56
Figure 15-38 Structure of the one-channel 75-ohm-to-120-ohm clock transit cable.......................................15-58
Figure 15-39 Structure of the two-channel 75-ohm-to-120-ohm clock transit cable.......................................15-58
Figure B-1 Positions of the labels affixed to the OptiX OSN 3500 II subrack...................................................B-4
Figure B-2 Positions of the labels affixed to the cabinet.....................................................................................B-5
Figure B-3 Positions of the labels affixed to the board.......................................................................................B-5
Figure B-4 Optical module label.........................................................................................................................B-5

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Tables

Tables
Table 2-1 Meanings of the status of the indicators...............................................................................................2-4
Table 2-2 Technical specifications of the ETSI cabinet.......................................................................................2-6
Table 3-1 Mapping relation between slots for the interface boards and slots for the processing boards.............3-6
Table 3-2 Paired slots...........................................................................................................................................3-6
Table 3-3 Dimensions and weight of the OptiX OSN 3500 II subrack................................................................3-7
Table 3-4 Maximum power consumption of the OptiX OSN 3500 II subrack....................................................3-7
Table 4-1 Appearances and dimensions of the boards used on the OptiX OSN 3500 II.....................................4-2
Table 4-2 SDH boards that the OptiX OSN 3500 II supports..............................................................................4-5
Table 4-3 PDH boards that the OptiX OSN 3500 II supports..............................................................................4-6
Table 4-4 Data boards that the OptiX OSN 3500 II supports..............................................................................4-6
Table 4-5 Interface boards and switching and bridging boards that the OptiX OSN 3500 II supports................4-7
Table 4-6 Cross-connect boards and system control boards that the OptiX OSN 3500 II supports....................4-8
Table 4-7 Auxiliary boards that the OptiX OSN 3500 II supports.......................................................................4-9
Table 4-8 WDM boards that the OptiX OSN 3500 II supports............................................................................4-9
Table 4-9 Microwave boards that the OptiX OSN 3500 II supports....................................................................4-9
Table 4-10 Optical amplifier boards and dispersion compensation boards that the OptiX OSN 3500 II supports
.............................................................................................................................................................................4-10
Table 4-11 Power boards that the OptiX OSN 3500 II supports........................................................................4-10
Table 5-1 Versions of the SL1..............................................................................................................................5-4
Table 5-2 Functions and features of the SL1........................................................................................................5-5
Table 5-3 Optical interfaces of the SL1..............................................................................................................5-10
Table 5-4 Relationship between the feature code of the SL1 and the type of optical interface.........................5-10
Table 5-5 Parameters specified for the optical interfaces of the SL1.................................................................5-11
Table 5-6 Functions and features of the SL1A...................................................................................................5-13
Table 5-7 Optical interfaces of the SL1A...........................................................................................................5-18
Table 5-8 Relationship between the feature code of the SL1A and the type of optical interface......................5-18
Table 5-9 Parameters specified for the optical interfaces of the SL1A..............................................................5-19
Table 5-10 Versions of the SLQ1.......................................................................................................................5-21
Table 5-11 Functions and features of the SLQ1.................................................................................................5-21
Table 5-12 Optical interfaces of the SLQ1.........................................................................................................5-26
Table 5-13 Relationship between the feature code of the SLQ1 and the type of optical interface....................5-26
Table 5-14 Parameters specified for the optical interfaces of the SLQ1............................................................5-27
Table 5-15 Functions and features of the SLQ1A..............................................................................................5-29
Table 5-16 Optical interfaces of the SLQ1A......................................................................................................5-34
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Table 5-17 Relationship between the feature code of the SLQ1A and the type of optical interface.................5-34
Table 5-18 Parameters specified for the optical interfaces of the SLQ1A.........................................................5-35
Table 5-19 Versions of the SLO1.......................................................................................................................5-37
Table 5-20 Functions and features of the SLO1 board.......................................................................................5-37
Table 5-21 Optical interfaces of the SLO1.........................................................................................................5-42
Table 5-22 Relationship between the feature code of the SLO1 and the type of optical interface....................5-42
Table 5-23 Parameters specified for the optical interfaces of the SLO1............................................................5-43
Table 5-24 Functions and features of the SLT1.................................................................................................5-45
Table 5-25 Optical interfaces of the SLT1.........................................................................................................5-50
Table 5-26 Parameters specified for the optical interfaces of the SLT1............................................................5-50
Table 5-27 Functions and features of the SLH1B..............................................................................................5-52
Table 5-28 Access capabilities of the SLH1B when the SLH1 works with different interface boards and electrical
interface switching boards...................................................................................................................................5-53
Table 5-29 Slots for the SLH1B, EU08, and TSB8............................................................................................5-59
Table 5-30 Parameters specified for the optical interfaces of the SLH1B.........................................................5-60
Table 5-31 Functions and features of the SEP1.................................................................................................5-62
Table 5-32 Access capabilities of the SEP1 when the SEP1 works with different interface boards and electrical
interface switching boards...................................................................................................................................5-63
Table 5-33 Electrical interfaces of the SEP1......................................................................................................5-69
Table 5-34 Slots for the SEP1, EU08, and TSB8...............................................................................................5-71
Table 5-35 Parameters specified for the interfaces of the SEP1........................................................................5-72
Table 5-36 Versions of the SL4..........................................................................................................................5-73
Table 5-37 Functions and features of the SL4....................................................................................................5-74
Table 5-38 Optical interfaces of the SL4............................................................................................................5-78
Table 5-39 Relationship between the feature code of the SL4 and the type of optical interface.......................5-78
Table 5-40 Parameters specified for the optical interfaces of the SL4...............................................................5-79
Table 5-41 Functions and features of the SL4A.................................................................................................5-81
Table 5-42 Optical interfaces of the SL4A.........................................................................................................5-86
Table 5-43 Relationship between the feature code of the SL4A and the type of optical interface....................5-86
Table 5-44 Parameters specified for the optical interfaces of the SL4A............................................................5-87
Table 5-45 Versions of the SLD4.......................................................................................................................5-89
Table 5-46 Functions and features of the SLD4.................................................................................................5-89
Table 5-47 Optical interfaces of the SLD4.........................................................................................................5-94
Table 5-48 Relationship between the feature code of the SLD4 and the type of optical interface....................5-94
Table 5-49 Parameters specified for the optical interfaces of the SLD4............................................................5-95
Table 5-50 Functions and features of the SLD4A..............................................................................................5-97
Table 5-51 Optical interfaces of the SLD4A....................................................................................................5-102
Table 5-52 Relationship between the feature code of the SLD4A and the type of optical interface...............5-102
Table 5-53 Parameters specified for the optical interfaces of the SLD4A.......................................................5-103
Table 5-54 Versions of the SLQ4.....................................................................................................................5-105
Table 5-55 Functions and features of the SLQ4...............................................................................................5-105
Table 5-56 Optical interfaces of the SLQ4.......................................................................................................5-110
Table 5-57 Relationship between the feature code of the SLQ4 and the type of optical interface..................5-110

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Tables

Table 5-58 Parameters specified for the optical interfaces of the SLQ4..........................................................5-111
Table 5-59 Functions and features of the SLQ4A............................................................................................5-113
Table 5-60 Optical interfaces of the SLQ4A....................................................................................................5-118
Table 5-61 Relationship between the feature code of the SLQ4A and the type of optical interface...............5-118
Table 5-62 Parameters specified for the optical interfaces of the SLQ4A.......................................................5-119
Table 5-63 Versions of the SL16......................................................................................................................5-121
Table 5-64 Functions and features of the SL16................................................................................................5-121
Table 5-65 Optical interfaces of the SL16........................................................................................................5-127
Table 5-66 Relationship between the feature code of the SL16 and the type of optical interface...................5-127
Table 5-67 Parameters specified for the optical interfaces of the SL16...........................................................5-128
Table 5-68 Parameters specified for the optical interfaces that comply with the standard wavelengths specified in
ITU-T G.692......................................................................................................................................................5-129
Table 5-69 Versions of the SL16A...................................................................................................................5-130
Table 5-70 Functions and features of the SL16A.............................................................................................5-131
Table 5-71 Optical interfaces of the SL16A.....................................................................................................5-136
Table 5-72 Relationship between the feature code of the SL16A and the type of optical interface................5-136
Table 5-73 Parameters specified for the optical interfaces of the SL16A........................................................5-137
Table 5-74 Functions and features of the SLD16.............................................................................................5-139
Table 5-75 Optical interfaces of the SLD16.....................................................................................................5-144
Table 5-76 Relationship between the feature code of the SLD16 and the type of optical interface................5-144
Table 5-77 Parameters specified for the optical interfaces of the SLD16........................................................5-145
Table 5-78 Versions of the SLQ16...................................................................................................................5-147
Table 5-79 Functions and features of the SLQ16.............................................................................................5-147
Table 5-80 Optical interfaces of the SLQ16.....................................................................................................5-153
Table 5-81 Relationship between the feature code of the SLQ16 and the type of optical interface................5-153
Table 5-82 Parameters specified for the optical interfaces of the SLQ16........................................................5-154
Table 5-83 Functions and features of the SF16................................................................................................5-156
Table 5-84 Optical interfaces of the SF16........................................................................................................5-161
Table 5-85 Parameters specified for the optical interfaces of the SF16...........................................................5-161
Table 5-86 Parameters specified for the optical interfaces that comply with the standard wavelengths specified in
ITU-T G.692......................................................................................................................................................5-162
Table 5-87 Functions and features of the SL64................................................................................................5-164
Table 5-88 Optical interfaces of the SL64........................................................................................................5-169
Table 5-89 Relationship between the feature code of the SL64 and the type of optical interface...................5-169
Table 5-90 Parameters specified for the optical interfaces of the SL64...........................................................5-170
Table 5-91 Parameters specified for the optical interfaces that comply with the standard wavelengths specified in
ITU-T G.692......................................................................................................................................................5-171
Table 5-92 Functions and features of the SF64................................................................................................5-173
Table 5-93 Optical interfaces of the SF64........................................................................................................5-177
Table 5-94 Specifications of optical interfaces of the SF64.............................................................................5-177
Table 5-95 Parameters specified for the optical interfaces that comply with the standard wavelengths specified in
ITU-T G.692......................................................................................................................................................5-178
Table 5-96 Functions and features of the SF64A.............................................................................................5-179
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Table 5-97 Optical interfaces of the SF64A.....................................................................................................5-184
Table 5-98 Specifications of optical interfaces of the SF64A..........................................................................5-184
Table 5-99 Parameters specified for the optical interfaces that comply with the standard wavelengths specified in
ITU-T G.692......................................................................................................................................................5-185
Table 5-100 Functions and features of the SLQ41...........................................................................................5-187
Table 5-101 Optical interfaces of the SLQ41...................................................................................................5-192
Table 5-102 Relationship between the feature code of the SLQ41 and the type of optical interface..............5-192
Table 5-103 Parameters specified for the optical interfaces of the SLQ41 when the STM-1 optical module is used
...........................................................................................................................................................................5-193
Table 5-104 Parameters specified for the optical interfaces of the SLQ41 when the STM-4 optical module is used
...........................................................................................................................................................................5-194
Table 6-1 Versions of the PQ1.............................................................................................................................6-3
Table 6-2 Functions and features of the PQ1.......................................................................................................6-4
Table 6-3 Slots valid for the PQ1 and the corresponding slots for the D75S, D12S, and D12B in the main subrack
...............................................................................................................................................................................6-9
Table 6-4 Relationship between the feature code of the PQ1 and the type of interface impedance..................6-10
Table 6-5 Slot configuration for the 1:10 TPS protection of the PQ1................................................................6-11
Table 6-6 Functions and features of the PO1.....................................................................................................6-14
Table 6-7 Interfaces of the PO1..........................................................................................................................6-18
Table 6-8 Slots valid for the PO1 and the corresponding slots for the D12S and D12B in the main subrack
.............................................................................................................................................................................6-18
Table 6-9 Relationship between the feature code of the PO1 and the type of interface impedance..................6-19
Table 6-10 Functions and features of the PQM..................................................................................................6-21
Table 6-11 Slots valid for the PQM and the corresponding slots for the D12S and D12B in the main subrack
.............................................................................................................................................................................6-25
Table 6-12 Slot configuration for the 1:10 TPS protection of the PQM............................................................6-27
Table 6-13 Versions of the PL3..........................................................................................................................6-30
Table 6-14 Functions and features of the PL3....................................................................................................6-30
Table 6-15 Slots valid for the PL3 and the corresponding slots for the C34S in the main subrack...................6-34
Table 6-16 Slots for the PL3, C34S, and TSB8/TSB4.......................................................................................6-36
Table 6-17 Versions of the PL3A.......................................................................................................................6-38
Table 6-18 Functions and features of the PL3A.................................................................................................6-39
Table 6-19 Parameters specified for the electrical interfaces of the PL3A........................................................6-43
Table 6-20 Versions of the PD3.........................................................................................................................6-45
Table 6-21 Functions and features of the PD3...................................................................................................6-45
Table 6-22 Slots valid for the PD3 and the corresponding slots for the D34S in the main subrack..................6-50
Table 6-23 Slot configuration for the two 1:3 TPS protection groups of the PD3.............................................6-51
Table 6-24 Slots for the PD3, D34S, and TSB8.................................................................................................6-52
Table 6-25 Functions and features of the PQ3...................................................................................................6-54
Table 6-26 Slots valid for the PQ3 and the corresponding slots for the D34S...................................................6-58
Table 6-27 Slot configuration for the 1:3 TPS protection of the PQ3................................................................6-60
Table 6-28 Slots for the PQ3, D34S, and TSB8.................................................................................................6-60
Table 6-29 Functions and features of the DX1...................................................................................................6-62
Table 6-30 Slots valid for the DX1 and the corresponding slots for the DM12.................................................6-66

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Tables

Table 6-31 Relationship between the feature code of the DX1 and the type of interface impedance................6-66
Table 6-32 Slots for the DX1 and DM12...........................................................................................................6-68
Table 6-33 Functions and features of the DXA..................................................................................................6-70
Table 6-34 Versions of the SPQ4.......................................................................................................................6-74
Table 6-35 Functions and features of the SPQ4.................................................................................................6-74
Table 6-36 Slots valid for the SPQ4 and the corresponding slots for the MU04...............................................6-81
Table 6-37 Slots for the SPQ4, MU04, and TSB8/TSB4...................................................................................6-83
Table 7-1 Functions and features of the EFT8.....................................................................................................7-3
Table 7-2 Interfaces of the EFT8..........................................................................................................................7-9
Table 7-3 Pins of the RJ-45 connector ................................................................................................................7-9
Table 7-4 Throughput specifications of the EFT8..............................................................................................7-11
Table 7-5 Packet loss ratio in the case of overloading of the EFT8...................................................................7-12
Table 7-6 Latency specifications of the EFT8....................................................................................................7-12
Table 7-7 Back-to-back specifications of the EFT8...........................................................................................7-13
Table 7-8 Functions and features of the EFT8A................................................................................................7-14
Table 7-9 Interfaces of the EFT8A.....................................................................................................................7-19
Table 7-10 Pins of the RJ-45 connector.............................................................................................................7-19
Table 7-11 Throughput specifications of the EFT8A.........................................................................................7-22
Table 7-12 Packet loss ratio in the case of overloading of the EFT8A..............................................................7-22
Table 7-13 Latency specifications of the EFT8A...............................................................................................7-23
Table 7-14 Back-to-back specifications of the EFT8A......................................................................................7-23
Table 7-15 Functions and features of the EGT2.................................................................................................7-25
Table 7-16 Optical interfaces of the N1EGT2/N2EGT2....................................................................................7-31
Table 7-17 Electrical interfaces of the N2EGT2................................................................................................7-31
Table 7-18 Pin assignments of the RJ-45 interface of the N2EGT2..................................................................7-31
Table 7-19 Relationship between the feature code of the EGT2 and the type of interface................................7-32
Table 7-20 Parameters specified for the optical interfaces of the EGT2............................................................7-33
Table 7-21 Throughput specifications of the EGT2...........................................................................................7-34
Table 7-22 Packet loss ratio in the case of overloading of the EGT2................................................................7-35
Table 7-23 Latency specifications of the EGT2.................................................................................................7-35
Table 7-24 Back-to-back specifications of the EGT2........................................................................................7-36
Table 7-25 Versions of the EFS0.......................................................................................................................7-37
Table 7-26 Functions and features of the EFS0.................................................................................................7-38
Table 7-27 Slots valid for the EFS0 and the corresponding slots for the ETF8 and EFF8................................7-45
Table 7-28 Slots for the EFS0, ETS8, and TSB8...............................................................................................7-46
Table 7-29 Throughput specifications of the EFS0............................................................................................7-48
Table 7-30 Packet loss ratio in the case of overloading of the EFS0.................................................................7-48
Table 7-31 Latency specifications of the EFS0..................................................................................................7-49
Table 7-32 Back-to-back specifications of the EFS0.........................................................................................7-50
Table 7-33 Functions and features of the EFS0A...............................................................................................7-52
Table 7-34 Slots valid for the EFS0A and the corresponding slots for the ETF8 and EFF8.............................7-59
Table 7-35 Slots for the EFS0A, ETS8, and TSB8............................................................................................7-60
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Table 7-36 Throughput specifications of the EFS0A.........................................................................................7-62
Table 7-37 Packet loss ratio in the case of overloading of the EFS0A..............................................................7-62
Table 7-38 Latency specifications of the EFS0A...............................................................................................7-63
Table 7-39 Back-to-back specifications of the EFS0A......................................................................................7-64
Table 7-40 Versions of the EFS4.......................................................................................................................7-66
Table 7-41 Functions and features of the EFS4.................................................................................................7-66
Table 7-42 Interfaces of the EFS4......................................................................................................................7-73
Table 7-43 Pins of the RJ-45 connector.............................................................................................................7-73
Table 7-44 Throughput specifications of the EFS4............................................................................................7-75
Table 7-45 Packet loss ratio in the case of overloading of the EFS4.................................................................7-75
Table 7-46 Latency specifications of the EFS4..................................................................................................7-76
Table 7-47 Back-to-back specifications of the EFS4.........................................................................................7-77
Table 7-48 Functions and features of the EGS2.................................................................................................7-79
Table 7-49 Optical interfaces of the N2EGS2/N3EGS2....................................................................................7-86
Table 7-50 Electrical interfaces of the N3EGS2................................................................................................7-86
Table 7-51 Pin assignments of the RJ-45 interface of the N3EGS2..................................................................7-86
Table 7-52 Relationship between the feature code of the EGS2 and the type of interface................................7-87
Table 7-53 Parameters specified for the optical interfaces of the EGS2............................................................7-88
Table 7-54 Throughput specifications of the EGS2...........................................................................................7-89
Table 7-55 Packet loss ratio in the case of overloading of the EGS2.................................................................7-90
Table 7-56 Latency specifications of the EGS2.................................................................................................7-90
Table 7-57 Back-to-back specifications of the EGS2.........................................................................................7-91
Table 7-58 Functions and features of the EMS2................................................................................................7-93
Table 7-59 Optical interfaces of the EMS2......................................................................................................7-101
Table 7-60 Electrical interfaces of the EMS2...................................................................................................7-101
Table 7-61 Pin assignments of the RJ-45 interface of the EMS2.....................................................................7-101
Table 7-62 Slots valid for the EMS2 and the corresponding slots for the ETF8 and EFF8.............................7-102
Table 7-63 Relationship between the feature code of the EMS2 and the type of interface.............................7-102
Table 7-64 Parameters specified for the optical interfaces of the EMS2.........................................................7-103
Table 7-65 Functions and features of the EMS4..............................................................................................7-105
Table 7-66 Optical interfaces of the EMS4......................................................................................................7-112
Table 7-67 Electrical interfaces of the EMS4...................................................................................................7-112
Table 7-68 Pin assignments of the RJ-45 interface of the EMS4.....................................................................7-112
Table 7-69 Slots valid for the EMS4 and the corresponding slots for the ETF8 and EFF8.............................7-113
Table 7-70 Relationship between the feature code of the EMS4 and the type of interface.............................7-113
Table 7-71 Parameters specified for the optical interfaces of the EMS4.........................................................7-117
Table 7-72 Throughput specifications of the EMS4 (one VC-4 is bound on the FE port)..............................7-119
Table 7-73 Throughput specifications of the EMS4 (24 VC-3s are bound on the GE port)............................7-119
Table 7-74 Packet loss ratio in the case of overloading of the EMS4 (one VC-4 is bound on the FE port)
...........................................................................................................................................................................7-120
Table 7-75 Packet loss ratio in the case of overloading of the EMS4 (24 VC-3s are bound on the GE port)
...........................................................................................................................................................................7-121
Table 7-76 Latency specifications of the EMS4 (one VC-4 is bound on the FE port).....................................7-122

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Tables

Table 7-77 Latency specifications of the EMS4 (24 VC-3s are bound on the GE port)..................................7-123
Table 7-78 Back-to-back specifications of the EMS4 (one VC-4 is bound on the FE port)............................7-124
Table 7-79 Back-to-back specifications of the EMS4 (24 VC-3s are bound on the GE port).........................7-125
Table 7-80 Versions of the EGS4.....................................................................................................................7-127
Table 7-81 Functions and features of the EGS4...............................................................................................7-128
Table 7-82 Optical interfaces of the N1EGS4/N3EGS4/N4EGS4...................................................................7-135
Table 7-83 Electrical interfaces of the N1EGS4/N4EGS4...............................................................................7-135
Table 7-84 Pin assignments of the RJ-45 interface of the N1EGS4/N4EGS4.................................................7-135
Table 7-85 Relationship between the feature code of the EGS4 and the type of interface..............................7-136
Table 7-86 Parameters specified for the optical interfaces of the EGS4..........................................................7-140
Table 7-87 Throughput specifications of the EGS4 (one VC-4 is bound on the FE port)...............................7-142
Table 7-88 Throughput specifications of the EGS4 (24 VC-3s are bound on the GE port).............................7-142
Table 7-89 Packet loss ratio in the case of overloading of the EGS4 (one VC-4 is bound on the FE port)
...........................................................................................................................................................................7-143
Table 7-90 Packet loss ratio in the case of overloading of the EGS4 (24 VC-3s are bound on the GE port)
...........................................................................................................................................................................7-144
Table 7-91 Latency specifications of the EGS4 (one VC-4 is bound on the FE port).....................................7-145
Table 7-92 Latency specifications of the EGS4 (24 VC-3s are bound on the GE port)...................................7-146
Table 7-93 Back-to-back specifications of the EGS4 (one VC-4 is bound on the FE port).............................7-147
Table 7-94 Back-to-back specifications of the EGS4 (24 VC-3s are bound on the GE port)..........................7-148
Table 7-95 Functions and features of the EGR2..............................................................................................7-150
Table 7-96 Optical interfaces of the EGR2 .....................................................................................................7-157
Table 7-97 Relationship between the feature code of the EGR2 and the type of optical interface..................7-157
Table 7-98 Parameters specified for the optical interfaces of the EGR2.........................................................7-158
Table 7-99 Throughput specifications of the EGR2.........................................................................................7-159
Table 7-100 Packet loss ratio in the case of overloading of the EGR2............................................................7-160
Table 7-101 Latency specifications of the EGR2.............................................................................................7-161
Table 7-102 Back-to-back specifications of the EGR2....................................................................................7-161
Table 7-103 Functions and features of the EMR0............................................................................................7-163
Table 7-104 Interfaces of the EMR0................................................................................................................7-170
Table 7-105 Slots valid for the EMR0 and the corresponding slots for the ETF8 and EFF8..........................7-170
Table 7-106 Relationship between the feature code of the EMR0 and the type of optical interface...............7-171
Table 7-107 Parameters specified for the optical interfaces of the EMR0.......................................................7-172
Table 7-108 Throughput specifications of the EMR0 (eight VC-4s are bound on the FE port)......................7-173
Table 7-109 Throughput specifications of the EMR0 (eight VC-4s are bound on the GE port).....................7-174
Table 7-110 Packet loss ratio in the case of overloading of the EMR0 (eight VC-4s are bound on the FE port)
...........................................................................................................................................................................7-175
Table 7-111 Packet loss ratio in the case of overloading of the EMR0 (eight VC-4s are bound on the GE port)
...........................................................................................................................................................................7-175
Table 7-112 Latency specifications of the EMR0 (eight VC-4s are bound on the FE port)............................7-176
Table 7-113 Latency specifications of the EMR0 (eight VC-4s are bound on the GE port)...........................7-177
Table 7-114 Back-to-back specifications of the EMR0 (eight VC-4s are bound on the FE port)...................7-178
Table 7-115 Back-to-back specifications of the EMR0 (eight VC-4s are bound on the GE port)...................7-179
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Hardware Description
Table 7-116 Functions and features of the EAS2 board...................................................................................7-180
Table 7-117 Interfaces of the EAS2.................................................................................................................7-185
Table 7-118 Parameters specified for the optical interfaces of the EAS2........................................................7-186
Table 7-119 Throughput specifications of the EAS2.......................................................................................7-187
Table 7-120 Packet loss ratio in the case of overloading of the EAS2.............................................................7-187
Table 7-121 Latency specifications of the EAS2.............................................................................................7-188
Table 7-122 Functions and features of the ADL4............................................................................................7-189
Table 7-123 Optical interface of the ADL4 .....................................................................................................7-194
Table 7-124 Relationship between the feature code of the ADL4 and the type of optical interface................7-194
Table 7-125 Parameters specified for the optical interfaces of the ADL4.......................................................7-195
Table 7-126 Functions and features of the ADQ1............................................................................................7-196
Table 7-127 Optical interfaces of the ADQ1....................................................................................................7-201
Table 7-128 Relationship between the feature code of the ADQ1 and the type of optical interface...............7-201
Table 7-129 Parameters specified for the optical interfaces of the ADQ1.......................................................7-202
Table 7-130 Functions and features of the IDL4..............................................................................................7-204
Table 7-131 Optical interface of the IDL4.......................................................................................................7-209
Table 7-132 Relationship between the feature code of the IDL4 and the type of optical interface.................7-209
Table 7-133 Parameters specified for the optical interfaces of the IDL4.........................................................7-210
Table 7-134 Functions and features of the IDL4A...........................................................................................7-212
Table 7-135 Optical interface of the IDL4A....................................................................................................7-217
Table 7-136 Relationship between the feature code of the IDL4A and the type of optical interface..............7-217
Table 7-137 Parameters specified for the optical interfaces of the IDL4A......................................................7-218
Table 7-138 Functions and features of the IDQ1.............................................................................................7-220
Table 7-139 Optical interfaces of the IDQ1.....................................................................................................7-225
Table 7-140 Relationship between the feature code of the IDQ1 and the type of optical interface.................7-225
Table 7-141 Parameters specified for the optical interfaces of the IDQ1........................................................7-226
Table 7-142 Functions and features of the IDQ1A..........................................................................................7-228
Table 7-143 Optical interfaces of the IDQ1A .................................................................................................7-233
Table 7-144 Relationship between the feature code of the IDQ1A and the type of optical interface..............7-233
Table 7-145 Parameters specified for the optical interfaces of the IDQ1A.....................................................7-234
Table 8-1 Interfaces of the D12B.........................................................................................................................8-5
Table 8-2 Pin assignments of the DB44 interface................................................................................................8-5
Table 8-3 Slots valid for the PQ1/PQM/PO1 and the corresponding slots for the D12B....................................8-6
Table 8-4 Parameters specified for the electrical interfaces of the D12B............................................................8-7
Table 8-5 Interfaces of the D12S........................................................................................................................8-10
Table 8-6 Pin assignments of the DB44 interface..............................................................................................8-10
Table 8-7 Slots valid for the PQ1/PQM/PO1 and the corresponding slots for the D12S...................................8-11
Table 8-8 Parameters specified for the electrical interfaces of the D12S...........................................................8-12
Table 8-9 Interfaces of the D75S........................................................................................................................8-15
Table 8-10 Pin assignments of the DB44 interface............................................................................................8-15
Table 8-11 Slots valid for the PQ1 and the corresponding slots for the D75S...................................................8-16
Table 8-12 Parameters specified for the electrical interfaces of the D75S.........................................................8-17

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Tables

Table 8-13 Interfaces of the D34S......................................................................................................................8-20


Table 8-14 Parameters specified for the electrical interfaces of the D34S.........................................................8-20
Table 8-15 Interfaces of the C34S......................................................................................................................8-23
Table 8-16 Slots valid for the PL3 and the corresponding slots for the C34S...................................................8-24
Table 8-17 Parameters specified for the electrical interfaces of the C34S.........................................................8-24
Table 8-18 Interfaces of the EU04.....................................................................................................................8-27
Table 8-19 Slots valid for the SEP and the corresponding slots for the EU04...................................................8-28
Table 8-20 Parameters specified for the electrical interfaces of the EU04........................................................8-28
Table 8-21 Interfaces of the EU08.....................................................................................................................8-31
Table 8-22 Slots valid for the SLH1B and the corresponding slots for the EU08.............................................8-32
Table 8-23 Slots valid for the SEP and the corresponding slots for the EU08...................................................8-32
Table 8-24 Parameters specified for the electrical interfaces of the EU08........................................................8-33
Table 8-25 Versions of the OU08.......................................................................................................................8-34
Table 8-26 Interfaces of the N1OU08................................................................................................................8-37
Table 8-27 Interfaces of the N2OU08................................................................................................................8-38
Table 8-28 Slots valid for the SLH1B and the corresponding slots for the OU08.............................................8-38
Table 8-29 Slots valid for the SEP1 and the corresponding slots for the OU08................................................8-39
Table 8-30 Parameters specified for the optical interfaces of the OU08............................................................8-39
Table 8-31 Interfaces of the MU04....................................................................................................................8-42
Table 8-32 Slots valid for the SPQ4 and the corresponding slots for the MU04...............................................8-43
Table 8-33 Parameters specified for the electrical interfaces of the MU04.......................................................8-43
Table 8-34 Slots valid for the TSB4 and the corresponding slots for the SPQ4 and MU04..............................8-46
Table 8-35 Slots valid for the TSB4 and the corresponding slots for the SEP1 and EU04...............................8-47
Table 8-36 Slots valid for the TSB4 and the corresponding slots for the PL3 and C34S..................................8-47
Table 8-37 Slots valid for the TSB8 and the corresponding slots for the SPQ4 and MU04..............................8-50
Table 8-38 Slots valid for the TSB8 and the corresponding slots for the PL3 and C34S..................................8-51
Table 8-39 Slots valid for the TSB8 and the corresponding slots for the PD3 and D34S.................................8-51
Table 8-40 Slots valid for the TSB8 and the corresponding slots for the PQ3 and D34S.................................8-52
Table 8-41 Slots valid for the TSB8 and the corresponding slots for the SEP1 and EU04...............................8-52
Table 8-42 Slots valid for the TSB8 and the corresponding slots for the SEP1 and EU08...............................8-52
Table 8-43 Slots valid for the TSB8 and the corresponding slots for the SLH1B and EU08............................8-53
Table 8-44 Slots valid for the TSB8 and the corresponding slots for the EFS0 and ETS8................................8-53
Table 8-45 Interfaces of the EFF8......................................................................................................................8-57
Table 8-46 Slots valid for the EFT8/EFS0/EMR0 and the corresponding slots for the EFF8...........................8-57
Table 8-47 Slots valid for the EMS4 and the corresponding slots for the EFF8................................................8-57
Table 8-48 Parameters specified for the optical interfaces of the EFF8.............................................................8-58
Table 8-49 Interfaces of the EFF8A...................................................................................................................8-62
Table 8-50 Slots valid for the N5EFS0 and the corresponding slots for the EFF8A.........................................8-62
Table 8-51 Parameters specified for the optical interfaces of the EFF8A..........................................................8-63
Table 8-52 Interfaces of the ETF8......................................................................................................................8-66
Table 8-53 Pin assignments of the RJ-45 connector of the ETF8......................................................................8-66
Table 8-54 Slots valid for the EFT8/EFS0/EMR0 and the corresponding slots for the ETF8...........................8-66
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Hardware Description
Table 8-55 Slots valid for the EMS4 and the corresponding slots for the ETF8...............................................8-67
Table 8-56 Parameters specified for the optical interfaces of the ETF8............................................................8-68
Table 8-57 Interfaces of the ETF8A...................................................................................................................8-70
Table 8-58 Pin assignments of the RJ-45 connector of the ETF8A...................................................................8-71
Table 8-59 Slots valid for the N5EFS0 and the corresponding slots for the ETF8A.........................................8-71
Table 8-60 Parameters specified for the optical interfaces of the ETF8A.........................................................8-72
Table 8-61 Interfaces of the ETS8......................................................................................................................8-75
Table 8-62 Pin assignments of the RJ-45 connector of the ETS8......................................................................8-75
Table 8-63 Slots valid for the EFS0 and the corresponding slots for the ETS8.................................................8-75
Table 8-64 Slots valid for the EFS0A and the corresponding slots for the ETS8..............................................8-76
Table 8-65 Parameters specified for the optical interfaces of the ETS8............................................................8-76
Table 8-66 Interfaces of the DM12....................................................................................................................8-79
Table 8-67 Pin assignments of the DB44 interface............................................................................................8-80
Table 8-68 Pin assignments of the DB28 interface............................................................................................8-81
Table 8-69 Slots valid for the DX1 and the corresponding slots for the DM12.................................................8-81
Table 8-70 Parameters specified for the electrical interfaces of the DM12.......................................................8-82
Table 9-1 Versions of the CXLLN.......................................................................................................................9-3
Table 9-2 Functions and features of the SDH processing unit of the CXLLN....................................................9-3
Table 9-3 Functions and features of the SCC unit of the CXLLN.......................................................................9-5
Table 9-4 Functions and features of the cross-connect unit of the CXLLN.........................................................9-6
Table 9-5 Functions and features of the clock unit of the CXLLN......................................................................9-6
Table 9-6 Jumpers of the Q5CXLLN.................................................................................................................9-11
Table 9-7 Jumper of the Q6CXLLN...................................................................................................................9-12
Table 9-8 DIP switch of the CXLLN.................................................................................................................9-12
Table 9-9 DIP switch SW1.................................................................................................................................9-12
Table 9-10 Optical interface and switches of the CXLLN.................................................................................9-14
Table 9-11 Logical slots displayed on the T2000 for the Q5CXLLN................................................................9-15
Table 9-12 Logical slots displayed on the T2000 for the Q6CXLLN................................................................9-15
Table 9-13 Parameters specified for the optical interfaces of the CXLLN when the STM-1 optical module is used
.............................................................................................................................................................................9-16
Table 9-14 Parameters specified for the optical interfaces of the CXLLN when the STM-4 optical module is used
.............................................................................................................................................................................9-16
Table 9-15 Parameters specified for the optical interfaces of the CXLLN when the STM-16 optical module is used
.............................................................................................................................................................................9-17
Table 9-16 Versions of the CXLQ41.................................................................................................................9-20
Table 9-17 Functions and features of the SDH processing unit of the CXLQ41...............................................9-20
Table 9-18 Functions and features of the SCC unit of the CXLQ41.................................................................9-22
Table 9-19 Functions and features of the cross-connect unit of the CXLQ41...................................................9-23
Table 9-20 Functions and features of the clock unit of the CXLQ41................................................................9-23
Table 9-21 Jumpers of the Q5CXLQ41.............................................................................................................9-28
Table 9-22 Jumper of the Q6CXLQ41...............................................................................................................9-29
Table 9-23 DIP switch of the CXLQ41..............................................................................................................9-29
Table 9-24 DIP switch SW1...............................................................................................................................9-29

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Tables

Table 9-25 Optical interfaces and switches of the CXLQ41..............................................................................9-31


Table 9-26 Logical slots displayed on the T2000 for the Q5CXLQ41..............................................................9-32
Table 9-27 Logical slots displayed on the T2000 for the Q6CXLQ41..............................................................9-32
Table 9-28 Parameters specified for the optical interfaces of the CXLQ41 when the STM-1 optical module is used
.............................................................................................................................................................................9-33
Table 9-29 Parameters specified for the optical interfaces of the CXLQ41 when the STM-4 optical module is used
.............................................................................................................................................................................9-33
Table 9-30 Functions and features of the SCC unit of the CXS.........................................................................9-36
Table 9-31 Functions and features of the cross-connect unit of the CXS..........................................................9-37
Table 9-32 Functions and features of the clock unit of the CXS.......................................................................9-37
Table 9-33 Jumpers of the CXS.........................................................................................................................9-40
Table 9-34 DIP switch of the CXS.....................................................................................................................9-41
Table 9-35 DIP switch SW1...............................................................................................................................9-41
Table 9-36 Switches of the CXS........................................................................................................................9-43
Table 9-37 Logical slots displayed on the T2000 for the CXS..........................................................................9-43
Table 10-1 Functions and features of the EOW.................................................................................................10-2
Table 10-2 Interfaces of the EOW......................................................................................................................10-5
Table 10-3 Pins of the PHONE interface...........................................................................................................10-6
Table 10-4 Pins of the S1, S2, S3, and S4 interfaces.........................................................................................10-6
Table 10-5 Functions and features of the AUX..................................................................................................10-8
Table 10-6 Jumpers on the AUX......................................................................................................................10-10
Table 10-7 Interfaces of the AUX....................................................................................................................10-11
Table 10-8 Pins of the CLK interface...............................................................................................................10-12
Table 10-9 Pins of the ETH and COM interfaces............................................................................................10-12
Table 10-10 Pins of the LAMP1 and LAMP2 interfaces.................................................................................10-12
Table 10-11 Functions and features of the SEI................................................................................................10-15
Table 10-12 Interfaces of the SEI.....................................................................................................................10-17
Table 10-13 Pins of the CLK1 and CLK2 interfaces.......................................................................................10-18
Table 10-14 Pins of the F1 interface................................................................................................................10-19
Table 10-15 Pins of the F&f interface..............................................................................................................10-19
Table 10-16 Pins of the PHONE, V1, and V2 interfaces.................................................................................10-19
Table 10-17 Pins of the LAMP1 and LAMP2 interfaces.................................................................................10-20
Table 10-18 Pins of the ALM01 and ALM02 interfaces..................................................................................10-20
Table 10-19 Pins of the OAM interface...........................................................................................................10-21
Table 10-20 Pins of the S1, S2, S3, and S4 interfaces.....................................................................................10-21
Table 10-21 Pins of the ALMI1 interface........................................................................................................10-22
Table 10-22 Pins of the ALMI2 interface........................................................................................................10-22
Table 10-23 Functions and features of the FAN/FANB...................................................................................10-24
Table 10-24 Functions and features of the FANA...........................................................................................10-28
Table 11-1 Functions and features of the CMR2...............................................................................................11-2
Table 11-2 Optical interfaces of the CMR2.......................................................................................................11-5
Table 11-3 Feature code of the CMR2...............................................................................................................11-6
Table 11-4 Parameters specified for the optical interfaces of the CMR2...........................................................11-6
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Hardware Description
Table 11-5 Functions and features of the CMR4...............................................................................................11-8
Table 11-6 Optical interfaces of the CMR4.....................................................................................................11-11
Table 11-7 Feature code of the CMR4.............................................................................................................11-11
Table 11-8 Parameters specified for the optical interfaces of the CMR4.........................................................11-12
Table 11-9 Functions and features of the MR2................................................................................................11-14
Table 11-10 Optical interfaces of the MR2......................................................................................................11-17
Table 11-11 Feature code of the MR2..............................................................................................................11-17
Table 11-12 Parameters specified for the optical interfaces of the MR2.........................................................11-18
Table 11-13 Functions and features of the MR2A...........................................................................................11-20
Table 11-14 Optical interfaces of the MR2A...................................................................................................11-23
Table 11-15 Parameters specified for the optical interfaces of the MR2A......................................................11-23
Table 11-16 Functions and features of the MR2C...........................................................................................11-25
Table 11-17 Optical interfaces of the MR2C...................................................................................................11-28
Table 11-18 Parameters specified for the optical interfaces of the MR2C.......................................................11-29
Table 11-19 Functions and features of the MR4..............................................................................................11-31
Table 11-20 Optical interfaces of the MR4......................................................................................................11-34
Table 11-21 Feature code of the MR4..............................................................................................................11-34
Table 11-22 Parameters specified for the optical interfaces of the MR4.........................................................11-35
Table 11-23 Functions and features of the LWX.............................................................................................11-37
Table 11-24 Optical interfaces of the LWX.....................................................................................................11-41
Table 11-25 Relationship between the feature code of the LWX and the signal receive/transmit scheme.....11-41
Table 11-26 Parameters specified for the client-side optical interfaces of the LWX.......................................11-42
Table 11-27 Parameters specified for the WDM-side optical interfaces of the LWX.....................................11-43
Table 11-28 Functions and features of the FIB................................................................................................11-46
Table 11-29 Optical interfaces of the FIB .......................................................................................................11-47
Table 11-30 Parameters specified for the optical interfaces of the FIB...........................................................11-48
Table 12-1 Functions and features of the IFSD1................................................................................................12-2
Table 12-2 Interfaces of the IFSD1....................................................................................................................12-7
Table 12-3 Radio work modes............................................................................................................................12-8
Table 12-4 IF performance...............................................................................................................................12-10
Table 12-5 Baseband signal processing performance of the modem...............................................................12-11
Table 12-6 Functions and features of the RPWR.............................................................................................12-12
Table 12-7 Interfaces of the RPWR.................................................................................................................12-15
Table 13-1 Functions and features of the BA2...................................................................................................13-3
Table 13-2 Optical interface of the one-interface BA2......................................................................................13-8
Table 13-3 Optical interfaces of the two-interface BA2....................................................................................13-8
Table 13-4 Relationship between the feature code of the BA2 and the output optical power...........................13-9
Table 13-5 Parameters specified for the optical interfaces of the BA2..............................................................13-9
Table 13-6 Versions of the BPA.......................................................................................................................13-10
Table 13-7 Functions and features of the BPA.................................................................................................13-11
Table 13-8 Optical interfaces of the BPA........................................................................................................13-15
Table 13-9 Relationship between the feature code of the BPA and the output optical power.........................13-15

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Tables

Table 13-10 Parameters specified for the optical interfaces of the BPA..........................................................13-16
Table 13-11 Versions of the COA....................................................................................................................13-17
Table 13-12 Functions and features of the 61COA/N1COA...........................................................................13-18
Table 13-13 Functions and features of the 62COA..........................................................................................13-20
Table 13-14 Pin assignments of the RS-232 serial port...................................................................................13-24
Table 13-15 Pin assignments of the MONITOR interfaces.............................................................................13-25
Table 13-16 Pin assignments of the RJ-45 connector of the 62COA...............................................................13-25
Table 13-17 Relationship between the feature code of the 61COA and the output optical power..................13-27
Table 13-18 Parameters specified for the optical interfaces of the COA.........................................................13-27
Table 13-19 Functions and features of the RPC01...........................................................................................13-29
Table 13-20 Interfaces of the RPC01...............................................................................................................13-32
Table 13-21 Feature code of the RPC01..........................................................................................................13-33
Table 13-22 Serial numbers of the optical interfaces on the front panel of the RPC01 on the NMS..............13-33
Table 13-23 Parameters specified for the optical interfaces of the RPC01......................................................13-34
Table 13-24 Functions and features of the RPC02...........................................................................................13-36
Table 13-25 Interfaces of the RPC02...............................................................................................................13-39
Table 13-26 Feature code of the RPC02..........................................................................................................13-40
Table 13-27 Serial numbers of the optical interfaces on the front panel of the RPC02 on the NMS..............13-40
Table 13-28 Parameters specified for the optical interfaces of the RPC02......................................................13-41
Table 13-29 Functions and features of the OBU1............................................................................................13-42
Table 13-30 Optical interfaces of the OBU1....................................................................................................13-46
Table 13-31 Feature code of the OBU1............................................................................................................13-46
Table 13-32 Parameters specified for the optical interfaces of the OBU1.......................................................13-47
Table 13-33 Versions of the DCU....................................................................................................................13-49
Table 13-34 Functions and features of the DCU..............................................................................................13-50
Table 13-35 Optical interface of the one-interface DCU.................................................................................13-54
Table 13-36 Optical interfaces of the two-interface DCU................................................................................13-54
Table 13-37 Relationship between the feature code of the DCU and the compensated dispersion.................13-54
Table 13-38 Parameters specified for the optical interfaces of the DCU.........................................................13-55
Table 14-1 Functions and features of the UPM..................................................................................................14-3
Table 14-2 Interfaces of the UPM......................................................................................................................14-5
Table 14-3 Power parameters of the UPM.........................................................................................................14-6
Table 14-4 Functions and features of the PIU....................................................................................................14-8
Table 14-5 Interfaces of the PIU......................................................................................................................14-10
Table 14-6 Pin assignments of the PWS interface of the PIU..........................................................................14-11
Table 15-1 Categories of the fiber jumpers that the OptiX OSN equipment uses............................................. 15-2
Table 15-2 Types of fiber connectors.................................................................................................................15-3
Table 15-3 Pin assignments of the subrack power cable....................................................................................15-9
Table 15-4 Pin assignments of the COA power cable......................................................................................15-10
Table 15-5 Pin assignments of the cabinet indicator cable...............................................................................15-12
Table 15-6 Pin assignments of the indicator cascading cable between subracks or the alarm cascading cable between
the OptiX OSN equipment................................................................................................................................15-13

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Table 15-7 Pin assignments of the alarm cascading cable between the OptiX OSN equipment and the other Huawei
transmission equipment.....................................................................................................................................15-15
Table 15-8 Pin assignments of the alarm input/output cable............................................................................15-17
Table 15-9 Pin assignments of the OAM serial port cable...............................................................................15-19
Table 15-10 Pin assignments of the serial 14/F1/F&f serial port cable.........................................................15-20
Table 15-11 Pin assignments of the RS-232/RS-422 serial port cable.............................................................15-22
Table 15-12 Pin assignments of the ordinary telephone line............................................................................15-23
Table 15-13 Pin assignments of the COA cascading cable..............................................................................15-24
Table 15-14 Pin assignments of the straight through cable..............................................................................15-25
Table 15-15 Pin assignments of the crossover cable........................................................................................15-26
Table 15-16 Pin assignments of the 75-ohm 8xE1 cable.................................................................................15-28
Table 15-17 Specifications of the 75-ohm E1 cable with the external braid shield layer................................15-29
Table 15-18 Specifications of the 75-ohm E1 cable without the external braid shield layer...........................15-30
Table 15-19 Pin assignments of the 120-ohm 8xE1 cable...............................................................................15-31
Table 15-20 Pin assignments of the 120-ohm 21xE1 cable.............................................................................15-33
Table 15-21 Pin assignments of the DB28 connector of the DM12.................................................................15-37
Table 15-22 Pin assignments of the V.35 DCE cable......................................................................................15-39
Table 15-23 Pin assignments of the V.35 DTE cable.......................................................................................15-41
Table 15-24 Pin assignments of the V.24 DCE cable......................................................................................15-43
Table 15-25 Technical specifications of the V.24 DCE cable..........................................................................15-43
Table 15-26 Pin assignments of the V.24 DTE cable.......................................................................................15-44
Table 15-27 Technical specifications of the V.24 DTE cable..........................................................................15-45
Table 15-28 Pin assignments of the X.21 DCE cable......................................................................................15-45
Table 15-29 Technical specifications of the X.21 DCE cable..........................................................................15-46
Table 15-30 Pin assignments of the X.21 DTE cable.......................................................................................15-47
Table 15-31 Technical specifications of the X.12 DTE cable..........................................................................15-48
Table 15-32 Pin assignments of the RS-449 DCE cable..................................................................................15-48
Table 15-33 Technical specifications of the RS-449 DCE cable.....................................................................15-49
Table 15-34 Pin assignments of the RS-449 DTE cable..................................................................................15-50
Table 15-35 Technical specifications of the RS-449 DTE cable.....................................................................15-51
Table 15-36 Pin assignments of the RS-530 DCE cable..................................................................................15-52
Table 15-37 Technical specifications of the RS-530 DCE cable.....................................................................15-53
Table 15-38 Pin assignments of the RS-530 DTE cable..................................................................................15-54
Table 15-39 Technical specifications of the RS-530 DTE cable.....................................................................15-55
Table 15-40 Pin assignments of the 120-ohm clock cable...............................................................................15-57
Table 15-41 Pin assignments of the two-channel 75-ohm-to-120-ohm clock transit cable.............................15-58
Table B-1 Labels on the equipment.....................................................................................................................B-2
Table B-2 Part numbers and descriptions of the optical modules used on the OptiX OSN equipment..............B-6
Table C-1 Power consumption and weight of each board...................................................................................C-1
Table D-1 Information on whether a board of a specific version is supported by the OptiX OSN products
..............................................................................................................................................................................D-1
Table E-1 Loopback capability of the SDH boards.............................................................................................E-1

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Tables

Table E-2 Information on whether each SDH board of the OptiX OSN equipment supports the insertion of the
AU_AIS when the board is looped back..............................................................................................................E-4
Table E-3 Loopback capability of the PDH boards.............................................................................................E-6
Table E-4 Loopback capability of the data boards of the OptiX OSN equipment..............................................E-7
Table E-5 Loopback capability of the ATM/IMA boards of the OptiX OSN equipment...................................E-8
Table F-1 Relation between the service type and the value of the C2 byte.........................................................F-2
Table F-2 Relation between the service type and the value of the C2 byte.........................................................F-3
Table F-3 Relation between the service type and the value of the V5 byte.........................................................F-4
Table F-4 Relation between the service type and the value of the V5 byte.........................................................F-6
Table F-5 Parameters that need to be set for the cross-connect and timing units..............................................F-21

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Hardware Description

About This Document

About This Document


Purpose
This document describes the structure, composition, boards, and cables of the OptiX OSN
equipment.
The readers can have a comprehensive understanding of the hardware of the OptiX OSN
equipment through this document.

Related Versions
The following table lists the product versions related to this document.
Product Name

Version

OptiX OSN 3500 II

V100R009

Intended Audience
This document is intended for:
l

Network design and planning engineers

Hardware installers

Organization
This document is organized as follows.

Issue 02 (2009-07-30)

Chapter

Description

1 Equipment Structure

Introduces the structure of the equipment.

2 Cabinet

Describes the dimensions, appearances, technical


specifications, and configurations of the cabinets that can
house the equipment.
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Hardware Description

About This Document

Chapter

Description

3 Subrack

Describes the structure of the subrack.

4 Board List and


Classification

Describes the appearance and classification of the boards.

5 SDH Boards

Describes the versions, functions, working principles, front


panels, interfaces, valid slots, and technical specifications
of the SDH boards.

6 PDH Boards

Describes the versions, functions, working principles, front


panels, interfaces, valid slots, and technical specifications
of the PDH boards.

7 Data Boards

Describes the versions, functions, working principles, front


panels, interfaces, valid slots, and technical specifications
of the data boards.

8 Interface Boards and


Switching and Bridging
Boards

Describes the versions, functions, working principles, front


panels, interfaces, valid slots, and technical specifications
of the interface boards and switching and bridging boards.

9 Cross-Connect Boards and


System Control Boards

Describes the functions, working principles, front panels,


jumpers, interfaces, and technical specifications of the
cross-connect boards and SCC boards.

10 Auxiliary Boards

Describes the versions, functions, working principles, front


panels, interfaces, valid slots, and technical specifications
of the auxiliary boards.

11 WDM Boards

Describes the versions, functions, working principles, front


panels, interfaces, valid slots, and technical specifications
of the WDM boards.

12 Microwave Boards

Describes the versions, functions, working principles, front


panels, interfaces, valid slots, and technical specifications
of the microwave boards.

13 Optical Amplifier Boards


and Dispersion
Compensation Boards

Describes the versions, functions, working principles, front


panels, interfaces, valid slots, and technical specifications
of the optical amplifier boards and dispersion compensation
boards.

14 Power Boards

Describes the versions, functions, working principles, front


panels, interfaces, valid slots, and technical specifications
of the power boards.

15 Cables

Describes the structure, appearance, pin assignments, and


technical specifications of the external cables and internal
cables that the equipment uses.

A Indicators

Describes the indicators on the equipment and the indicators


on the boards of the equipment.

B Labels

Describes the safety labels, optical module labels, and


engineering labels on the equipment.
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About This Document

Chapter

Description

C Power Consumption and


Weight of Each Board

Provides the power and weight of each board of the


equipment.

D Compatibility of Board
Versions with the Products

Provides information on whether a board of a specific


version is supported by the equipment.

E Loopback Capability of the


Boards

Provides the loopback capability of the boards.

F Parameter Settings

Describes the parameters that can be set by using the T2000.

G Glossary

Lists the terms that are used in this document.

H Acronyms and
Abbreviations

Lists the acronyms and abbreviations that are used in this


document.

Conventions
Symbol Conventions
The symbols that may be found in this document are defined as follows.
Symbol

Description

DANGER

WARNING

CAUTION

Indicates a hazard with a high level of risk, which if not


avoided, will result in death or serious injury.
Indicates a hazard with a medium or low level of risk, which
if not avoided, could result in minor or moderate injury.
Indicates a potentially hazardous situation, which if not
avoided, could result in equipment damage, data loss,
performance degradation, or unexpected results.

TIP

Indicates a tip that may help you solve a problem or save


time.

NOTE

Provides additional information to emphasize or supplement


important points of the main text.

General Conventions
The general conventions that may be found in this document are defined as follows.

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Hardware Description

About This Document

Convention

Description

Times New Roman

Normal paragraphs are in Times New Roman.

Boldface

Names of files, directories, folders, and users are in


boldface. For example, log in as user root.

Italic

Book titles are in italics.

Courier New

Examples of information displayed on the screen are in


Courier New.

Command Conventions
The command conventions that may be found in this document are defined as follows.
Convention

Description

Boldface

The keywords of a command line are in boldface.

Italic

Command arguments are in italics.

[]

Items (keywords or arguments) in brackets [ ] are optional.

{ x | y | ... }

Optional items are grouped in braces and separated by


vertical bars. One item is selected.

[ x | y | ... ]

Optional items are grouped in brackets and separated by


vertical bars. One item is selected or no item is selected.

{ x | y | ... }*

Optional items are grouped in braces and separated by


vertical bars. A minimum of one item or a maximum of all
items can be selected.

[ x | y | ... ]*

Optional items are grouped in brackets and separated by


vertical bars. Several items or no item can be selected.

GUI Conventions
The GUI conventions that may be found in this document are defined as follows.

Convention

Description

Boldface

Buttons, menus, parameters, tabs, window, and dialog titles


are in boldface. For example, click OK.

>

Multi-level menus are in boldface and separated by the ">"


signs. For example, choose File > Create > Folder.

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About This Document

Keyboard Operations
The keyboard operations that may be found in this document are defined as follows.
Format

Description

Key

Press the key. For example, press Enter and press Tab.

Key 1+Key 2

Press the keys concurrently. For example, pressing Ctrl+Alt


+A means the three keys should be pressed concurrently.

Key 1, Key 2

Press the keys in turn. For example, pressing Alt, A means


the two keys should be pressed in turn.

Mouse Operations
The mouse operations that may be found in this document are defined as follows.
Action

Description

Click

Select and release the primary mouse button without moving


the pointer.

Double-click

Press the primary mouse button twice continuously and


quickly without moving the pointer.

Drag

Press and hold the primary mouse button and move the
pointer to a certain position.

Update History
Updates between document issues are cumulative. Therefore, the latest document issue contains
all updates made in previous issues.

Updates in Issue 02 (2009-07-30) Based on Product Version V100R009


This document of the V100R009 version is of the second release. Compared with Issue 01, this
version has the following new or optimized content:
The "Working Principle and Signal Flow" part of the SDH boards, PDH boards, data boards,
and EOW board are updated.
The "Functions and Features" part of the FAN, FANB, and FANA are updated.

Updates in Issue 01 (2009-07-15) Based on Product Version V100R009


This document of the V100R009 version is of the first release.

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Hardware Description

1 Equipment Structure

Equipment Structure

The OptiX OSN 3500 II equipment consists of the cabinet, side panels, DC power distribution
unit (PDU), subracks, boards, and cables.
NOTE

The OptiX OSN 7500 equipment and the OptiX OSN 9500 equipment are installed in the same cabinet.
The upper subrack houses the OptiX OSN 7500 equipment and the lower subrack houses the OptiX OSN
9500 equipment.

Figure 1-1 shows the appearance of the OptiX OSN 3500 II that is installed in the ETSI cabinet.

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OptiX OSN 3500 II Intelligent Optical Transmission System


Hardware Description

1 Equipment Structure

Figure 1-1 Appearance of the OptiX OSN 3500 II that is installed in the ETSI cabinet

6
1
2

5
7

H
D

1. DC PDU

2. Side panel

3. Upper subrack

4. Lower subrack

5. Fiber management tray

6. Enclosure frame

Figure 1-2 shows the appearance of the OptiX OSN 3500 II subrack that is installed with boards.

1-2

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1 Equipment Structure

Figure 1-2 Appearance of the OptiX OSN 3500 II subrack that is installed with boards

1. Interface board area

Issue 02 (2009-07-30)

2. Fan area 3. Processing board area

4. Cable routing area

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5. Mounting ear

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OptiX OSN 3500 II Intelligent Optical Transmission System


Hardware Description

2 Cabinet

Cabinet

About This Chapter


The OptiX OSN subracks are installed in the cabinets.
2.1 Types of Cabinets
The OptiX OSN 3500 II subrack can be installed in the 300 mm ETSI (N63E) cabinet.
2.2 Configuration of the Cabinet
An ETSI cabinet has indicators and a DC PDU at the top.
2.3 Technical Specifications
The technical specifications of the cabinet include the dimensions, weight, and number of
permitted subracks.

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OptiX OSN 3500 II Intelligent Optical Transmission System


Hardware Description

2 Cabinet

2.1 Types of Cabinets


The OptiX OSN 3500 II subrack can be installed in the 300 mm ETSI (N63E) cabinet.
NOTE

The cabinets described in this topic are provided by Huawei.

The equipment can be installed in the N63E cabinet. Figure 2-1 shows the appearance of the
N63E cabinet.
Figure 2-1 Appearance of the N63E cabinet

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Hardware Description

2 Cabinet

2.2 Configuration of the Cabinet


An ETSI cabinet has indicators and a DC PDU at the top.
Figure 2-2 shows the positions of the indicators and the DC PDU.
Figure 2-2 ETSI cabinet
1
2
PowerCritical MajorMinor

Power distribution unit

H
W

1. Indicators

2. DC PDU

2.2.1 Indicators
The ETSI cabinet has one power indicator and three alarm severity indicators.
2.2.2 DC PDU
The DC PDU is at the top of the cabinet and is used to supply power to the equipment.
2.2.3 Other Configurations
External case-shaped devices can be installed in a cabinet as required.

2.2.1 Indicators
The ETSI cabinet has one power indicator and three alarm severity indicators.
Table 2-1 provides the meanings of the status of the indicators.

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Hardware Description

2 Cabinet

Table 2-1 Meanings of the status of the indicators


Indicator

Status

Meaning

Power indicator Power (green)

On

Power is supplied to the


equipment.

Off

Power is not supplied to


the equipment.

On

A critical alarm occurs


on the equipment.

Off

No critical alarm
occurs on the
equipment.

On

A major alarm occurs


on the equipment.

Off

No major alarm occurs


on the equipment.

On

A minor alarm occurs


on the equipment.

Off

No minor alarm occurs


on the equipment.

Critical alarm indicator Critical (red)

Major alarm indicator Major (orange)

Minor alarm indicator Minor (yellow)

CAUTION
The status of the indicators is controlled by the AUX on the subrack. The indicators work only
after the cables of the indicators are correctly connected and the subrack is powered on.

2.2.2 DC PDU
The DC PDU is at the top of the cabinet and is used to supply power to the equipment.
Figure 2-3 shows the appearance of the PDU.

2-4

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2 Cabinet

Figure 2-3 Appearance of the DC PDU


INPUT A
2
1

INPUT B
4
3

10

7
OUTPUT A

OUTPUT B

1: Input power grounding cable on side A (RTN(+))

2: Input power cable on side A (NEG())

3: Input power grounding cable on side B (RTN(+))

4: Input power cable on side B (NEG())

5: Output 48 V power cable on side A (A1(-) and A2 6: Output 48 V power cable on side B (B1(-) and B2
(-))
(-))
7: Output 48 V power grounding cable on side A (A1 8: Output power grounding cable on side B (B1(+) and
(+) and A2(+))
B2(+))
9: PGND

10: Power switch

The DC PDU consists of side A and side B, which function as a mutual backup for each other.
The DC PDU provides two inputs and four outputs, and can supply power to a maximum of two
OptiX OSN 3500 II subracks.
NOTE

When a subrack accesses two power inputs, each power input carries a 10 A current. The nominal current
of a single subrack, however, is set to 20 A according to the power distribution principle of the equipment
room. Hence, when one power input fails, the subrack still has normal power supply.

2.2.3 Other Configurations


External case-shaped devices can be installed in a cabinet as required.
l

Uninterruptible power module (UPM)

Roman pump amplifiers RPC01 and RPC02

Dispersion compensation module (DCM)

Case-shaped optical amplifier (COA)

Fiber management tray, which is used to manage the excess fibers inside the cabinet.

2.3 Technical Specifications


The technical specifications of the cabinet include the dimensions, weight, and number of
permitted subracks.
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Hardware Description

2 Cabinet

Table 2-2 Technical specifications of the ETSI cabinet

2-6

Dimensions (mm)

Weight (kg)

Number of Permitted
Subracks

600 (W) x 300 (D) x 2600 (H) (N63E)

51.6

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3 Subrack

Subrack

About This Chapter


This topic describes the structure, capacity, slot layout, and technical specifications of the
subrack.
3.1 Slot Access Capacity
When the OptiX OSN 3500 II uses the Q5CXL, Q6CXL, and Q5CXS series boards, the access
capacity of each slot is different from each other.
3.2 Structure
The OptiX OSN 3500 II subrack has a two-layer structure. The subrack consists of the processing
board area, interface board area, fan area, and cable routing area.
3.3 Slot Allocation
The OptiX OSN 3500 II subrack consists of the upper layer and the lower layer. The upper layer
is the slot area in which 20 slots are available for interface boards. The lower layer is the slot
area in which 19 slots are available for processing boards.
3.4 Technical Specifications
The technical specifications of the subrack include the dimensions, weight, and maximum power
consumption.

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OptiX OSN 3500 II Intelligent Optical Transmission System


Hardware Description

3 Subrack

3.1 Slot Access Capacity


When the OptiX OSN 3500 II uses the Q5CXL, Q6CXL, and Q5CXS series boards, the access
capacity of each slot is different from each other.
Figure 3-1 Access capacity of each slot when using the Q5CXL series boards

2.5Gbit/s

2.5Gbit/s
5Gbit/s

S
L
O
T
1
1

S
L
O
T
1
2

S
L
O
T
1
3

S
L
O
T
1
4

S
L
O
T
1
5

S
S L
O
L T
O 43
T
1
6
S
L
O
T
42
EOW

2.5Gbit/s

S
L
O
T
1
0

AUX

2.5Gbit/s

S
L
O
T
9

2.5Gbit/s

S S
L L
O O
T T
7 8

2.5Gbit/s

S
L
O
T
6

2.5Gbit/s
2.5Gbit/s

S
L
O
T
5

2.5Gbit/s

S
L
O
T
4

46FAN

2.5Gbit/s CXL
2.5Gbit/s CXL

S
L
O
T
3

2.5Gbit/s

PIU

S
L
O
T
41

2.5Gbit/s

PIU

S
L S
O L
T
O
1
T
2

45FAN

2.5Gbit/s

44FAN

Cable routing

Figure 3-2 Access capacity of each slot when using the Q6CXL series boards

S
L
O
T
9

S
L
O
T
1
0

S S
L L
O O
T T
1 1
1 2

S
L
O
T
1
3

S
L
O
T
1
4

S
L
O
T
1
5

5Gbit/s

10Gbit/s

2.5Gbit/s CXL

2.5Gbit/s CXL

10Gbit/s

5Gbit/s

5Gbit/s

5Gbit/s

S
S L
O
L T
O 43
T
1
6
S
L
O
T
42

EOW

S S
L L
O O
T T
7 8

AUX

S
L
O
T
6

5Gbit/s

S
L
O
T
5

10Gbit/s

S
L
O
T
4

10Gbit/s

S
L
O
T
3

5Gbit/s

46FAN

5Gbit/s

PIU

S
L
O
T
41

5Gbit/s

PIU

S
L S
O L
T
O
1
T
2

45FAN

5Gbit/s

44FAN

Cable routing

3-2

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3 Subrack

Figure 3-3 Access capacity of each slot when using the Q5CXS series boards

S
L
O
T
1
4

S
L
O
T
1
5

S
S L
O
L T
O 43
T
1
6
S
L
O
T
42
EOW

S
L
O
T
1
3

AUX

2.5Gbit/s

S
L
O
T
1
2

2.5Gbit/s

2.5Gbit/s

S
L
O
T
1
1

2.5Gbit/s

S S
L L
O O
T T
7 8

5Gbit/s
2.5Gbit/s

S
L
O
T
6

46FAN

5Gbit/s

S
L
O
T
5

2.5Gbit/s

S
L
O
T
1
0
CXS

S
L
O
T
4

2.5Gbit/s

S
L
O
T
9

5Gbit/s
CXS

S
L
O
T
3

2.5Gbit/s

PIU

S
L
O
T
41

2.5Gbit/s

PIU

S
L S
O L
T
O
1
T
2

45FAN

2.5Gbit/s

44FAN

Cable routing

3.2 Structure
The OptiX OSN 3500 II subrack has a two-layer structure. The subrack consists of the processing
board area, interface board area, fan area, and cable routing area.
Figure 3-4 shows the structure of the OptiX OSN 3500 II subrack.

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OptiX OSN 3500 II Intelligent Optical Transmission System


Hardware Description

3 Subrack

Figure 3-4 Structure of the OptiX OSN 3500 II subrack

2
5
3

1. Interface board area

2. Fan area 3. Processing board area

4. Cable routing area

5. Mounting ear

The functions of the areas are as follows:


l

Processing board area: These areas house the processing boards of the OptiX OSN 3500
II.

Interface board area: This area houses the interface boards of the OptiX OSN 3500 II.

Fan area: This area houses three fan modules, which dissipate heat generated by the
equipment.

Cable routing area: This area houses the fiber jumpers in the subrack.
NOTE

The interface board is also called the access board or transit board. The interface board provides physical
interfaces for optical signals and electrical signals, and transmits the optical signals or electrical signals to
the corresponding processing board.

3.3 Slot Allocation


The OptiX OSN 3500 II subrack consists of the upper layer and the lower layer. The upper layer
is the slot area in which 20 slots are available for interface boards. The lower layer is the slot
area in which 19 slots are available for processing boards.
Figure 3-5 shows the slot layout of the OptiX OSN 3500 II subrack.

3-4

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3 Subrack

Figure 3-5 Slot layout of the OptiX OSN 3500 II subrack


S

S
S

LL

O
O

TT

22

77

FAN

FAN
SLOT

44

SLOT

FAN
45

SLOT

46

4
3

E
O
W
S

4
1

C
X
L

P
I

C
X
L

4
2
A
U
X

Fiber Routing

Slot Area for Interface Boards


Slots for the interface boards: slots 21-40

Slot Area for Processing Boards


Slots for the processing boards: slots 2-8 and 11-16

Other Slots
l

Slots for integrated boards of the line, SCC, cross-connect and timing units: slots 9-10

Slots for the SEI auxiliary interface board: slot 32

Slots for the PIU boards: slots 1 and 41

Slot for the auxiliary interface board: slots 42 and 43

Slots for the fan boards: slots 44-46

Mapping Relation Between Slots for Interface Boards and Slots for Processing
Boards
Table 3-1 lists the mapping relation between slots for the interface boards and slots for the
processing boards.
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3 Subrack

Table 3-1 Mapping relation between slots for the interface boards and slots for the processing
boards
Slots for
Processing
Boards

Slots for Interface


Boards

Slots for
Processing
Boards

Slots for Interface


Boards

Slot 3

Slots 21 and 22

Slot 12

Slots 31 and 32

Slot 4

Slots 23 and 24

Slot 13

Slots 33 and 34

Slot 5

Slots 25 and 26

Slot 14

Slots 35 and 36

Slot 6

Slots 27 and 28

Slot 15

Slots 37 and 38

Slot 7

Slots 29 and 30

Slot 16

Slots 39 and 40

Paired Slots
If the overhead bytes pass through the backplane bus between two slots, the two slots are paired
slots. When an NE is configured with an orderwire phone, realizes the service protection in DPS
mode, or is configured with the ring MSP at the STM-16/STM-64 level, the two boards that
form a ring must be inserted in the paired slots. Table 3-2 lists the paired slots.
Table 3-2 Paired slots
Slot

Paired Slot

Slot 3

Slot 16

Slot 4

Slot 15

Slot 5

Slot 14

Slot 6

Slot 13

Slot 7

Slot 12

Slot 8

Slot 11

slot 9

slot 10

3.4 Technical Specifications


The technical specifications of the subrack include the dimensions, weight, and maximum power
consumption.
Table 3-3 lists the dimensions and weight of the OptiX OSN 3500 II subrack.

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3 Subrack

Table 3-3 Dimensions and weight of the OptiX OSN 3500 II subrack
Dimensions (mm)

Weight (kg)

436 (W) x 295 (D) x 722 (H)

14 (net weight of the subrack that is not


installed with boards and fans)

Table 3-4 lists the maximum power consumption of the OptiX OSN 3500 II subrack.
Table 3-4 Maximum power consumption of the OptiX OSN 3500 II subrack

Issue 02 (2009-07-30)

Maximum Configuration

Typical Configuration

Maximum Power
Consumption

Fuse
Capacity

Typical
Power
Consumpt
ion

Remarks

1100 W

32 A

275 W

The typical configuration is as


follows:
l

Two Q5CXL (L-16.2, LC) boards

One Q1AUX board

Two Q2PIU boards

Three N3SL16 boards

Two N1EMS2 boards

Two N2PQ1 boards

Four N1D75S boards

One R1EOW board

One N1SEI board

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Board List and Classification

About This Chapter


This topic describes the appearances, dimensions, bar codes, and classification of the boards
used on the OptiX OSN systems.
4.1 Appearances and Dimensions of the Boards
Different boards have different appearances and dimensions.
4.2 Bar Codes of the Boards
The bar code on the front panel of a board indicates the version, name, and feature code of the
board.
4.3 Classification of the Boards
The boards are classified into SDH boards, PDH boards, data boards, WDM boards, and auxiliary
boards according to the functions of the boards.

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4 Board List and Classification

4.1 Appearances and Dimensions of the Boards


Different boards have different appearances and dimensions.
Table 4-1 provides information about the appearances and dimensions of the boards used on
the OptiX OSN 3500 II.
Table 4-1 Appearances and dimensions of the boards used on the OptiX OSN 3500 II
Parameter

Appearance and Dimensions

Board appearance

Board classification

Optical interface board


(for example, SL16)

Service processing board


(for example, PQ1)

Service interface
board (for example,
D75S)

Height (mm)

262.05

262.05

262.05

Depth (mm)

220

220

110

Width (mm)

25.4

25.4

22

Board classification

SCC unit, cross-connect


unit, and line unit
integrated board (for
example, Q5CXL)

System auxiliary
interface board (AUX)

Power interface unit


(PIU)

Height (mm)

262.05

262.05

110

Depth (mm)

220

111.8

220

Board appearance

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Parameter

Appearance and Dimensions

Width (mm)

25.4

25.4

Note: The figure in the right cell shows the three dimensions. "H" and "W"
indicate the height and width of the front panel respectively and "D" indicates
the depth of the printed circuit board (PCB).

4 Board List and Classification

37
H
D

CAUTION
Wear an antistatic wrist strap when holding a board. To prevent the static discharge from
damaging the board, ensure that the antistatic wrist strap is grounded properly.

DANGER
Do not look directly at the optical interface board or optical interface. The laser beams inside
the fiber can damage your eyes.

CAUTION
l

A level optical module cannot be directly connected to an optical attenuator. If an optical


attenuator is required, use the attenuator on the optical distribution frame (ODF) side.

If an optical attenuator is required, insert the attenuator in the IN interface instead of the OUT
interface.

Add an attenuator when performing a loopback to prevent the optical module from being
damaged.

4.2 Bar Codes of the Boards


The bar code on the front panel of a board indicates the version, name, and feature code of the
board.
Two types of bar codes are used for the boards of the OptiX OSN 3500 II, which are as follows:
l

16-digit manufacturing code + board version + board name + board feature code

20-digit manufacturing code + board version + board name + board feature code

The bar code is affixed to the front panel of a board. Figure 4-1 shows the bar code with a 16digit manufacturing code.

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Figure 4-1 Bar code of a board

Bar code

0364401055000015 -SSN3SL16A01

Last six digits of the BOM code


Internal code
Board version
Board name
5 Board feature code

NOTE

For details on the feature code of a board, see the topic that describes the feature code of the board.

4.3 Classification of the Boards


The boards are classified into SDH boards, PDH boards, data boards, WDM boards, and auxiliary
boards according to the functions of the boards.
NOTE

For details on the board version replacement relation between boards, refer to the table of board version
replacement relations in the Parts Replacement.

SDH Boards
The OptiX OSN 3500 II supports the SDH boards that operate at the STM-64, STM-16, STM-4,
and STM-1 rates.
Table 4-2 lists the SDH boards that the OptiX OSN 3500 II supports.

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4 Board List and Classification

Table 4-2 SDH boards that the OptiX OSN 3500 II supports
Board

Description

Board

Description

N1SL64,
N4SL64

1xSTM-64 optical interface


board

N1SLD4A

2xSTM-4 optical interface


board

N1SF64,
N1SF64A,
N4SF64

1xSTM-64 optical interface


board (with the out-band
forward error correction
(FEC) function)

N1SL4 and
N2SL4

1xSTM-4 optical interface


board

N1SLQ16

4xSTM-16 optical interface


board

N1SL4A

1xSTM-4 optical interface


board

N2SLQ16,
N4SLQ16

4xSTM-16 optical interface


board

N3SLQ41

4xSTM-4/STM-1 optical
interface board

N1SLD16

2xSTM-16 optical interface


board

N1SLH1B

16xSTM-1 optical interface


board

N1SL16A,
N2SL16A,
and
N3SL16A

1xSTM-16 optical interface


board

N1SLT1

12xSTM-1 optical interface


board

N1SL16,
N2SL16,
and N3SL16

1xSTM-16 optical interface


board

N2SLO1 and
N3SLO1

8xSTM-1 AU-3 optical


interface board

N1SF16

1xSTM-16 optical interface


board (with FEC function)

N1SLQ1,
N2SLQ1, and
N1SLQ1A

4xSTM-1 optical interface


board

N1SLQ4,
N2SLQ4,
and
N1SLQ4A

4xSTM-4 optical interface


board

N1SL1,
N2SL1, and
N1SL1A

1xSTM-1 optical interface


board

N1SLD4
and
N2SLD4

2xSTM-4 optical interface


board

N1SEP1

2xSTM-1 line processing


board when the interfaces
are available on the front
panel
8xSTM-1 line processing
board when the interfaces
are available on the
corresponding interface
board

N3SLH41

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16xSTM-1/STM-4 optical
interface board

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PDH Boards
The OptiX OSN 3500 II supports the PDH boards that operate at different rates and have different
impedances.
Table 4-3 lists the PDH boards that the OptiX OSN 3500 II supports.
Table 4-3 PDH boards that the OptiX OSN 3500 II supports
Board

Description

N1SPQ4 and N2SPQ4

4xE4/STM-1 electrical processing board (The interfaces are


available on the corresponding interface board.)

N1PD3 and N2PD3

6xE3/T3 service processing board

N1PL3 and N2PL3

3xE3/T3 service processing board

N1PL3A and N2PL3A

3xE3/T3 service processing board (The interfaces are available


on the front panel.)

N2PQ3

12xE3/T3 service processing board

N1PQ1 and N2PQ1

63xE1 service processing board

N2PO1

126xE1 service processing board

N1PQM

63xE1/T1 service processing board

N1DX1

DDN service accessing and converging board

N1DXA

DDN service converging and processing board

Data Boards
The OptiX OSN 3500 II supports the data boards that provide the transparent transmission
function, switching function, or RPR function.
Table 4-4 lists the data boards that the OptiX OSN 3500 II supports.
Table 4-4 Data boards that the OptiX OSN 3500 II supports

4-6

Board

Description

Board

Description

N1EFT8

8xFE or 16xFE transparent


transmission board

N1EMS4

4xGE and 16xFE


transparent transmission
and converging board

N1EFT8A

8xFE transparent
transmission board (The
interfaces are available on
the front panel.)

N1EMS2

2xGE and 16xFE


transparent transmission
and converging board

N1EGT2 and
N2EGT2

2xGE transparent
transmission board

N2EGR2

2xGE ring processing board

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Board

Description

Board

Description

N1EFS0,
N2EFS0,
N4EFS0, and
N5EFS0

8xFE switching and


processing board

N1EMR0
and
N2EMR0

12xFE and 1xGE ring


processing board

N1EFS0A

16xFE switching and


processing board

N1ADL4

1xSTM-4 ATM service


processing board

N1EFS4,
N2EFS4, and
N3EFS4

4xFE switching and


processing board

N1ADQ1

4xSTM-1 ATM service


processing board

N1EAS2

2-port 10xGE Layer 2


switching and processing
board

N1IDL4,
N1IDL4A

1xSTM-4 ATM service


processing board

N1EGS4,
N3EGS4, and
N4EGS4

4xGE switching and


processing board

N1IDQ1,
N1IDQ1A

4xSTM-1 ATM service


processing board

N2EGS2,
N3EGS2,
N1EGS2A

2xGE switching and


processing board

N1EFP0

8-port PDH-based Ethernet


switching and processing
board

Interface Boards and Switching and Bridging Boards


The OptiX OSN 3500 II supports optical interface boards, electrical interface boards, and
switching and bridging boards.
Table 4-5 lists the interface boards and switching and bridging boards that the OptiX OSN 3500
II supports.
Table 4-5 Interface boards and switching and bridging boards that the OptiX OSN 3500 II
supports

Issue 02 (2009-07-30)

Board

Description

Board

Description

N1EU08

8xSTM-1 electrical interface


board

N1D12S

32xE1/T1 switching access


board (120 ohms)

N1OU08

8xSTM-1 optical interface


board (LC)

N1D12B

32xE1/T1 access board (120


ohms)

N2OU08

8xSTM-1 optical interface


board (SC)

N1EFF8
and
N1EFF8A

8x100M Ethernet optical


interface board

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Board

Description

Board

Description

N1D75S

32xE1 switching access board


(75 ohms)

N1ETF8
and
N1ETF8A

8x100M Ethernet twisted


pair interface board

N1MU04

4xE4/STM-1 electrical
interface board

N1ETS8

8x10/100M Ethernet twisted


pair interface switching
board

N1D34S

6xE3/T3 switching access board

N1DM12

DDN service interface board

N1C34S

3xE3/T3 switching access board

N1TSB4

4-channel electrical
interface protection
switching board

N1EU04

4xSTM-1 electrical interface


board

N1TSB8

8-channel electrical
interface protection
switching board

Cross-Connect Boards and SCC Boards


The OptiX OSN 3500 II supports multiple system control boards and cross-connect boards that
have different cross-connect capacities.
Table 4-6 lists the cross-connect boards and system control boards that the OptiX OSN 3500 II
supports.
Table 4-6 Cross-connect boards and system control boards that the OptiX OSN 3500 II supports
Board

Description

Q5CXLLN

1xSTM-16/STM-4/STM-1 SCC unit, cross-connect unit, timing


unit, and line unit integrated board

Q5CXLQ41

4xSTM-4/STM-1 SCC unit, cross-connect unit, timing unit, and


line unit integrated board

Q6CXLLN

1xSTM-16/STM-4/STM-1 SCC unit, cross-connect unit, timing


unit and line unit integrated board

Q6CXLQ41

4xSTM-4/STM-1 SCC unit, cross-connect unit, timing unit, and


line unit integrated board

Q5CXS

SCC unit, cross-connect unit, and timing unit integrated board

Auxiliary Boards
The OptiX OSN 3500 II supports auxiliary boards such as the system auxiliary interface board
and fan board.
Table 4-7 lists the auxiliary boards that the OptiX OSN 3500 II supports.
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Table 4-7 Auxiliary boards that the OptiX OSN 3500 II supports
Board

Description

Board

Description

R1EOW

Orderwire processing
board

N1SEI

Signal extended
interface board

N1FAN and
N1FANB

Fan board

Q1AUX

System auxiliary
interface board

WDM Boards
The OptiX OSN 3500 II supports WDM boards such as the optical add/drop multiplexing board
and optical amplifier board.
Table 4-8 lists the WDM boards that the OptiX OSN 3500 II supports.
Table 4-8 WDM boards that the OptiX OSN 3500 II supports
Board

Description

Board

Description

TN11CMR2

2-channel optical add/


drop multiplexing board

N1MR2C

2-channel optical add/drop


multiplexing board

TN11CMR4

4-channel optical add/


drop multiplexing board

N1LWX

Arbitrary bit rate


wavelength conversion
board

TN11MR2

2-channel optical add/


drop multiplexing board

TN11OBU1

Optical booster amplifier


board

TN11MR4

4-channel optical add/


drop multiplexing board

N1FIB

Filter isolating board

N1MR2A

2-channel optical add/


drop multiplexing board

Microwave Boards
The OptiX OSN 3500 II supports microwave boards such as the microwave IF board and
microwave power board.
Table 4-9 lists the microwave boards that the OptiX OSN 3500 II supports.
Table 4-9 Microwave boards that the OptiX OSN 3500 II supports

Issue 02 (2009-07-30)

Board

Description

N1IFSD1

Dual-port IF board

N1RPWR

6-channel ODU power board

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Optical Amplifier Boards and Dispersion Compensation Boards


The OptiX OSN 3500 II supports multiple optical amplifier boards and dispersion compensation
boards.
Table 4-10 lists the optical amplifier boards and dispersion compensation boards that the OptiX
OSN 3500 II supports.
Table 4-10 Optical amplifier boards and dispersion compensation boards that the OptiX OSN
3500 II supports
Board

Description

Board

Description

N1BPA and
N2BPA

Optical booster and


pre-amplifier board

N1RPC01

Forward Raman
driving board
(external)

N1COA,
61COA, and
62COA

Case-shaped optical
amplifier

N1RPC02

Backward Raman
driving board
(external)

N1BA2

Optical booster
amplifier board

N1DCU and N2DCU

Dispersion
compensation board

Power Boards
The OptiX OSN 3500 II supports power boards such as the UPM and power interface board.
Table 4-11 lists the power boards that the OptiX OSN 3500 II supports.
Table 4-11 Power boards that the OptiX OSN 3500 II supports

4-10

Board

Description

UPM

Uninterruptible power module

Q2PIU

Power interface board

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5 SDH Boards

SDH Boards

About This Chapter


This topic describes the SDH boards that operate at the STM-64, STM-16, STM-4, and STM-1
rates.
5.1 SL1
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the SL1 (1xSTM-1 optical interface board).
5.2 SL1A
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the SL1A (1xSTM-1 optical interface board).
5.3 SLQ1
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the SLQ1 (4xSTM-1 optical interface board).
5.4 SLQ1A
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the SLQ1A (4xSTM-1 optical interface board).
5.5 SLO1
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the SLO1 (8xSTM-1 optical interface board).
5.6 SLT1
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the SLT1 (12xSTM-1 optical interface board).
5.7 SLH1B
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the SLH1B (16xSTM-1 signal processing board).
5.8 SEP1
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the SEP1 (2xSTM-1 line processing board).
5.9 SL4
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This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the SL4 (1xSTM-4 optical interface board).
5.10 SL4A
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the SL4A (1xSTM-4 optical interface board).
5.11 SLD4
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the SLD4 (2xSTM-4 optical interface board).
5.12 SLD4A
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the SLD4A (2xSTM-4 optical interface board).
5.13 SLQ4
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the SLQ4 (4xSTM-4 optical interface board).
5.14 SLQ4A
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the SLQ4A (4xSTM-4 optical interface board).
5.15 SL16
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the SL16 (1xSTM-16 optical interface board).
5.16 SL16A
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the SL16A (1xSTM-16 optical interface board).
5.17 SLD16
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the SLD16 (2xSTM-16 optical interface board).
5.18 SLQ16
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the SLQ16 (4xSTM-16 optical interface board).
5.19 SF16
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the SF16 (1xSTM-16 optical interface board with the out-band FEC
function).
5.20 SL64
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the SL64 (1xSTM-64 optical interface board).
5.21 SF64
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the SF64 (1xSTM-64 optical interface board with the FEC function).
5.22 SF64A
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the SF64A (1xSTM-64 optical interface board with the FEC function).
5.23 SLQ41

5-2

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5 SDH Boards

This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the SLQ41 (4xSTM-4/STM-1 optical interface board).

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5 SDH Boards

5.1 SL1
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the SL1 (1xSTM-1 optical interface board).
5.1.1 Version Description
The SL1 is available in two functional versions, namely, N1 and N2. The difference between
the two versions is with regard to whether they support the tandem connection monitoring (TCM)
function and AU-3 services. The N1SL1 is no longer manufactured.
5.1.2 Functions and Features
The SL1 transmits and receives STM-1 optical signals, performs O/E conversion for the STM-1
optical signals, extracts and inserts overhead bytes, and generates alarm signals on the line.
5.1.3 Working Principle and Signal Flow
The SL1 consists of the O/E converting module, CDR module, SDH overhead processing
module, logic and control module, DC/DC converter, and other modules.
5.1.4 Front Panel
The front panel of the SL1 has indicators, interfaces, a bar code, and a laser safety class label.
5.1.5 Valid Slots
The SL1 can be installed in slots 28 and 1116 in the subrack.
5.1.6 Feature Code
The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the SL1 indicates the type of optical interface.
5.1.7 Parameter Settings
You can set the parameters for the SL1 by using the T2000.
5.1.8 Technical Specifications
The technical specifications of the SL1 include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.

5.1.1 Version Description


The SL1 is available in two functional versions, namely, N1 and N2. The difference between
the two versions is with regard to whether they support the tandem connection monitoring (TCM)
function and AU-3 services. The N1SL1 is no longer manufactured.
Table 5-1 describes the versions of the SL1.
Table 5-1 Versions of the SL1

5-4

Item

Description

Functional
versions

The SL1 is available in two functional versions, namely, N1 and N2.

Differences

The N2SL1 supports the TCM function and AU-3 services, but the
TCM function and AU-3 services cannot be available at the same
time.

The N1SL1 does not support the TCM function or AU-3 services.

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Item

Description

Substitution

The versions cannot be substituted with each other.

5 SDH Boards

NOTE

When you configure the multiplex section protection (MSP) or sub-network connection protection (SNCP),
you cannot configure the N1SL1 as the protection board if the working board is the N2SL1 on which the
TCM function is enabled or AU-3 services are configured. Otherwise, the services are interrupted when a
switching operation is performed.

5.1.2 Functions and Features


The SL1 transmits and receives STM-1 optical signals, performs O/E conversion for the STM-1
optical signals, extracts and inserts overhead bytes, and generates alarm signals on the line.
Table 5-2 provides the functions and features of the SL1.
Table 5-2 Functions and features of the SL1
Function and
Feature

SL1

Basic functions

Transmits and receives 1xSTM-1 optical signals.

Specifications of
the optical
interface

Supports different types of standard optical interfaces, namely, the I-1,


S-1.1, L-1.1, L-1.2, and Ve-1.2.

The characteristics of the optical interfaces of the I-1, S-1.1, L-1.1, and
L-1.2 types comply with ITU-T G.957.

The characteristics of the optical interface of the Ve-1.2 type comply


with the standards defined by Huawei.

Supports the detection and query of the information about the optical
module.

Supports the usage and detection of the small form-factor pluggable


(SFP) optical module, which facilitates the maintenance of the optical
module.

Provides the automatic laser shutdown (ALS) function. The optical


interface supports the setting of the on/off state of a laser.

Service
processing

Supports the VC-12 services, VC-3 services, and VC-4 services.

The N2SL1 supports the AU-3 services.

Overhead
processing

Processes the section overheads of the STM-1 signals.

Supports the transparent transmission and termination of the path


overheads.

Supports the setting and query of the J0, J1, J2, and C2 bytes.

Supports one channel of ECC communication.

Specifications of
the optical
module

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Function and
Feature

SL1

Alarms and
performance
events

Reports various alarms and performance events, which facilitates the


management and maintenance of the equipment.

Protection
schemes

Supports the two-fiber ring MSP, four-fiber ring MSP, linear MSP, SNCP,
sub-network connection tunnel protection (SNCTP), and sub-network
connection multi-protection (SNCMP).

Maintenance
features

Supports inloops and outloops at optical interfaces.

The N1SL1 supports inloops on VC-4 paths.

Supports warm resets and cold resets. The warm reset does not affect
services.

Supports the query of the manufacturing information of the board.

Supports the in-service loading of the FPGA.

Supports the upgrade of the board software without affecting services.

The N2SL1 supports the TCM function.

Supports the press-to-collect function in fault data collection.

5.1.3 Working Principle and Signal Flow


The SL1 consists of the O/E converting module, CDR module, SDH overhead processing
module, logic and control module, DC/DC converter, and other modules.
Figure 5-1 shows the functional block diagram of the SL1.

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Figure 5-1 Functional block diagram of the SL1


155 MHz
155
Mbit/s

O/E
E/O

O/E
E/O

S
P
I

155
CDR Mbit/s
155
Mbit/s

CDR

K1 and K2 insertion/
extraction

K1 and K2
High-speed
bus

....

....

155
Mbit/s
155
Mbit/s

S
P
I

155
Mbit/s

Reference clock

155 MHz
PLL

RST
155
Mbit/s

IIC
LOS

MST

MSA

HPT

High-speed
bus
DCC

SDH overhead processing


module

Logic and control


module

Frame header
Communication

Laser shutdown
+3.3 V
DC/DC
converter

DC/DC
converter

Fuse

Crossconnect unit

Crossconnect unit
Cross-connect
unit A
Cross-connect
unit B
SCC unit

Crossconnect unit
SCC unit
-48 V/ -60 V
-48 V/ -60 V

PLL: phase-locked loop

SPI: SDH physical interface

RST: regenerator section


termination

MST: multiplex section termination MSA: multiplex section adaptation

HPT: higher order path termination IIC: inter-integrated circuit

SDH: synchronous digital hierarchy

CDR: clock and data recovery

The functional modules of the STM-1 units are described as follows:

O/E Converting Module


l

In the receive direction, the module converts the received optical signals into electrical
signals.

In the transmit direction, the module converts the electrical signals into SDH optical signals
and sends the SDH optical signals to fibers for transmission.

The SPI detects the R_LOS alarm and provides the function of shutting down the laser.

CDR Module
This module restores the data signal and the clock signal.

SDH Overhead Processing Module


This module includes the RST, MST, MSA, and HPT sub-modules. This module provides the
inloop and outloop functions.
l

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RST sub-module
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In the receive direction, the RST sub-module detects the frame alignment bytes (A1 and
A2), performs descrambling, restores the regenerator section trace byte (J0), detects a
J0 mismatch, and counts BIP-8 errored blocks.

In the transmit direction, the RST sub-module inserts the frame alignment bytes, inserts
the J0 byte, performs scrambling, and performs BIP-8 calculation and insertion.

MST sub-module

In the receive direction, the MST sub-module counts BIP-24 errored blocks, restores
the multiplex section-remote error indication (MS_REI), and detects the multiplex
section-remote defect indication (MS_RDI), multiplex section-alarm indication signal
(MS_AIS), and multiplex section-excessive errors alarm (MS-EXC).

In the transmit direction, the MST sub-module performs BIP-24 calculation and
insertion and inserts the MS_REI, MS_RDI, and MS_AIS.

The MST sub-module extracts or inserts the K1, K2, E2, D4D12, S1, B2, and M1
bytes.

MSA sub-module

In the receive direction, the MSA sub-module interprets the AU-4 pointer, detects the
LOP and AIS, and performs pointer justifications.

In the transmit direction, the MSA sub-module assembles the administration unit group
(AUG) and generates the AU-4 pointer and the AU_AIS.

HPT sub-module

Terminates the overheads.

Restores the J1 path trace message.

Restores the REI information.

Detects the HP_RDI (monitors the status of the path).

Detects the UNEQ and AIS (monitors the signal label).

Counts the VC-4 BIP-8 errored blocks.

Logic and Control Module


l

Manages and configures the other modules of the board.

Performs inter-board communication through the internal Ethernet interface.

Traces the clock signal from the active and standby cross-connect units.

Controls the laser.

Passes the orderwire and embedded control channel (ECC) bytes through an add/drop
multiplexer (ADM) that consists of two paired slots when the CXL is not online.

Selects the clock signal and frame header signal from the active and standby cross-connect
units.

Controls the indicators on the board.

DC/DC Converter
It converts the 48/60 V power supply into the DC voltages that the modules of the board
require.

5.1.4 Front Panel


The front panel of the SL1 has indicators, interfaces, a bar code, and a laser safety class label.
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Diagram of the Front Panel


Figure 5-2 shows the appearance of the front panel of the SL1.
Figure 5-2 Front panel of the SL1

SL1
STAT
ACT
PROG
SRV

CLASS 1
LASER
PRODUCT

OUT1
IN1

SL1

Indicators
The front panel of the board has the following indicators:
l

Board hardware status indicator (STAT) two colors (red and green)

Service activation status indicator (ACT) one color (green)

Board software status indicator (PROG) two colors (red and green)

Service alarm indicator (SRV) three colors (red, green, and yellow)

For the meanings of the status of the indicators, see A Indicators.


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Interfaces
The front panel of the SL1 has one optical interface. Table 5-3 describes the types and usage of
the optical interfaces of the SL1.
Table 5-3 Optical interfaces of the SL1
Interface

Type of
Interface

Usage

IN

LC

Receives optical signals.

OUT

LC

Transmits optical signals.

5.1.5 Valid Slots


The SL1 can be installed in slots 28 and 1116 in the subrack.

5.1.6 Feature Code


The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the SL1 indicates the type of optical interface.
Table 5-4 provides the relationship between the feature code of the SL1 and the type of optical
interface.
Table 5-4 Relationship between the feature code of the SL1 and the type of optical interface
Board

Feature Code

Type of Optical Interface

SSN1SL110 and
SSN2SL110

10

S-1.1

SSN1SL111 and
SSN2SL111

11

L-1.1

SSN1SL112 and
SSN2SL112

12

L-1.2

SSN1SL113 and
SSN2SL113

13

Ve-1.2

SSN1SL114 and
SSN2SL114

14

I-1

5.1.7 Parameter Settings


You can set the parameters for the SL1 by using the T2000.
You can set the following parameters for the SL1 by using the T2000:
l

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J0
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l

J1

J2

C2

5 SDH Boards

For the description of each parameter, see F Parameter Settings.

5.1.8 Technical Specifications


The technical specifications of the SL1 include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.

Parameters Specified for Optical Interfaces


Table 5-5 lists the parameters specified for the optical interfaces of the SL1.
Table 5-5 Parameters specified for the optical interfaces of the SL1
Parameter

Value

Nominal bit rate

155520 kbit/s

Line code
pattern

Non-return to zero (NRZ)

Application
code

I-1

S-1.1

L-1.1

L-1.2

Ve-1.2

Transmission
distance (km)

0 to 2

2 to 15

20 to 40

60 to 80

80 to 100

Type of fiber

Single-mode LC Single-mode LC

Single-mode
LC

Single-mode LC

Single-mode LC

Operating
wavelength
range (nm)

1260 to 1360

1261 to 1360

1263 to 1360

1480 to 1580

1480 to 1580

Launched
optical power
range (dBm)

-15 to -8

-15 to -8

-5 to 0

-5 to 0

-3 to 0

Receiver
sensitivity
(dBm)

-23

-28

-34

-34

-34

Minimum
overload (dBm)

-8

-8

-10

-10

-10

Minimum
extinction ratio
(dB)

8.2

8.2

10

10

10

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Laser Safety Class


The safety class of the laser on the board is Class 1. The maximum launched optical power of
the optical interfaces is less than 10 dBm (10 mW).

Mechanical Specifications
The mechanical specifications of the N1SL1 and N2SL1 are as follows:
l

Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)

Weight of the N1SL1 (kg): 0.6

Weight of the N2SL1 (kg): 1.0

Power Consumption
The maximum power consumption of the N1SL1 at room temperature (25C) is 17 W.
The maximum power consumption of the N2SL1 at room temperature (25C) is 14 W.

5.2 SL1A
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the SL1A (1xSTM-1 optical interface board).
5.2.1 Version Description
The SL1A is available in one functional version, namely, N1.
5.2.2 Functions and Features
The SL1A transmits and receives STM-1 optical signals, performs O/E conversion for the
STM-1 optical signals, extracts and inserts overhead bytes, and generates alarm signals on the
line.
5.2.3 Working Principle and Signal Flow
The SL1A consists of the O/E converting module, CDR module, SDH overhead processing
module, logic and control module, DC/DC converter, and other modules.
5.2.4 Front Panel
The front panel of the SL1A has indicators, interfaces, a bar code, and a laser safety class label.
5.2.5 Valid Slots
The SL1A can be installed in slots 28 and 1116 in the subrack.
5.2.6 Feature Code
The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the SL1A indicates the type of optical interface.
5.2.7 Parameter Settings
You can set the parameters for the SL1A by using the T2000.
5.2.8 Technical Specifications
The technical specifications of the SL1A include the parameters specified for optical interfaces,
laster safety class, mechanical specifications, and power consumption.

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5.2.1 Version Description


The SL1A is available in one functional version, namely, N1.

5.2.2 Functions and Features


The SL1A transmits and receives STM-1 optical signals, performs O/E conversion for the
STM-1 optical signals, extracts and inserts overhead bytes, and generates alarm signals on the
line.
Table 5-6 provides the functions and features of the SL1A.
Table 5-6 Functions and features of the SL1A
Function and
Feature

SL1A

Basic functions

Transmits and receives 1xSTM-1 optical signals.

Specifications of
the optical
interface

Supports different types of standard optical interfaces, namely, the I-1,


S-1.1, L-1.1, L-1.2, and Ve-1.2.

The characteristics of the optical interfaces of the I-1, S-1.1, L-1.1, and
L-1.2 types comply with ITU-T G.957.

The characteristics of the optical interface of the Ve-1.2 type comply


with the standards defined by Huawei.

Supports the detection and query of the information about the optical
module.

Supports the usage and detection of the SFP optical module, which
facilitates the maintenance and upgrading of the optical module.

Provides the ALS function. The optical interface supports the setting
of the on/off state of a laser.

Specifications of
the optical
module

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Service
processing

Supports the VC-12 services, VC-3 services, and VC-4 services.

Overhead
processing

Processes the section overheads of the STM-1 signals.

Supports the transparent transmission and termination of the path


overheads.

Supports the setting and query of the J0, J1, J2, and C2 bytes.

Supports one channel of ECC communication.

Supports the time synchronization feature and transmission of the time


information by using the section overhead bytes.

Alarms and
performance
events

Reports various alarms and performance events, which facilitates the


management and maintenance of the equipment.

Protection
schemes

Supports the two-fiber ring MSP, four-fiber ring MSP, linear MSP, SNCP,
SNCTP, and SNCMP.

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Function and
Feature

SL1A

Maintenance
features

Supports inloops and outloops at optical interfaces.

Supports inloops and outloops on VC-4 paths.

Supports warm resets and cold resets. The warm reset does not affect
services.

Supports the query of the manufacturing information of the board.

Supports the in-service loading of the FPGA.

Supports the upgrade of the board software without affecting services.

Supports the press-to-collect function in fault data collection.

5.2.3 Working Principle and Signal Flow


The SL1A consists of the O/E converting module, CDR module, SDH overhead processing
module, logic and control module, DC/DC converter, and other modules.
Figure 5-3 shows the functional block diagram of the SL1A.
Figure 5-3 Functional block diagram of the SL1A
155 MHz
155
Mbit/s

O/E
E/O

O/E
E/O

S
P
I

155
CDR Mbit/s
155
Mbit/s

CDR

K1 and K2 insertion/
extraction

K1 and K2
High-speed
bus

....

....

155
Mbit/s
155
Mbit/s

S
P
I

155
Mbit/s

Reference clock

155 MHz
PLL

RST
155
Mbit/s

IIC
LOS

MST

MSA

HPT

High-speed
bus
DCC

SDH overhead processing


module

Logic and control


module

Frame header
Communication

Laser shutdown
+3.3 V
DC/DC
converter

DC/DC
converter

Crossconnect unit
Cross-connect
unit A
Cross-connect
unit B
SCC unit

Crossconnect unit
SCC unit
-48 V/ -60 V
-48 V/ -60 V

PLL: phase-locked loop

SPI: SDH physical interface

RST: regenerator section


termination

MST: multiplex section termination MSA: multiplex section adaptation

HPT: higher order path termination IIC: inter-integrated circuit

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Crossconnect unit

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SDH: synchronous digital hierarchy

CDR: clock and data recovery

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The functional modules of the STM-1 units are described as follows:

O/E Converting Module


l

In the receive direction, the module converts the received optical signals into electrical
signals.

In the transmit direction, the module converts the electrical signals into SDH optical signals
and sends the SDH optical signals to fibers for transmission.

The SPI detects the R_LOS alarm and provides the function of shutting down the laser.

CDR Module
This module restores the data signal and the clock signal.

SDH Overhead Processing Module


This module includes the RST, MST, MSA, and HPT sub-modules. This module provides the
inloop and outloop functions.
l

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RST sub-module

In the receive direction, the RST sub-module detects the frame alignment bytes (A1 and
A2), performs descrambling, restores the regenerator section trace byte (J0), detects a
J0 mismatch, and counts BIP-8 errored blocks.

In the transmit direction, the RST sub-module inserts the frame alignment bytes, inserts
the J0 byte, performs scrambling, and performs BIP-8 calculation and insertion.

MST sub-module

In the receive direction, the MST sub-module counts BIP-24 errored blocks, restores
the MS_REI, and detects the MS_RDI, MS_AIS, and MS-EXC.

In the transmit direction, the MST sub-module performs BIP-24 calculation and
insertion and inserts the MS_REI, MS_RDI, and MS_AIS.

The MST sub-module extracts or inserts the K1, K2, E2, D4D12, S1, B2, and M1
bytes.

MSA sub-module

In the receive direction, the MSA sub-module interprets the AU-4 pointer, detects the
LOP and AIS, and performs pointer justifications.

In the transmit direction, the MSA sub-module assembles the AUG and generates the
AU-4 pointer and the AU_AIS.

HPT sub-module

Terminates the overheads.

Restores the J1 path trace message.

Restores the REI information.

Detects the HP_RDI (monitors the status of the path).

Detects the UNEQ and AIS (monitors the signal label).

Counts the VC-4 BIP-8 errored blocks.

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Logic and Control Module


l

Manages and configures the other modules of the board.

Performs inter-board communication through the internal Ethernet interface.

Traces the clock signal from the active and standby cross-connect units.

Controls the laser.

Passes the orderwire and ECC bytes through an ADM that consists of two paired slots when
the CXL is not online.

Selects the clock signal and frame header signal from the active and standby cross-connect
units.

Controls the indicators on the board.

DC/DC Converter
It converts the 48/60 V power supply into the DC voltages that the modules of the board
require.

5.2.4 Front Panel


The front panel of the SL1A has indicators, interfaces, a bar code, and a laser safety class label.

Diagram of the Front Panel


Figure 5-4 shows the appearance of the front panel of the SL1A.

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Figure 5-4 Front panel of the SL1A

SL1A
STAT
ACT
PROG
SRV

CLASS 1
LASER
PRODUCT

OUT1
IN1

SL1A

Indicators
The front panel of the board has the following indicators:
l

Board hardware status indicator (STAT) two colors (red and green)

Service activation status indicator (ACT) one color (green)

Board software status indicator (PROG) two colors (red and green)

Service alarm indicator (SRV) three colors (red, green, and yellow)

For the meanings of the status of the indicators, see A Indicators.

Interfaces
The front panel of the SL1A has one optical interface. Table 5-7 describes the types and usage
of the optical interfaces of the SL1A.
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Table 5-7 Optical interfaces of the SL1A


Interface

Type of
Interface

Usage

IN

LC

Receives optical signals.

OUT

LC

Transmits optical signals.

5.2.5 Valid Slots


The SL1A can be installed in slots 28 and 1116 in the subrack.

5.2.6 Feature Code


The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the SL1A indicates the type of optical interface.
Table 5-8 provides the relationship between the feature code of the SL1A and the type of optical
interface.
Table 5-8 Relationship between the feature code of the SL1A and the type of optical interface
Board

Feature Code

Type of Optical Interface

SSN1SL1A10

10

S-1.1

SSN1SL1A11

11

L-1.1

SSN1SL1A12

12

L-1.2

SSN1SL1A13

13

Ve-1.2

SSN1SL1A14

14

I-1

5.2.7 Parameter Settings


You can set the parameters for the SL1A by using the T2000.
You can set the following parameters for the SL1A by using the T2000:
l

J0

J1

J2

C2

For the description of each parameter, see F Parameter Settings.

5.2.8 Technical Specifications


The technical specifications of the SL1A include the parameters specified for optical interfaces,
laster safety class, mechanical specifications, and power consumption.
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Parameters Specified for Optical Interfaces


Table 5-9 lists the parameters specified for the optical interfaces of the SL1A.
Table 5-9 Parameters specified for the optical interfaces of the SL1A
Parameter

Value

Nominal bit
rate

155520 kbit/s

Line code
pattern

NRZ

Application
code

I-1

S-1.1

L-1.1

L-1.2

Ve-1.2

Transmissio
n distance
(km)

0 to 2

2 to 15

20 to 40

60 to 80

80 to 100

Type of fiber

Single-mode
LC

Single-mode
LC

Single-mode
LC

Single-mode
LC

Single-mode
LC

Operating
wavelength
range (nm)

1260 to 1360

1261 to 1360

1263 to 1360 1480 to 1580

1480 to 1580

Launched
optical
power range
(dBm)

-15 to -8

-15 to -8

-5 to 0

-5 to 0

-3 to 0

Receiver
sensitivity
(dBm)

-23

-28

-34

-34

-34

Minimum
overload
(dBm)

-8

-8

-10

-10

-10

Minimum
extinction
ratio (dB)

8.2

8.2

10

10

10

Laser Safety Class


The safety class of the laser on the board is Class 1. The maximum launched optical power of
the optical interfaces is less than 10 dBm (10 mW).

Mechanical Specifications
The mechanical specifications of the SL1A are as follows:
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l

Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)

Weight (kg): 0.6

Power Consumption
The maximum power consumption of the SL1A at room temperature (25C) is 17 W.

5.3 SLQ1
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the SLQ1 (4xSTM-1 optical interface board).
5.3.1 Version Description
The SLQ1 is available in two functional versions, namely, N1 and N2. The difference between
the two versions is with regard to whether they support the TCM function and AU-3 services.
The N1SLQ1 is no longer manufactured.
5.3.2 Functions and Features
The SLQ1 transmits and receives 4xSTM-1 optical signals, performs O/E conversion for the
STM-1 optical signals, extracts and inserts overhead bytes, and generates alarm signals on the
line.
5.3.3 Working Principle and Signal Flow
The SLQ1 consists of the O/E converting module, CDR module, SDH overhead processing
module, logic and control module, DC/DC converter, and other modules.
5.3.4 Front Panel
The front panel of the SLQ1 has indicators, interfaces, a bar code, and a laser safety class label.
5.3.5 Valid Slots
The SLQ1 can be installed in slots 28 and 1116 in the subrack.
5.3.6 Feature Code
The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the SLQ1 indicates the type of optical interface.
5.3.7 Parameter Settings
You can set the parameters for the SLQ1 by using the T2000.
5.3.8 Technical Specifications
The technical specifications of the SLQ1 include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.

5.3.1 Version Description


The SLQ1 is available in two functional versions, namely, N1 and N2. The difference between
the two versions is with regard to whether they support the TCM function and AU-3 services.
The N1SLQ1 is no longer manufactured.
Table 5-10 describes the versions of the SLQ1.

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Table 5-10 Versions of the SLQ1


Item

Description

Functional
versions

The SLQ1 is available in two functional versions, namely, N1 and N2.

Differences

The N2SLQ1 supports the TCM function and AU-3 services, but the
TCM function and AU-3 services cannot be available at the same
time.

The N1SLQ1 does not support the TCM function or AU-3 services.

Substitution

The versions cannot be substituted with each other.

NOTE

When you configure the MSP or SNCP, you cannot configure the N1SLQ1 as the protection board if the
working board is the N2SLQ1 on which the TCM function is enabled or AU-3 services are configured.
Otherwise, the services are interrupted when a switching operation is performed.

5.3.2 Functions and Features


The SLQ1 transmits and receives 4xSTM-1 optical signals, performs O/E conversion for the
STM-1 optical signals, extracts and inserts overhead bytes, and generates alarm signals on the
line.
Table 5-11 provides the functions and features of the SLQ1.
Table 5-11 Functions and features of the SLQ1
Function and
Feature

SLQ1

Basic functions

Transmits and receives 4xSTM-1 optical signals.

Specifications of
the optical
interface

Supports different types of standard optical interfaces, namely, the I-1,


S-1.1, L-1.1, L-1.2, Ie-1, and Ve-1.2.

The characteristics of the optical interfaces of the I-1, S-1.1, L-1.1, and
L-1.2 types comply with ITU-T G.957.

The characteristics of the optical interfaces of the Ie-1 and Ve-1.2 types
comply with the standards defined by Huawei.

Supports the detection and query of the information about the optical
module.

Provides the ALS function. The optical interface supports the setting
of the on/off state of a laser.

Supports the usage and detection of the SFP optical module, which
facilitates the maintenance of the optical module.

Supports the VC-12 services, VC-3 services, and VC-4 services.

The N2SLQ1 supports the AU-3 services.

Specifications of
the optical
module

Service
processing

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Function and
Feature

SLQ1

Overhead
processing

Processes the section overheads of the STM-1 signals.

Supports the transparent transmission and termination of the path


overheads.

Supports the setting and query of the J0, J1, J2, and C2 bytes.

Supports one to four channels of ECC communication.

Alarms and
performance
events

Reports various alarms and performance events, which facilitates the


management and maintenance of the equipment.

Protection
schemes

Supports the two-fiber ring MSP, four-fiber ring MSP, linear MSP, SNCP,
SNCTP, and SNCMP.

Maintenance
features

Supports inloops and outloops at optical interfaces.

The N1SLQ1 supports inloops on VC-4 paths.

Supports warm resets and cold resets. The warm reset does not affect
services.

Supports the query of the manufacturing information of the board.

Supports the in-service loading of the FPGA.

Supports the upgrade of the board software without affecting services.

The N2SLQ1 supports the TCM function.

Supports the press-to-collect function in fault data collection.

5.3.3 Working Principle and Signal Flow


The SLQ1 consists of the O/E converting module, CDR module, SDH overhead processing
module, logic and control module, DC/DC converter, and other modules.
Figure 5-5 shows the functional block diagram of the SLQ1.

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Figure 5-5 Functional block diagram of the SLQ1


155 MHz
155
Mbit/s

O/E
E/O

O/E
E/O

S
P
I

155
CDR Mbit/s
155
Mbit/s

CDR

K1 and K2 insertion/
extraction

K1 and K2
High-speed
bus

....

....

155
Mbit/s
155
Mbit/s

S
P
I

155
Mbit/s

Reference clock

155 MHz
PLL

RST
155
Mbit/s

IIC
LOS

MST

MSA

HPT

High-speed
bus
DCC

SDH overhead processing


module

Logic and control


module

Frame header
Communication

Laser shutdown
+3.3 V
DC/DC
converter

DC/DC
converter

Fuse

Crossconnect unit

Crossconnect unit
Cross-connect
unit A
Cross-connect
unit B
SCC unit

Crossconnect unit
SCC unit
-48 V/ -60 V
-48 V/ -60 V

PLL: phase-locked loop

SPI: SDH physical interface

RST: regenerator section


termination

MST: multiplex section termination MSA: multiplex section adaptation

HPT: higher order path termination IIC: inter-integrated circuit

SDH: synchronous digital hierarchy

CDR: clock and data recovery

The functional modules of the STM-1 units are described as follows:

O/E Converting Module


l

In the receive direction, the module converts the received optical signals into electrical
signals.

In the transmit direction, the module converts the electrical signals into SDH optical signals
and sends the SDH optical signals to fibers for transmission.

The SPI detects the R_LOS alarm and provides the function of shutting down the laser.

CDR Module
This module restores the data signal and the clock signal.

SDH Overhead Processing Module


This module includes the RST, MST, MSA, and HPT sub-modules. This module provides the
inloop and outloop functions.
l

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RST sub-module
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In the receive direction, the RST sub-module detects the frame alignment bytes (A1 and
A2), performs descrambling, restores the regenerator section trace byte (J0), detects a
J0 mismatch, and counts BIP-8 errored blocks.

In the transmit direction, the RST sub-module inserts the frame alignment bytes, inserts
the J0 byte, performs scrambling, and performs BIP-8 calculation and insertion.

MST sub-module

In the receive direction, the MST sub-module counts BIP-24 errored blocks, restores
the MS_REI, and detects the MS_RDI, MS_AIS, and MS-EXC.

In the transmit direction, the MST sub-module performs BIP-24 calculation and
insertion and inserts the MS_REI, MS_RDI, and MS_AIS.

The MST sub-module extracts or inserts the K1, K2, E2, D4D12, S1, B2, and M1
bytes.

MSA sub-module

In the receive direction, the MSA sub-module interprets the AU-4 pointer, detects the
LOP and AIS, and performs pointer justifications.

In the transmit direction, the MSA sub-module assembles the AUG and generates the
AU-4 pointer and the AU_AIS.

HPT sub-module

Terminates the overheads.

Restores the J1 path trace message.

Restores the REI information.

Detects the HP_RDI (monitors the status of the path).

Detects the UNEQ and AIS (monitors the signal label).

Counts the VC-4 BIP-8 errored blocks.

Logic and Control Module


l

Manages and configures the other modules of the board.

Performs inter-board communication through the internal Ethernet interface.

Traces the clock signal from the active and standby cross-connect units.

Controls the laser.

Passes the orderwire and ECC bytes through an ADM that consists of two paired slots when
the CXL is not online.

Selects the clock signal and frame header signal from the active and standby cross-connect
units.

Controls the indicators on the board.

DC/DC Converter
It converts the 48/60 V power supply into the DC voltages that the modules of the board
require.

5.3.4 Front Panel


The front panel of the SLQ1 has indicators, interfaces, a bar code, and a laser safety class label.
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Diagram of the Front Panel


Figure 5-6 shows the appearance of the front panel of the SLQ1.
Figure 5-6 Front panel of the SLQ1

SLQ1
STAT
ACT
PROG
SRV

CLASS 1
LASER
PRODUCT

OUT1 IN1
OUT2 IN2
OUT3 IN3
OUT4 IN4

SLQ1

Indicators
The front panel of the board has the following indicators:
l

Board hardware status indicator (STAT) two colors (red and green)

Service activation status indicator (ACT) one color (green)

Board software status indicator (PROG) two colors (red and green)

Service alarm indicator (SRV) three colors (red, green, and yellow)

For the meanings of the status of the indicators, see A Indicators.


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Interfaces
The front panel of the SLQ1 has four optical interfaces. Table 5-12 describes the types and usage
of the optical interfaces of the SLQ1.
Table 5-12 Optical interfaces of the SLQ1
Interface

Type of
Interface

Usage

IN1-IN4

LC

Receives optical signals.

OUT1-OUT4

LC

Transmits optical signals.

5.3.5 Valid Slots


The SLQ1 can be installed in slots 28 and 1116 in the subrack.

5.3.6 Feature Code


The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the SLQ1 indicates the type of optical interface.
Table 5-13 provides the relationship between the feature code of the SLQ1 and the type of optical
interface.
Table 5-13 Relationship between the feature code of the SLQ1 and the type of optical interface
Board

Feature Code

Type of Optical Interface

SSN1SLQ110 and
SSN2SLQ110

10

S-1.1

SSN1SLQ111 and
SSN2SLQ111

11

L-1.1

SSN1SLQ112 and
SSN2SLQ112

12

L-1.2

SSN1SLQ113 and
SSN2SLQ113

13

Ve-1.2

SSN1SLQ114 and
SSN2SLQ114

14

I-1

SSN1SLQ115

15

Ie-1

5.3.7 Parameter Settings


You can set the parameters for the SLQ1 by using the T2000.
You can set the following parameters for the SLQ1 by using the T2000:
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l

J0

J1

J2

C2

5 SDH Boards

For the description of each parameter, see F Parameter Settings.

5.3.8 Technical Specifications


The technical specifications of the SLQ1 include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.

Parameters Specified for Optical Interfaces


Table 5-14 lists the parameters specified for the optical interfaces of the SLQ1.
Table 5-14 Parameters specified for the optical interfaces of the SLQ1
Parameter

Value

Nominal bit rate

155520 kbit/s

Line code
pattern

NRZ

Application
code

I-1

S-1.1

L-1.1

L-1.2

Ve-1.2

Ie-1

Transmission
distance (km)

0 to 2

2 to 15

20 to 40

60 to 80

80 to 100

0 to 2

Type of fiber

Singlemode LC

Singlemode LC

Singlemode LC

Singlemode LC

Single-mode
LC

Multi-mode LC

Operating
wavelength
range (nm)

1260 to
1360

1261 to 1360

1263 to
1360

1480 to
1580

1480 to 1580

1270 to 1380

Launched
optical power
range (dBm)

-15 to -8

-15 to -8

-5 to 0

-5 to 0

-3 to 0

-19 to -14

Receiver
sensitivity
(dBm)

-23

-28

-34

-34

-34

-30

Minimum
overload (dBm)

-8

-8

-10

-10

-10

-14

Minimum
extinction ratio
(dB)

8.2

8.2

10

10

10

10

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Laser Safety Class


The safety class of the laser on the board is Class 1. The maximum launched optical power of
the optical interfaces is less than 10 dBm (10 mW).

Mechanical Specifications
The mechanical specifications of the N1SLQ1 and N2SLQ1 are as follows:
l

Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)

Weight (kg): 1.0

Power Consumption
The maximum power consumption of the N1SLQ1 and N2SLQ1 at room temperature (25C) is
15 W.

5.4 SLQ1A
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the SLQ1A (4xSTM-1 optical interface board).
5.4.1 Version Description
The SLQ1A is available in one functional version, namely, N1.
5.4.2 Functions and Features
The SLQ1A transmits and receives STM-1 optical signals, performs O/E conversion for the
STM-1 optical signals, extracts and inserts overhead bytes, and generates alarm signals on the
line.
5.4.3 Working Principle and Signal Flow
The SLQ1A consists of the O/E converting module, CDR module, SDH overhead processing
module, logic and control module, DC/DC converter, and other modules.
5.4.4 Front Panel
The front panel of the SLQ1A has indicators, interfaces, a bar code, and a laser safety class label.
5.4.5 Valid Slots
The SLQ1A can be installed in slots 28 and 1116 in the subrack.
5.4.6 Feature Code
The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the SLQ1A indicates the type of optical interface.
5.4.7 Parameter Settings
You can set the parameters for the SLQ1A by using the T2000.
5.4.8 Technical Specifications
The technical specifications of the SLQ1A include the parameters specified for optical
interfaces, laser safety class, mechanical specifications, and power consumption.

5.4.1 Version Description


The SLQ1A is available in one functional version, namely, N1.
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5.4.2 Functions and Features


The SLQ1A transmits and receives STM-1 optical signals, performs O/E conversion for the
STM-1 optical signals, extracts and inserts overhead bytes, and generates alarm signals on the
line.
Table 5-15 provides the functions and features of the SLQ1A.
Table 5-15 Functions and features of the SLQ1A
Function and
Feature

SLQ1A

Basic functions

Transmits and receives 4xSTM-1 optical signals.

Specifications of
the optical
interface

Supports different types of standard optical interfaces, namely, the I-1,


S-1.1, L-1.1, L-1.2, Ie-1, and Ve-1.2.

The characteristics of the optical interfaces of the I-1, S-1.1, L-1.1, and
L-1.2 types comply with ITU-T G.957.

The characteristics of the optical interfaces of the Ie-1 and Ve-1.2 types
comply with the standards defined by Huawei.

Supports the detection and query of the information about the optical
module.

Provides the ALS function. The optical interface supports the setting
of the on/off state of a laser.

Supports the usage and detection of the SFP optical module, which
facilitates the maintenance and upgrading of the optical module.

Specifications of
the optical
module

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Service
processing

Supports the VC-12 services, VC-3 services, and VC-4 services.

Overhead
processing

Processes the section overheads of the STM-1 signals.

Supports the transparent transmission and termination of the path


overheads.

Supports the setting and query of the J0, J1, J2, and C2 bytes.

Supports one to four channels of ECC communication.

Supports the time synchronization feature and transmission of the time


information by using the section overhead bytes.

Alarms and
performance
events

Reports various alarms and performance events, which facilitates the


management and maintenance of the equipment.

Protection
schemes

Supports the two-fiber ring MSP, four-fiber ring MSP, linear MSP, SNCP,
SNCTP, and SNCMP.

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Function and
Feature

SLQ1A

Maintenance
features

Supports inloops and outloops at optical interfaces.

Supports inloops and outloops on VC-4 paths.

Supports warm resets and cold resets. The warm reset does not affect
services.

Supports the query of the manufacturing information of the board.

Supports the in-service loading of the FPGA.

Supports the upgrade of the board software without affecting services.

Supports the press-to-collect function in fault data collection.

5.4.3 Working Principle and Signal Flow


The SLQ1A consists of the O/E converting module, CDR module, SDH overhead processing
module, logic and control module, DC/DC converter, and other modules.
Figure 5-7 shows the functional block diagram of the SLQ1A.
Figure 5-7 Functional block diagram of the SLQ1A
155 MHz

155 Mbit/s
155 Mbit/s

O/E
E/O

S
P
I

155
Mbit/s

E/O

S
P
I

155
Mbit/s

CDR

Cross-connect unit

K1 and K2
Cross-connect unit

K1 and K2 insertion/extraction
High-speed
bus

....

155 Mbit/s

O/E

155
Mbit/s
155
Mbit/s

....

155 Mbit/s

CDR

Reference clock

155 MHz
PLL

RST

155
Mbit/s

MS
T

MS
A

HPT

High-speed
bus

155
Mbit/s

DCC
SDH overhead processing module

IIC
LOS
Laser shutdown

Logic and
control
module
+3.3 V

DC/DC
converter

Frame header
Communication

Fuse

Cross-connect unit A

Cross-connect unit B
SCC unit

Cross-connect unit
SCC unit

-48 V/ -60 V
-48 V/ -60 V

DC/DC
converter

PLL: phase-locked loop

SPI: SDH physical interface

RST: regenerator section


termination

MST: multiplex section termination MSA: multiplex section adaptation

HPT: higher order path termination IIC: inter-integrated circuit

SDH: synchronous digital hierarchy

CDR: clock and data recovery

The functional modules of the STM-1 units are described as follows.


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O/E Converting Module


l

In the receive direction, the module converts the received optical signals into electrical
signals.

In the transmit direction, the module converts the electrical signals into SDH optical signals
and sends the SDH optical signals to fibers for transmission.

The SPI detects the R_LOS alarm and provides the function of shutting down the laser.

CDR Module
This module restores the data signal and the clock signal.

SDH Overhead Processing Module


This module includes the RST, MST, MSA, and HPT sub-modules. This module provides the
inloop and outloop functions.
l

RST sub-module

In the receive direction, the RST sub-module detects the frame alignment bytes (A1 and
A2), performs descrambling, restores the regenerator section trace byte (J0), detects a
J0 mismatch, and counts BIP-8 errored blocks.

In the transmit direction, the RST sub-module inserts the frame alignment bytes, inserts
the J0 byte, performs scrambling, and performs BIP-8 calculation and insertion.

MST sub-module

In the receive direction, the MST sub-module counts BIP-24 errored blocks, restores
the MS_REI, and detects the MS_RDI, MS_AIS, and MS-EXC.

In the transmit direction, the MST sub-module performs BIP-24 calculation and
insertion and inserts the MS_REI, MS_RDI, and MS_AIS.

The MST sub-module extracts or inserts the K1, K2, E2, D4D12, S1, B2, and M1
bytes.

MSA sub-module

In the receive direction, the MSA sub-module interprets the AU-4 pointer, detects the
LOP and AIS, and performs pointer justifications.

In the transmit direction, the MSA sub-module assembles the AUG and generates the
AU-4 pointer and the AU_AIS.

HPT sub-module

Terminates the overheads.

Restores the J1 path trace message.

Restores the REI information.

Detects the HP_RDI (monitors the status of the path).

Detects the UNEQ and AIS (monitors the signal label).

Counts the VC-4 BIP-8 errored blocks.

Logic and Control Module


l

Manages and configures the other modules of the board.

Performs inter-board communication through the internal Ethernet interface.

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l

Traces the clock signal from the active and standby cross-connect units.

Controls the laser.

Passes the orderwire and ECC bytes through an ADM that consists of two optical interface
boards when the CXL is not online.

Selects the clock signal and frame header signal from the active and standby cross-connect
units.

Controls the indicators on the board.

DC/DC Converter
It converts the 48/60 V power supply into the DC voltages that the modules of the board
require.

5.4.4 Front Panel


The front panel of the SLQ1A has indicators, interfaces, a bar code, and a laser safety class label.

Diagram of the Front Panel


Figure 5-8 shows the appearance of the front panel of the SLQ1A.

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Figure 5-8 Front panel of the SLQ1A

SLQ1A
STAT
ACT
PROG
SRV

CLASS 1
LASER
PRODUCT

OUT1 IN1
OUT2 IN2
OUT3 IN3
OUT4 IN4

SLQ1A

Indicators
The front panel of the board has the following indicators:
l

Board hardware status indicator (STAT) two colors (red and green)

Service activation status indicator (ACT) one color (green)

Board software status indicator (PROG) two colors (red and green)

Service alarm indicator (SRV) three colors (red, green, and yellow)

For the meanings of the status of the indicators, see A Indicators.

Interfaces
The front panel of the SLQ1A has four optical interfaces. Table 5-16 describes the types and
usage of the optical interfaces of the SLQ1A.
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Table 5-16 Optical interfaces of the SLQ1A


Interface

Type of
Interface

Usage

IN1IN4

LC

Receives optical signals.

OUT1OUT4

LC

Transmits optical signals.

5.4.5 Valid Slots


The SLQ1A can be installed in slots 28 and 1116 in the subrack.

5.4.6 Feature Code


The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the SLQ1A indicates the type of optical interface.
Table 5-17 provides the relationship between the feature code of the SLQ1A and the type of
optical interface.
Table 5-17 Relationship between the feature code of the SLQ1A and the type of optical interface
Board

Feature Code

Type of Optical Interface

SSN1SLQ1A10

10

S-1.1

SSN1SLQ1A11

11

L-1.1

SSN1SLQ1A12

12

L-1.2

SSN1SLQ1A13

13

Ve-1.2

SSN1SLQ1A14

14

I-1

SSN1SLQ1A15

15

Ie-1

5.4.7 Parameter Settings


You can set the parameters for the SLQ1A by using the T2000.
You can set the following parameters for the SLQ1A by using the T2000:
l

J0

J1

J2

C2

For the description of each parameter, see F Parameter Settings.


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5.4.8 Technical Specifications


The technical specifications of the SLQ1A include the parameters specified for optical
interfaces, laser safety class, mechanical specifications, and power consumption.

Parameters Specified for Optical Interfaces


Table 5-18 lists the parameters specified for the optical interfaces of the SLQ1A.
Table 5-18 Parameters specified for the optical interfaces of the SLQ1A
Parameter

Value

Nominal bit
rate

155520 kbit/s

Line code
pattern

NRZ

Application
code

I-1

S-1.1

L-1.1

L-1.2

Ve-1.2

Ie-1

Transmissio
n distance
(km)

0 to 2

2 to 15

20 to 40

60 to 80

80 to 100

0 to 2

Type of fiber

Singlemode LC

Singlemode LC

Singlemode LC

Singlemode LC

Singlemode LC

Multi-mode
LC

Operating
wavelength
range (nm)

1260 to
1360

1261 to
1360

1263 to
1360

1480 to
1580

1480 to
1580

1270 to
1380

Launched
optical
power range
(dBm)

-15 to -8

-15 to -8

-5 to 0

-5 to 0

-3 to 0

-19 to -14

Receiver
sensitivity
(dBm)

-23

-28

-34

-34

-34

-30

Minimum
overload
(dBm)

-8

-8

-10

-10

-10

-14

Minimum
extinction
ratio (dB)

8.2

8.2

10

10

10

10

Laser Safety Class


The safety class of the laser on the board is Class 1. The maximum launched optical power of
the optical interfaces is less than 10 dBm (10 mW).
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Mechanical Specifications
The mechanical specifications of the SLQ1A are as follows:
l

Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)

Weight (kg): 1.0

Power Consumption
The maximum power consumption of the SLQ1A at room temperature (25C) is 15 W.

5.5 SLO1
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the SLO1 (8xSTM-1 optical interface board).
5.5.1 Version Description
The SLO1 is available in two functional versions, namely, N2 and N3. The difference between
the two versions is with regard to whether they support the TCM function or AU-3 services. The
N3SLO1 is discontinued.
5.5.2 Functions and Features
The SLO1 transmits and receives 8xSTM-1 optical signals, performs O/E conversion for the
STM-1 optical signals, extracts and inserts overhead bytes, and generates alarm signals on the
line.
5.5.3 Working Principle and Signal Flow
The SLO1 consists of the O/E converting module, CDR module, SDH overhead processing
module, logic and control module, DC/DC converter, and other modules.
5.5.4 Front Panel
The front panel of the SLO1 has indicators, interfaces, a bar code, and a laser safety class label.
5.5.5 Valid Slots
The SLO1 can be installed in slots 28 and 1116 in the subrack.
5.5.6 Feature Code
The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the SLO1 indicates the type of optical interface.
5.5.7 Parameter Settings
You can set the parameters for the SLO1 by using the T2000.
5.5.8 Technical Specifications
The technical specifications of the SLO1 include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.

5.5.1 Version Description


The SLO1 is available in two functional versions, namely, N2 and N3. The difference between
the two versions is with regard to whether they support the TCM function or AU-3 services. The
N3SLO1 is discontinued.
Table 5-19 describes the versions of the SLO1.
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Table 5-19 Versions of the SLO1


Item

Description

Functional versions

The SLO1 is available in two functional versions, namely, N2 and N3.

Differences

The N2SLO1 supports the TCM function and AU-3 services, but the
TCM function and AU-3 services cannot be available at the same
time.

The N3SLO1 does not support the TCM function and AU-3 services.

Substitution

When the N2SLO1 is not configured with the TCM function and AU-3
services, the N3SLO1 can substitute for the N2SLO1.

NOTE

When you configure the MSP or SNCP, you cannot configure the N3SLO1 as the protection board if the
working board is the N2SLO1 on which the TCM function or AU-3 services are configured. Otherwise,
the services are interrupted when a switching operation is performed.

5.5.2 Functions and Features


The SLO1 transmits and receives 8xSTM-1 optical signals, performs O/E conversion for the
STM-1 optical signals, extracts and inserts overhead bytes, and generates alarm signals on the
line.
Table 5-20 provides the functions and features of the SLO1.
Table 5-20 Functions and features of the SLO1 board
Function and
Feature

SLO1

Basic functions

Receives and transmits 8xSTM-1 optical signals.

Specifications of
the optical interface

Supports different types of standard optical interfaces, namely, the


I-1, S-1.1, L-1.1, L-1.2, and Ve-1.2.

The characteristics of the optical interfaces of the I-1, S-1.1, L-1.1,


and L-1.2 types comply with ITU-T G.957.

The characteristics of the optical interface of the Ve-1.2 type comply


with the standards defined by Huawei.

Supports the detection and query of the information about the optical
module.

Provides the ALS function. The optical interface supports the setting
of the on/off state of a laser.

Supports the usage and detection of the SFP optical module, which
facilitates the maintenance and upgrading of the optical module.

Supports the VC-12 services, VC-3 services, and VC-4 services.

The N2SLO1 supports the AU-3 services.

Specifications of
the optical module

Service processing

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Function and
Feature

SLO1

Overhead
processing

Processes the section overheads of the STM-1 signals.

Processes the path overheads.

Supports the setting and query of the J0, J1, J2, and C2 bytes.

Supports one to eight channels of ECC communication.

Alarms and
performance events

Reports various alarms and performance events, which facilitates the


management and maintenance of the equipment.

Protection schemes

Supports the two-fiber ring MSP, four-fiber ring MSP, linear MSP,
SNCP, SNCTP, and SNCMP.

Maintenance
features

Supports inloops and outloops at optical interfaces.

The N3SLO1 supports inloops and outloops on VC-4 paths.

Supports warm resets and cold resets. The warm reset does not affect
services.

Supports the query of the manufacturing information of the board.

Supports the in-service loading of the FPGA.

Supports the upgrade of the board software without affecting


services.

The N2SLO1 supports the TCM function.

The N3SLO1 supports the PRBS function.

Supports the press-to-collect function in fault data collection.

5.5.3 Working Principle and Signal Flow


The SLO1 consists of the O/E converting module, CDR module, SDH overhead processing
module, logic and control module, DC/DC converter, and other modules.
Figure 5-9 shows the functional block diagram of the SLO1.

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Figure 5-9 Functional block diagram of the SLO1


155 MHz
155
Mbit/s

O/E
E/O

O/E
E/O

S
P
I

155
CDR Mbit/s
155
Mbit/s

CDR

K1 and K2 insertion/
extraction

K1 and K2
High-speed
bus

....

....

155
Mbit/s
155
Mbit/s

S
P
I

155
Mbit/s

Reference clock

155 MHz
PLL

RST
155
Mbit/s

IIC
LOS

MST

MSA

HPT

High-speed
bus
DCC

SDH overhead processing


module

Logic and control


module

Frame header
Communication

Laser shutdown
+3.3 V
DC/DC
converter

DC/DC
converter

Fuse

Crossconnect unit

Crossconnect unit
Cross-connect
unit A
Cross-connect
unit B
SCC unit

Crossconnect unit
SCC unit
-48 V/ -60 V
-48 V/ -60 V

PLL: phase-locked loop

SPI: SDH physical interface

RST: regenerator section


termination

MST: multiplex section termination MSA: multiplex section adaptation

HPT: higher order path termination IIC: inter-integrated circuit

SDH: synchronous digital hierarchy

CDR: clock and data recovery

The functional modules of the STM-1 units are described as follows:

O/E Converting Module


l

In the receive direction, the module converts the received optical signals into electrical
signals.

In the transmit direction, the module converts the electrical signals into SDH optical signals
and sends the SDH optical signals to fibers for transmission.

The SPI detects the R_LOS alarm and provides the function of shutting down the laser.

CDR Module
This module restores the data signal and the clock signal.

SDH Overhead Processing Module


This module includes the RST, MST, MSA, and HPT sub-modules. This module provides the
inloop and outloop functions.
l

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RST sub-module
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In the receive direction, the RST sub-module detects the frame alignment bytes (A1 and
A2), performs descrambling, restores the regenerator section trace byte (J0), detects a
J0 mismatch, and counts BIP-8 errored blocks.

In the transmit direction, the RST sub-module inserts the frame alignment bytes, inserts
the J0 byte, performs scrambling, and performs BIP-8 calculation and insertion.

MST sub-module

In the receive direction, the MST sub-module counts BIP-24 errored blocks, restores
the MS_REI, and detects the MS_RDI, MS_AIS, and MS-EXC.

In the transmit direction, the MST sub-module performs BIP-24 calculation and
insertion and inserts the MS_REI, MS_RDI, and MS_AIS.

The MST sub-module extracts or inserts the K1, K2, E2, D4D12, S1, B2, and M1
bytes.

MSA sub-module

In the receive direction, the MSA sub-module interprets the AU-4 pointer, detects the
LOP and AIS, and performs pointer justifications.

In the transmit direction, the MSA sub-module assembles the AUG and generates the
AU-4 pointer and the AU_AIS.

HPT sub-module

Terminates the overheads.

Restores the J1 path trace message.

Restores the REI information.

Detects the HP_RDI (monitors the status of the path).

Detects the UNEQ and AIS (monitors the signal label).

Counts the VC-4 BIP-8 errored blocks.

Logic and Control Module


l

Manages and configures the other modules of the board.

Performs inter-board communication through the internal Ethernet interface.

Traces the clock signal from the active and standby cross-connect units.

Controls the laser.

Passes the orderwire and ECC bytes through an ADM that consists of two paired slots when
the CXL is not online.

Selects the clock signal and frame header signal from the active and standby cross-connect
units.

Controls the indicators on the board.

DC/DC Converter
It converts the 48/60 V power supply into the DC voltages that the modules of the board
require.

5.5.4 Front Panel


The front panel of the SLO1 has indicators, interfaces, a bar code, and a laser safety class label.
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Diagram of the Front Panel


Figure 5-10 shows the appearance of the front panel of the SLO1.
Figure 5-10 Front panel of the SLO1

SLO1
STAT
ACT
PROG
SRV

OUT1 IN1 OUT2 IN2 OUT3 IN3 OUT4 IN4 OUT5 IN5 OUT6 IN6 OUT7 IN7 OUT8 IN8
CLASS 1
LASER
PRODUCT

SLO1

Indicators
The front panel of the board has the following indicators:
l

Board hardware status indicator (STAT) two colors (red and green)

Service activation status indicator (ACT) one color (green)

Board software status indicator (PROG) two colors (red and green)

Service alarm indicator (SRV) three colors (red, green, and yellow)

For the meanings of the status of the indicators, see A Indicators.


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Interfaces
The front panel of the SLO1 has eight optical interfaces. Table 5-21 describes the types and
usage of the optical interfaces of the SLO1.
Table 5-21 Optical interfaces of the SLO1
Interface

Type of
Interface

Usage

IN1IN8

LC

Receives optical signals.

OUT1OUT8

LC

Transmits optical signals.

CAUTION
The optical interfaces of the SLO1 are level optical interfaces. Hence, use an optical attenuator
only on the ODF side.

5.5.5 Valid Slots


The SLO1 can be installed in slots 28 and 1116 in the subrack.

5.5.6 Feature Code


The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the SLO1 indicates the type of optical interface.
Table 5-22 provides the relationship between the feature code of the SLO1 and the type of optical
interface.
Table 5-22 Relationship between the feature code of the SLO1 and the type of optical interface

5-42

Board

Feature Code

Type of Optical interface

SSN2SLO110 and
SSN3SLO110

10

S-1.1

SSN2SLO111 and
SSN3SLO111

11

L-1.1

SSN2SLO112 and
SSN3SLO112

12

L-1.2

SSN2SLO113 and
SSN3SLO113

13

Ve-1.2

SSN2SLO114 and
SSN3SLO114

14

I-1

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5.5.7 Parameter Settings


You can set the parameters for the SLO1 by using the T2000.
You can set the following parameters for the SLO1 by using the T2000:
l

J0

J1

J2

C2

For the description of each parameter, see F Parameter Settings.

5.5.8 Technical Specifications


The technical specifications of the SLO1 include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.

Parameters Specified for Optical Interfaces


Table 5-23 lists the parameters specified for the optical interfaces of the SLO1.
Table 5-23 Parameters specified for the optical interfaces of the SLO1

Issue 02 (2009-07-30)

Parameter

Value

Nominal bit rate

155520 kbit/s

Line code pattern

NRZ

Application code

I-1.1

S-1.1

L-1.1

L-1.2

Ve-1.2

Transmission
distance (km)

0 to 2

2 to 15

20 to 40

60 to 80

80 to 100

Type of fiber

Singlemode LC

Singlemode LC

Singlemode LC

Singlemode LC

Singlemode LC

Operating
wavelength range
(nm)

1261 to
1360

1261 to
1360

1263 to
1360

1480 to
1580

1480 to
1580

Launched optical
power range (dBm)

-15 to -8

-15 to -8

-5 to 0

-5 to 0

-3 to 0

Receiver sensitivity
(dBm)

-23

-28

-34

-34

-34

Minimum overload
(dBm)

-8

-8

-10

-10

-10

Minimum extinction
ratio (dB)

8.2

8.2

10

10

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Laser Safety Class


The safety class of the laser on the board is Class 1. The maximum launched optical power of
the optical interfaces is less than 10 dBm (10 mW).

Mechanical Specifications
The mechanical specifications of the N2SLO1 are as follows:
l

Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)

Weight (kg): 1.1

The mechanical specifications of the N3SLO1 are as follows:


l

Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)

Weight (kg): 1.2

Power Consumption
The maximum power consumption of the N2SLO1 at room temperature (25C) is 26 W.
The maximum power consumption of the N3SLO1 at room temperature (25C) is 20 W.

5.6 SLT1
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the SLT1 (12xSTM-1 optical interface board).
5.6.1 Version Description
The SLT1 is available in one functional version, namely, N1.
5.6.2 Functions and Features
The SLT1 transmits and receives STM-1 optical signals, performs O/E conversion for the STM-1
optical signals, extracts and inserts overhead bytes, and generates alarm signals on the line.
5.6.3 Working Principle and Signal Flow
The SLT1 consists of the O/E converting module, CDR module, SDH overhead processing
module, logic and control module, DC/DC converter, and other modules. The external services
are accessed by the external interface boards EU08 and OU08. The EU08 is an electrical interface
board and the OU08 is an optical interface board.
5.6.4 Front Panel
The front panel of the SLT1 has indicators, interfaces, a bar code, and a laser safety class label.
5.6.5 Valid Slots
The SLT1 can be installed in slots 28 and 1116 in the subrack.
5.6.6 Parameter Settings
You can set the parameters for the SLT1 by using the T2000.
5.6.7 Technical Specifications
The technical specifications of the SLT1 include the parameters specified for optical interfaces,
dimensions, weight, and power consumption.
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5.6.1 Version Description


The SLT1 is available in one functional version, namely, N1.

5.6.2 Functions and Features


The SLT1 transmits and receives STM-1 optical signals, performs O/E conversion for the STM-1
optical signals, extracts and inserts overhead bytes, and generates alarm signals on the line.
Table 5-24 provides the functions and features of the SLT1.
Table 5-24 Functions and features of the SLT1
Function and
Feature

SLT1

Basic functions

Transmits and receives 12xSTM-1 optical signals.

Specifications of Supports S-1.1 standard optical interfaces whose characteristics comply


the optical
with ITU-T G.957.
interface
Specifications of
the optical
module

Issue 02 (2009-07-30)

Supports the detection and query of the information about the optical
module.

Provides the ALS function. The optical interface supports the setting
of the on/off state of a laser.

Supports the usage and detection of the SFP optical module, which
facilitates the maintenance of the optical module.

Service
processing

Supports the VC-12 services, VC-3 services, and VC-4 services.

Overhead
processing

Processes the section overheads of the STM-1 signals.

Supports the transparent transmission and termination of the path


overheads.

Supports the setting and query of the J0, J1, J2, and C2 bytes.

Supports one to twelve channels of ECC communication. Port 1 to port


8 support the ECC communication by using bytes D1D12. Port 9 to
port 12 support the ECC communication by using bytes D1D3.

Supports the time synchronization feature and transmission of the time


information by using the section overhead bytes.

Alarms and
performance
events

Reports various alarms and performance events, which facilitates the


management and maintenance of the equipment.

Protection
schemes

Supports the two-fiber ring MSP, four-fiber ring MSP, linear MSP, SNCP,
SNCTP, and SNCMP.

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Function and
Feature

SLT1

Maintenance
features

Supports inloops and outloops at optical interfaces.

Supports inloops and outloops on VC-4 paths.

Supports warm resets and cold resets. The warm reset does not affect
services.

Supports the query of the manufacturing information of the board.

Supports the in-service loading of the FPGA.

Supports the upgrade of the board software without affecting services.

Supports the PRBS function.

Supports the press-to-collect function in fault data collection.

5.6.3 Working Principle and Signal Flow


The SLT1 consists of the O/E converting module, CDR module, SDH overhead processing
module, logic and control module, DC/DC converter, and other modules. The external services
are accessed by the external interface boards EU08 and OU08. The EU08 is an electrical interface
board and the OU08 is an optical interface board.
Figure 5-11 shows the functional block diagram of the SLT1.
Figure 5-11 Functional block diagram of the SLT1
155 MHz
155
Mbit/s

O/E
E/O

O/E
E/O

S
P
I

155
CDR Mbit/s
155
Mbit/s

CDR

K1 and K2 insertion/
extraction

K1 and K2
High-speed
bus

....

....

155
Mbit/s
155
Mbit/s

S
P
I

155
Mbit/s

Reference clock

155 MHz
PLL

RST
155
Mbit/s

IIC
LOS

MST

MSA

HPT

High-speed
bus
DCC

SDH overhead processing


module

Logic and control


module

Frame header
Communication

Laser shutdown
+3.3 V
DC/DC
converter

PLL: phase-locked loop

5-46

DC/DC
converter

SPI: SDH physical interface

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Fuse

Crossconnect unit

Crossconnect unit
Cross-connect
unit A
Cross-connect
unit B
SCC unit

Crossconnect unit
SCC unit
-48 V/ -60 V
-48 V/ -60 V

SDH: synchronous digital hierarchy

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RST: regenerator section
termination

5 SDH Boards

MST: multiplex section termination MSA: multiplex section adaptation

HPT: higher order path termination IIC: inter-integrated circuit

CDR: clock and data recovery

The functional modules of the STM-1 units are described as follows:

O/E Converting Module


l

In the receive direction, the module converts the received optical signals into electrical
signals.

In the transmit direction, the module converts the electrical signals into SDH optical signals
and sends the SDH optical signals to fibers for transmission.

The SPI detects the R_LOS alarm and provides the function of shutting down the laser.

CDR Module
This module restores the data signal and the clock signal.

SDH Overhead Processing Module


This module includes the RST, MST, MSA, and HPT sub-modules. This module provides the
inloop and outloop functions.
l

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RST sub-module

In the receive direction, the RST sub-module detects the frame alignment bytes (A1 and
A2), performs descrambling, restores the regenerator section trace byte (J0), detects a
J0 mismatch, and counts BIP-8 errored blocks.

In the transmit direction, the RST sub-module inserts the frame alignment bytes, inserts
the J0 byte, performs scrambling, and performs BIP-8 calculation and insertion.

MST sub-module

In the receive direction, the MST sub-module counts BIP-24 errored blocks, restores
the MS_REI, and detects the MS_RDI, MS_AIS, and MS-EXC.

In the transmit direction, the MST sub-module performs BIP-24 calculation and
insertion and inserts the MS_REI, MS_RDI, and MS_AIS.

The MST sub-module extracts or inserts the K1, K2, E2, D4D12, S1, B2, and M1
bytes.

MSA sub-module

In the receive direction, the MSA sub-module interprets the AU-4 pointer, detects the
LOP and AIS, and performs pointer justifications.

In the transmit direction, the MSA sub-module assembles the AUG and generates the
AU-4 pointer and the AU_AIS.

HPT sub-module

Terminates the overheads.

Restores the J1 path trace message.

Restores the REI information.

Detects the HP_RDI (monitors the status of the path).


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Detects the UNEQ and AIS (monitors the signal label).

Counts the VC-4 BIP-8 errored blocks.

Logic and Control Module


l

Manages and configures the other modules of the board.

Performs inter-board communication through the internal Ethernet interface.

Traces the clock signal from the active and standby cross-connect units.

Controls the laser.

Passes the orderwire and ECC bytes through an ADM that consists of two paired slots when
the CXL is not online.

Selects the clock signal and frame header signal from the active and standby cross-connect
units.

Controls the indicators on the board.

DC/DC Converter
It converts the 48/60 V power supply into the DC voltages that the modules of the board
require.

5.6.4 Front Panel


The front panel of the SLT1 has indicators, interfaces, a bar code, and a laser safety class label.

Diagram of the Front Panel


Figure 5-12 shows the appearance of the front panel of the SLT1.

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Figure 5-12 Front panel of the SLT1

SLT1
STAT
ACT
PROG
SRV

OUT1 IN1 OUT2 IN2 OUT3 IN3 OUT4 IN4 OUT5 IN5 OUT6 IN6 OUT7 IN7 OUT8 IN8 OUT9 IN9 OUT10IN10OUT11IN11OUT12IN12
CLASS 1
LASER
PRODUCT

SLT1

Indicators
The front panel of the board has the following indicators:
l

Board hardware status indicator (STAT) two colors (red and green)

Service activation status indicator (ACT) one color (green)

Board software status indicator (PROG) two colors (red and green)

Service alarm indicator (SRV) three colors (red, green, and yellow)

For the meanings of the status of the indicators, see A Indicators.

Interfaces
The front panel of the SLT1 has 12 optical interfaces. Table 5-25 describes the types and usage
of the optical interfaces of the SLT1.
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Table 5-25 Optical interfaces of the SLT1


Interface

Type of
Interface

Usage

IN1IN12

LC

Receives optical signals.

OUT1OUT12

LC

Transmits optical signals.

CAUTION
The optical interfaces of the SLT1 are level optical interfaces. Hence, use an optical attenuator
only on the ODF side.

5.6.5 Valid Slots


The SLT1 can be installed in slots 28 and 1116 in the subrack.

5.6.6 Parameter Settings


You can set the parameters for the SLT1 by using the T2000.
You can set the following parameters for the SLT1 by using the T2000:
l

J0

J1

J2

C2

For the description of each parameter, see F Parameter Settings.

5.6.7 Technical Specifications


The technical specifications of the SLT1 include the parameters specified for optical interfaces,
dimensions, weight, and power consumption.

Parameters Specified for Optical Interfaces


Table 5-26 lists the parameters specified for the optical interfaces of the SLT1.
Table 5-26 Parameters specified for the optical interfaces of the SLT1

5-50

Parameter

Value

Nominal bit rate

155520 kbit/s

Line code pattern

NRZ

Application code

S-1.1

L-1.1

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Parameter

Value

Transmission distance (km)

2 to 15

20 to 40

60 to 80

Type of fiber

Single-mode LC

Single-mode LC

Single-mode LC

Operating wavelength range


(nm)

1261 to 1360

1263 to 1360

1480 to 1580

Launched optical power


range (dBm)

-15 to -8

-5 to 0

-5 to 0

Receiver sensitivity (dBm)

-28

-34

-34

Minimum overload (dBm)

-8

-10

-10

Minimum extinction ratio


(dB)

8.2

10

10

Laser Safety Class


The safety class of the laser on the board is Class 1. The maximum launched optical power of
the optical interfaces is less than 10 dBm (10 mW).

Mechanical Specifications
The mechanical specifications of the SLT1 are as follows:
l

Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)

Weight (kg): 1.3

Power Consumption
The maximum power consumption of the SLT1 at room temperature (25C) is 22 W.

5.7 SLH1B
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the SLH1B (16xSTM-1 signal processing board).
5.7.1 Version Description
The SLH1B is available in one functional version, namely, N1.
5.7.2 Functions and Features
The SLH1B processes STM-1 optical and electrical signals.
5.7.3 Working Principle and Signal Flow
The SLH1B consists of the CDR module, SDH overhead processing module, logic and control
module, DC/DC converter, and other modules. The external services are accessed by the external
interface boards EU08 and OU08. The EU08 is an electrical interface board and the OU08 is an
optical interface board.
5.7.4 Front Panel
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The front panel of the SLH1B has indicators and a bar code.
5.7.5 Valid Slots
The SLH1B can be installed in slots 37 and 1216 in the subrack.
5.7.6 Board Protection
The SLH1B supports the 1:N (N3) TPS protection.
5.7.7 Parameter Settings
You can set the parameters for the SLH1B by using the T2000.
5.7.8 Technical Specifications
The technical specifications of the SLH1B include the parameters specified for optical interfaces,
mechanical specifications, and power consumption.

5.7.1 Version Description


The SLH1B is available in one functional version, namely, N1.

5.7.2 Functions and Features


The SLH1B processes STM-1 optical and electrical signals.
Table 5-27 provides the functions and features of the SLH1B.
Table 5-27 Functions and features of the SLH1B
Function and
Feature

SLH1B

Basic functions

Processes 16xSTM-1 signals.

Specifications of
the optical
module

Supports the detection and query of the information about the optical
module.

Provides the ALS function. The optical interface supports the setting
of the on/off state of a laser.

Supports the usage and detection of the SFP optical module, which
facilitates the maintenance and upgrading of the optical module.

Service
processing

Supports the VC-12 services, VC-3 services, and VC-4 services.

Overhead
processing

Processes the section overheads of the STM-1 signals.

Supports the transparent transmission and termination of the path


overheads. Supports the setting and query of the J0, J1, J2, and C2
bytes.

Supports one to sixteen channels of ECC communication. Port 1 to


port 8 support the ECC communication by using bytes D1D12. Port
9 to port 16 support the ECC communication by using bytes D1D3.

Alarm and
Performance
Event
5-52

Reports various alarms and performance events, which facilitates the


management and maintenance of the equipment.

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Function and
Feature

SLH1B

Protection
schemes

Supports the TPS protection when used with the interface board and
the switching and bridging board.

Supports the two-fiber ring MSP, four-fiber ring MSP, linear MSP,
SNCP, SNCTP, and SNCMP.

Supports inloops and outloops at optical interfaces.

Supports inloops and outloops on VC-4 paths.

Supports warm resets and cold resets. The warm reset does not affect
services.

Supports the query of the manufacturing information of the board.

Supports the in-service loading of the FPGA.

Supports the upgrade of the board software without affecting services.

Supports the PRBS function.

Supports the press-to-collect function in fault data collection.

Maintenance
features

When the SLH1B works with different interface boards and electrical interface switching boards,
the access capabilities for the STM-1 signals are different. For details, refer to Table 5-28.
Table 5-28 Access capabilities of the SLH1B when the SLH1 works with different interface
boards and electrical interface switching boards
Interface Board

SLH1B

None

The SLH1B cannot access signals.

EU08

Accesses and processes 8-channel or 16-channel electrical signals.

OU08a

Accesses and processes 8-channel or 16-channel optical signals.

EU08 + OU08a

Accesses and processes 8-channel electrical signals and 8-channel


optical signals.

EU08 + TSB8

Accesses and processes 8-channel or 16-channel STM-1 electrical


signals, and realizes the 1:N (N3) TPS protection.

a: The N2OU08 does not support the usage and monitoring of the SFP optical module.

5.7.3 Working Principle and Signal Flow


The SLH1B consists of the CDR module, SDH overhead processing module, logic and control
module, DC/DC converter, and other modules. The external services are accessed by the external
interface boards EU08 and OU08. The EU08 is an electrical interface board and the OU08 is an
optical interface board.

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Figure 5-13 shows the functional block diagram of the SLH1B when the SLH1B works with
the EU08 by describing how to process 1xSTM-1 signals.
Figure 5-13 Functional block diagram of the SLH1B when the SLH1B works with the EU08
155 MHz

EU08
SPI

155
Mbit/s
155
Mbit/s

CMI
Transformer

Encode/
Decode

155
155
Mbit/s CDR Mbit/s
155
Mbit/s
CDR

Reference clock

155 MHz
PLL

K1 and K2 insertion/
extraction

K1 and K2
Highspeed bus

RST

MST

MSA

HPT

155
Mbit/s

Highspeed bus
DCC

SDH overhead processing


module
LOS

Logic and
control module
+3.3 V
DC/DC
converter

DC/DC
converter

Frame header
Communication

Fuse

Crossconnect unit
Crossconnect unit
Cross-connect
unit A
Cross-connect
unit B
SCC unit

Crossconnect unit
SCC unit
-48 V/ -60 V
-48 V/ -60 V

PLL: phase-locked loop

SPI: SDH physical interface

RST: regenerator section


termination

MST: multiplex section termination MSA: multiplex section adaptation

HPT: higher order path termination IIC: inter-integrated circuit

SDH: synchronous digital hierarchy

CDR: clock and data recovery

Figure 5-14 shows the functional block diagram of the SLH1B when the SLH1B works with
the OU08 by describing how to process 1xSTM-1 signals.

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Figure 5-14 Functional block diagram of the SLH1B when the SLH1B works with the OU08
155 MHz
OU08
155
Mbit/s
155
Mbit/s

O/E
E/O

S
P
I

155 MHz
PLL

K1 and K2 insertion/
extraction

155
155
Mbit/s CDR Mbit/s
155
Mbit/s
NRZ

K1 and K2
Highspeed bus

RST

CDR

Reference clock

155
Mbit/s

LOS
Laser shut dow

MST

HPT

Highspeed bus
DCC

SDH overhead processing


module
Frame header

Logic and
control module
+3.3 V

DC/DC
converter

MSA

Communication

DC/DC
converter

Fuse

Crossconnect unit
Crossconnect unit
Crossconnect unit A
Crossconnect unit B
SCC unit

Crossconnect unit
SCC unit
-48 V/ -60 V
-48 V/ -60 V

PLL: phase-locked loop

SPI: SDH physical interface

RST: regenerator section


termination

MST: multiplex section termination MSA: multiplex section adaptation

HPT: higher order path termination CDR: clock and data recovery

SDH: synchronous digital hierarchy

The functional modules of the STM-1 units are described as follows:

CDR Module
This module restores the data signal and the clock signal.

SDH Overhead Processing Module


This module includes the RST, MST, MSA, and HPT sub-modules. This module provides the
inloop and outloop functions.
l

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RST sub-module

In the receive direction, the RST sub-module detects the frame alignment bytes (A1 and
A2), performs descrambling, restores the regenerator section trace byte (J0), detects a
J0 mismatch, and counts BIP-8 errored blocks.

In the transmit direction, the RST sub-module inserts the frame alignment bytes, inserts
the J0 byte, performs scrambling, and performs BIP-8 calculation and insertion.

MST sub-module

In the receive direction, the MST sub-module counts BIP-24 errored blocks, restores
the MS_REI, and detects the MS_RDI, MS_AIS, and MS-EXC.

In the transmit direction, the MST sub-module performs BIP-24 calculation and
insertion and inserts the MS_REI, MS_RDI, and MS_AIS.
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The MST sub-module extracts or inserts the K1, K2, E2, D4D12, S1, B2, and M1
bytes.

MSA sub-module

In the receive direction, the MSA sub-module interprets the AU-4 pointer, detects the
LOP and AIS, and performs pointer justifications.

In the transmit direction, the MSA sub-module assembles the AUG and generates the
AU-4 pointer and the AU_AIS.

HPT sub-module

Terminates the overheads.

Restores the J1 path trace message.

Restores the REI information.

Detects the HP_RDI (monitors the status of the path).

Detects the UNEQ and AIS (monitors the signal label).

Counts the VC-4 BIP-8 errored blocks.

Logic and Control Module


l

Manages and configures the other modules of the board.

Performs inter-board communication through the internal Ethernet interface.

Traces the clock signal from the active and standby cross-connect units.

Controls the laser.

Passes the orderwire and ECC bytes through an ADM that consists of two paired slots when
the CXL is not online.

Selects the clock signal and frame header signal from the active and standby cross-connect
units.

Controls the indicators on the board.

DC/DC Converter
It converts the 48/60 V power supply into the DC voltages that the modules of the board
require.

5.7.4 Front Panel


The front panel of the SLH1B has indicators and a bar code.

Diagram of the Front Panel


The front panel of the SLH1B does not have an interface. Hence, the SLH1B must be used with
the EU08 or OU08. Figure 5-15 shows the appearance of the front panel of the SLH1B.

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Figure 5-15 Front panel of the SLH1B

SLH1
STAT
ACT
PROG
SRV

SLH1

Indicators
The front panel of the board has the following indicators:
l

Board hardware status indicator (STAT) two colors (red and green)

Service activation status indicator (ACT) one color (green)

Board software status indicator (PROG) two colors (red and green)

Service alarm indicator (SRV) three colors (red, green, and yellow)

For the meanings of the status of the indicators, see A Indicators.

5.7.5 Valid Slots


The SLH1B can be installed in slots 37 and 1216 in the subrack.
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5.7.6 Board Protection


The SLH1B supports the 1:N (N3) TPS protection.

Protection Principle
The TPS protection is equipment-level protection. When the working board fails, the accessed
signals are switched to the protection board. Hence, complex network-level protection
operations such as the MSP and SNCP are not triggered. In addition, the reliability of the
equipment is enhanced.
The SLH1B can work with the EU08 and TSB8 to realize the 1:N (N3) TPS protection for
8xSTM-1 or 16xSTM-1 electrical signals.Figure 5-16 shows the 1:3 TPS protection for
8xSTM-1 electrical signals. The principle of the 1:3 TPS protection for 16xSTM-1 electrical
signals is the same as the principle of the 1:3 TPS protection for 8xSTM-1 electrical signals.
Figure 5-16 1:3 TPS protection provided by the SLH1B
8xSTM-1(e) 8xSTM-1(e)

EU08

TSB8

8xSTM-1(e)

Sw itching
control
EU08 signal

EU08

Protection

Working

Working

Working

SLH1A

SLH1A

SLH1A

SLH1A

Crossconnect
and timing
board
Slot 9/10

Failed
Slot 3

Slot 4

Slot 5

Slot 6

Normal state
When each working board functions normally, the traffic signal is directly transmitted to
the SLH1B through position 1 of the control switch on the EU08.

Switching state
When a working board detects a failure and requires the switching operation, the system
protects the working boards in the following manner:

5-58

When the working board in slot 5 fails, the control switch of the corresponding EU08
switches from position 1 to position 2. At the same time, the control switch of the TSB8
switches from position 1 to position 2 so that the protection board in slot 3 can protect
the working board in slot 5.

When the working board in slot 4 fails, the control switch of the corresponding EU08
switches from position 1 to position 2, but the control switch of the TSB8 does not act
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and is still in position 1. In this case, the protection board in slot 3 protects the working
board in slot 4.
When the working board in slot 6 fails, the control switch of the corresponding EU08
switches from position 1 to position 2. At the same time, the control switch of the TSB8
switches from position 1 to position 3 so that the protection board in slot 3 can protect
the working board in slot 6.

Hardware Configuration
Figure 5-17 shows the slot configuration for the two 1:3 TPS protection groups of the SLH1B.
Figure 5-17 Slot configuration for the two 1:3 TPS protection groups of the SLH1B
S
L
O
T

S
L
O
T

S
L
O
T

S
L
O
T

S
L
O
T

S
L
O
T

2 2 2 2 2 2 2 2
1 2 3 4 5 6 7 8

S
L
O
T

2
9

3
1

3
2

3
3

3
4

3 3 3 3
5 6 7 8

S
L
O
T

3 4
9 0

S
L
O
T

S
L
O
T

11 12 13 14 15 16

S 43 EOW
S 42 AUX

10

S S
L L
O O
T T

Working 2

Working 1

S 41 PIU

S
L
O
T

Protection 2

Working 1

7 8

S
L
O
T

Working 2

S
L
O
T

Working 2

S
L
O
T

CXL

S
L
O
T

FAN

CXL

2 3

Protection 1

S S S S
L L L L
O O O O
T T T T

Working 1

S 1 PIU

S
L
O
T

S
L
O
T

EU08

FAN

S
L
O
T

S
L
O
T

EU08
EU08

FAN
S
L
O
T

3
0

S
L
O
T

TSB8

S
L
O
T

TSB8

S S
L L
O O
T T

EU08

S
L
O
T

EU08

EU08
EU08
EU08

EU08

EU08
TSB8
TSB8

S S
L L
O O
T T

EU08

S
L
O
T

EU08

S
L
O
T

Fiber routing area

In Figure 5-17, the board in slot 3 protects the boards in slots 46. The board in slot 16 protects
the boards in slots 1315.
Table 5-29 lists the slots for the SLH1B, EU08, and TSB8.
Table 5-29 Slots for the SLH1B, EU08, and TSB8

Issue 02 (2009-07-30)

Board

Protection Group 1

Protection Group 2

SLH1B (protection
board)

Slot 3

Slot 16

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Board

Protection Group 1

Protection Group 2

TSB8

Slots 21 and 22

Slots 39 and 40

SLH1B (working
board)

Slots 46

Slots 1315

EU08

Slots 23, 25, and 27

Slots 33, 35, and 37

5.7.7 Parameter Settings


You can set the parameters for the SLH1B by using the T2000.
You can set the following parameters for the SLH1B by using the T2000:
l

J0

J1

J2

C2

For the description of each parameter, see F Parameter Settings.

5.7.8 Technical Specifications


The technical specifications of the SLH1B include the parameters specified for optical interfaces,
mechanical specifications, and power consumption.

Parameters Specified for Optical Interfaces


Table 5-30 lists the parameters specified for the optical interfaces of the SLH1B.
Table 5-30 Parameters specified for the optical interfaces of the SLH1B
Parameter

Value

Nominal bit rate

155520 kbit/s

Line code pattern

CMI and NRZ

Mechanical Specifications
The mechanical specifications of the SLH1B are as follows:
l

Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)

Weight (kg): 1.1

Power Consumption
The maximum power consumption of the SLH1B at room temperature (25C) is 21 W.
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5.8 SEP1
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the SEP1 (2xSTM-1 line processing board).
5.8.1 Version Description
The SEP1 is available in one functional version, namely, N1.
5.8.2 Functions and Features
The SEP1 processes STM-1 signals.
5.8.3 Working Principle and Signal Flow
The SEP1 consists of the line interface module, CDR module, SDH overhead processing module,
logic and control module, DC/DC converter, and other modules. The external services are
accessed by the external interface boards EU08 and OU08. The EU08 is an electrical interface
board and the OU08 is an optical interface board.
5.8.4 Front Panel
The front panel of the SEP1 has indicators, interfaces, and a bar code.
5.8.5 Valid Slots
When the interfaces are available on the front panel of the SEP1, the SEP1 can be installed in
slots 27 and 1216 in the subrack. When the SEP1 is used with the interface board, it is defined
as SEP. When the SEP is used with the interface board, it can be installed in slots 37 and 12
16 in the subrack.
5.8.6 Board Protection
The TPS protection is equipment-level protection. When the working board fails, the accessed
services are switched to the protection board.
5.8.7 Parameter Settings
You can set the parameters for the SEP1 by using the T2000.
5.8.8 Technical Specifications
The technical specifications of the SEP1 include the parameters specified for interfaces,
mechanical specifications, and power consumption.

5.8.1 Version Description


The SEP1 is available in one functional version, namely, N1.
When the interfaces are available on the front panel of the SEP1 (the logical board of the SEP1
is displayed as SEP1 on the T2000), the SEP1 processes 2xSTM-1 electrical signals. In this case,
the SEP1 is a 2xSTM-1 signal processing board. When the SEP1 is used with the interface board
(the logical board of the SEP1 is displayed as SEP on the T2000), the SEP1 processes 8xSTM-1
optical signals or 8xSTM-1 electrical signals. In this case, the SEP1 is an 8xSTM-1 signal
processing board. The physical boards of the two types of logical boards (SEP1 and SEP) are
the same and are the SEP1. When the logical boards need not be differentiated, both the SEP1
and SEP are defined as SEP1.

5.8.2 Functions and Features


The SEP1 processes STM-1 signals.
Table 5-31 provides the functions and features of the SEP1.
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Table 5-31 Functions and features of the SEP1


Function and
Feature

SEP1

Basic functions

Processes 2xSTM-1 signals when the interfaces are available on the


front panel.

Processes 8xSTM-1 signals when the SEP1 works with an interface


board.

Supports the detection and query of the information about the optical
module.

Provides the ALS function. The optical interface supports the setting
of the on/off state of a laser.

Supports the usage and monitoring of the SFP optical module, which
facilitates the maintenance and upgrading of the optical module.

Specifications of
the optical
module

Service
processing

Supports the VC-12 services, VC-3 services, and VC-4 services.

Overhead
processing

Processes the section overheads of the STM-1 signals.

Supports the transparent transmission and termination of the path


overheads.

Supports the setting and query of the J0, J1, J2, and C2 bytes.

Supports one or two channels of ECC communication.

Alarms and
performance
events

Reports various alarms and performance events, which facilitates the


management and maintenance of the equipment.

Protection
schemes

Supports the TPS protection when used with the interface board and
the switching and bridging board.

Supports the two-fiber ring MSP, four-fiber ring MSP, linear MSP, and
SNCP.

Supports inloops and outloops at optical interfaces.

Supports inloops on VC-4 paths.

Supports warm resets and cold resets. The warm reset does not affect
services.

Supports the query of the manufacturing information of the board.

Supports the in-service loading of the FPGA.

Supports the upgrade of the board software without affecting services.

Supports the press-to-collect function in fault data collection.

Maintenance
features

When the SEP1 works with different interface boards and electrical interface switching boards,
the access capabilities for the STM-1 signals are different. For details, refer to Table 5-32.

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Table 5-32 Access capabilities of the SEP1 when the SEP1 works with different interface boards
and electrical interface switching boards
Interface Board

SEP1

None

Accesses and processes 2xSTM-1 electrical signals, but does not


support the TPS protection.

EU08

Accesses and processes 8xSTM-1 electrical signals.

OU08

Accesses and processes 8xSTM-1 optical signals.

EU08 + OU08

Cannot work with the EU08 and OU08 at the same time.

EU08 + TSB8

Accesses and processes 8xSTM-1 electrical signals, and supports the


TPS protection.

CAUTION
When the SEP1 works with an interface board, the two interfaces on the front panel of the SEP1
are invalid. The SEP1 cannot work with the EU08 and OU08 at the same time.

5.8.3 Working Principle and Signal Flow


The SEP1 consists of the line interface module, CDR module, SDH overhead processing module,
logic and control module, DC/DC converter, and other modules. The external services are
accessed by the external interface boards EU08 and OU08. The EU08 is an electrical interface
board and the OU08 is an optical interface board.
Figure 5-18 shows the functional block diagram of the SEP1.

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Figure 5-18 Functional block diagram of the SEP1


155 MHz
PLL

Reference
clock

SDH overhead processing


K1 and
module
K1 and K2
K2
insertion/extraction

155 Mbit/s
Port 1 155 Mbit/s
Port 2

Transfor
mer

155 Mbit/s

Transfor
155 Mbit/s
mer

CMI

CMI

155
Mbit/s
NRZ
SPI
CDR
Encode/
155
Decode
Mbit/s
Encode/
Decode

NRZ

CDR

Highspeed
bus
RS
T

MS
T

MS
A

HP
T

155
Mbit/s

DCC

155
Mbit/s
LO
S

Highspeed
bus

Logic and
control module
+3.3 V

DC/DC
converter

DC/DC
converter

Crossconnect unit

Crossconnect unit

Cross-connect
unit A
Cross-connect
unit B
SCC
unit

CrossFrame header
Communication connect unit
SCC unit
Fuse

-48 V/ -60 V
-48 V/ -60 V

PLL: phase-locked loop

SPI: SDH physical interface

RST: regenerator section


termination

MST: multiplex section termination MSA: multiplex section adaptation

HPT: higher order path termination CDR: clock and data recovery

SDH: synchronous digital hierarchy

Figure 5-19 shows the functional block diagram of the SEP when the SEP works with the EU08.

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Figure 5-19 Functional block diagram of the SEP when the SEP works with the EU08
EU08
155 Mbit/s

Transfor
Port 1 155 Mbit/s mer
155 Mbit/s
Port 8
155 Mbit/s

Transfor
mer

CMI

CMI

155 Mbit/s Transfor CMI


Port 1 155 Mbit/s
mer
Port 2

155 Mbit/s
155 Mbit/s

Transfor
mer

CMI

SPI
Encode/
Decode

Encode/
Decode

Encode/
Decode

155 MHz
PLL

155
Mbit/s

SDH overhead
processing module
K1 and K2
insertion/extraction

CDR
155 Mbit/s
CDR

155
Mbit/s

155 Mbit/s
155
NRZ CDR Mbit/s

Reference
clock

K1 and
K2
Highspeed
bus

RST MST MSA HPT

155 Mbit/s
155
NRZ
CDR Mbit/s
Encode/
Decode
155 Mbit/s

DCC

Logic and
control module

LOS

Highspeed
bus

+3.3 V
DC/DC
converter

DC/DC
converter

Frame
header
Communication

Fuse

Crossconnect unit

Crossconnect unit
Crossconnect unit A
Crossconnect unit B
SCC unit
Crossconnect unit
SCC unit
-48 V/ -60 V
-48 V/ -60 V

PLL: phase-locked loop

SPI: SDH physical interface

RST: regenerator section


termination

MST: multiplex section termination MSA: multiplex section adaptation

HPT: higher order path termination CDR: clock and data recovery

SDH: synchronous digital hierarchy

Figure 5-20 shows the functional block diagram of the SEP when the SEP works with the OU08.

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Figure 5-20 Functional block diagram of the SEP when the SEP works with the OU08

155
Mbit/s
Port 1

Port 8

Port 1

155 Mbit/s
155 Mbit/s

Port 2

155 Mbit/s
155 Mbit/s

155
Mbit/s

O/E
S
P
I

O/E

NRZ

E/O
SPI
Encode/
Decode

CMI

Transfor
mer

CMI

Encode/
Decode

Reference clock

155
SDH overhead processing
CDR Mbit/s
module
155 Mbit/s
K1 and K2
insertion/extraction
155
Mbit/s
CDR
155 Mbit/s

NRZ

E/O

155
Mbit/s
155
Mbit/s
Transfor
mer

155 MHz
PLL

OU08

155
NRZ
CDR Mbit/s
155 Mbit/s
155
NRZ CDR Mbit/s

RST MST

MSA

K1 and K2

High-speed
bus

HPT

High-speed
bus

155 Mbit/s

LOS
LOS
Laser shut dow

DCC

Logic and
control module
+3.3 V

DC/DC
converter

DC/DC
converter

Frame header
Communication

Fuse

Cross-connect
unit

Cross-connect
unit

Cross-connect
unit A
Cross-connect
unit B

SCC unit

Cross-connect
unit
SCC unit
-48 V/ -60 V
-48 V/ -60 V

PLL: phase-locked loop

SPI: SDH physical interface

RST: regenerator section


termination

MST: multiplex section termination MSA: multiplex section adaptation

HPT: higher order path termination CDR: clock and data recovery

SDH: synchronous digital hierarchy

The functional modules are described as follows:

Line Interface Module and CDR Module


l

In the receive direction, the received electrical signals (CMI codes) are isolated through
the converter and then transmitted to the decoding unit. The CDR module restores the data
and clock signals after decoding.

In the transmit direction, the SDH signals, which are processed by the SDH overhead
processing module, are transmitted to the encoding unit. The converter isolates the 155
Mbit/s electrical signals (CMI codes) and sends the signals. The encoding and decoding
units monitor R_LOS alarms.

SDH Overhead Processing Module


This module includes the RST, MST, MSA, and HPT sub-modules. This module provides the
inloop and outloop functions.
l

5-66

RST sub-module

In the receive direction, the RST sub-module detects the frame alignment bytes (A1 and
A2), performs descrambling, restores the regenerator section trace byte (J0), detects a
J0 mismatch, and counts BIP-8 errored blocks.

In the transmit direction, the RST sub-module inserts the frame alignment bytes, inserts
the J0 byte, performs scrambling, and performs BIP-8 calculation and insertion.
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MST sub-module

In the receive direction, the MST sub-module counts BIP-24 errored blocks, restores
the MS_REI, and detects the MS_RDI, MS_AIS, and MS-EXC.

In the transmit direction, the MST sub-module performs BIP-24 calculation and
insertion and inserts the MS_REI, MS_RDI, and MS_AIS.

The MST sub-module extracts or inserts the K1, K2, E2, D4D12, S1, B2, and M1
bytes.

MSA sub-module

In the receive direction, the MSA sub-module interprets the AU-4 pointer, detects the
LOP and AIS, and performs pointer justifications.

In the transmit direction, the MSA sub-module assembles the AUG and generates the
AU-4 pointer and the AU_AIS.

HPT sub-module

Terminates the overheads.

Restores the J1 path trace message.

Restores the REI information.

Detects the HP_RDI (monitors the status of the path).

Detects the UNEQ and AIS (monitors the signal label).

Counts the VC-4 BIP-8 errored blocks.

Logic and Control Module


l

Manages and configures the other modules of the board.

Performs inter-board communication through the internal Ethernet interface.

Traces the clock signal from the active and the standby cross-connect unit.

Controls the laser.

Passes the orderwire and ECC bytes through an ADM that consists of two paired slots when
the CXL is not online.

Selects the clock signal and frame header signal from the active and standby cross-connect
units.

Controls the indicators on the board.

DC/DC Converter
It converts the 48/60 V power supply into the DC voltages that the modules of the board
require.

5.8.4 Front Panel


The front panel of the SEP1 has indicators, interfaces, and a bar code.

Diagram of the Front Panel


Figure 5-21 shows the appearance of the front panel of the SEP1.
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Figure 5-21 Front panel of the SEP1

SEP1
STAT
ACT
PROG
SRV

AOUT
AIN
BOUT
BIN

SEP1

Indicators
The front panel of the board has the following indicators:
l

Board hardware status indicator (STAT) two colors (red and green)

Service activation status indicator (ACT) one color (green)

Board software status indicator (PROG) two colors (red and green)

Service alarm indicator (SRV) three colors (red, green, and yellow)

For the meanings of the status of the indicators, see A Indicators.

Interfaces
The front panel of the SEP1 has two pairs of electrical interfaces. Table 5-33 describes the types
and usage of the electrical interfaces of the SEP1.
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Table 5-33 Electrical interfaces of the SEP1


Interface

Type of Interface

Usage

AINBIN

75-ohm SMB

Receives the STM-1 signals.

AOUTBOUT

75-ohm SMB

Transmits the STM-1 signals.

Note: The SEP1 can be used with the interface board EU04, EU08, or OU08. In this case,
the SEP1 is defined as SEP. When the SEP1 is used with the interface board, the two interfaces
on the front panel are invalid.

5.8.5 Valid Slots


When the interfaces are available on the front panel of the SEP1, the SEP1 can be installed in
slots 27 and 1216 in the subrack. When the SEP1 is used with the interface board, it is defined
as SEP. When the SEP is used with the interface board, it can be installed in slots 37 and 12
16 in the subrack.

5.8.6 Board Protection


The TPS protection is equipment-level protection. When the working board fails, the accessed
services are switched to the protection board.
Hence, complex network-level protection operations such as the MSP and SNCP are not
triggered. In addition, the reliability of the equipment is enhanced.
The SEP1 can work with the EU08 and TSB8 to provide two 1:N (N3) TPS protection groups
for 8xSTM-1 electrical signals.
The SEP1 can also work with the EU04 and TSB4 to provide two 1:N (N3) TPS protection
groups for 4xSTM-1 electrical signals.

Protection Principle
When the SEP1 works with the EU08 and TSB8 to realize the TPS protection, the protection
principle and valid slots of the involved boards are the same as the protection principle and valid
slots of the involved boards when the SEP1 works with the EU04 and TSB4 to realize the TPS
protection. This topic considers the TPS protection realized when the SEP1 works with the EU08
and TSB8 as an example to describe the protection principle.
Figure 5-22 shows the TPS protection provided by the SEP1.

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Figure 5-22 TPS protection provided by the SEP1

8xSTM-1(e)

TSB8

8xSTM-1(e)

EU08

8xSTM-1(e)

Sw itching
control
EU08 signal

EU08

Crossconnect
and timing
board
Slot 9/10
Protection
SEP

Working
SEP

Working
SEP

Working
SEP

Failed
Slot 3

Slot 4

Slot 5

Slot 6

Normal state: When each working board functions normally, the traffic signal is directly
transmitted to the SEP1 through position 1 of the control switch on the EU08.

Switching state: When a working board detects a failure and requires the switching
operation, the system protects the working boards in the following manner:

When the working board in slot 5 fails, the control switch of the corresponding EU08
switches from position 1 to position 2. At the same time, the control switch of the TSB8
switches from position 1 to position 2 so that the protection board in slot 3 can protect
the working board in slot 5.

When the working board in slot 4 fails, the control switch of the corresponding EU08
switches from position 1 to position 2, but the control switch of the TSB8 does not act
and is still in position 1. In this case, the protection board in slot 3 protects the working
board in slot 4.

When the working board in slot 6 fails, the control switch of the corresponding EU08
switches from position 1 to position 2. At the same time, the control switch of the TSB8
switches from position 1 to position 3 so that the protection board in slot 3 can protect
the working board in slot 6.

Hardware Configuration
Figure 5-23 shows the slot configuration for two 1:3 TPS protection groups of the SEP1.

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Figure 5-23 Slot configuration for two 1:3 TPS protection groups of the SEP1
S
L
O
T

S
L
O
T

S
L
O
T

S
L
O
T

S
L
O
T

S
L
O
T

2 2 2 2 2 2 2 2
1 2 3 4 5 6 7 8

S
L
O
T

2
9

3
1

3
2

3
3

3
4

3 3 3 3
5 6 7 8

S
L
O
T

3 4
9 0

S
L
O
T

S
L
O
T

11 12 13 14 15 16

S 43 EOW
S 42 AUX

10

S S
L L
O O
T T

Working 2

Working 1

S 41 PIU

S
L
O
T

Protection 2

Working 1

7 8

S
L
O
T

Working 2

S
L
O
T

Working 2

S
L
O
T

CXL

S
L
O
T

FAN

CXL

2 3

Protection 1

S S S S
L L L L
O O O O
T T T T

Working 1

S 1 PIU

S
L
O
T

S
L
O
T

EU08

FAN

S
L
O
T

S
L
O
T

EU08
EU08

FAN
S
L
O
T

3
0

S
L
O
T

TSB8

S
L
O
T

TSB8

S S
L L
O O
T T

EU08

S
L
O
T

EU08

EU08
EU08
EU08

EU08

EU08
TSB8
TSB8

S S
L L
O O
T T

EU08

S
L
O
T

EU08

S
L
O
T

Fiber routing area

In Figure 5-23, the board in slot 3 protects the boards in slots 46. The board in slot 16 protects
the boards in slots 1315.
Table 5-34 lists the slots for the SLH1, EU08, and TSB8.
Table 5-34 Slots for the SEP1, EU08, and TSB8
Board

Protection Group 1

Protection Group 2

SEP1 (protection
board)

Slot 3

Slot 16

TSB8

Slot 21

Slot 40

SLH1 (working
board)

Slots 46

Slots 1315

EU08

Slots 23, 25, and 27

Slots 33, 35, and 37

5.8.7 Parameter Settings


You can set the parameters for the SEP1 by using the T2000.
You can set the following parameters for the SEP1 by using the T2000:
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l

J0

J1

J2

C2

For the description of each parameter, see F Parameter Settings.

5.8.8 Technical Specifications


The technical specifications of the SEP1 include the parameters specified for interfaces,
mechanical specifications, and power consumption.

Parameters Specified for Interfaces


Table 5-35 lists the parameters specified for the interfaces of the SEP1.
Table 5-35 Parameters specified for the interfaces of the SEP1
Parameter

Value

Nominal bit rate

155520 kbit/s

Line code pattern

CMI and NRZ

Connector

SMB

Mechanical Specifications
The mechanical specifications of the SEP1 are as follows:
l

Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)

Weight (kg): 1.0

Power Consumption
The maximum power consumption of the SEP1 at room temperature (25C) is 17 W.

5.9 SL4
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the SL4 (1xSTM-4 optical interface board).
5.9.1 Version Description
The SL4 is available in two functional versions, namely, N1 and N2. The difference between
the two versions is with regard to whether they support the TCM function and AU-3 services.
The N1SL4 is no longer manufactured.
5.9.2 Functions and Features
The SL4 transmits and receives 1xSTM-4 optical signals, performs O/E conversion for the
STM-4 optical signals, extracts and inserts overhead bytes, and generates alarm signals on the
line.
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5.9.3 Working Principle and Signal Flow


The SL4 consists of the O/E converting module, CDR module, SDH overhead processing
module, logic and control module, DC/DC converter, and other modules.
5.9.4 Front Panel
The front panel of the SL4 has indicators, interfaces, a bar code, and a laser safety class label.
5.9.5 Valid Slots
The SL4 can be installed in slots 28 and 1116 in the subrack.
5.9.6 Feature Code
The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the SL4 indicates the type of optical interface.
5.9.7 Parameter Settings
You can set the parameters for the SL4 by using the T2000.
5.9.8 Technical Specifications
The technical specifications of the SL4 include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.

5.9.1 Version Description


The SL4 is available in two functional versions, namely, N1 and N2. The difference between
the two versions is with regard to whether they support the TCM function and AU-3 services.
The N1SL4 is no longer manufactured.
Table 5-36 describes the versions of the SL4.
Table 5-36 Versions of the SL4
Item

Description

Functional versions

The SL4 is available in two functional versions, namely, N1 and N2.

Differences

The N2SL4 supports the TCM function and AU-3 services, but the
TCM function and AU-3 services cannot be available at the same
time.

The N1SL4 does not support the TCM function or AU-3 services.

Substitution

The versions cannot be substituted with each other.

NOTE

When you configure the MSP or SNCP, you cannot configure the N1SL4 as the protection board if the
working board is the N2SL4 on which the TCM function is enabled or AU-3 services are configured.
Otherwise, the services are interrupted when a switching operation is performed.

5.9.2 Functions and Features


The SL4 transmits and receives 1xSTM-4 optical signals, performs O/E conversion for the
STM-4 optical signals, extracts and inserts overhead bytes, and generates alarm signals on the
line.
Table 5-37 provides the functions and features of the SL4.
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Table 5-37 Functions and features of the SL4


Function and
Feature

SL4

Basic functions

Receives and transmits 1xSTM-4 optical signals, and processes


1xSTM-4 standard or concatenation services.

Specifications of
the optical
interface

Supports different types of standard optical interfaces, namely, the


I-4, S-4.1, L-4.1, L-4.2, and Ve-4.2.

The characteristics of the optical interfaces of the I-4, S-4.1, L-4.1,


and L-4.2 types comply with ITU-T G.957.

The characteristics of the optical interface of the Ve-4.2 type comply


with the standards defined by Huawei.

Supports the detection and query of the information about the optical
module.

Provides the ALS function. The optical interface supports the setting
of the on/off state of a laser.

Supports the usage and monitoring of the SFP optical module, which
facilitates the maintenance and upgrading of the optical module.

Supports the VC-12 services, VC-3 services, VC-4 services, and


VC-4-4c concatenation services.

The N2SL4 supports the AU-3 services.

Processes the section overheads of the STM-4 signals.

Supports the transparent transmission and termination of the path


overheads. Supports the setting and query of the J0, J1, J2, and C2
bytes.

Supports one channel of ECC communication.

Specifications of
the optical module

Service
processing

Overhead
processing

Alarms and
performance
events

Reports various alarms and performance events, which facilitates the


management and maintenance of the equipment.

Protection
schemes

Supports the two-fiber ring MSP, four-fiber ring MSP, linear MSP,
SNCP, SNCTP, and SNCMP.

Supports the fiber-shared MSP and SNCP and processes two sets of
K bytes. One SL4 supports a maximum of two MSP protection rings.

Supports inloops and outloops at optical interfaces.

The N1SL4 supports inloops on VC-4 paths.

Supports warm resets and cold resets. The warm reset does not affect
services.

Supports the query of the manufacturing information of the board.

Supports the in-service loading of the FPGA.

Supports the upgrade of the board software without affecting services.

The N2SL4 supports the TCM function.

Supports the press-to-collect function in fault data collection.

Maintenance
features

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5.9.3 Working Principle and Signal Flow


The SL4 consists of the O/E converting module, CDR module, SDH overhead processing
module, logic and control module, DC/DC converter, and other modules.
Figure 5-24 shows the functional block diagram of the .SL4
Figure 5-24 Functional block diagram of the SL4
155 MHz

622 Mbit/s
622 Mbit/s

O/E
E/O

S
P
I

622
Mbit/s

CDR

Reference clock

155 MHz
PLL

622
Mbit/s

K1 and K2

K1 and K2 insertion/extraction

Cross-connect unit

Cross-connect unit

622 Mbit/s
High-speed bus

622 Mbit/s

O/E
E/O

S
P
I

....

....

622 Mbit/s

Cross-connect unit A

622
Mbit/s

CDR

622
Mbit/s

RST

MST

MSA

High-speed
bus

HPT

622 Mbit/s

DCC
SDH overhead processing module

IIC
LOS
Laser shutdown

Logic and
control
module

+3.3 V

DC/DC
converter

Frame header
Communication

Fuse

Cross-connect unit B
SCC unit

Cross-connect unit
SCC unit

-48 V/ -60 V
-48 V/ -60 V

DC/DC
converter

PLL: phase-locked loop

SPI: SDH physical interface

RST: regenerator section


termination

MST: multiplex section termination MSA: multiplex section adaptation

HPT: higher order path termination IIC: inter-integrated circuit

SDH: synchronous digital hierarchy

CDR: clock and data recovery

The functional modules of the STM-4 units are described as follows:

O/E Converting Module


l

In the receive direction, the module converts the received optical signals into electrical
signals.

In the transmit direction, the module converts the electrical signals into SDH optical signals
and sends the SDH optical signals to fibers for transmission.

The SPI detects the R_LOS alarm and provides the function of shutting down the laser.

CDR Module
This module restores the data signal and the clock signal.
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SDH Overhead Processing Module


This module includes the RST, MST, MSA, and HPT sub-modules. This module provides the
inloop and outloop functions.
l

RST sub-module

In the receive direction, the RST sub-module detects the frame alignment bytes (A1 and
A2), performs descrambling, restores the regenerator section trace byte (J0), detects a
J0 mismatch, and counts BIP-8 errored blocks.

In the transmit direction, the RST sub-module inserts the frame alignment bytes, inserts
the J0 byte, performs scrambling, and performs BIP-8 calculation and insertion.

MST sub-module

In the receive direction, the MST sub-module counts BIP-24 errored blocks, restores
the MS_REI, and detects the MS_RDI, MS_AIS, and MS-EXC.

In the transmit direction, the MST sub-module performs BIP-24 calculation and
insertion and inserts the MS_REI, MS_RDI, and MS_AIS.

The MST sub-module extracts or inserts the K1, K2, E2, D4D12, S1, B2, and M1
bytes.

MSA sub-module

In the receive direction, the MSA sub-module interprets the AU-4 pointer, detects the
LOP and AIS, and performs pointer justifications.

In the transmit direction, the MSA sub-module assembles the AUG and generates the
AU-4 pointer and the AU_AIS.

HPT sub-module

Terminates the overheads.

Restores the J1 path trace message.

Restores the REI information.

Detects the HP_RDI (monitors the status of the path).

Detects the UNEQ and AIS (monitors the signal label).

Counts the VC-4 BIP-8 errored blocks.

Logic and Control Module


l

Manages and configures the other modules of the board.

Performs inter-board communication through the internal Ethernet interface.

Traces the clock signal from the active and standby cross-connect units.

Controls the laser.

Passes the orderwire and ECC bytes through an ADM that consists of two paired slots when
the CXL is not online.

Selects the clock signal and frame header signal from the active and standby cross-connect
units.

Controls the indicators on the board.

DC/DC Converter
It converts the 48/60 V power supply into the DC voltages that the modules of the board
require.
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5.9.4 Front Panel


The front panel of the SL4 has indicators, interfaces, a bar code, and a laser safety class label.

Diagram of the Front Panel


Figure 5-25 shows the appearance of the front panel of the SL4.
Figure 5-25 Front panel of the SL4

SL4
STAT
ACT
PROG
SRV

CLASS 1
LASER
PRODUCT

OUT1
IN1

SL4

Indicators
The front panel of the board has the following indicators:
l

Board hardware status indicator (STAT) two colors (red and green)

Service activation status indicator (ACT) one color (green)

Board software status indicator (PROG) two colors (red and green)

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l

Service alarm indicator (SRV) three colors (red, green, and yellow)

For the meanings of the status of the indicators, see A Indicators.

Interfaces
The front panel of the SL4 has one optical interface. Table 5-38 describes the types and usage
of the optical interfaces of the SL4.
Table 5-38 Optical interfaces of the SL4
Interface

Type of
Interface

Usage

IN

LC

Receives optical signals.

OUT

LC

Transmits optical signals.

The SL4 can use the swappable optical modules to facilitate maintenance.

5.9.5 Valid Slots


The SL4 can be installed in slots 28 and 1116 in the subrack.

5.9.6 Feature Code


The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the SL4 indicates the type of optical interface.
Table 5-39 provides the relationship between the feature code of the SL4 and the type of optical
interface.
Table 5-39 Relationship between the feature code of the SL4 and the type of optical interface

5-78

Board

Feature Code

Type of Optical Interface

SSN1SL410 and
SSN2SL410

10

S-4.1

SSN1SL411 and
SSN2SL411

11

L-4.1

SSN1SL412 and
SSN2SL412

12

L-4.2

SSN1SL413 and
SSN2SL413

13

Ve-4.2

SSN1SL414 and
SSN2SL414

14

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5.9.7 Parameter Settings


You can set the parameters for the SL4 by using the T2000.
You can set the following parameters for the SL4 by using the T2000:
l

J0

J1

J2

C2

For the description of each parameter, see F Parameter Settings.

5.9.8 Technical Specifications


The technical specifications of the SL4 include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.

Parameters Specified for Optical Interfaces


Table 5-40 lists the parameters specified for the optical interfaces of the SL4.
Table 5-40 Parameters specified for the optical interfaces of the SL4

Issue 02 (2009-07-30)

Parameter

Value

Nominal bit rate

622080 kbit/s

Line code pattern

NRZ

Application code

I-4

S-4.1

L-4.1

L-4.2

Ve-4.2

Transmission
distance (km)

0 to 2

2 to 15

20 to 40

50 to 80

80 to 100

Type of fiber

Single-mode
LC

Single-mode
LC

Singlemode LC

Singlemode LC

Singlemode LC

Operating
wavelength range
(nm)

1261 to 1360

1274 to 1356

1280 to
1335

1480 to
1580

1480 to
1580

Launched optical
power range
(dBm)

-15 to -8

-15 to -8

-3 to +2

-3 to +2

-3 to +2

Receiver
sensitivity (dBm)

-23

-28

-28

-28

-34

Minimum
overload (dBm)

-8

-8

-8

-8

-13

Minimum
extinction ratio
(dB)

8.2

8.2

10

10

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Laser Safety Class


The safety class of the laser on the board is Class 1. The maximum launched optical power of
the optical interfaces is less than 10 dBm (10 mW).

Mechanical Specifications
The mechanical specifications of the N1SL4 and N2SL4 are as follows:
l

Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)

Weight of the N1SL4 (kg): 0.6

Weight of the N2SL4 (kg): 1.0

Power Consumption
The maximum power consumption of the N1SL4 at room temperature (25C) is 17 W.
The maximum power consumption of the N2SL4 at room temperature (25C) is 15 W.

5.10 SL4A
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the SL4A (1xSTM-4 optical interface board).
5.10.1 Version Description
The SL4A is available in one functional version, namely, N1.
5.10.2 Functions and Features
The SL4A transmits and receives 1xSTM-4 optical signals, performs O/E conversion for the
STM-4 optical signals, extracts and inserts overhead bytes, and generates alarm signals on the
line.
5.10.3 Working Principle and Signal Flow
The SL4A consists of the O/E converting module, CDR module, SDH overhead processing
module, logic and control module, DC/DC converter, and other modules.
5.10.4 Front Panel
The front panel of the SL4A has indicators, interfaces, a bar code, and a laser safety class label.
5.10.5 Valid Slots
The SL4A can be installed in slots 28 and 1116 in the subrack.
5.10.6 Feature Code
The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the SL4A indicates the type of optical interface.
5.10.7 Parameter Settings
You can set the parameters for the SL4A by using the T2000.
5.10.8 Technical Specifications
The technical specifications of the SL4A include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.

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5.10.1 Version Description


The SL4A is available in one functional version, namely, N1.

5.10.2 Functions and Features


The SL4A transmits and receives 1xSTM-4 optical signals, performs O/E conversion for the
STM-4 optical signals, extracts and inserts overhead bytes, and generates alarm signals on the
line.
Table 5-41 provides the functions and features of the SL4A.
Table 5-41 Functions and features of the SL4A
Function and
Feature

SL4A

Basic functions

Receives and transmits 1xSTM-4 optical signals, and processes


1xSTM-4 standard or concatenation services.

Specifications of
the optical
interface

Supports different types of standard optical interfaces, namely, the


I-4, S-4.1, L-4.1, L-4.2, and Ve-4.2.

The characteristics of the optical interfaces of the I-4, S-4.1, L-4.1,


and L-4.2 types comply with ITU-T G.957.

The characteristics of the optical interface of the Ve-4.2 type comply


with the standards defined by Huawei.

Supports the detection and query of the information about the optical
module.

Provides the ALS function. The optical interface supports the setting
of the on/off state of a laser.

Supports the usage and monitoring of the SFP optical module, which
facilitates the maintenance and upgrading of the optical module.

Specifications of
the optical module

Service
processing

Supports the VC-12 services, VC-3 services, VC-4 services, and


VC-4-4c concatenation services.

Overhead
processing

Processes the section overheads of the STM-4 signals.

Supports the transparent transmission and termination of the path


overheads. Supports the setting and query of the J0, J1, J2, and C2
bytes.

Supports one channel of ECC communication.

Supports the time synchronization feature and transmission of the


time information by using the section overhead bytes.

Alarms and
performance
events

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Reports various alarms and performance events, which facilitates the


management and maintenance of the equipment.

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Function and
Feature

SL4A

Protection
schemes

Supports the two-fiber ring MSP, four-fiber ring MSP, linear MSP,
SNCP, SNCTP, and SNCMP.

Supports the fiber-shared MSP and SNCP and processes two sets of
K bytes. One SL4A supports a maximum of two MSP protection rings.

Supports inloops and outloops at optical interfaces.

Supports inloops and outloops on VC-4 paths.

Supports warm resets and cold resets. The warm reset does not affect
services.

Supports the query of the manufacturing information of the board.

Supports the in-service loading of the FPGA.

Supports the upgrade of the board software without affecting services.

Supports the press-to-collect function in fault data collection.

Maintenance
features

5.10.3 Working Principle and Signal Flow


The SL4A consists of the O/E converting module, CDR module, SDH overhead processing
module, logic and control module, DC/DC converter, and other modules.
Figure 5-26 shows the functional block diagram of the SL4A.

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Figure 5-26 Functional block diagram of the SL4A


155 MHz

622 Mbit/s
622 Mbit/s

O/E
E/O

S
P
I

622
Mbit/s

CDR

Reference clock

155 MHz
PLL

622
Mbit/s

K1 and K2

K1 and K2 insertion/extraction

Cross-connect unit

Cross-connect unit

622 Mbit/s
High-speed bus

622 Mbit/s

O/E
E/O

S
P
I

....

....

622 Mbit/s

Cross-connect unit A

622
Mbit/s

CDR

622
Mbit/s

RST

MST

MSA

High-speed
bus

HPT

622 Mbit/s

DCC
SDH overhead processing module

IIC
LOS
Laser shutdown

Logic and
control
module

+3.3 V

DC/DC
converter

Frame header
Communication

Fuse

Cross-connect unit B
SCC unit

Cross-connect unit
SCC unit

-48 V/ -60 V
-48 V/ -60 V

DC/DC
converter

PLL: phase-locked loop

SPI: SDH physical interface

RST: regenerator section


termination

MST: multiplex section termination MSA: multiplex section adaptation

HPT: higher order path termination IIC: inter-integrated circuit

SDH: synchronous digital hierarchy

CDR: clock and data recovery

The functional modules of the STM-4 units are described as follows:

O/E Converting Module


l

In the receive direction, the module converts the received optical signals into electrical
signals.

In the transmit direction, the module converts the electrical signals into SDH optical signals
and sends the SDH optical signals to fibers for transmission.

The SPI detects the R_LOS alarm and provides the function of shutting down the laser.

CDR Module
This module restores the data signal and the clock signal.

SDH Overhead Processing Module


This module includes the RST, MST, MSA, and HPT sub-modules. This module provides the
inloop and outloop functions.
l

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RST sub-module
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In the receive direction, the RST sub-module detects the frame alignment bytes (A1 and
A2), performs descrambling, restores the regenerator section trace byte (J0), detects a
J0 mismatch, and counts BIP-8 errored blocks.

In the transmit direction, the RST sub-module inserts the frame alignment bytes, inserts
the J0 byte, performs scrambling, and performs BIP-8 calculation and insertion.

MST sub-module

In the receive direction, the MST sub-module counts BIP-24 errored blocks, restores
the MS_REI, and detects the MS_RDI, MS_AIS, and MS-EXC.

In the transmit direction, the MST sub-module performs BIP-24 calculation and
insertion and inserts the MS_REI, MS_RDI, and MS_AIS.

The MST sub-module extracts or inserts the K1, K2, E2, D4D12, S1, B2, and M1
bytes.

MSA sub-module

In the receive direction, the MSA sub-module interprets the AU-4 pointer, detects the
LOP and AIS, and performs pointer justifications.

In the transmit direction, the MSA sub-module assembles the AUG and generates the
AU-4 pointer and the AU_AIS.

HPT sub-module

Terminates the overheads.

Restores the J1 path trace message.

Restores the REI information.

Detects the HP_RDI (monitors the status of the path).

Detects the UNEQ and AIS (monitors the signal label).

Counts the VC-4 BIP-8 errored blocks.

Logic and Control Module


l

Manages and configures the other modules of the board.

Performs inter-board communication through the internal Ethernet interface.

Traces the clock signal from the active and standby cross-connect units.

Controls the laser.

Passes the orderwire and ECC bytes through an ADM that consists of two paired slots when
the CXL is not online.

Selects the clock signal and frame header signal from the active and standby cross-connect
units.

Controls the indicators on the board.

DC/DC Converter
It converts the 48/60 V power supply into the DC voltages that the modules of the board
require.

5.10.4 Front Panel


The front panel of the SL4A has indicators, interfaces, a bar code, and a laser safety class label.
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Diagram of the Front Panel


Figure 5-27 shows the appearance of the front panel of the SL4A.
Figure 5-27 Front panel of the SL4A

SL4A
STAT
ACT
PROG
SRV

CLASS 1
LASER
PRODUCT

OUT1
IN1

SL4A

Indicators
The front panel of the board has the following indicators:
l

Board hardware status indicator (STAT) two colors (red and green)

Service activation status indicator (ACT) one color (green)

Board software status indicator (PROG) two colors (red and green)

Service alarm indicator (SRV) three colors (red, green, and yellow)

For the meanings of the status of the indicators, see A Indicators.


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Interfaces
The front panel of the SL4A has one optical interface. Table 5-42 describes the types and usage
of the optical interfaces of the SL4A.
Table 5-42 Optical interfaces of the SL4A
Interface

Type of
Interface

Usage

IN

LC

Receives optical signals.

OUT

LC

Transmits optical signals.

The SL4A can use the swappable optical modules to facilitate maintenance.

5.10.5 Valid Slots


The SL4A can be installed in slots 28 and 1116 in the subrack.

5.10.6 Feature Code


The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the SL4A indicates the type of optical interface.
Table 5-43 provides the relationship between the feature code of the SL4A and the type of optical
interface.
Table 5-43 Relationship between the feature code of the SL4A and the type of optical interface
Board

Feature Code

Type of Optical Interface

SSN1SL4A10

10

S-4.1

SSN1SL4A11

11

L-4.1

SSN1SL4A12

12

L-4.2

SSN1SL4A13

13

Ve-4.2

SSN1SL4A14

14

I-4

5.10.7 Parameter Settings


You can set the parameters for the SL4A by using the T2000.
You can set the following parameters for the SL4A by using the T2000:

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J0

J1

J2
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C2

For the description of each parameter, see F Parameter Settings.

5.10.8 Technical Specifications


The technical specifications of the SL4A include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.

Parameters Specified for Optical Interfaces


Table 5-44 lists the parameters specified for the optical interfaces of the SL4A.
Table 5-44 Parameters specified for the optical interfaces of the SL4A
Parameter

Value

Nominal bit rate

622080 kbit/s

Line code pattern

NRZ

Application code

I-4

S-4.1

L-4.1

L-4.2

Ve-4.2

Transmission
distance (km)

0 to 2

2 to 15

20 to 40

50 to 80

80 to 100

Type of fiber

Single-mode
LC

Single-mode
LC

Singlemode LC

Singlemode LC

Singlemode LC

Operating
wavelength range
(nm)

1261 to 1360

1274 to 1356

1280 to
1335

1480 to
1580

1480 to
1580

Launched optical
power range
(dBm)

-15 to -8

-15 to -8

-3 to +2

-3 to +2

-3 to +2

Receiver
sensitivity (dBm)

-23

-28

-28

-28

-34

Minimum
overload (dBm)

-8

-8

-8

-8

-13

Minimum
extinction ratio
(dB)

8.2

8.2

10

10

10.5

Laser Safety Class


The safety class of the laser on the board is Class 1. The maximum launched optical power of
the optical interfaces is less than 10 dBm (10 mW).

Mechanical Specifications
The mechanical specifications of the SL4A are as follows:
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l

Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)

Weight (kg): 0.6

Power Consumption
The maximum power consumption of the SL4A at room temperature (25C) is 17 W.

5.11 SLD4
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the SLD4 (2xSTM-4 optical interface board).
5.11.1 Version Description
The SLD4 is available in two functional versions, namely, N1 and N2. The difference between
the two versions is with regard to whether they support the TCM function and AU-3 services.
The N1SLD4 is no longer manufactured.
5.11.2 Functions and Features
The SLD4 transmits and receives 2xSTM-4 optical signals, performs O/E conversion for the
STM-4 optical signals, extracts and inserts overhead bytes, and generates alarm signals on the
line.
5.11.3 Working Principle and Signal Flow
The SLD4 consists of the O/E converting module, CDR module, SDH overhead processing
module, logic and control module, DC/DC converter, and other modules.
5.11.4 Front Panel
The front panel of the SLD4 has indicators, interfaces, a bar code, and a laser safety class label.
5.11.5 Valid Slots
The SLD4 can be installed in slots 28 and 1116 in the subrack.
5.11.6 Feature Code
The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the SLD4 indicates the type of optical interface.
5.11.7 Parameter Settings
You can set the parameters for the SLD4 by using the T2000.
5.11.8 Technical Specifications
The technical specifications of the SLD4 include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.

5.11.1 Version Description


The SLD4 is available in two functional versions, namely, N1 and N2. The difference between
the two versions is with regard to whether they support the TCM function and AU-3 services.
The N1SLD4 is no longer manufactured.
Table 5-45 describes the versions of the SLD4.

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Table 5-45 Versions of the SLD4


Item

Description

Functional versions

The SLD4 is available in two functional versions, namely, N1 and


N2.

Differences

The N2SLD4 supports the TCM function and AU-3 services, but
the TCM function and AU-3 services cannot be available at the
same time.

The N1SLD4 does not support the TCM function or AU-3


services.

Substitution

The versions cannot be substituted with each other.

NOTE

When you configure the MSP or SNCP, you cannot configure the N1SLD4 as the protection board if the
working board is the N2SLD4 on which the TCM function is enabled or AU-3 services are configured.
Otherwise, the services are interrupted when a switching operation is performed.

5.11.2 Functions and Features


The SLD4 transmits and receives 2xSTM-4 optical signals, performs O/E conversion for the
STM-4 optical signals, extracts and inserts overhead bytes, and generates alarm signals on the
line.
Table 5-46 provides the functions and features of the SLD4.
Table 5-46 Functions and features of the SLD4
Function and
Feature

SLD4

Basic functions

Receives and transmits 2xSTM-4 optical signals, and processes


2xSTM-4 standard or concatenation services.

Specifications of
the optical
interface

Supports different types of standard optical interfaces, namely, the


I-4, S-4.1, L-4.1, L-4.2, and Ve-4.2.

The characteristics of the optical interfaces of the I-4, S-4.1, L-4.1,


and L-4.2 types comply with ITU-T G.957.

The characteristics of the optical interface of the Ve-4.2 type comply


with the standards defined by Huawei.

Supports the detection and query of the information about the optical
module.

Provides the ALS function. The optical interface supports the setting
of the on/off state of a laser.

Supports the usage and monitoring of the SFP optical module, which
facilitates the maintenance and upgrading of the optical module.

Specifications of
the optical module

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Function and
Feature

SLD4

Service
processing

Supports the VC-12 services, VC-3 services, VC-4 services, and


VC-4-4c concatenation services.

The N2SLD4 supports the AU-3 services.

Processes the section overheads of the STM-4 signals.

Supports the transparent transmission and termination of the path


overheads.

Supports the setting and query of the J0, J1, J2, and C2 bytes.

Supports one or two channels of ECC communication.

Overhead
processing

Alarms and
performance
events

Reports various alarms and performance events, which facilitates the


management and maintenance of the equipment.

Protection
schemes

Supports the two-fiber ring MSP, four-fiber ring MSP, linear MSP,
SNCP, SNCTP, and SNCMP.

Supports the fiber-shared MSP and SNCP and processes four sets of
K bytes. A single optical interface supports two MSP protection rings,
and one SLD4 supports a maximum of four MSP protection rings.

Supports inloops and outloops at optical interfaces.

The N1SLD4 supports inloops on VC-4 paths.

Supports warm resets and cold resets. The warm reset does not affect
services.

Supports the query of the manufacturing information of the board.

Supports the in-service loading of the FPGA.

Supports the upgrade of the board software without affecting services.

The N2SLD4 supports the TCM function.

Supports the press-to-collect function in fault data collection.

Maintenance
features

5.11.3 Working Principle and Signal Flow


The SLD4 consists of the O/E converting module, CDR module, SDH overhead processing
module, logic and control module, DC/DC converter, and other modules.
Figure 5-28 shows the functional block diagram of the SLD4.

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Figure 5-28 Functional block diagram of the SLD4


155 MHz

622 Mbit/s
622 Mbit/s

O/E
E/O

S
P
I

622
Mbit/s

CDR

Reference clock

155 MHz
PLL

622
Mbit/s

K1 and K2

K1 and K2 insertion/extraction

Cross-connect unit

Cross-connect unit

622 Mbit/s
High-speed bus

622 Mbit/s

O/E
E/O

S
P
I

....

....

622 Mbit/s

Cross-connect unit A

622
Mbit/s

CDR

622
Mbit/s

RST

MST

MSA

High-speed
bus

HPT

622 Mbit/s

DCC
SDH overhead processing module

IIC
LOS
Laser shutdown

Logic and
control
module

+3.3 V

DC/DC
converter

Frame header
Communication

Fuse

Cross-connect unit B
SCC unit

Cross-connect unit
SCC unit

-48 V/ -60 V
-48 V/ -60 V

DC/DC
converter

PLL: phase-locked loop

SPI: SDH physical interface

RST: regenerator section


termination

MST: multiplex section termination MSA: multiplex section adaptation

HPT: higher order path termination IIC: inter-integrated circuit

SDH: synchronous digital hierarchy

CDR: clock and data recovery

The functional modules of the STM-4 units are described as follows:

O/E Converting Module


l

In the receive direction, the module converts the received optical signals into electrical
signals.

In the transmit direction, the module converts the electrical signals into SDH optical signals
and sends the SDH optical signals to fibers for transmission.

The SPI detects the R_LOS alarm and provides the function of shutting down the laser.

CDR Module
This module restores the data signal and the clock signal.

SDH Overhead Processing Module


This module includes the RST, MST, MSA, and HPT sub-modules. This module provides the
inloop and outloop functions.
l

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In the receive direction, the RST sub-module detects the frame alignment bytes (A1 and
A2), performs descrambling, restores the regenerator section trace byte (J0), detects a
J0 mismatch, and counts BIP-8 errored blocks.

In the transmit direction, the RST sub-module inserts the frame alignment bytes, inserts
the J0 byte, performs scrambling, and performs BIP-8 calculation and insertion.

MST sub-module

In the receive direction, the MST sub-module counts BIP-24 errored blocks, restores
the MS_REI, and detects the MS_RDI, MS_AIS, and MS-EXC.

In the transmit direction, the MST sub-module performs BIP-24 calculation and
insertion and inserts the MS_REI, MS_RDI, and MS_AIS.

The MST sub-module extracts or inserts the K1, K2, E2, D4D12, S1, B2, and M1
bytes.

MSA sub-module

In the receive direction, the MSA sub-module interprets the AU-4 pointer, detects the
LOP and AIS, and performs pointer justifications.

In the transmit direction, the MSA sub-module assembles the AUG and generates the
AU-4 pointer and the AU_AIS.

HPT sub-module

Terminates the overheads.

Restores the J1 path trace message.

Restores the REI information.

Detects the HP_RDI (monitors the status of the path).

Detects the UNEQ and AIS (monitors the signal label).

Counts the VC-4 BIP-8 errored blocks.

Logic and Control Module


l

Manages and configures the other modules of the board.

Performs inter-board communication through the internal Ethernet interface.

Traces the clock signal from the active and standby cross-connect units.

Controls the laser.

Passes the orderwire and ECC bytes through an ADM that consists of two paired slots when
the CXL is not online.

Selects the clock signal and frame header signal from the active and standby cross-connect
units.

Controls the indicators on the board.

DC/DC Converter
It converts the 48/60 V power supply into the DC voltages that the modules of the board
require.

5.11.4 Front Panel


The front panel of the SLD4 has indicators, interfaces, a bar code, and a laser safety class label.
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Diagram of the Front Panel


Figure 5-29 shows the appearance of the front panel of the SLD4.
Figure 5-29 Front panel of the SLD4

SLD4
STAT
ACT
PROG
SRV

CLASS 1
LASER
PRODUCT

OUT1
IN1
OUT2
IN2

SLD4

Indicators
The front panel of the board has the following indicators:
l

Board hardware status indicator (STAT) two colors (red and green)

Service activation status indicator (ACT) one color (green)

Board software status indicator (PROG) two colors (red and green)

Service alarm indicator (SRV) three colors (red, green, and yellow)

For the meanings of the status of the indicators, see A Indicators.


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Interfaces
The front panel of the SLD4 has two optical interfaces. Table 5-47 describes the types and usage
of the optical interfaces of the SLD4.
Table 5-47 Optical interfaces of the SLD4
Interface

Type of
Interface

Usage

IN1-IN2

LC

Receives optical signals.

OUT1-OUT2

LC

Transmits optical signals.

The SLD4 can use the swappable optical modules to facilitate maintenance.

5.11.5 Valid Slots


The SLD4 can be installed in slots 28 and 1116 in the subrack.

5.11.6 Feature Code


The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the SLD4 indicates the type of optical interface.
Table 5-48 provides the relationship between the feature code of the SLD4 and the type of optical
interface.
Table 5-48 Relationship between the feature code of the SLD4 and the type of optical interface
Board

Feature Code

Type of Optical Interface

SSN1SLD410 and
SSN2SLD410

10

S-4.1

SSN1SLD411 and
SSN2SLD411

11

L-4.1

SSN1SLD412 and
SSN2SLD412

12

L-4.2

SSN1SLD413 and
SSN2SLD413

13

Ve-4.2

SSN1SLD414 and
SSN2SLD414

14

I-4

5.11.7 Parameter Settings


You can set the parameters for the SLD4 by using the T2000.
You can set the following parameters for the SLD4 by using the T2000:
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J0

J1

J2

C2

5 SDH Boards

For the description of each parameter, see F Parameter Settings.

5.11.8 Technical Specifications


The technical specifications of the SLD4 include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.

Parameters Specified for Optical Interfaces


Table 5-49 lists the parameters specified for the optical interfaces of the SLD4.
Table 5-49 Parameters specified for the optical interfaces of the SLD4

Issue 02 (2009-07-30)

Parameter

Value

Nominal bit rate

622080 kbit/s

Line code
pattern

NRZ

Application
code

I-4

S-4.1

L-4.1

L-4.2

Ve-4.2

Transmission
distance (km)

0 to 2

2 to 15

20 to 40

50 to 80

80 to 100

Type of fiber

Singlemode LC

Singlemode LC

Singlemode LC

Singlemode LC

Single-mode
LC

Operating
wavelength
range (nm)

1261 to
1360

1274 to
1356

1280 to
1335

1480 to
1580

1480 to 1580

Launched
optical power
range (dBm)

-15 to -8

-15 to -8

-3 to +2

-3 to +2

-3 to +2

Receiver
sensitivity
(dBm)

-23

-28

-28

-28

-34

Minimum
overload (dBm)

-8

-8

-8

-8

-13

Minimum
extinction ratio
(dB)

8.2

8.2

10

10

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Laser Safety Class


The safety class of the laser on the board is Class 1. The maximum launched optical power of
the optical interfaces is less than 10 dBm (10 mW).

Mechanical Specifications
The mechanical specifications of the N1SLD4 and N2SLD4 are as follows:
l

Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)

Weight of the N1SLD4 (kg): 0.6

Weight of the N2SLD4 (kg): 1.0

Power Consumption
The maximum power consumption of the N1SLD4 at room temperature (25C) is 17 W.
The maximum power consumption of the N2SLD4 at room temperature (25C) is 15 W.

5.12 SLD4A
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the SLD4A (2xSTM-4 optical interface board).
5.12.1 Version Description
The SLD4A is available in one functional version, namely, N1.
5.12.2 Functions and Features
The SLD4A transmits and receives STM-4 optical signals, performs O/E conversion for the
STM-4 optical signals, extracts and inserts overhead bytes, and generates alarm signals on the
line.
5.12.3 Working Principle and Signal Flow
The SLD4A consists of the O/E converting module, CDR module, SDH overhead processing
module, logic and control module, DC/DC converter, and other modules.
5.12.4 Front Panel
The front panel of the SLD4A has indicators, interfaces, a bar code, and a laser safety class label.
5.12.5 Valid Slots
The SLD4A can be installed in slots 28 and 1116 in the subrack.
5.12.6 Feature Code
The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the SLD4A indicates the type of optical interface.
5.12.7 Parameter Settings
You can set the parameters for the SLD4A by using the T2000.
5.12.8 Technical Specifications
The technical specifications of the SLD4A include the parameters specified for optical
interfaces, laser safety class, mechanical specifications, and power consumption.

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5.12.1 Version Description


The SLD4A is available in one functional version, namely, N1.

5.12.2 Functions and Features


The SLD4A transmits and receives STM-4 optical signals, performs O/E conversion for the
STM-4 optical signals, extracts and inserts overhead bytes, and generates alarm signals on the
line.
Table 5-50 provides the functions and features of the SLD4A.
Table 5-50 Functions and features of the SLD4A
Function and
Feature

SLD4A

Basic functions

Receives and transmits 2xSTM-4 optical signals, and processes


2xSTM-4 standard or concatenation services.

Specifications of
the optical
interface

Supports different types of standard optical interfaces, namely, the


I-4, S-4.1, L-4.1, L-4.2, and Ve-4.2.

The characteristics of the optical interfaces of the I-4, S-4.1, L-4.1,


and L-4.2 types comply with ITU-T G.957.

The characteristics of the optical interface of the Ve-4.2 type comply


with the standards defined by Huawei.

Supports the detection and query of the information about the optical
module.

Provides the ALS function. The optical interface supports the setting
of the on/off state of a laser.

Supports the usage and monitoring of the SFP optical module, which
facilitates the maintenance and upgrading of the optical module.

Specifications of
the optical module

Service
processing

Supports the VC-12 services, VC-3 services, VC-4 services, and


VC-4-4c concatenation services.

Overhead
processing

Processes the section overheads of the STM-4 signals.

Supports the transparent transmission and termination of the path


overheads.

Supports the setting and query of the J0, J1, J2, and C2 bytes.

Supports one or two channels of ECC communication.

Supports the time synchronization feature and transmission of the


time information by using the section overhead bytes.

Alarms and
performance
events

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Reports various alarms and performance events, which facilitates the


management and maintenance of the equipment.

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Function and
Feature

SLD4A

Protection
schemes

Supports the two-fiber ring MSP, four-fiber ring MSP, linear MSP,
SNCP, SNCTP, and SNCMP.

Supports the fiber-shared MSP and SNCP and processes four sets of
K bytes. A single optical interface supports two MSP protection rings,
and one SLD4A supports a maximum of four MSP protection rings.

Supports inloops and outloops at optical interfaces.

Supports inloops and outloops on VC-4 paths.

Supports warm resets and cold resets. The warm reset does not affect
services.

Supports the query of the manufacturing information of the board.

Supports the in-service loading of the FPGA.

Supports the upgrade of the board software without affecting services.

Supports the press-to-collect function in fault data collection.

Maintenance
features

5.12.3 Working Principle and Signal Flow


The SLD4A consists of the O/E converting module, CDR module, SDH overhead processing
module, logic and control module, DC/DC converter, and other modules.
Figure 5-30 shows the functional block diagram of the SLD4A.

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Figure 5-30 Functional block diagram of the SLD4A


155 MHz

622 Mbit/s
622 Mbit/s

O/E
E/O

S
P
I

622
Mbit/s

CDR

Reference clock

155 MHz
PLL

622
Mbit/s

K1 and K2

K1 and K2 insertion/extraction

Cross-connect unit

Cross-connect unit

622 Mbit/s
High-speed bus

622 Mbit/s

O/E
E/O

S
P
I

....

....

622 Mbit/s

Cross-connect unit A

622
Mbit/s

CDR

622
Mbit/s

RST

MST

MSA

High-speed
bus

HPT

622 Mbit/s

DCC
SDH overhead processing module

IIC
LOS
Laser shutdown

Logic and
control
module

+3.3 V

DC/DC
converter

Frame header
Communication

Fuse

Cross-connect unit B
SCC unit

Cross-connect unit
SCC unit

-48 V/ -60 V
-48 V/ -60 V

DC/DC
converter

PLL: phase-locked loop

SPI: SDH physical interface

RST: regenerator section


termination

MST: multiplex section termination MSA: multiplex section adaptation

HPT: higher order path termination IIC: inter-integrated circuit

SDH: synchronous digital hierarchy

CDR: clock and data recovery

The functional modules of the STM-4 units are described as follows:

O/E Converting Module


l

In the receive direction, the module converts the received optical signals into electrical
signals.

In the transmit direction, the module converts the electrical signals into SDH optical signals
and sends the SDH optical signals to fibers for transmission.

The SPI detects the R_LOS alarm and provides the function of shutting down the laser.

CDR Module
This module restores the data signal and the clock signal.

SDH Overhead Processing Module


This module includes the RST, MST, MSA, and HPT sub-modules. This module provides the
inloop and outloop functions.
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RST sub-module
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In the receive direction, the RST sub-module detects the frame alignment bytes (A1 and
A2), performs descrambling, restores the regenerator section trace byte (J0), detects a
J0 mismatch, and counts BIP-8 errored blocks.

In the transmit direction, the RST sub-module inserts the frame alignment bytes, inserts
the J0 byte, performs scrambling, and performs BIP-8 calculation and insertion.

MST sub-module

In the receive direction, the MST sub-module counts BIP-24 errored blocks, restores
the MS_REI, and detects the MS_RDI, MS_AIS, and MS-EXC.

In the transmit direction, the MST sub-module performs BIP-24 calculation and
insertion and inserts the MS_REI, MS_RDI, and MS_AIS.

The MST sub-module extracts or inserts the K1, K2, E2, D4D12, S1, B2, and M1
bytes.

MSA sub-module

In the receive direction, the MSA sub-module interprets the AU-4 pointer, detects the
LOP and AIS, and performs pointer justifications.

In the transmit direction, the MSA sub-module assembles the AUG and generates the
AU-4 pointer and the AU_AIS.

HPT sub-module

Terminates the overheads.

Restores the J1 path trace message.

Restores the REI information.

Detects the HP_RDI (monitors the status of the path).

Detects the UNEQ and AIS (monitors the signal label).

Counts the VC-4 BIP-8 errored blocks.

Logic and Control Module


l

Manages and configures the other modules of the board.

Performs inter-board communication through the internal Ethernet interface.

Traces the clock signal from the active and standby cross-connect units.

Controls the laser.

Passes the orderwire and ECC bytes through an ADM that consists of two paired slots when
the CXL is not online.

Selects the clock signal and frame header signal from the active and standby cross-connect
units.

Controls the indicators on the board.

DC/DC Converter
It converts the 48/60 V power supply into the DC voltages that the modules of the board
require.

5.12.4 Front Panel


The front panel of the SLD4A has indicators, interfaces, a bar code, and a laser safety class label.
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Diagram of the Front Panel


Figure 5-31 shows the appearance of the front panel of the SLD4A.
Figure 5-31 Front panel of the SLD4A

SLD4A
STAT
ACT
PROG
SRV

CLASS 1
LASER
PRODUCT

OUT1
IN1
OUT2
IN2

SLD4A

Indicators
The front panel of the board has the following indicators:
l

Board hardware status indicator (STAT) two colors (red and green)

Service activation status indicator (ACT) one color (green)

Board software status indicator (PROG) two colors (red and green)

Service alarm indicator (SRV) three colors (red, green, and yellow)

For the meanings of the status of the indicators, see A Indicators.


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Interfaces
The front panel of the SLD4A has two optical interfaces. Table 5-51 describes the types and
usage of the optical interfaces of the SLD4A.
Table 5-51 Optical interfaces of the SLD4A
Interface

Type of
Interface

Usage

IN1IN2

LC

Receives optical signals.

OUT1OUT2

LC

Transmits optical signals.

The SLD4A can use the swappable optical modules to facilitate maintenance.

5.12.5 Valid Slots


The SLD4A can be installed in slots 28 and 1116 in the subrack.

5.12.6 Feature Code


The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the SLD4A indicates the type of optical interface.
Table 5-52 provides the relationship between the feature code of the SLD4A and the type of
optical interface.
Table 5-52 Relationship between the feature code of the SLD4A and the type of optical interface
Board

Feature Code

Type of Optical Interface

SSN1SLD4A10

10

S-4.1

SSN1SLD4A11

11

L-4.1

SSN1SLD4A12

12

L-4.2

SSN1SLD4A13

13

Ve-4.2

SSN1SLD4A14

14

I-4

5.12.7 Parameter Settings


You can set the parameters for the SLD4A by using the T2000.
You can set the following parameters for the SLD4A by using the T2000:

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J1

J2
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C2

For the description of each parameter, see F Parameter Settings.

5.12.8 Technical Specifications


The technical specifications of the SLD4A include the parameters specified for optical
interfaces, laser safety class, mechanical specifications, and power consumption.

Parameters Specified for Optical Interfaces


Table 5-53 lists the parameters specified for the optical interfaces of the SLD4A.
Table 5-53 Parameters specified for the optical interfaces of the SLD4A
Parameter

Value

Nominal bit rate

622080 kbit/s

Line code
pattern

NRZ

Application
code

I-4

S-4.1

L-4.1

L-4.2

Ve-4.2

Transmission
distance (km)

0 to 2

2 to 15

20 to 40

50 to 80

80 to 100

Type of fiber

Singlemode LC

Singlemode LC

Singlemode LC

Singlemode LC

Single-mode
LC

Operating
wavelength
range (nm)

1261 to
1360

1274 to
1356

1280 to
1335

1480 to
1580

1480 to 1580

Launched
optical power
range (dBm)

-15 to -8

-15 to -8

-3 to +2

-3 to +2

-3 to +2

Receiver
sensitivity
(dBm)

-23

-28

-28

-28

-34

Minimum
overload (dBm)

-8

-8

-8

-8

-13

Minimum
extinction ratio
(dB)

8.2

8.2

10

10

10.5

Laser Safety Class


The safety class of the laser on the board is Class 1. The maximum launched optical power of
the optical interfaces is less than 10 dBm (10 mW).
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Mechanical Specifications
The mechanical specifications of the SLD4A are as follows:
l

Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)

Weight (kg): 0.6

Power Consumption
The maximum power consumption of the SLD4A at room temperature (25C) is 17 W.

5.13 SLQ4
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the SLQ4 (4xSTM-4 optical interface board).
5.13.1 Version Description
The SLQ4 is available in two functional versions, namely, N1 and N2. The difference between
the two versions is with regard to whether they support the TCM function and AU-3 services.
The N1SLQ4 is no longer manufactured.
5.13.2 Functions and Features
The SLQ4 transmits and receives STM-4 optical signals, performs O/E conversion for the
STM-4 optical signals, extracts and inserts overhead bytes, and generates alarm signals on the
line.
5.13.3 Working Principle and Signal Flow
The SLQ4 consists of the O/E converting module, CDR module, SDH overhead processing
module, logic and control module, DC/DC converter, and other modules.
5.13.4 Front Panel
The front panel of the SLQ4 has indicators, interfaces, a bar code, and a laser safety class label.
5.13.5 Valid Slots
The SLQ4 can be installed in slots 28 and 1116 in the subrack.
5.13.6 Feature Code
The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the SLQ4 indicates the type of optical interface.
5.13.7 Parameter Settings
You can set the parameters for the SLQ4 by using the T2000.
5.13.8 Technical Specifications
The technical specifications of the SLQ4 include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.

5.13.1 Version Description


The SLQ4 is available in two functional versions, namely, N1 and N2. The difference between
the two versions is with regard to whether they support the TCM function and AU-3 services.
The N1SLQ4 is no longer manufactured.
Table 5-54 describes the versions of the SLQ4.
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Table 5-54 Versions of the SLQ4


Item

Description

Functional
versions

The SLQ4 is available in two functional versions, namely, N1 and N2.

Differences

The N2SLQ4 supports the TCM function and AU-3 services, but the
TCM function and AU-3 services cannot be available at the same
time.

The N1SLQ4 does not support the TCM function or AU-3 services.

Substitution

The versions cannot be substituted with each other.

NOTE

When you configure the MSP or SNCP, you cannot configure the N1SLQ4 as the protection board if the
working board is the N2SLQ4 on which the TCM function is enabled or AU-3 services are configured.
Otherwise, the services are interrupted when a switching operation is performed.

5.13.2 Functions and Features


The SLQ4 transmits and receives STM-4 optical signals, performs O/E conversion for the
STM-4 optical signals, extracts and inserts overhead bytes, and generates alarm signals on the
line.
Table 5-55 provides the functions and features of the SLQ4.
Table 5-55 Functions and features of the SLQ4
Function and
Feature

SLQ4

Basic functions

Transmits and receives 4xSTM-4 optical signals.

Specifications of
the optical
interface

Supports different types of standard optical interfaces, namely, the I-4,


S-4.1, L-4.1, L-4.2, and Ve-4.2.

The characteristics of the optical interfaces of the I-4, S-4.1, L-4.1, and
L-4.2 types comply with ITU-T G.957.

The characteristics of the optical interface of the Ve-4.2 type comply


with the standards defined by Huawei.

Supports the detection and query of the information about the optical
module.

Provides the ALS function. The optical interface supports the setting
of the on/off state of a laser.

Supports the usage and monitoring of the SFP optical module, which
facilitates the maintenance and upgrading of the optical module.

Supports the VC-12 services, VC-3 services, VC-4 services, and


VC-4-4c concatenation services.

The N2SLQ4 supports the AU-3 services.

Specifications of
the optical
module

Service
processing

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Function and
Feature

SLQ4

Overhead
processing

Processes the section overheads of the STM-4 signals.

Supports the transparent transmission and termination of the path


overheads.

Supports the setting and query of the J0, J1, J2, and C2 bytes.

Supports one to four channels of ECC communication.

Alarms and
performance
events

Reports various alarms and performance events, which facilitates the


management and maintenance of the equipment.

Protection
schemes

Supports the two-fiber ring MSP, four-fiber ring MSP, linear MSP,
SNCP, SNCTP, and SNCMP.

Supports the fiber-shared MSP and SNCP and processes eight sets of
K bytes. A single optical interface supports two MSP protection rings,
and one SLQ4 supports a maximum of eight MSP protection rings.

Supports inloops and outloops at optical interfaces.

The N1SLQ4 supports inloops on VC-4 paths.

Supports warm resets and cold resets. The warm reset does not affect
services.

Supports the query of the manufacturing information of the board.

Supports the in-service loading of the FPGA.

Supports the upgrade of the board software without affecting services.

The N2SLQ4 supports the TCM function.

Supports the press-to-collect function in fault data collection.

Maintenance
features

5.13.3 Working Principle and Signal Flow


The SLQ4 consists of the O/E converting module, CDR module, SDH overhead processing
module, logic and control module, DC/DC converter, and other modules.
Figure 5-32 shows the functional block diagram of the SLQ4.

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Figure 5-32 Functional block diagram of the SLQ4


155 MHz

622 Mbit/s
622 Mbit/s

O/E
E/O

S
P
I

622
Mbit/s

CDR

Reference clock

155 MHz
PLL

622
Mbit/s

K1 and K2

K1 and K2 insertion/extraction

Cross-connect unit

Cross-connect unit

622 Mbit/s
High-speed bus

622 Mbit/s

O/E
E/O

S
P
I

....

....

622 Mbit/s

Cross-connect unit A

622
Mbit/s

CDR

622
Mbit/s

RST

MST

MSA

High-speed
bus

HPT

622 Mbit/s

DCC
SDH overhead processing module

IIC
LOS
Laser shutdown

Logic and
control
module

+3.3 V

DC/DC
converter

Frame header
Communication

Fuse

Cross-connect unit B
SCC unit

Cross-connect unit
SCC unit

-48 V/ -60 V
-48 V/ -60 V

DC/DC
converter

PLL: phase-locked loop

SPI: SDH physical interface

RST: regenerator section


termination

MST: multiplex section termination MSA: multiplex section adaptation

HPT: higher order path termination IIC: inter-integrated circuit

SDH: synchronous digital hierarchy

CDR: clock and data recovery

The functional modules of the STM-4 units are described as follows:

O/E Converting Module


l

In the receive direction, the module converts the received optical signals into electrical
signals.

In the transmit direction, the module converts the electrical signals into SDH optical signals
and sends the SDH optical signals to fibers for transmission.

The SPI detects the R_LOS alarm and provides the function of shutting down the laser.

CDR Module
This module restores the data signal and the clock signal.

SDH Overhead Processing Module


This module includes the RST, MST, MSA, and HPT sub-modules. This module provides the
inloop and outloop functions.
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In the receive direction, the RST sub-module detects the frame alignment bytes (A1 and
A2), performs descrambling, restores the regenerator section trace byte (J0), detects a
J0 mismatch, and counts BIP-8 errored blocks.

In the transmit direction, the RST sub-module inserts the frame alignment bytes, inserts
the J0 byte, performs scrambling, and performs BIP-8 calculation and insertion.

MST sub-module

In the receive direction, the MST sub-module counts BIP-24 errored blocks, restores
the MS_REI, and detects the MS_RDI, MS_AIS, and MS-EXC.

In the transmit direction, the MST sub-module performs BIP-24 calculation and
insertion and inserts the MS_REI, MS_RDI, and MS_AIS.

The MST sub-module extracts or inserts the K1, K2, E2, D4D12, S1, B2, and M1
bytes.

MSA sub-module

In the receive direction, the MSA sub-module interprets the AU-4 pointer, detects the
LOP and AIS, and performs pointer justifications.

In the transmit direction, the MSA sub-module assembles the AUG and generates the
AU-4 pointer and the AU_AIS.

HPT sub-module

Terminates the overheads.

Restores the J1 path trace message.

Restores the REI information.

Detects the HP_RDI (monitors the status of the path).

Detects the UNEQ and AIS (monitors the signal label).

Counts the VC-4 BIP-8 errored blocks.

Logic and Control Module


l

Manages and configures the other modules of the board.

Performs inter-board communication through the internal Ethernet interface.

Traces the clock signal from the active and standby cross-connect units.

Controls the laser.

Passes the orderwire and ECC bytes through an ADM that consists of two paired slots when
the CXL is not online.

Selects the clock signal and frame header signal from the active and standby cross-connect
units.

Controls the indicators on the board.

DC/DC Converter
It converts the 48/60 V power supply into the DC voltages that the modules of the board
require.

5.13.4 Front Panel


The front panel of the SLQ4 has indicators, interfaces, a bar code, and a laser safety class label.
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Diagram of the Front Panel


Figure 5-33 shows the appearance of the front panel of the SLQ4.
Figure 5-33 Front panel of the SLQ4

SLQ4
STAT
ACT
PROG
SRV

CLASS 1
LASER
PRODUCT

OUT1 IN1
OUT2 IN2
OUT3 IN3
OUT4 IN4

SLQ4

Indicators
The front panel of the board has the following indicators:
l

Board hardware status indicator (STAT) two colors (red and green)

Service activation status indicator (ACT) one color (green)

Board software status indicator (PROG) two colors (red and green)

Service alarm indicator (SRV) three colors (red, green, and yellow)

For the meanings of the status of the indicators, see A Indicators.


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Interfaces
The front panel of the SLQ4 has four optical interfaces. Table 5-56 describes the types and usage
of the optical interfaces of the SLQ4.
Table 5-56 Optical interfaces of the SLQ4
Interface

Type of
Interface

Usage

IN1-IN4

LC

Receives optical signals.

OUT1-OUT4

LC

Transmits optical signals.

The SLQ4 can use the swappable optical modules to facilitate maintenance.

5.13.5 Valid Slots


The SLQ4 can be installed in slots 28 and 1116 in the subrack.

5.13.6 Feature Code


The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the SLQ4 indicates the type of optical interface.
Table 5-57 provides the relationship between the feature code of the SLQ4 and the type of optical
interface.
Table 5-57 Relationship between the feature code of the SLQ4 and the type of optical interface
Board

Feature Code

Type of Optical Interface

SSN1SLQ410 and
SSN2SLQ410

10

S-4.1

SSN1SLQ411 and
SSN2SLQ411

11

L-4.1

SSN1SLQ412 and
SSN2SLQ412

12

L-4.2

SSN1SLQ413 and
SSN2SLQ413

13

Ve-4.2

SSN1SLQ414 and
SSN2SLQ414

14

I-4

5.13.7 Parameter Settings


You can set the parameters for the SLQ4 by using the T2000.
You can set the following parameters for the SLQ4 by using the T2000:
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J0

J1

J2

C2

5 SDH Boards

For the description of each parameter, see F Parameter Settings.

5.13.8 Technical Specifications


The technical specifications of the SLQ4 include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.

Parameters Specified for Optical Interfaces


Table 5-58 lists the parameters specified for the optical interfaces of the SLQ4.
Table 5-58 Parameters specified for the optical interfaces of the SLQ4

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Parameter

Value

Nominal bit rate

622080 kbit/s

Line code
pattern

NRZ

Application
code

I-4

S-4.1

L-4.1

L-4.2

Ve-4.2

Transmission
distance (km)

0 to 2

2 to 15

20 to 40

50 to 80

80 to 100

Type of fiber

Singlemode LC

Singlemode LC

Singlemode LC

Singlemode LC

Single-mode
LC

Operating
wavelength
range (nm)

1261 to
1360

1274 to
1356

1280 to
1335

1480 to
1580

1480 to 1580

Launched
optical power
range (dBm)

-15 to -8

-15 to -8

-3 to +2

-3 to +2

-3 to +2

Receiver
sensitivity
(dBm)

-23

-28

-28

-28

-34

Minimum
overload (dBm)

-8

-8

-8

-8

-13

Minimum
extinction ratio
(dB)

8.2

8.2

10

10

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Laser Safety Class


The safety class of the laser on the board is Class 1. The maximum launched optical power of
the optical interfaces is less than 10 dBm (10 mW).

Mechanical Specifications
The mechanical specifications of the SLQ4 are as follows:
l

Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)

Weight (kg): 1.0

Power Consumption
The maximum power consumption of the SLQ4 at room temperature (25C) is 17 W.

5.14 SLQ4A
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the SLQ4A (4xSTM-4 optical interface board).
5.14.1 Version Description
The SLQ4A is available in one functional version, namely, N1.
5.14.2 Functions and Features
The SLQ4A transmits and receives STM-4 optical signals, performs O/E conversion for the
STM-4 optical signals, extracts and inserts overhead bytes, and generates alarm signals on the
line.
5.14.3 Working Principle and Signal Flow
The SLQ4A consists of the O/E converting module, CDR module, SDH overhead processing
module, logic and control module, DC/DC converter, and other modules.
5.14.4 Front Panel
The front panel of the SLQ4A has indicators, interfaces, a bar code, and a laser safety class label.
5.14.5 Valid Slots
The SLQ4A can be installed in slots 28 and 1116 in the subrack.
5.14.6 Feature Code
The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the SLQ4A indicates the type of optical interface.
5.14.7 Parameter Settings
You can set the parameters for the SLQ4A by using the T2000.
5.14.8 Technical Specifications
The technical specifications of the SLQ4A include the parameters specified for optical
interfaces, laser safety class, mechanical specifications, and power consumption.

5.14.1 Version Description


The SLQ4A is available in one functional version, namely, N1.
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5.14.2 Functions and Features


The SLQ4A transmits and receives STM-4 optical signals, performs O/E conversion for the
STM-4 optical signals, extracts and inserts overhead bytes, and generates alarm signals on the
line.
Table 5-59 provides the functions and features of the SLQ4A.
Table 5-59 Functions and features of the SLQ4A
Function and
Feature

SLQ4A

Basic functions

Transmits and receives 4xSTM-4 optical signals.

Specifications of
the optical
interface

Supports different types of standard optical interfaces, namely, the I-4,


S-4.1, L-4.1, L-4.2, and Ve-4.2.

The characteristics of the optical interfaces of the I-4, S-4.1, L-4.1, and
L-4.2 types comply with ITU-T G.957.

The characteristics of the optical interface of the Ve-4.2 type comply


with the standards defined by Huawei.

Supports the detection and query of the information about the optical
module.

Provides the ALS function. The optical interface supports the setting
of the on/off state of a laser.

Supports the usage and monitoring of the SFP optical module, which
facilitates the maintenance and upgrading of the optical module.

Specifications of
the optical
module

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Service
processing

Supports the VC-12 services, VC-3 services, VC-4 services, and VC-4-4c
concatenation services.

Overhead
processing

Processes the section overheads of the STM-4 signals.

Supports the transparent transmission and termination of the path


overheads.

Supports the setting and query of the J0, J1, J2, and C2 bytes.

Supports one to four channels of ECC communication.

Supports the time synchronization feature and transmission of the time


information by using the section overhead bytes.

Alarms and
performance
events

Reports various alarms and performance events, which facilitates the


management and maintenance of the equipment.

Protection
schemes

Supports the two-fiber ring MSP, four-fiber ring MSP, linear MSP,
SNCP, SNCTP, and SNCMP.

Supports the fiber-shared MSP and SNCP and processes eight sets of
K bytes. A single optical interface supports two MSP protection rings,
and one SLQ4A supports a maximum of eight MSP protection rings.

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Function and
Feature

SLQ4A

Maintenance
features

Supports inloops and outloops at optical interfaces.

Supports inloops and outloops on VC-4 paths.

Supports warm resets and cold resets. The warm reset does not affect
services.

Supports the query of the manufacturing information of the board.

Supports the in-service loading of the FPGA.

Supports the upgrade of the board software without affecting services.

Supports the press-to-collect function in fault data collection.

5.14.3 Working Principle and Signal Flow


The SLQ4A consists of the O/E converting module, CDR module, SDH overhead processing
module, logic and control module, DC/DC converter, and other modules.
Figure 5-34 shows the functional block diagram of the SLQ4A.
Figure 5-34 Functional block diagram of the SLQ4A
155 MHz

622 Mbit/s
622 Mbit/s

O/E
E/O

S
P
I

622
Mbit/s

E/O

S
P
I

K1 and K2

K1 and K2 insertion/extraction

High-speed
bus

....

622 Mbit/s

O/E

622
Mbit/s

622 Mbit/s

....

622 Mbit/s

CDR

Reference clock

155 MHz
PLL

622
Mbit/s

RST

622
CDR Mbit/s

MST

MSA

High-speed
bus

HPT

622 Mbit/s

DCC
SDH overhead processing module

IIC
LOS
Laser shutdown

Logic and
control
module
+3.3
V

DC/DC
converter

DC/DC
converter

Frame header
Communication

Fuse

Cross-connect
unit

Cross-connect
unit
Cross-connect
unit A
Cross-connect
unit B
SCC unit

Cross-connect
unit
SCC unit
-48 V/ -60 V
-48 V/ -60 V

PLL: phase-locked loop

SPI: SDH physical interface

RST: regenerator section


termination

MST: multiplex section termination MSA: multiplex section adaptation

HPT: higher order path termination IIC: inter-integrated circuit

SDH: synchronous digital hierarchy

CDR: clock and data recovery

The functional modules of the STM-4 units are described as follows:


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O/E Converting Module


l

In the receive direction, the module converts the received optical signals into electrical
signals.

In the transmit direction, the module converts the electrical signals into SDH optical signals
and sends the SDH optical signals to fibers for transmission.

The SPI detects the R_LOS alarm and provides the function of shutting down the laser.

CDR Module
This module restores the data signal and the clock signal.

SDH Overhead Processing Module


This module includes the RST, MST, MSA, and HPT sub-modules. This module provides the
inloop and outloop functions.
l

RST sub-module

In the receive direction, the RST sub-module detects the frame alignment bytes (A1 and
A2), performs descrambling, restores the regenerator section trace byte (J0), detects a
J0 mismatch, and counts BIP-8 errored blocks.

In the transmit direction, the RST sub-module inserts the frame alignment bytes, inserts
the J0 byte, performs scrambling, and performs BIP-8 calculation and insertion.

MST sub-module

In the receive direction, the MST sub-module counts BIP-24 errored blocks, restores
the MS_REI, and detects the MS_RDI, MS_AIS, and MS-EXC.

In the transmit direction, the MST sub-module performs BIP-24 calculation and
insertion and inserts the MS_REI, MS_RDI, and MS_AIS.

The MST sub-module extracts or inserts the K1, K2, E2, D4D12, S1, B2, and M1
bytes.

MSA sub-module

In the receive direction, the MSA sub-module interprets the AU-4 pointer, detects the
LOP and AIS, and performs pointer justifications.

In the transmit direction, the MSA sub-module assembles the AUG and generates the
AU-4 pointer and the AU_AIS.

HPT sub-module

Terminates the overheads.

Restores the J1 path trace message.

Restores the REI information.

Detects the HP_RDI (monitors the status of the path).

Detects the UNEQ and AIS (monitors the signal label).

Counts the VC-4 BIP-8 errored blocks.

Logic and Control Module


l

Manages and configures the other modules of the board.

Performs inter-board communication through the internal Ethernet interface.

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l

Traces the clock signal from the active and standby cross-connect units.

Controls the laser.

Passes the orderwire and ECC bytes through an ADM that consists of two paired slots when
the CXL is not online.

Selects the clock signal and frame header signal from the active and standby cross-connect
units.

Controls the indicators on the board.

DC/DC Converter
It converts the 48/60 V power supply into the DC voltages that the modules of the board
require.

5.14.4 Front Panel


The front panel of the SLQ4A has indicators, interfaces, a bar code, and a laser safety class label.

Diagram of the Front Panel


Figure 5-35 shows the appearance of the front panel of the SLQ4A.

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Figure 5-35 Front panel of the SLQ4A

SLQ4A
STAT
ACT
PROG
SRV

CLASS 1
LASER
PRODUCT

OUT1 IN1
OUT2 IN2
OUT3 IN3
OUT4 IN4

SLQ4A

Indicators
The front panel of the board has the following indicators:
l

Board hardware status indicator (STAT) two colors (red and green)

Service activation status indicator (ACT) one color (green)

Board software status indicator (PROG) two colors (red and green)

Service alarm indicator (SRV) three colors (red, green, and yellow)

For the meanings of the status of the indicators, see A Indicators.

Interfaces
The front panel of the SLQ4A has four optical interfaces. Table 5-60 describes the types and
usage of the optical interfaces of the SLQ4A.
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Table 5-60 Optical interfaces of the SLQ4A


Interface

Type of
Interface

Usage

IN1IN4

LC

Receives optical signals.

OUT1OUT4

LC

Transmits optical signals.

The SLQ4A can use the swappable optical modules to facilitate maintenance.

5.14.5 Valid Slots


The SLQ4A can be installed in slots 28 and 1116 in the subrack.

5.14.6 Feature Code


The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the SLQ4A indicates the type of optical interface.
Table 5-61 provides the relationship between the feature code of the SLQ4A and the type of
optical interface.
Table 5-61 Relationship between the feature code of the SLQ4A and the type of optical interface
Board

Feature Code

Type of Optical Interface

SSN1SLQ4A10

10

S-4.1

SSN1SLQ4A11

11

L-4.1

SSN1SLQ4A12

12

L-4.2

SSN1SLQ4A13

13

Ve-4.2

SSN1SLQ4A14

14

I-4

5.14.7 Parameter Settings


You can set the parameters for the SLQ4A by using the T2000.
You can set the following parameters for the SLQ4A by using the T2000:
l

J0

J1

J2

C2

For the description of each parameter, see F Parameter Settings.


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5.14.8 Technical Specifications


The technical specifications of the SLQ4A include the parameters specified for optical
interfaces, laser safety class, mechanical specifications, and power consumption.

Parameters Specified for Optical Interfaces


Table 5-62 lists the parameters specified for the optical interfaces of the SLQ4A.
Table 5-62 Parameters specified for the optical interfaces of the SLQ4A
Parameter

Value

Nominal bit rate

622080 kbit/s

Line code
pattern

NRZ

Application
code

I-4

S-4.1

L-4.1

L-4.2

Ve-4.2

Transmission
distance (km)

0 to 2

2 to 15

20 to 40

50 to 80

80 to 100

Type of fiber

Singlemode LC

Singlemode LC

Singlemode LC

Singlemode LC

Single-mode
LC

Operating
wavelength
range (nm)

1261 to
1360

1274 to
1356

1280 to
1335

1480 to
1580

1480 to 1580

Launched
optical power
range (dBm)

-15 to -8

-15 to -8

-3 to +2

-3 to +2

-3 to +2

Receiver
sensitivity
(dBm)

-23

-28

-28

-28

-34

Minimum
overload (dBm)

-8

-8

-8

-8

-13

Minimum
extinction ratio
(dB)

8.2

8.2

10

10

10.5

Laser Safety Class


The safety class of the laser on the board is Class 1. The maximum launched optical power of
the optical interfaces is less than 10 dBm (10 mW).

Mechanical Specifications
The mechanical specifications of the SLQ4A are as follows:
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l

Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)

Weight (kg): 1.0

Power Consumption
The maximum power consumption of the SLQ4A at room temperature (25C) is 17 W.

5.15 SL16
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the SL16 (1xSTM-16 optical interface board).
5.15.1 Version Description
The SL16 is available in three functional versions, namely, N1, N2, and N3. The difference
between the three versions is with regard to whether they support the TCM function and AU-3
services. The N1SL16 and N2SL16 are no longer manufactured.
5.15.2 Functions and Features
The SL16 receives and transmits 1xSTM-16 optical signals and processes overhead bytes.
5.15.3 Working Principle and Signal Flow
The SL16 consists of the O/E converting module, MUX/DEMUX module, SDH overhead
processing module, logic and control module, DC/DC converter, and other modules.
5.15.4 Front Panel
The front panel of the SL16 has indicators, interfaces, a bar code, a laser safety class label, and
an APD alarm label.
5.15.5 Valid Slots
The SL16 can be installed in slots 28 and 1116 in the subrack.
5.15.6 Feature Code
The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the SL16 indicates the type of optical interface.
5.15.7 Parameter Settings
You can set the parameters for the SL16 by using the T2000.
5.15.8 Technical Specifications
The technical specifications of the SL16 include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.

5.15.1 Version Description


The SL16 is available in three functional versions, namely, N1, N2, and N3. The difference
between the three versions is with regard to whether they support the TCM function and AU-3
services. The N1SL16 and N2SL16 are no longer manufactured.
Table 5-63 describes the versions of the SL16.

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Table 5-63 Versions of the SL16


Item

Description

Functional
versions

The SL16 is available in three functional versions, namely, N1, N2, and
N3.

Differences

The N1SL16 does not support the TCM function or AU-3 services.

The N2SL16 supports the TCM function and AU-3 services, but the
TCM function and AU-3 services cannot be available at the same
time.

The N3SL16 supports the TCM function but does not support AU-3
services.

The N1SL16 and N2SL16 cannot be substituted with each other.

Substitution

The N3SL16 supports the board version replacement function.


l

The N3SL16 can substitute for the N1SL16.

When the AU-3 services are not required, the N3SL16 can substitute
for the N2SL16.

After the N3SL16 substitutes for the N1SL16 or N2SL16, the


configuration and service status of the N3SL16 are the same as the
configuration and service status of the N1SL16 or N2SL16.

NOTE

In the case of the board of different versions, adhere to the following principles when configuring the MSP
or SNCP:
l

You cannot configure the N1SL16 as the protection board if the working board is the N2SL16 or
N3SL16 on which the TCM function is enabled. Otherwise, the services are interrupted when a
switching operation is performed.

You cannot configure the N1SL16 or N3SL16 as the protection board if the working board is the
N2SL16 on which the AU-3 services are configured. Otherwise, the services are interrupted when a
switching operation is performed.

5.15.2 Functions and Features


The SL16 receives and transmits 1xSTM-16 optical signals and processes overhead bytes.
Table 5-64 provides the functions and features of the SL16.
Table 5-64 Functions and features of the SL16

Issue 02 (2009-07-30)

Function and
Feature

SL16

Basic functions

Transmits and receives 1xSTM-16 optical signals.

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Function and
Feature

SL16

Specifications
of the optical
interface

Supports different types of standard optical interfaces, namely, the


L-16.2, L-16.2Je, V-16.2Je (with the booster amplifier (BA)), and
U-16.2Je (with the BA and pre-amplifier (PA)). The characteristics of
the optical interface of the L-16.2 type comply with ITU-T G.957 and
ITU-T G.692. The characteristics of the optical interfaces of the
L-16.2Je, V-16.2Je (with the BA), and U-16.2Je (with the BA and PA)
types comply with the standards defined by Huawei.

Supports the output of the standard wavelengths that comply with ITUT G.692. The U-16.2Je optical interface can be directly connected to
the dense wavelength division multiplexing (DWDM) equipment.

Supports the detection and query of the information about the optical
module.

Provides the ALS function. The optical interface supports the setting of
the on/off state of a laser.

Supports the usage and detection of the SFP optical module, which
facilitates the maintenance and upgrading of the optical module.

Supports the VC-12 services, VC-3 services, VC-4 services, VC-4-4c


concatenation services, VC-4-8c concatenation services, and VC-4-16c
concatenation services.

The N2SL16 supports the AU-3 services.

Processes the section overheads of the STM-16 signals.

Supports the transparent transmission and termination of the path


overheads.

Supports the setting and query of the J0, J1, J2, and C2 bytes.

Supports one channel of ECC communication.

Specifications
of the optical
module

Service
processing

Overhead
processing

5-122

Alarms and
performance
events

Reports various alarms and performance events, which facilitates the


management and maintenance of the equipment.

Specifications
of the REG

The N2SL16 and N3SL16 support the setting and query of the REG
working mode.

Protection
schemes

Supports the two-fiber ring MSP, four-fiber ring MSP, linear MSP,
SNCP, SNCTP, and SNCMP.

Supports the fiber-shared MSP and SNCP and processes two sets of K
bytes. One SL16 supports a maximum of two MSP protection rings.

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Function and
Feature

SL16

Maintenance
features

Supports inloops and outloops at optical interfaces.

The N1SL16 supports inloops on VC-4 paths. The N3SL16 supports


inloops and outloops on paths.

Supports warm resets and cold resets. The warm reset does not affect
services.

Supports the query of the manufacturing information of the board.

Supports the in-service loading of the FPGA.

The N2SL16 and N3SL16 support the TCM function.

Supports the upgrade of the board software without affecting services.

The N2SL16 and N3SL16 support the TCM function.

The N3SL16 supports the PRBS function.

Supports the press-to-collect function in fault data collection.

5.15.3 Working Principle and Signal Flow


The SL16 consists of the O/E converting module, MUX/DEMUX module, SDH overhead
processing module, logic and control module, DC/DC converter, and other modules.
Figure 5-36 shows the functional block diagram of the SL16.
Figure 5-36 Functional block diagram of the SL16
155 MHz

2.488
Gbit/s

2.488
Gbit/s

K1 and K2

K1 and K2 insertion/
extraction

16x155
Mbit/s
DEMUX

O/E
S
P
I

2.488
Gbit/s

Reference clock

155 MHz
PLL

2.488
Gbit/s

16x155
Mbit/s

MUX

E/O

High-speed
bus
RST

MST

MSA

HPT

High-speed
bus
DCC

SDH overhead processing module

IIC
LOS
Laser shutdown

Logic and
control module

+3.3 V
DC/DC
converter

PLL: phase-locked loop

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DC/DC
converter

SPI: SDH physical interface

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Frame header
Communication

Fuse

Cross-connect
unit

Cross-connect
unit

Cross-connect
unit A
Cross-connect
unit A
SCC unit

Cross-connect
unit
SCC unit
-48 V/-60 V
-48 V/-60 V

SDH: synchronous digital hierarchy

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RST: regenerator section
termination

MST: multiplex section termination MSA: multiplex section adaptation

HPT: higher order path termination IIC: inter-integrated circuit

O/E Converting Module


l

In the receive direction, the module converts the received optical signals into electrical
signals.

In the transmit direction, the module converts the electrical signals into SDH optical signals
and sends the SDH optical signals to fibers for transmission.

The SPI detects the R_LOS alarm and provides the function of shutting down the laser.

MUX/DEMUX Module
l

In the receive direction, the DEMUX part demultiplexes the high-rate electrical signals into
multiple parallel electrical signals and restores the clock signal at the same time.

In the transmit direction, the MUX part multiplexes the parallel electrical signals received
from the SDH overhead processing module into high-rate electrical signals.

SDH Overhead Processing Module


This module includes the RST, MST, MSA, and HPT sub-modules. This module provides the
inloop and outloop functions.
l

5-124

RST sub-module

In the receive direction, the RST sub-module detects the frame alignment bytes (A1 and
A2), performs descrambling, restores the regenerator section trace byte (J0), detects a
J0 mismatch, and counts BIP-8 errored blocks.

In the transmit direction, the RST sub-module inserts the frame alignment bytes, inserts
the J0 byte, performs scrambling, and performs BIP-8 calculation and insertion.

MST sub-module

In the receive direction, the MST sub-module counts BIP-24 errored blocks, restores
the MS_REI, and detects the MS_RDI, MS_AIS, and MS-EXC.

In the transmit direction, the MST sub-module performs BIP-24 calculation and
insertion and inserts the MS_REI, MS_RDI, and MS_AIS.

The MST sub-module extracts or inserts the K1, K2, E2, D4D12, S1, B2, and M1
bytes.

MSA sub-module

In the receive direction, the MSA sub-module interprets the AU-4 pointer, detects the
LOP and AIS, and performs pointer justifications.

In the transmit direction, the MSA sub-module assembles the AUG and generates the
AU-4 pointer and the AU_AIS.

HPT sub-module

Terminates the overheads.

Restores the J1 path trace message.

Restores the REI information.


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Detects the HP_RDI (monitors the status of the path).

Detects the UNEQ and AIS (monitors the signal label).

Counts the VC-4 BIP-8 errored blocks.

5 SDH Boards

Logic and Control Module


l

Manages and configures the other modules of the board.

Performs inter-board communication through the internal Ethernet interface.

Traces the clock signal from the active and standby cross-connect units.

Controls the laser.

Passes the orderwire and ECC bytes through an ADM that consists of two paired slots when
the CXL is not online.

Selects the clock signal and frame header signal from the active and standby cross-connect
units.

Controls the indicators on the board.

DC/DC Converter
It converts the 48/60 V power supply into the DC voltages that the modules of the board
require.

5.15.4 Front Panel


The front panel of the SL16 has indicators, interfaces, a bar code, a laser safety class label, and
an APD alarm label.

Diagram of the Front Panel


Figure 5-37 shows the appearance of the front panel of the SL16.

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Figure 5-37 Front panel of the SL16

SL16
STAT
ACT
PROG
SRV

CLASS 1
LASER
PRODUCT

APD

Receiver
MAX:-9dBm

OUT

IN

SL16

Indicators
The front panel of the board has the following indicators:
l

Board hardware status indicator (STAT) two colors (red and green)

Service activation status indicator (ACT) one color (green)

Board software status indicator (PROG) two colors (red and green)

Service alarm indicator (SRV) three colors (red, green, and yellow)

For the meanings of the status of the indicators, see A Indicators.

Interfaces
The front panel of the SL16 has one optical interface. Table 5-65 describes the types and usage
of the optical interfaces of the SL16.
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Table 5-65 Optical interfaces of the SL16


Interface

Type of Interface

Usage

IN

LC

Receives optical signals.

OUT

LC

Transmits optical signals.

5.15.5 Valid Slots


The SL16 can be installed in slots 28 and 1116 in the subrack.

5.15.6 Feature Code


The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the SL16 indicates the type of optical interface.
Table 5-66 provides the relationship between the feature code of the SL16 and the type of optical
interface
Table 5-66 Relationship between the feature code of the SL16 and the type of optical interface
Board

Feature Code

Type of Optical Interface

SSN1SL1601, SSN2SL1601
and SSN3SL1601

01

L-16.2

SSN1SL1602, SSN2SL1602
and SSN3SL1602

02

L-16.2Je

SSN1SL1603, SSN2SL1603
and SSN3SL1603

03

V-16.2Je

SSN1SL1604, SSN2SL1604
and SSN3SL1604

04

U-16.2

5.15.7 Parameter Settings


You can set the parameters for the SL16 by using the T2000.
You can set the following parameters for the SL16 by using the T2000:
l

J0

J1

J2

C2

For the description of each parameter, see F Parameter Settings.

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5.15.8 Technical Specifications


The technical specifications of the SL16 include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.

Parameters Specified for Optical Interfaces


Table 5-67 lists the parameters specified for the optical interfaces of the SL16.
Table 5-67 Parameters specified for the optical interfaces of the SL16

5-128

Parameter

Value

Nominal bit
rate

2488320 kbit/s

Line code
pattern

NRZ

Application
code

L-16.2

L-16.2Je

V-16.2Je (BA)

U-16.2Je (BA+PA)

Transmissio
n distance
(km)

50 to 80

80 to 100

105 to 140

145 to 170

Type of fiber

Singlemode LC

Singlemode LC

Single-mode LC

Single-mode LC

Operating
wavelength
range (nm)

1500 to
1580

1530 to
1560

1530 to 1565

1550.12

Launched
optical
power range
(dBm)

-2 to +3

5 to 7

-2 to +3
(without
the BA)

-2 to +3
(without
the BA
or PA)

15 to 18
(with the
BA)

Receiver
sensitivity
(dBm)

-28

-28

-28

-28
(without
the PA
or BA)

-32 (with
the PA)

Minimum
overload
(dBm)

-9

-9

-9

-9
(without
the PA
or BA)

-10 (with
the PA)

Minimum
extinction
ratio (dB)

8.2

8.2

8.2

8.2

13 to 15
(with the
BA)

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Value

Note: The optical interface of the Le-16.2 type is the same as the optical interface of the
L-16.2Je type.
The launched optical power of the optical interface of the V-16.2Je type is measured when
the BA is added. The launched optical power of the optical interface of the U-16.2Je type is
measured when the BA and PA are added. When no amplifier is added, the launched optical
power of the optical interfaces of the V-16.2Je and U-16.2Je types ranges from -2 dBm to 3
dBm.

Table 5-68 lists the parameters specified for the colored optical interfaces of the SL16.
Table 5-68 Parameters specified for the optical interfaces that comply with the standard
wavelengths specified in ITU-T G.692
Parameter

Value

Nominal bit rate

2488320 kbit/s

Dispersion limit (km)

170

640.a

Mean launched optical


power (dBm)

-2 to +3

-5 to -1

Receiver sensitivity (dBm)

-28

-28

Minimum overload (dBm)

-9

-9

Maximum allowed
dispersion (ps/nm)

3400

10880

Minimum extinction ratio


(dB)

8.2

10

Laser Safety Class


The safety class of the laser on the board is Class 1. The maximum launched optical power of
the optical interfaces is less than 10 dBm (10 mW).

Mechanical Specifications
The mechanical specifications of the SL16 are as follows:
l

Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)

Weight (kg): 1.1

Power Consumption
The maximum power consumption of the N1SL16 and N2SL16 at room temperature (25C) is
20 W.
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The maximum power consumption of the N3SL16 at room temperature (25C) is 22 W.

5.16 SL16A
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the SL16A (1xSTM-16 optical interface board).
5.16.1 Version Description
The SL16A is available in functional versions, namely, N3, N2, and N1. The difference between
the versions is with regard to whether they support the TCM function and AU-3 services. The
N1SL16A and N2SL16A are no longer manufactured.
5.16.2 Functions and Features
The SL16A receives and transmits 1xSTM-16 optical signals, processes overhead bytes, and
performs the MSP.
5.16.3 Working Principle and Signal Flow
The N1SL16A/N2SL16A/N3SL16A consists of the O/E converting module, MUX/DEMUX
module, SDH overhead processing module, logic and control module, and other modules.
5.16.4 Front Panel
The front panel of the SL16A has indicators, interfaces, a bar code, a laser safety class label,
and an APD alarm label.
5.16.5 Valid Slots
The SL16A can be installed in slots 28 and 1116 in the subrack.
5.16.6 Feature Code
The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the SL16A indicates the type of optical interface.
5.16.7 Parameter Settings
You can set the parameters for the SL16A by using the T2000.
5.16.8 Technical Specifications
The technical specifications of the SL16A include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.

5.16.1 Version Description


The SL16A is available in functional versions, namely, N3, N2, and N1. The difference between
the versions is with regard to whether they support the TCM function and AU-3 services. The
N1SL16A and N2SL16A are no longer manufactured.
Table 5-69 describes the versions of the SL16A.
Table 5-69 Versions of the SL16A

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Item

Description

Functional versions

The SL16A is available in functional versions, namely, N3, N2, and


N1.

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Item

Description

Differences

The N1SL16A does not support the TCM function or AU-3 services.

The N2SL16A supports the TCM function and AU-3 services, but
the TCM function and AU-3 services cannot be available at the same
time.

The N3SL16A supports the TCM function but does not support
AU-3 services.

The N1SL16A and N2SL16A cannot be substituted with each other.

Substitution

The N3SL16A supports the board version replacement function.


l

The N3SL16A can substitute for the N1SL16A.

When the AU-3 services are not required, the N3SL16A can
substitute for the N2SL16A.

After the N3SL16A substitutes for the N1SL16A or N2SL16A, the


configuration and service status of the N3SL16A are the same as the
configuration and service status of the N1SL16A or N2SL16A.

NOTE

In the case of the board of different versions, adhere to the following principles when configuring the MSP
or SNCP:
l

You cannot configure the N1SL16A as the protection board if the working board is the N2SL16A or
N3SL16A on which the TCM function is enabled. Otherwise, the services are interrupted when a
switching operation is performed.

You cannot configure the N3SL16A or N1SL16A as the protection board if the working board is the
N2SL16A on which the AU-3 services are configured. Otherwise, the services are interrupted when a
switching operation is performed.

5.16.2 Functions and Features


The SL16A receives and transmits 1xSTM-16 optical signals, processes overhead bytes, and
performs the MSP.
Table 5-70 provides the functions and features of the SL16A.
Table 5-70 Functions and features of the SL16A

Issue 02 (2009-07-30)

Function and
Feature

SL16A

Basic functions

Transmits and receives 1xSTM-16 optical signals.

Specifications of the
optical interface

Supports different types of standard optical interfaces, namely,


the I-16, S-16.1, L-16.1, and L-16.2. The characteristics of the
optical interfaces comply with ITU-T G.957 and ITU-T G.692.

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Function and
Feature

SL16A

Specifications of the
optical module

Supports the detection and query of the information about the


optical module.

Provides the ALS function. The optical interface supports the


setting of the on/off state of a laser.

Supports the usage and monitoring of the SFP optical module,


which facilitates the maintenance and upgrading of the optical
module.

Supports the VC-12 services, VC-3 services, VC-4 services,


VC-4-4c concatenation services, VC-4-8c concatenation
services, and VC-4-16c concatenation services.

The N2SL16A supports the AU-3 services.

Processes the section overheads of the STM-16 signals.

Supports the transparent transmission and termination of the path


overheads.

Supports the setting and query of the J0, J1, J2, and C2 bytes.

Supports one channel of ECC communication.

The N3SL16A supports the time synchronization feature and


transmission of the time information by using the section
overhead bytes.

Service processing

Overhead processing

Alarms and
performance events

Reports various alarms and performance events, which facilitates the


management and maintenance of the equipment.

Specifications of the
REG

The N2SL16A and N3SL16A support the setting and query of the
REG working mode.

Protection schemes

Supports the two-fiber ring MSP, four-fiber ring MSP, linear


MSP, SNCP, SNCTP, and SNCMP.

Supports the fiber-shared MSP and SNCP and processes two sets
of K bytes.

Supports inloops and outloops at optical interfaces.

The N1SL16A supports inloops on VC-4 paths. The N3SL16A


supports inloops and outloops on VC-4 paths.

Supports warm resets and cold resets. The warm reset does not
affect services.

Supports the query of the manufacturing information of the board.

Supports the in-service loading of the FPGA.

The N2SL16A and N3SL16A support the TCM function.

Supports the upgrade of the board software without affecting


services.

The N3SL16A supports the PRBS function.

Supports the press-to-collect function in fault data collection.

Maintenance features

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5.16.3 Working Principle and Signal Flow


The N1SL16A/N2SL16A/N3SL16A consists of the O/E converting module, MUX/DEMUX
module, SDH overhead processing module, logic and control module, and other modules.
Figure 5-38 shows the functional block diagram of the N1SL16A/N2SL16A/N3SL16A.
Figure 5-38 Functional block diagram of the N1SL16A/N2SL16A/N3SL16A
155 MHz

2.488
Gbit/s

2.488
Gbit/s

K1 and K2

K1 and K2 insertion/
extraction

16x155
Mbit/s
DEMUX

O/E
S
P
I

2.488
Gbit/s

Reference clock

155 MHz
PLL

2.488
Gbit/s

16x155
Mbit/s

MUX

E/O

High-speed
bus
RST

MST

MSA

HPT

High-speed
bus
DCC

SDH overhead processing module

IIC
LOS
Laser shutdown

Frame header

Logic and
control module

+3.3 V
DC/DC
converter

Communication

Fuse

DC/DC
converter

Cross-connect
unit

Cross-connect
unit

Cross-connect
unit A
Cross-connect
unit A
SCC unit

Cross-connect
unit
SCC unit
-48 V/-60 V
-48 V/-60 V

PLL: phase-locked loop

SPI: SDH physical interface

RST: regenerator section


termination

MST: multiplex section termination MSA: multiplex section adaptation

HPT: higher order path termination IIC: inter-integrated circuit

SDH: synchronous digital hierarchy

O/E Converting Module


l

In the receive direction, the module converts the received optical signals into electrical
signals.

In the transmit direction, the module converts the electrical signals into SDH optical signals
and sends the SDH optical signals to fibers for transmission.

The SPI detects the R_LOS alarm and provides the function of shutting down the laser.

MUX/DEMUX Module
l

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In the receive direction, the DEMUX part demultiplexes the high-rate electrical signals into
multiple parallel electrical signals and restores the clock signal at the same time.
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l

In the transmit direction, the MUX part multiplexes the parallel electrical signals received
from the SDH overhead processing module into high-rate electrical signals.

SDH Overhead Processing Module


This module includes the RST, MST, MSA, and HPT sub-modules. This module provides the
inloop and outloop functions.
l

RST sub-module

In the receive direction, the RST sub-module detects the frame alignment bytes (A1 and
A2), performs descrambling, restores the regenerator section trace byte (J0), detects a
J0 mismatch, and counts BIP-8 errored blocks.

In the transmit direction, the RST sub-module inserts the frame alignment bytes, inserts
the J0 byte, performs scrambling, and performs BIP-8 calculation and insertion.

MST sub-module

In the receive direction, the MST sub-module counts BIP-24 errored blocks, restores
the MS_REI, and detects the MS_RDI, MS_AIS, and MS-EXC.

In the transmit direction, the MST sub-module performs BIP-24 calculation and
insertion and inserts the MS_REI, MS_RDI, and MS_AIS.

The MST sub-module extracts or inserts the K1, K2, E2, D4D12, S1, B2, and M1
bytes.

MSA sub-module

In the receive direction, the MSA sub-module interprets the AU-4 pointer, detects the
LOP and AIS, and performs pointer justifications.

In the transmit direction, the MSA sub-module assembles the AUG and generates the
AU-4 pointer and the AU_AIS.

HPT sub-module

Terminates the overheads.

Restores the J1 path trace message.

Restores the REI information.

Detects the HP_RDI (monitors the status of the path).

Detects the UNEQ and AIS (monitors the signal label).

Counts the VC-4 BIP-8 errored blocks.

Logic and Control Module

5-134

Manages and configures the other modules of the board.

Performs inter-board communication through the internal Ethernet interface.

Traces the clock signal from the active and standby cross-connect units.

Controls the laser.

Passes the orderwire and ECC bytes through an ADM that consists of two paired slots when
the CXL is not online.

Selects the clock signal and frame header signal from the active and standby cross-connect
units.

Controls the indicators on the board.


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DC/DC Converter
It converts the 48/60 V power supply into the DC voltages that the modules of the board
require.

5.16.4 Front Panel


The front panel of the SL16A has indicators, interfaces, a bar code, a laser safety class label,
and an APD alarm label.

Diagram of the Front Panel


Figure 5-39 shows the appearance of the front panel of the SL16A.
Figure 5-39 Front panel of the SL16A

SL16A
STAT
ACT
PROG
SRV

CLASS 1
LASER
PRODUCT

APD

Receiver
MAX:-9dBm

OUT
IN

SL16A

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Indicators
The front panel of the board has the following indicators:
l

Board hardware status indicator (STAT) two colors (red and green)

Service activation status indicator (ACT) one color (green)

Board software status indicator (PROG) two colors (red and green)

Service alarm indicator (SRV) three colors (red, green, and yellow)

For the meanings of the status of the indicators, see A Indicators.

Interfaces
The front panel of the SL16A has one optical interface. Table 5-71 describes the types and usage
of the optical interfaces of the SL16A.
Table 5-71 Optical interfaces of the SL16A
Interface

Type of Interface

Usage

IN

LC

Receives optical signals.

OUT

LC

Transmits optical signals.

5.16.5 Valid Slots


The SL16A can be installed in slots 28 and 1116 in the subrack.

5.16.6 Feature Code


The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the SL16A indicates the type of optical interface.
Table 5-72 provides the relationship between the feature code of the SL16A and the type of
optical interface.
Table 5-72 Relationship between the feature code of the SL16A and the type of optical interface
Board

Feature Code

Type of Optical Interface

SSN3SL16A01

01

I-16

SSN3SL16A02

02

S-16.1

SSN3SL16A03

03

L-16.1

SSN3SL16A04

04

L-16.2

5.16.7 Parameter Settings


You can set the parameters for the SL16A by using the T2000.
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You can set the following parameters for the SL16A by using the T2000:
l

J0

J1

J2

C2

For the description of each parameter, see F Parameter Settings.

5.16.8 Technical Specifications


The technical specifications of the SL16A include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.

Parameters Specified for Optical Interfaces


Table 5-73 lists the parameters specified for the optical interfaces of the SL16A.
Table 5-73 Parameters specified for the optical interfaces of the SL16A

Issue 02 (2009-07-30)

Parameter

Value

Nominal bit
rate

2488320 kbit/s

Application
code

I-16

S-16.1

L-16.1

L-16.2

Transmission
distance (km)

0 to 2

2 to 15

25 to 40

50 to 80

Type of fiber

Single-mode
LC

Single-mode
LC

Single-mode LC

Single-mode LC

Operating
wavelength
range (nm)

1266 to 1360

1260 to 1360

1280 to 1335

1500 to 1580

Launched
optical power
range (dBm)

-10 to -3

-5 to 0

-2 to +3

-2 to +3

Receiver
sensitivity
(dBm)

-18

-18

-27

-28

Minimum
overload
(dBm)

-3

-9

-9

Minimum
extinction
ratio (dB)

8.2

8.2

8.2

8.2

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Laser Safety Class


The safety class of the laser on the board is Class 1. The maximum launched optical power of
the optical interfaces is less than 10 dBm (10 mW).

Mechanical Specifications
The mechanical specifications of the SL16A are as follows:
l

Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)

Weight of the N1SL16A (kg): 0.6

Weight of the N2SL16A (kg): 1.1

Weight of the N3SL16A (kg): 0.6

Power Consumption
The maximum power consumption of the N1SL16A at room temperature (25C) is 20 W.
The maximum power consumption of the N3SL16A at room temperature (25C) is 22 W.
The maximum power consumption of the N2SL16A at room temperature (25C) is 20 W.

5.17 SLD16
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the SLD16 (2xSTM-16 optical interface board).
5.17.1 Version Description
The SLD16 is available in one functional version, namely, N1.
5.17.2 Functions and Features
The SLD16 receives and transmits 2xSTM-16 optical signals, processes overhead bytes, and
performs the MSP.
5.17.3 Working Principle and Signal Flow
The SLD16 consists of the O/E converting module, MUX/DEMUX module, SDH overhead
processing module, logic and control module, DC/DC converter, and other modules.
5.17.4 Front Panel
The front panel of the SLD16 has indicators, interfaces, a bar code, and a laser safety class label.
5.17.5 Valid Slots
The slots valid for the SLD16 vary with the cross-connect capacity of the subrack.
5.17.6 Feature Code
The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the SLD16 indicates the type of optical interface.
5.17.7 Parameter Settings
You can set the parameters for the SLD16 by using the T2000.
5.17.8 Technical Specifications
The technical specifications of the SLD16 include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.
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5.17.1 Version Description


The SLD16 is available in one functional version, namely, N1.

5.17.2 Functions and Features


The SLD16 receives and transmits 2xSTM-16 optical signals, processes overhead bytes, and
performs the MSP.
Table 5-74 provides the functions and features of the SLD16.
Table 5-74 Functions and features of the SLD16
Function and
Feature

SLD16

Basic functions

Transmits and receives 2xSTM-16 optical signals.

Specifications
of the optical
interface

Supports different types of standard optical interfaces, namely, the I-16,


S-16.1, L-16.1, and L-16.2. The characteristics of the optical interfaces
comply with ITU-T G.957 and ITU-T G.692.

Supports the output of the standard wavelengths that comply with ITUT G.692.

Supports the detection and query of the information about the optical
module.

Provides the ALS function. The optical interface supports the setting of
the on/off state of a laser.

Supports the usage and detection of the SFP optical module, which
facilitates the maintenance and upgrading of the optical module.

Specifications
of the optical
module

Issue 02 (2009-07-30)

Service
processing

Supports the VC-12 services, VC-3 services, VC-4 services, VC-4-4c


concatenation services, VC-4-8c concatenation services, and VC-4-16c
concatenation services.

Overhead
processing

Processes the section overheads of the STM-16 signals.

Supports the transparent transmission and termination of the path


overheads.

Supports the setting and query of the J0, J1, J2, and C2 bytes.

Supports one or two channels of ECC communication.

Supports the time synchronization feature and transmission of the time


information by using the section overhead bytes.

Alarms and
performance
events

Reports various alarms and performance events, which facilitates the


management and maintenance of the equipment.

Specifications
of the REG

Does not support the REG.

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Function and
Feature

SLD16

Protection
schemes

Supports the two-fiber ring MSP, four-fiber ring MSP, linear MSP,
SNCP, SNCTP, and SNCMP.

Supports the fiber-shared MSP and SNCP and processes four sets of K
bytes. A single optical interface supports two MSP protection rings, and
one SLD16 supports a maximum of four MSP protection rings.

Supports inloops and outloops at optical interfaces.

Supports inloops and outloops on VC-4 paths.

Supports warm resets and cold resets. The warm reset does not affect
services.

Supports the query of the manufacturing information of the board.

Supports the in-service loading of the FPGA.

Supports the upgrade of the board software without affecting services.

Supports the press-to-collect function in fault data collection.

Maintenance
features

5.17.3 Working Principle and Signal Flow


The SLD16 consists of the O/E converting module, MUX/DEMUX module, SDH overhead
processing module, logic and control module, DC/DC converter, and other modules.
Figure 5-40 shows the functional block diagram of the SLD16 by describing how to process
1xSTM-16 signals.

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Figure 5-40 Functional block diagram of the SLD16


155 MHz

2.488
Gbit/s

2.488
Gbit/s

K1 and K2

K1 and K2 insertion/
extraction

16x155
Mbit/s
DEMUX

O/E
S
P
I

2.488
Gbit/s

Reference clock

155 MHz
PLL

2.488
Gbit/s

16x155
Mbit/s

MUX

E/O

High-speed
bus
RST

MST

MSA

HPT

High-speed
bus
DCC

SDH overhead processing module

IIC
LOS
Laser shutdown

Frame header

Logic and
control module

+3.3 V
DC/DC
converter

Communication

Fuse

DC/DC
converter

Cross-connect
unit

Cross-connect
unit

Cross-connect
unit A
Cross-connect
unit A
SCC unit

Cross-connect
unit
SCC unit
-48 V/-60 V
-48 V/-60 V

PLL: phase-locked loop

SPI: SDH physical interface

RST: regenerator section


termination

MST: multiplex section termination MSA: multiplex section adaptation

HPT: higher order path termination IIC: inter-integrated circuit

SDH: synchronous digital hierarchy

O/E Converting Module


l

In the receive direction, the module converts the received optical signals into electrical
signals.

In the transmit direction, the module converts the electrical signals into SDH optical signals
and sends the SDH optical signals to fibers for transmission.

The SPI detects the R_LOS alarm and provides the function of shutting down the laser.

MUX/DEMUX Module
l

In the receive direction, the DEMUX part demultiplexes the high-rate electrical signals into
multiple parallel electrical signals and restores the clock signal at the same time.

In the transmit direction, the MUX part multiplexes the parallel electrical signals received
from the SDH overhead processing module into high-rate electrical signals.

SDH Overhead Processing Module


This module includes the RST, MST, MSA, and HPT sub-modules. This module provides the
inloop and outloop functions.
l

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In the receive direction, the RST sub-module detects the frame alignment bytes (A1 and
A2), performs descrambling, restores the regenerator section trace byte (J0), detects a
J0 mismatch, and counts BIP-8 errored blocks.

In the transmit direction, the RST sub-module inserts the frame alignment bytes, inserts
the J0 byte, performs scrambling, and performs BIP-8 calculation and insertion.

MST sub-module

In the receive direction, the MST sub-module counts BIP-24 errored blocks, restores
the MS_REI, and detects the MS_RDI, MS_AIS, and MS-EXC.

In the transmit direction, the MST sub-module performs BIP-24 calculation and
insertion and inserts the MS_REI, MS_RDI, and MS_AIS.

The MST sub-module extracts or inserts the K1, K2, E2, D4D12, S1, B2, and M1
bytes.

MSA sub-module

In the receive direction, the MSA sub-module interprets the AU-4 pointer, detects the
LOP and AIS, and performs pointer justifications.

In the transmit direction, the MSA sub-module assembles the AUG and generates the
AU-4 pointer and the AU_AIS.

HPT sub-module

Terminates the overheads.

Restores the J1 path trace message.

Restores the REI information.

Detects the HP_RDI (monitors the status of the path).

Detects the UNEQ and AIS (monitors the signal label).

Counts the VC-4 BIP-8 errored blocks.

Logic and Control Module


l

Manages and configures the other modules of the board.

Performs inter-board communication through the internal Ethernet interface.

Traces the clock signal from the active and standby cross-connect units.

Controls the laser.

Passes the orderwire and ECC bytes through an ADM that consists of two paired slots when
the GSCC is not online.

Selects the clock signal and frame header signal from the active and standby cross-connect
units.

Controls the indicators on the board.

DC/DC Converter
It converts the 48/60 V power supply into the DC voltages that the modules of the board
require.

5.17.4 Front Panel


The front panel of the SLD16 has indicators, interfaces, a bar code, and a laser safety class label.
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Diagram of the Front Panel


Figure 5-41 shows the appearance of the front panel of the SLD16.
Figure 5-41 Front panel of the SLD16

SLD16
STAT
ACT
PROG
SRV

CLASS 1
LASER
PRODUCT

OUT1
IN1
OUT2
IN2

SLD16

Indicators
The front panel of the board has the following indicators:
l

Board hardware status indicator (STAT) two colors (red and green)

Service activation status indicator (ACT) one color (green)

Board software status indicator (PROG) two colors (red and green)

Service alarm indicator (SRV) three colors (red, green, and yellow)

For the meanings of the status of the indicators, see A Indicators.


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Interfaces
The front panel of the SLD16 has two optical interfaces. Table 5-75 describes the types and
usage of the optical interfaces of the SLD16.
Table 5-75 Optical interfaces of the SLD16
Interface

Type of
Interface

Usage

IN1IN2

LC

Receives optical signals.

OUT1OUT2

LC

Transmits optical signals.

5.17.5 Valid Slots


The slots valid for the SLD16 vary with the cross-connect capacity of the subrack.
The slots valid for the SLD16 are as follows:
l

When the cross-connect capacity is 60 Gbit/s, the SLD16 can be installed in slots 28 and
1116. When the SLD16 is installed in slots 27 and 1116, one optical interface can be
configured. When the SLD16 is installed in slot 8, one or two optical interfaces can be
configured.

When the cross-connect capacity is 110 Gbit/s, the SLD16 can be installed in slots 28 and
1116. In this case, one or two optical interfaces can be configured.

5.17.6 Feature Code


The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the SLD16 indicates the type of optical interface.
Table 5-76 provides the relationship between the feature code of the SLD16 and the type of
optical interface.
Table 5-76 Relationship between the feature code of the SLD16 and the type of optical interface
Board

Feature Code

Type of Optical Interface

SSN1SLD1600

00

SSN1SLD1601

01

I-16

SSN1SLD1602

02

S-16.1

SSN1SLD1603

03

L-16.1

SSN1SLD1604

04

L-16.2

5.17.7 Parameter Settings


You can set the parameters for the SLD16 by using the T2000.
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You can set the following parameters for the SLD16 by using the T2000:
l

J0

J1

J2

C2

For the description of each parameter, see F Parameter Settings.

5.17.8 Technical Specifications


The technical specifications of the SLD16 include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.

Parameters Specified for Optical Interfaces


Table 5-77 lists the parameters specified for the optical interfaces of the SLD16.
Table 5-77 Parameters specified for the optical interfaces of the SLD16

Issue 02 (2009-07-30)

Parameter

Value

Nominal bit
rate

2488320 kbit/s

Application
code

I-16

S-16.1

L-16.1

L-16.2

Transmissio
n distance
(km)

0 to 2

2 to 15

25 to 40

50 to 80

Type of fiber

Single-mode LC

Single-mode LC

Single-mode LC

Single-mode LC

Operating
wavelength
range (nm)

1266 to 1360

1260 to 1360

1280 to 1335

1500 to 1580

Launched
optical
power range
(dBm)

-10 to -3

-5 to 0

-2 to +3

-2 to +3

Receiver
sensitivity
(dBm)

-18

-18

-27

-28

Minimum
overload
(dBm)

-3

-9

-9

Minimum
extinction
ratio (dB)

8.2

8.2

8.2

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Laser Safety Class


The safety class of the laser on the board is Class 1. The maximum launched optical power of
the optical interfaces is less than 10 dBm (10 mW).

Mechanical Specifications
The mechanical specifications of the SLD16 are as follows:
l

Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)

Weight (kg): 0.9

Power Consumption
The maximum power consumption of the SLD16 at room temperature (25C) is 23 W.

5.18 SLQ16
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the SLQ16 (4xSTM-16 optical interface board).
5.18.1 Version Description
The SLQ16 is available in two functional versions, namely, N1 and N2. The difference between
the two versions is with regard to whether they support the TCM function and AU-3 services.
The N2SLQ16 is no longer manufactured.
5.18.2 Functions and Features
The SLQ16 receives and transmits 4xSTM-16 optical signals, processes overhead bytes, and
performs the MSP.
5.18.3 Working Principle and Signal Flow
The SLQ16 consists of the O/E converting module, MUX/DEMUX module, SDH overhead
processing module, logic and control module, DC/DC converter, and other modules.
5.18.4 Front Panel
The front panel of the SLQ16 has indicators, interfaces, a bar code, and a laser safety class label.
5.18.5 Valid Slots
The slots valid for the SLQ16 vary with the cross-connect capacity of the subrack.
5.18.6 Feature Code
The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the SLQ16 indicates the type of optical interface.
5.18.7 Parameter Settings
You can set the parameters for the SLQ16 by using the T2000.
5.18.8 Technical Specifications
The technical specifications of the SLQ16 include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.
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5.18.1 Version Description


The SLQ16 is available in two functional versions, namely, N1 and N2. The difference between
the two versions is with regard to whether they support the TCM function and AU-3 services.
The N2SLQ16 is no longer manufactured.
Table 5-78 describes the versions of the SLQ16.
Table 5-78 Versions of the SLQ16
Item

Description

Functional Versions

The SLQ16 is available in two functional versions, namely, N1 and


N2.

Differences

The N1SLQ16 does not support the TCM function or AU-3


services.

The N2SLQ16 supports the TCM function and AU-3 services, but
the TCM function and AU-3 services cannot be available at the
same time.

Substitution

When the AU-3 services and TCM function are not required, the
N1SLQ16 and N2SLQ16 can be substituted with each other.

NOTE

When you configure the MSP or SNCP, you cannot configure the N1SLQ16 as the protection board if the
working board is the N2SLQ16 on which the TCM function is enabled or AU-3 services are configured.
Otherwise, the services are interrupted when a switching operation is performed.

5.18.2 Functions and Features


The SLQ16 receives and transmits 4xSTM-16 optical signals, processes overhead bytes, and
performs the MSP.
Table 5-79 provides the functions and features of the SLQ16.
Table 5-79 Functions and features of the SLQ16

Issue 02 (2009-07-30)

Function and
Feature

SLQ16

Basic functions

Transmits and receives 4xSTM-16 optical signals.

Specifications of
the optical interface

Supports different types of standard optical interfaces, namely, the I-16,


S-16.1, L-16.1, and L-16.2. The characteristics of the optical interfaces
comply with ITU-T G.957 and ITU-T G.692.

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Function and
Feature

SLQ16

Specifications of
the optical module

Supports the detection and query of the information about the optical
module.

Provides the ALS function. The optical interface supports the setting
of the on/off state of a laser.

Supports the usage and detection of the SFP optical module, which
facilitates the maintenance and upgrading of the optical module.

Supports the VC-12 services, VC-3 services, VC-4 services, and


VC-4-4c to VC-4-16c concatenation services.

The N2SLQ16 supports the AU-3 services.

Processes the section overheads of the STM-16 signals.

Supports the configuration of the D1D12, E1, and E2 bytes as


transparent transmission bytes or into other unused overheads bytes.

Supports the transparent transmission and termination of the path


overheads.

Supports the setting and query of the J0, J1, J2, and C2 bytes.

Supports one to four channels of ECC communication.

Service processing

Overhead
processing

Alarms and
performance events

Reports various alarms and performance events, which facilitates the


management and maintenance of the equipment.

Specifications of
the REG

Does not support the REG.

Protection schemes

Supports the two-fiber ring MSP, four-fiber ring MSP, linear MSP,
SNCP, SNCTP, and SNCMP.

Supports the fiber-shared MSP and SNCP and processes eight sets
of K bytes. A single optical interface supports two MSP protection
rings. One SLQ16 supports a maximum of eight MSP protection
rings.

Supports inloops and outloops at optical interfaces.

The N1SLQ16 supports inloops and outloops on VC-4 paths.

Supports warm resets and cold resets. The warm reset does not affect
services.

Supports the query of the manufacturing information of the board.

Supports the in-service loading of the FPGA.

Supports the upgrade of the board software without affecting


services.

Supports the press-to-collect function in fault data collection.

The N2SLQ16 supports the TCM function.

Maintenance
features

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5.18.3 Working Principle and Signal Flow


The SLQ16 consists of the O/E converting module, MUX/DEMUX module, SDH overhead
processing module, logic and control module, DC/DC converter, and other modules.
Figure 5-42 shows the functional block diagram of the SLQ16 by describing how to process
1xSTM-16 signals.
Figure 5-42 Functional block diagram of the SLQ16
Backplane
155 MHz
PLL

155 MHz

2.488
Gbit/s

2.488
Gbit/s

O/E

2.488
Gbit/s

2.488
Gbit/s

E/O
O/E
converting
module

16x155
Mbit/s

MUX

Cross-connect
unit

K1 and K2

Cross-connect
unit

K1 and K2
insertion/extraction

DEMU 16x155
X
Mbit/s

SPI

Reference clock

High-speed
bus
RST MST MSA HPT

High-speed
bus
DCC

SDH overhead
processing module

MUX/
DEMUX
IIC
LOS
Laser shutdown

Logic and
control module
+3.3 V
DC/DC
Converter

Frame header
Communication
Fuse

DC/DC
Converter

Cross-connect
unit A
Cross-connect
unit B
SCC unit

Cross-connect
unit
SCC unit
-48 V/-60
V
-48 V/-60 V

PLL: phase-locked loop

SPI: SDH physical interface

RST: regenerator section


termination

MST: multiplex section termination MSA: multiplex section adaptation

HPT: higher order path termination IIC: inter-integrated circuit

SDH: synchronous digital hierarchy

O/E Converting Module


l

In the receive direction, the module converts the received optical signals into electrical
signals.

In the transmit direction, the module converts the electrical signals into SDH optical signals
and sends the SDH optical signals to fibers for transmission.

The SPI detects the R_LOS alarm and provides the function of shutting down the laser.

MUX/DEMUX Module
l

In the receive direction, the DEMUX part demultiplexes the high-rate electrical signals into
multiple parallel electrical signals and restores the clock signal at the same time.

In the transmit direction, the MUX part multiplexes the parallel electrical signals received
from the SDH overhead processing module into high-rate electrical signals.

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SDH Overhead Processing Module


This module includes the RST, MST, MSA, and HPT sub-modules. This module provides the
inloop and outloop functions.
l

RST sub-module

In the receive direction, the RST sub-module detects the frame alignment bytes (A1 and
A2), performs descrambling, restores the regenerator section trace byte (J0), detects a
J0 mismatch, and counts BIP-8 errored blocks.

In the transmit direction, the RST sub-module inserts the frame alignment bytes, inserts
the J0 byte, performs scrambling, and performs BIP-8 calculation and insertion.

MST sub-module

In the receive direction, the MST sub-module counts BIP-24 errored blocks, restores
the MS_REI, and detects the MS_RDI, MS_AIS, and MS-EXC.

In the transmit direction, the MST sub-module performs BIP-24 calculation and
insertion and inserts the MS_REI, MS_RDI, and MS_AIS.

The MST sub-module extracts or inserts the K1, K2, E2, D4D12, S1, B2, and M1
bytes.

MSA sub-module

In the receive direction, the MSA sub-module interprets the AU-4 pointer, detects the
LOP and AIS, and performs pointer justifications.

In the transmit direction, the MSA sub-module assembles the AUG and generates the
AU-4 pointer and the AU_AIS.

HPT sub-module

Terminates the overheads.

Restores the J1 path trace message.

Restores the REI information.

Detects the HP_RDI (monitors the status of the path).

Detects the UNEQ and AIS (monitors the signal label).

Counts the VC-4 BIP-8 errored blocks.

Logic and Control Module


l

Manages and configures the other modules of the board.

Performs inter-board communication through the internal Ethernet interface.

Traces the clock signal from the active and standby cross-connect units.

Passes the orderwire and ECC bytes through an ADM that consists of two paired slots when
the GSCC is not online.

Selects the clock signal and frame header signal from the active and standby cross-connect
units.

Controls the indicators on the board.

DC/DC Converter
It converts the 48/60 V power supply into the DC voltages that the modules of the board
require.
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5.18.4 Front Panel


The front panel of the SLQ16 has indicators, interfaces, a bar code, and a laser safety class label.

Diagram of the Front Panel


Figure 5-43 shows the appearance of the front panel of the N1SLQ16.
Figure 5-43 Front panel of the N1SLQ16

SLQ16
STAT
ACT
PROG
SRV

CLASS 1
LASER
PRODUCT

OUT1
IN1
OUT2
IN2
OUT3
IN3
OUT4
IN4

SLQ16

Figure 5-44 shows the appearance of the front panel of the N2SLQ16.

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Figure 5-44 Front panel of the N2SLQ16

SLQ16
STAT
ACT
PROG
SRV

CLASS 1
LASER
PRODUCT

OUT1
IN1
OUT2
IN2
OUT3
IN3
OUT4
IN4

SLQ16

Indicators
The front panel of the board has the following indicators:
l

Board hardware status indicator (STAT) two colors (red and green)

Service activation status indicator (ACT) one color (green)

Board software status indicator (PROG) two colors (red and green)

Service alarm indicator (SRV) three colors (red, green, and yellow)

For the meanings of the status of the indicators, see A Indicators.

Interfaces
The front panel of the SLQ16 has four optical interfaces. Table 5-80 describes the types and
usage of the optical interfaces of the SLQ16.
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Table 5-80 Optical interfaces of the SLQ16


Interface

Type of
Interface

Usage

IN1IN4

LC

Receives optical signals.

OUT1OUT4

LC

Transmits optical signals.

5.18.5 Valid Slots


The slots valid for the SLQ16 vary with the cross-connect capacity of the subrack.
l

When the cross-connect capacity is 60 Gbit/s, the SLQ16 can be installed in slot 8. In this
case, one or two optical interfaces can be configured.

When the cross-connect capacity is 110 Gbit/s, the SLQ16 can be installed in slots 28 and
1116. When the SLQ16 is installed in slots 26 and 1316, one or two optical interfaces
can be configured. When the SLQ16 is installed in slots 7, 8, 11, and 12, one to four optical
interfaces can be configured.

5.18.6 Feature Code


The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the SLQ16 indicates the type of optical interface.
Table 5-81 provides the relationship between the feature code of the SLQ16 and the type of
optical interface.
Table 5-81 Relationship between the feature code of the SLQ16 and the type of optical interface

Issue 02 (2009-07-30)

Board

Feature Code

Type of Optical Interface

SSN1SLQ1601 and
SSN2SLQ1601

01

I-16

SSN1SLQ1602 and
SSN2SLQ1602

02

S-16.1

SSN1SLQ1603 and
SSN2SLQ1603

03

L-16.1

SSN1SLQ1604 and
SSN2SLQ1604

04

L-16.2

SSN1SLQ16A10

10

I-16

SSN1SLQ16A11

11

S-16.1

SSN1SLQ16A12

12

L-16.1

SSN1SLQ16A13

13

L-16.2

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5.18.7 Parameter Settings


You can set the parameters for the SLQ16 by using the T2000.
You can set the following parameters for the SLQ16 by using the T2000:
l

J0

J1

J2

C2

For the description of each parameter, see F Parameter Settings.

5.18.8 Technical Specifications


The technical specifications of the SLQ16 include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.

Parameters Specified for Optical Interfaces


Table 5-82 lists the parameters specified for the optical interfaces of the SLQ16.
Table 5-82 Parameters specified for the optical interfaces of the SLQ16

5-154

Parameter

Value

Nominal bit rate

2488320 kbit/s

Application code

I-16

S-16.1

L-16.1

L-16.2

Transmission
distance (km)

0 to 2

2 to 15

25 to 40

50 to 80

Type of fiber

Single-mode
LC

Single-mode
LC

Single-mode LC

Single-mode
LC

Operating
wavelength range
(nm)

1266 to 1360

1260 to 1360

1280 to 1335

1500 to 1580

Launched optical
power range (dBm)

-10 to -3

-5 to 0

-2 to +3

-2 to +3

Receiver sensitivity
(dBm)

-18

-18

-27

-28

Minimum overload
(dBm)

-3

-9

-9

Minimum extinction
ratio (dB)

8.2

8.2

8.2

8.2

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Laser Safety Class


The safety class of the laser on the board is Class 1. The maximum launched optical power of
the optical interfaces is less than 10 dBm (10 mW).

Mechanical Specifications
The mechanical specifications of the SLQ16 are as follows:
l

Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)

Weight of the N1SLQ16 (kg): 0.9

Weight of the N2SLQ16 (kg): 1.3

Power Consumption
The maximum power consumption of the N1SLQ16 at room temperature (25C) is 20 W.
The maximum power consumption of the N2SLQ16 at room temperature (25C) is 35 W.

5.19 SF16
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the SF16 (1xSTM-16 optical interface board with the out-band FEC
function).
5.19.1 Version Description
The SF16 is available in one functional version, namely, N1.
5.19.2 Functions and Features
The SF16 receives and transmits 1xOTU1 optical signals (2.666 Gbit/s with the FEC function)
and processes overhead bytes.
5.19.3 Working Principle and Signal Flow
The SF16 consists of the O/E converting module, MUX/DEMUX module, FEC module, SDH
overhead processing module, logic and control module, DC/DC converter, and other modules.
5.19.4 Front Panel
The front panel of the SF16 has indicators, interfaces, a bar code, and a laser safety class label.
5.19.5 Valid Slots
The SF16 can be installed in slots 28 and 1116 in the OptiX OSN 3500 II subrack.
5.19.6 Parameter Settings
You can set the parameters for the SF16 by using the T2000.
5.19.7 Technical Specifications
The technical specifications of the SF16 include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.

5.19.1 Version Description


The SF16 is available in one functional version, namely, N1.

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5.19.2 Functions and Features


The SF16 receives and transmits 1xOTU1 optical signals (2.666 Gbit/s with the FEC function)
and processes overhead bytes.
Table 5-83 provides the functions and features of the SF16.
Table 5-83 Functions and features of the SF16
Function and
Feature

SF16

Basic functions

Receives and transmits 1xOTU1 optical signals (2.666 Gbit/s with the
FEC function).

Supports the enabling or disabling of the FEC function.

Supports different types of standard optical interfaces, namely, the


Ve-16.2c, Ve-16.2d, and Ve-16.2f. The characteristics of the optical
interfaces comply with the standards defined by Huawei.

Supports the output of the standard wavelengths that comply with ITUT G.692 and can be directly connected to the DWDM equipment.

Specifications
of the optical
module

Supports the detection and query of the information about the optical
module.

Provides the ALS function. The optical interface supports the setting of
the on/off state of a laser.

Service
processing

Supports the VC-12 services, VC-3 services, VC-4 services, VC-4-4c


concatenation services, VC-4-8c concatenation services, and VC-4-16c
concatenation services.

Encapsulates and encodes the signals with the FEC function, and
processes overhead bytes, which comply with ITU-T G.709.

Supports the processing of the OTU, ODU, and OPU overhead bytes,
performance monitoring, and alarm detection, which comply with ITUT G.709.

Processes the section overheads of the STM-16 signals.

Supports the transparent transmission and termination of the path


overheads.

Supports the setting and query of the J0, J1, J2, and C2 bytes.

Supports one channel of ECC communication.

Alarms and
performance
events

Reports various alarms and performance events.

Supports the alarms and performance events that are related to the OTU
layer, ODU layer, OPU layer, and FEC function.

Specifications
of the REG

Does not support the REG.

Specifications
of the optical
interface

Overhead
processing

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Function and
Feature

SF16

Protection
schemes

Supports the two-fiber ring MSP, four-fiber ring MSP, linear MSP,
SNCP, SNCTP, and SNCMP.

Supports the fiber-shared MSP and SNCP and processes two sets of K
bytes. One SF16 supports a maximum of two MSP protection rings.

Supports inloops and outloops at optical interfaces.

Supports inloops on VC-4 paths.

Supports warm resets and cold resets. The warm reset does not affect
services.

Supports the query of the manufacturing information of the board.

Supports the in-service loading of the FPGA.

Supports the upgrade of the board software without affecting services.

Supports the press-to-collect function in fault data collection.

Maintenance
features

5.19.3 Working Principle and Signal Flow


The SF16 consists of the O/E converting module, MUX/DEMUX module, FEC module, SDH
overhead processing module, logic and control module, DC/DC converter, and other modules.
Figure 5-45 shows the functional block diagram of the SF16.
Figure 5-45 Functional block diagram of the SF16
155 MHz PLL

2.666
Gbit/s

2.666
Gbit/s

2.666
Gbit/s

O/E
S
P
I

DEMUX

16x166
Mbit/s

Reference clock

155 MHz PLL

K1 and K2 insertion/
extraction

16x155
Mbit/s

K1 and K2

High-speed
bus

FEC

2.666
Gbit/s

E/O

16x166
Mbit/s

155 MHz

16x155
Mbit/s

RST

MST

MSA

HPT

High-speed
bus

MUX
DCC
SDH overhead processing
module

166 MHz PLL


IIC
LOS
Laser shutdown

Frame header
Logic and
control module
+3.3 V

DC/DC
converter

PLL: phase-locked loop

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Communication

DC/DC
converter

Fuse

Cross-connect
unit

Cross-connect
unit
Cross-connect
unit
Cross-connect
unit
SCC unit

Cross-connect
unit
SCC unit
-48 V/-60 V
-48 V/-60 V

SDH: synchronous digital hierarchy

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RST: regenerator section
termination

MST: multiplex section termination MSA: multiplex section adaptation

HPT: higher order path termination IIC: inter-integrated circuit

The functional modules are described as follows:

O/E Converting Module


l

In the receive direction, the module converts the received 2.666 Gbit/s FEC optical signals
into electrical signals.

In the transmit direction, the module converts the electrical signals into SDH optical signals
and sends the SDH optical signals to fibers for transmission.

The SPI detects the R_LOS alarm and provides the function of shutting down the laser.

MUX/DEMUX Module
l

In the receive direction, the DEMUX part demultiplexes the high-rate electrical signals into
multiple parallel electrical signals and restores the clock signal at the same time.

In the transmit direction, the MUX part multiplexes the parallel electrical signals received
from the FEC module into high-rate electrical signals.

In the downstream direction, the FEC encoding and decoding module receives 2.488 Gbit/
s SDH signals, which are sent by the SDH overhead processing module. After frame
searching, FEC encoding, data packet encapsulation, and scrambling, the 2.488 Gbit/s SDH
signals are converted into 2.666 Gbit/s signals and then transmitted to the MUX module.

In the upstream direction, the reverse process is performed. The FEC encoding and
decoding module receives the 2.666 Gbit/s signals from the DEMUX module. After frame
searching, FEC encoding, data packets encapsulation, and scrambling in the FEC module,
the 2.488 Gbit/s signals are recovered and then transmitted to the SDH overhead processing
module. The frame format of the 2.666 Gbit/s signals complies with ITU G.709.

The FEC processing module is connected to the logic and control module through a CPU
bus. The CPU controls the working modes of the FEC module by configuring the internal
register. The working mode can be the regenerator mode, namely, REG mode. The CPU
can monitor the performance through the internal register.

FEC Module

SDH Overhead Processing Module


This module includes the RST, MST, MSA, and HPT sub-modules. This module provides the
inloop and outloop functions.
l

5-158

RST sub-module

In the receive direction, the RST sub-module detects the frame alignment bytes (A1 and
A2), performs descrambling, restores the regenerator section trace byte (J0), detects a
J0 mismatch, and counts BIP-8 errored blocks.

In the transmit direction, the RST sub-module inserts the frame alignment bytes, inserts
the J0 byte, performs scrambling, and performs BIP-8 calculation and insertion.

MST sub-module
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In the receive direction, the MST sub-module counts BIP-24 errored blocks, restores
the MS_REI, and detects the MS_RDI, MS_AIS, and MS-EXC.

In the transmit direction, the MST sub-module performs BIP-24 calculation and
insertion and inserts the MS_REI, MS_RDI, and MS_AIS.

The MST sub-module extracts or inserts the K1, K2, E2, D4D12, S1, B2, and M1
bytes.

MSA sub-module

In the receive direction, the MSA sub-module interprets the AU-4 pointer, detects the
LOP and AIS, and performs pointer justifications.

In the transmit direction, the MSA sub-module assembles the AUG and generates the
AU-4 pointer and the AU_AIS.

HPT sub-module

Terminates the overheads.

Restores the J1 path trace message.

Restores the REI information.

Detects the HP_RDI (monitors the status of the path).

Detects the UNEQ and AIS (monitors the signal label).

Counts the VC-4 BIP-8 errored blocks.

Logic and Control Module


l

Manages and configures the other modules of the board.

Performs inter-board communication through the internal Ethernet interface.

Traces the clock signal from the active and the standby cross-connect unit.

Controls the laser.

Passes the orderwire and ECC bytes through an ADM that consists of two paired slots when
the CXL is not online.

Selects the clock signal and frame header signal from the active and standby cross-connect
units.

Controls the indicators on the board.

DC/DC Converter
It converts the 48/60 V power supply into the DC voltages that the modules of the board
require.

5.19.4 Front Panel


The front panel of the SF16 has indicators, interfaces, a bar code, and a laser safety class label.

Diagram of the Front Panel


Figure 5-46 shows the appearance of the front panel of the SF16.

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Figure 5-46 Front panel of the SF16

SF16
STAT
ACT
PROG
SRV

CLASS 1
LASER
PRODUCT

OUT

IN

SF16

Indicators
The front panel of the board has the following indicators:
l

Board hardware status indicator (STAT) two colors (red and green)

Service activation status indicator (ACT) one color (green)

Board software status indicator (PROG) two colors (red and green)

Service alarm indicator (SRV) three colors (red, green, and yellow)

For the meanings of the status of the indicators, see A Indicators.

Interfaces
The front panel of the SF16 has one optical interface. Table 5-84 describes the types and usage
of the optical interfaces of the SF16.
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NOTE

The SF16 uses the unswappable optical module.

Table 5-84 Optical interfaces of the SF16


Interface

Type of
Interface

Usage

IN

LC

Receives optical signals.

OUT

LC

Transmits optical signals.

5.19.5 Valid Slots


The SF16 can be installed in slots 28 and 1116 in the OptiX OSN 3500 II subrack.

5.19.6 Parameter Settings


You can set the parameters for the SF16 by using the T2000.
You can set the following parameters for the SF16 by using the T2000:
l

J0

J1

J2

C2

For the description of each parameter, see F Parameter Settings.

5.19.7 Technical Specifications


The technical specifications of the SF16 include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.

Parameters Specified for Optical Interfaces


Table 5-85 lists the parameters specified for the optical interfaces of the SF16.
Table 5-85 Parameters specified for the optical interfaces of the SF16

Issue 02 (2009-07-30)

Parameter

Value

Nominal bit rate

2666057.143 kbit/s

Processing capability

1xSTM-16 standard services or concatenation services

Line code pattern

NRZ

Application codea

Ue-16.2c

Ue-16.2d

Ue-16.2f

FEC + BA (14) +
PA

FEC + BA (17) +
PA

FEC + BA (17) + RA + PA

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Parameter

Value

Type of fiber

Single-mode LC

Operating
wavelength range
(nm)

1550.12

Launched optical
power range (dBm)b

Single-mode LC

Single-mode LC

-5 to -1

-5 to -1

-5 to -1

Launched optical
power range (dBm)c

13 to 15

13 to 15

15 to 18

Receiver sensitivity
(dBm)b

-27.5

-27.5

-27.5

Receiver sensitivity
(dBm)d

-37

-37

-42

Minimum overload
(dBm)d

-10

-10

-10

Minimum extinction
ratio (dB)b

10

10

10

a: The numbers in the brackets indicate the corresponding parameter values. For example,
"BA (14)" indicates that the optical power amplified by the BA is 14 dBm. "FEC + BA + PA
+ RA" indicates that the specifications of the optical interface are measured when the FEC,
BA, PA, and Raman amplifier are used.
b: The parameter values are applicable only to the optical modules. The parameter values of
the amplifier are not provided.
c: The parameter values are applicable to the BA.
d: The parameter values are applicable to the PA.

Table 5-86 lists the parameters specified for the colored optical interfaces of the SF16.
Table 5-86 Parameters specified for the optical interfaces that comply with the standard
wavelengths specified in ITU-T G.692

5-162

Parameter

Value

Nominal bit rate

2666057.143 kbit/s

Dispersion limit (km)

640

Mean launched optical


power (dBm)

-5 to -1

Receiver sensitivity (dBm)

-28

Minimum overload (dBm)

-9

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Parameter

Value

Maximum allowed
dispersion (ps/nm)

10880

Minimum extinction ratio


(dB)

8.2

5 SDH Boards

Laser Safety Class


The safety class of the laser on the board is Class 1. The maximum launched optical power of
the optical interfaces is less than 10 dBm (10 mW).

Mechanical Specifications
The mechanical specifications of the SF16 are as follows:
l

Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)

Weight (kg): 1.1

Power Consumption
The maximum power consumption of the SF16 at room temperature (25C) is 26 W.

5.20 SL64
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the SL64 (1xSTM-64 optical interface board).
5.20.1 Version Description
The SL64 is available in one functional version, namely, N1.
5.20.2 Functions and Features
The SL64 receives and transmits 1xSTM-64 optical signals and processes overhead bytes.
5.20.3 Working Principle and Signal Flow
The N1SL64 consists of the O/E converting module, MUX/DEMUX Module, SDH overhead
processing module, logic and control module, lower order alarm processing module, DC/DC
converter, and other modules.
5.20.4 Front Panel
The front panel of the SL64 has indicators, interfaces, a bar code, a laser safety class label, and
an APD alarm label.
5.20.5 Valid Slots
The slots valid for the SL64 vary with the cross-connect capacity of the subrack.
5.20.6 Feature Code
The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the SL64 indicates the type of optical interface.
5.20.7 Parameter Settings
You can set the parameters for the SL64 by using the T2000.
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5.20.8 Technical Specifications


The technical specifications of the SL64 include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.

5.20.1 Version Description


The SL64 is available in one functional version, namely, N1.

5.20.2 Functions and Features


The SL64 receives and transmits 1xSTM-64 optical signals and processes overhead bytes.
Table 5-87 provides the functions and features of the SL64.
Table 5-87 Functions and features of the SL64

5-164

Function and
Feature

SL64

Basic functions

Transmits and receives 1xSTM-64 optical signals.

Specifications of the
optical interface

Supports the output of the standard wavelengths that comply with


ITU-T G.692. The V-64.2b optical interface can be directly
connected to the DWDM equipment.

Specifications of the
optical module

Supports the detection and query of the information about the


optical module.

Provides the ALS function. The optical interface supports the


setting of the on/off state of a laser.

Service processing

Supports the VC-12 services, VC-3 services, and VC-4 services.

Overhead processing

Processes the section overheads of the STM-64 signals.

Supports the transparent transmission and termination of the path


overheads.

Supports the setting and query of the J0, J1, J2, and C2 bytes.

Supports one channel of ECC communication.

Alarms and
performance events

Reports various alarms and performance events.

Specifications of the
REG

Supports the setting and query of the REG working mode.

Protection schemes

Supports the two-fiber ring MSP, four-fiber ring MSP, linear MSP,
SNCP, SNCTP, and SNCMP.

Supports the fiber-shared SNCP and MSP and processes two sets
of K bytes. One SL64 supports a maximum of two MSP protection
rings.

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Function and
Feature

SL64

Maintenance
features

Supports inloops and outloops at optical interfaces.

The supports inloops and outloops on VC-4 paths.

Supports warm resets and cold resets. The warm reset does not
affect services.

Supports the query of the manufacturing information of the board.

Supports the in-service loading of the FPGA.

The supports the TCM function.

Supports the upgrade of the board software without affecting


services.

Supports the press-to-collect function in fault data collection.

5.20.3 Working Principle and Signal Flow


The N1SL64 consists of the O/E converting module, MUX/DEMUX Module, SDH overhead
processing module, logic and control module, lower order alarm processing module, DC/DC
converter, and other modules.
Figure 5-47 shows the functional block diagram of the N1SL64.
Figure 5-47 Functional block diagram of the N1SL64
Backplane
622 MHz
PLL

622 MHz

9.953
Gbit/s

SPI 9.953
E/O
Gbit/s

O/E
SPI
E/
O
O/E
converting
module

9.953
Gbit/s

MUX

16x622
Mbit/s

Cross-connect
unit

K1 and K2

Cross-connect
unit

K1 and K2
insertion/extraction

DEMU 16x622
X
Mbit/s

. .
. .

9.953
Gbit/s

O/E

Reference clock

High-speed
bus
RST MST MSA HPT

High-speed
bus
DCC

SDH overhead
processing module

MUX/
DEMUX
IIC
LOS
Laser shutdown

Logic and
control module
+3.3 V
DC/DC
Converter

Frame header
Communication
Fuse

DC/DC
Converter

Cross-connect
unit A
Cross-connect
unit B
SCC unit

Cross-connect
unit
SCC unit
-48 V/-60
V
-48 V/-60 V

PLL: phase-locked loop

SPI: SDH physical interface

RST: regenerator section


termination

MST: multiplex section termination MSA: multiplex section adaptation

HPT: higher order path termination IIC: inter-integrated circuit

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The functional modules are described as follows:

O/E Converting Module


l

In the receive direction, the module converts the received optical signals into electrical
signals.

In the transmit direction, the module converts the electrical signals into SDH optical signals
and sends the SDH optical signals to fibers for transmission.

The SPI detects the R_LOS alarm and provides the function of shutting down the laser.

MUX/DEMUX Module
l

In the receive direction, the DEMUX part demultiplexes the high-rate electrical signals into
multiple parallel electrical signals and restores the clock signal at the same time.

In the transmit direction, the MUX part multiplexes the parallel electrical signals received
from the SDH overhead processing module into high-rate electrical signals.

SDH Overhead Processing Module


This module includes the RST, MST, MSA, and HPT sub-modules. This module provides the
inloop and outloop functions.
l

5-166

RST sub-module

In the receive direction, the RST sub-module detects the frame alignment bytes (A1 and
A2), performs descrambling, restores the regenerator section trace byte (J0), detects a
J0 mismatch, and counts BIP-8 errored blocks.

In the transmit direction, the RST sub-module inserts the frame alignment bytes, inserts
the J0 byte, performs scrambling, and performs BIP-8 calculation and insertion.

MST sub-module

In the receive direction, the MST sub-module counts BIP-24 errored blocks, restores
the MS_REI, and detects the MS_RDI, MS_AIS, and MS-EXC.

In the transmit direction, the MST sub-module performs BIP-24 calculation and
insertion and inserts the MS_REI, MS_RDI, and MS_AIS.

The MST sub-module extracts or inserts the K1, K2, E2, D4D12, S1, B2, and M1
bytes.

MSA sub-module

In the receive direction, the MSA sub-module interprets the AU-4 pointer, detects the
LOP and AIS, and performs pointer justifications.

In the transmit direction, the MSA sub-module assembles the AUG and generates the
AU-4 pointer and the AU_AIS.

HPT sub-module

Terminates the overheads.

Restores the J1 path trace message.

Restores the REI information.

Detects the HP_RDI (monitors the status of the path).

Detects the UNEQ and AIS (monitors the signal label).


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Counts the VC-4 BIP-8 errored blocks.

Logic and Control Module


l

Manages and configures the other modules of the board.

Performs inter-board communication through the internal Ethernet interface.

Traces the clock signal from the active and standby cross-connect units.

Controls the laser.

Passes the orderwire and ECC bytes through an ADM that consists of two paired slots when
the is not online.

Selects the clock signal and frame header signal from the active and standby cross-connect
units.

Controls the indicators on the board.

DC/DC Converter
It converts the 48/60 V power supply into the DC voltages that the modules of the board
require.

5.20.4 Front Panel


The front panel of the SL64 has indicators, interfaces, a bar code, a laser safety class label, and
an APD alarm label.

Diagram of the Front Panel


Figure 5-48 shows the appearance of the front panel of the SL64.

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Figure 5-48 Appearance of the front panel of the SL64

SL64
STAT
ACT
PROG
SRV

CLASS 1
LASER
PRODUCT

APD

Receiver
MAX:-9dBm

OUT

IN

SL64

Indicators
The front panel of the board has the following indicators:
l

Board hardware status indicator (STAT) two colors (red and green)

Service activation status indicator (ACT) one color (green)

Board software status indicator (PROG) two colors (red and green)

Service alarm indicator (SRV) three colors (red, green, and yellow)

For the meanings of the status of the indicators, see A Indicators.

Interfaces
The front panel of the SL64 has one optical interface. Table 5-88 describes the types and usage
of the optical interfaces of the SL64.
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Table 5-88 Optical interfaces of the SL64


Interface

Type of
Interface

Usage

IN

LC

Receives optical signals.

OUT

LC

Transmits optical signals.

5.20.5 Valid Slots


The slots valid for the SL64 vary with the cross-connect capacity of the subrack.
The slots valid for the SL64 are as follows:
l

When the cross-connect capacity is 60 Gbit/s, the SL64 cannot be installed in any slot of
the subrack.

When the cross-connect capacity is 110 Gbit/s or 200 Gbit/s, the SL64 can be installed in
slots 7, 8, 11, and 12.

5.20.6 Feature Code


The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the SL64 indicates the type of optical interface.
Table 5-89 provides the relationship between the feature code of the SL64 and the type of optical
interface.
Table 5-89 Relationship between the feature code of the SL64 and the type of optical interface

Issue 02 (2009-07-30)

Board

Feature Code

Type of Optical Interface

SSN1SL6400

00

Fixed-wavelength optical
interface

SSN1SL6401

01

I-64.2

SSN1SL6402

02

S-64.2b

SSN1SL6403

03

Le-64.2

SSN1SL6404

04

Ls-64.2

SSN1SL6405

05

L-64.2b

SSN1SL6406

06

V-64.2b

SSN2SL6400

00

Fixed-wavelength optical
interface

SSN2SL6411

11

I-64.2

SSN2SL6412

12

S-64.2b

SSN2SL6413

13

Le-64.2

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Board

Feature Code

Type of Optical Interface

SSN2SL6404

04

Ls-64.2

SSN2SL6415

15

L-64.2b

SSN2SL6416

16

V-64.2b

SSN3SL6401

01

I-64.1

SSN3SL6402

02

S-64.2b

5.20.7 Parameter Settings


You can set the parameters for the SL64 by using the T2000.
You can set the following parameters for the SL64 by using the T2000:
l

J0

J1

J2

C2

For the description of each parameter, see F Parameter Settings.

5.20.8 Technical Specifications


The technical specifications of the SL64 include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.

Parameters Specified for Optical Interfaces


Table 5-90 lists the parameters specified for the optical interfaces of the SL64.
Table 5-90 Parameters specified for the optical interfaces of the SL64

5-170

Paramet
er

Value

Nominal
bit rate

9953280 kbit/s

Applicati
on code

I-64.1

I-64.2

S-64.
2b

L-64.2b (BA)

Le-64
.2

Ls-64
.2

V-64.2b (BA +
PA + DCU)a

Transmiss
ion
distance
(km)

0 to 2

0 to
25

2 to 40

35 to 80

35 to
60

55 to
80

80 to 120

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Paramet
er

Value

Type of
fiber

Singl
emode
LC

Singl
emode
LC

Single
-mode
LC

Single-mode
LC

Singl
emode
LC

Singl
emode
LC

Single-mode LC

Operating
wavelengt
h range
(nm)

1290
to
1330

1530
to
1565

1530
to
1565

1530 to 1565

1530
to
1565

1530
to
1565

1550.12

Mean
launched
optical
power
(dBm)

-6 to
-1

-5 to
-1

-1 to
+2

-4 to +2
(without the
BA)

2 to 4

4 to 7

-4 to -1 (without
the BA, PA, or
DCU)

Receiver
sensitivity
(dBm)

-11

Minimum
overload
(dBm)

-1

-1

-1

-1

-8

-8

-1

Minimum
extinction
ratio (dB)

8.2

8.2

8.2

8.2

8.2

8.2

Maximum
dispersion
tolerance
(ps/nm)

6.6

500

800

1600

1200

1600

2040c

13 to 15 (with
the BA)
-14

-14

-14

13 to 15 (with the
BA)
-21

-21

-14 (without the


PA, BA, or DCU)
-26 (with the PA)

a: "BA + PA + DCU" indicates that the specifications of the V-64.2b optical interface are
measured when the BA, PA, and DCU are used.
c: The dispersion coefficient is 17 ps/nm when signals are transmitted by the G.652 fibers at
the wavelength of 1550.12 nm. Hence, the dispersion tolerance is 2040 ps/nm for a 120-km
distance.

Table 5-91 lists the parameters specified for the colored optical interfaces of the SL64.
Table 5-91 Parameters specified for the optical interfaces that comply with the standard
wavelengths specified in ITU-T G.692

Issue 02 (2009-07-30)

Parameter

Value

Nominal bit rate

9953280 kbit/s

Dispersion limit (km)

40

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Parameter

Value

Mean launched optical power (dBm)

-4 to -1

Receiver sensitivity (dBm)

-14

Minimum overload (dBm)

-1

Maximum allowed dispersion (ps/


nm)

800

Minimum extinction ratio (dB)

10

Laser Safety Class


The safety class of the laser on the board is Class 1. The maximum launched optical power of
the optical interfaces is less than 10 dBm (10 mW).

Mechanical Specifications
The mechanical specifications of the SL64 are as follows:
l

Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)

Weight (kg): 1.1

Power Consumption
The maximum power consumption of the N1SL64 at room temperature (25C) is 30 W.
The maximum power consumption of the N2SL64 at room temperature (25C) is 32 W.

5.21 SF64
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the SF64 (1xSTM-64 optical interface board with the FEC function).
5.21.1 Version Description
The SF64 is available in one functional version, namely, N1.
5.21.2 Functions and Features
The SF64 receives and transmits 1xSTM-64 optical signals and processes overhead bytes.
5.21.3 Working Principle and Signal Flow
The SF64 consists of the O/E converting module, MUX/DEMUX module, SDH overhead
processing module, logic and control module, DC/DC converter, and other modules.
5.21.4 Front Panel
The front panel of the SF64 has indicators, interfaces, a bar code, and a laser safety class label.
5.21.5 Valid Slots
The slots valid for the SF64 vary with the cross-connect capacity of the subrack.
5.21.6 Parameter Settings
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You can set the parameters for the SF64 by using the T2000.
5.21.7 Technical Specifications
The technical specifications of the SF64 include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.

5.21.1 Version Description


The SF64 is available in one functional version, namely, N1.

5.21.2 Functions and Features


The SF64 receives and transmits 1xSTM-64 optical signals and processes overhead bytes.
Table 5-92 provides the functions and features of the SF64.
Table 5-92 Functions and features of the SF64
Function and
Feature

SF64

Basic functions

Transmits and receives 1xSTM-64 optical signals.

Supports the enabling or disabling of the FEC function.

Supports different types of standard optical interfaces, namely, the


Ue-64.2c, Ue-64.2d, and Ue-64.2e. The characteristics of the optical
interfaces comply with the standards defined by Huawei.

Supports the output of the standard wavelengths that comply with


ITU-T G.692 and can be directly connected to the DWDM
equipment.

Supports the detection and query of the information about the optical
module.

Provides the ALS function. The optical interface supports the setting
of the on/off state of a laser.

Specifications of
the optical interface

Specifications of
the optical module

Issue 02 (2009-07-30)

Service processing

Supports the VC-12 services, VC-3 services, VC-4 services, VC-4-4c


concatenation services, VC-4-8c concatenation services, VC-4-16c
concatenation services, and VC-4-64c concatenation services.

Overhead
processing

Processes the section overheads of the STM-64 signals.

Supports the transparent transmission and termination of the path


overheads.

Supports the setting and query of the J0, J1, J2, and C2 bytes.

Supports one channel of ECC communication.

Alarms and
performance events

Reports various alarms and performance events.

Specifications of
the REG

Supports the setting and query of the REG working mode.

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Function and
Feature

SF64

Protection schemes

Supports the two-fiber ring MSP, four-fiber ring MSP, linear MSP,
SNCP, SNCTP, and SNCMP.

Supports the fiber-shared MSP and SNCP and processes two sets of
K bytes. One SF64 supports a maximum of two MSP protection
rings.

Supports inloops and outloops at optical interfaces.

Supports inloops and outloops on VC-4 paths.

Supports warm resets and cold resets. The warm reset does not affect
services.

Supports the query of the manufacturing information of the board.

Supports the in-service loading of the FPGA.

Supports the upgrade of the board software without affecting


services.

Supports the press-to-collect function in fault data collection.

Maintenance
features

5.21.3 Working Principle and Signal Flow


The SF64 consists of the O/E converting module, MUX/DEMUX module, SDH overhead
processing module, logic and control module, DC/DC converter, and other modules.
Figure 5-49 shows the functional block diagram of the SF64.
Figure 5-49 Functional block diagram of the SF64
Backplane
622 MHz
622 MHz
PLL
10.71
Gbit/s

O/E

10.71
Gbit/s

DEMU
X

16x622
Mbit/s

10.71
Gbit/s

MUX

16x622
Mbit/s

SPI
10.71
Gbit/s

E/O
O/E
converting
module

K1 and K2

Cross-connect
unit

RST MST MSA HPT

High-speed
bus
DCC

SDH overhead
processing module
669 MHz
PLL

IIC
LOS
Laser shutdown

Logic and
control module
+3.3 V
DC/DC
Converter

5-174

Cross-connect
unit

High-speed
bus

MUX/
DEMUX

PLL: phase-locked loop

Reference clock

K1 and K2
insertion/extraction

16x669
Mbit/s
FEC 16x669
Mbit/s

622 MHz
PLL

SPI: SDH physical interface

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DC/DC
Converter

Frame header
Communication
Fuse

Cross-connect
unit A
Cross-connect
unit B
SCC unit

Cross-connect
unit
SCC unit
-48 V/-60 V
-48 V/-60 V

SDH: synchronous digital hierarchy

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RST: regenerator section
termination

5 SDH Boards

MST: multiplex section termination MSA: multiplex section adaptation

HPT: higher order path termination IIC: inter-integrated circuit

The functional modules are described as follows:

O/E Converting Module


l

In the receive direction, the module converts the received optical signals into electrical
signals.

In the transmit direction, the module converts the electrical signals into SDH optical signals
and sends the SDH optical signals to fibers for transmission.

The SPI detects the R_LOS alarm and provides the function of shutting down the laser.

MUX/DEMUX Module
l

In the receive direction, the DEMUX part demultiplexes the high-rate electrical signals into
multiple parallel electrical signals and restores the clock signal at the same time.

In the transmit direction, the MUX part multiplexes the parallel electrical signals received
from the SDH overhead processing module into high-rate electrical signals.

SDH Overhead Processing Module


Logic and Control Module
l

Manages and configures the other modules of the board.

Performs inter-board communication through the internal Ethernet interface.

Traces the clock signal from the active and standby cross-connect units.

Controls the laser.

Passes the orderwire and ECC bytes through an ADM that consists of two paired slots when
the is not online.

Selects the clock signal and frame header signal from the active and standby cross-connect
units.

Controls the indicators on the board.

DC/DC Converter
It converts the 48/60 V power supply into the DC voltages that the modules of the board
require.

5.21.4 Front Panel


The front panel of the SF64 has indicators, interfaces, a bar code, and a laser safety class label.

Diagram of the Front Panel


Figure 5-50 shows the appearance of the front panel of the SF64.
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Figure 5-50 Front panel of the SF64

SF64
STAT
ACT
PROG
SRV

CLASS 1
LASER
PRODUCT

OUT

IN

SF64

Indicators
The front panel of the board has the following indicators:
l

Board hardware status indicator (STAT) two colors (red and green)

Service activation status indicator (ACT) one color (green)

Board software status indicator (PROG) two colors (red and green)

Service alarm indicator (SRV) three colors (red, green, and yellow)

For the meanings of the status of the indicators, see A Indicators.

Interfaces
The front panel of the SF64 has one optical interface. Table 5-93 describes the types and usage
of the optical interfaces of the SF64.
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Table 5-93 Optical interfaces of the SF64


Interface

Type of
Interface

Usage

IN

LC

Receives optical signals.

OUT

LC

Transmits optical signals.

5.21.5 Valid Slots


The slots valid for the SF64 vary with the cross-connect capacity of the subrack.
l

When the cross-connect capacity is 60 Gbit/s, the SF64 cannot be installed in any slot of
the subrack.

When the cross-connect capacity is 110 Gbit/s, the SF64 can be installed in slots 7, 8, 11,
and 12.

5.21.6 Parameter Settings


You can set the parameters for the SF64 by using the T2000.
You can set the following parameters for the SF64 by using the T2000:
l

J0

J1

J2

C2

For the description of each parameter, see F Parameter Settings.

5.21.7 Technical Specifications


The technical specifications of the SF64 include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.

Parameters Specified for Optical Interfaces


Table 5-94 lists the parameters specified for the optical interfaces of the SF64.
Table 5-94 Specifications of optical interfaces of the SF64

Issue 02 (2009-07-30)

Parameter

Value

Nominal bit rate

10.709 Gbit/s

Application
codea

Ue-64.2c

Ue-64.2d

Ue-64.2e

FEC + BA (14 dB) +


PAb + DCU (60 + 80)

FEC + BA (17 dB) +


PA + DCU (80 x 2)

FEC + BA (17 dB) +


RA + PA + DCU (60
x 3)

Type of fiber

Single-mode LC
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Parameter

Value

Operating
wavelength
range (nm)

1550.12

Launched optical -4 to -1
power range
(dBm)c
Minimum
extinction ratio
(dB)

10

a: The numbers in the brackets indicate the corresponding parameter values. For example,
"BA (14 dB)" indicates that the optical power amplified by the BA is 14 dBm.
b: "FEC + BA + PA + RA" indicates that the specifications of the optical interface are
measured when the FEC, BA, PA, and Raman amplifier are used.
c: The parameters are only for the optical modules. The parameters of the amplifier are not
provided.

Table 5-95 lists the parameters specified for the colored optical interfaces of the SF64.
Table 5-95 Parameters specified for the optical interfaces that comply with the standard
wavelengths specified in ITU-T G.692
Parameter

Value

Nominal bit rate

10.709 Gbit/s

Dispersion limit (km)

40

Mean launched optical power (dBm)

-4 to -1

Receiver sensitivity (dBm)

-14

Minimum overload (dBm)

-1

Maximum allowed dispersion (ps/


nm)

800

Minimum extinction ratio (dB)

10

Laser Safety Class


The safety class of the laser on the board is Class 1. The maximum launched optical power of
the optical interfaces is less than 10 dBm (10 mW).

Mechanical Specifications
The mechanical specifications of the SF64 are as follows:
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l

Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)

Weight (kg): 1.1

5 SDH Boards

Power Consumption
At room temperature (25C), the maximum power consumption of the SF64 is 33 W.

5.22 SF64A
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the SF64A (1xSTM-64 optical interface board with the FEC function).
5.22.1 Version Description
The SF64A is available in one functional version, namely, N1.
5.22.2 Functions and Features
The SF64A receives and transmits 1xSTM-64 optical signals and processes overhead bytes.
5.22.3 Working Principle and Signal Flow
The SF64A consists of the O/E converting module, MUX/DEMUX module, SDH overhead
processing module, logic and control module, DC/DC converter, and other modules.
5.22.4 Front Panel
The front panel of the SF64A has indicators, interfaces, a bar code, and a laser safety class label.
5.22.5 Valid Slots
The slots valid for the SF64A vary with the cross-connect capacity of the subrack.
5.22.6 Parameter Settings
You can set the parameters for the SF64A by using the T2000.
5.22.7 Technical Specifications
The technical specifications of the SF64A include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.

5.22.1 Version Description


The SF64A is available in one functional version, namely, N1.

5.22.2 Functions and Features


The SF64A receives and transmits 1xSTM-64 optical signals and processes overhead bytes.
Table 5-96 provides the functions and features of the SF64A.
Table 5-96 Functions and features of the SF64A

Issue 02 (2009-07-30)

Function and
Feature

SF64A

Basic functions

Transmits and receives 1xSTM-64 optical signals.

Supports the enabling or disabling of the FEC function.

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Function and
Feature

SF64A

Specifications of
the optical interface

Supports different types of standard optical interfaces, namely, the


Ue-64.2c, Ue-64.2d, and Ue-64.2e. The characteristics of the optical
interfaces comply with the standards defined by Huawei.

Supports the output of the standard wavelengths that comply with


ITU-T G.692 and can be directly connected to the DWDM
equipment.

Supports the detection and query of the information about the optical
module.

Provides the ALS function. The optical interface supports the setting
of the on/off state of a laser.

Specifications of
the optical module

Service processing

Supports the VC-12 services, VC-3 services, VC-4 services, VC-4-4c


concatenation services, VC-4-8c concatenation services, VC-4-16c
concatenation services, and VC-4-64c concatenation services.

Overhead
processing

Processes the section overheads of the STM-64 signals.

Supports the transparent transmission and termination of the path


overheads.

Supports the setting and query of the J0, J1, J2, and C2 bytes.

Supports one channel of ECC communication.

Alarms and
performance events

Reports various alarms and performance events.

Specifications of
the REG

Supports the setting and query of the REG working mode.

Protection schemes

Supports the two-fiber ring MSP, four-fiber ring MSP, linear MSP,
SNCP, SNCTP, and SNCMP.

Supports the fiber-shared MSP and SNCP and processes two sets of
K bytes. One SF64A supports a maximum of two MSP protection
rings.

Supports inloops and outloops at optical interfaces.

Supports inloops and outloops on VC-4 paths.

Supports warm resets and cold resets. The warm reset does not affect
services.

Supports the query of the manufacturing information of the board.

Supports the in-service loading of the FPGA.

Supports the upgrade of the board software without affecting


services.

Supports the press-to-collect function in fault data collection.

Maintenance
features

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5.22.3 Working Principle and Signal Flow


The SF64A consists of the O/E converting module, MUX/DEMUX module, SDH overhead
processing module, logic and control module, DC/DC converter, and other modules.
Figure 5-51 shows the functional block diagram of the SF64A.
Figure 5-51 Functional block diagram of the SF64A
Backplane
622 MHz
622 MHz
PLL
10.71
Gbit/s

10.71
Gbit/s

O/E

16x622
Mbit/s

MUX

FEC 16x669
16x622
Mbit/s
Mbit/s

SPI
10.71
Gbit/s

E/O

10.71
Gbit/s

O/E
converting
module

Reference clock

Cross-connect
unit

K1 and K2

Cross-connect
unit

K1 and K2
insertion/extraction

16x669
Mbit/s

DEMU
X

622 MHz
PLL

High-speed
bus
RST MST MSA HPT

High-speed
bus
DCC

SDH overhead
processing module

MUX/
DEMUX
669 MHz
PLL

IIC
LOS
Laser shutdown

Logic and
control module
+3.3 V
DC/DC
Converter

DC/DC
Converter

Frame header
Communication
Fuse

Cross-connect
unit A
Cross-connect
unit B
SCC unit

Cross-connect
unit
SCC unit
-48 V/-60 V
-48 V/-60 V

PLL: phase-locked loop

SPI: SDH physical interface

RST: regenerator section


termination

MST: multiplex section termination MSA: multiplex section adaptation

HPT: higher order path termination IIC: inter-integrated circuit

SDH: synchronous digital hierarchy

The functional modules are described as follows:

O/E Converting Module


l

In the receive direction, the module converts the received optical signals into electrical
signals.

In the transmit direction, the module converts the electrical signals into SDH optical signals
and sends the SDH optical signals to fibers for transmission.

The SPI detects the R_LOS alarm and provides the function of shutting down the laser.

MUX/DEMUX Module
l

In the receive direction, the DEMUX part demultiplexes the high-rate electrical signals into
multiple parallel electrical signals and restores the clock signal at the same time.

In the transmit direction, the MUX part multiplexes the parallel electrical signals received
from the SDH overhead processing module into high-rate electrical signals.

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SDH Overhead Processing Module


Logic and Control Module
l

Manages and configures the other modules of the board.

Performs inter-board communication through the internal Ethernet interface.

Traces the clock signal from the active and standby cross-connect units.

Controls the laser.

Passes the orderwire and ECC bytes through an ADM that consists of two paired slots when
the is not online.

Selects the clock signal and frame header signal from the active and standby cross-connect
units.

Controls the indicators on the board.

DC/DC Converter
It converts the 48/60 V power supply into the DC voltages that the modules of the board
require.

5.22.4 Front Panel


The front panel of the SF64A has indicators, interfaces, a bar code, and a laser safety class label.

Diagram of the Front Panel


Figure 5-52 shows the appearance of the front panel of the SF64A.

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Figure 5-52 Front panel of the SF64A

SF64A
STAT
ACT
PROG
SRV

CLASS 1
LASER
PRODUCT

OUT

IN

SF64A

Indicators
The front panel of the board has the following indicators:
l

Board hardware status indicator (STAT) two colors (red and green)

Service activation status indicator (ACT) one color (green)

Board software status indicator (PROG) two colors (red and green)

Service alarm indicator (SRV) three colors (red, green, and yellow)

For the meanings of the status of the indicators, see A Indicators.

Interfaces
The front panel of the SF64A has one optical interface. Table 5-97 describes the types and usage
of the optical interfaces of the SF64A.
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Table 5-97 Optical interfaces of the SF64A


Interface

Type of
Interface

Usage

IN

LC

Receives optical signals.

OUT

LC

Transmits optical signals.

TX

LC

Transmits service signals to the equipment on the


customer side.

RX

LC

Receives service signals from the equipment on the


customer side.

5.22.5 Valid Slots


The slots valid for the SF64A vary with the cross-connect capacity of the subrack.
l

When the cross-connect capacity is 60 Gbit/s, the SF64A cannot be installed in any slot of
the subrack.

When the cross-connect capacity is 110 Gbit/s, the SF64A can be installed in slots 7, 8, 11,
and 12.

5.22.6 Parameter Settings


You can set the parameters for the SF64A by using the T2000.
You can set the following parameters for the SF64A by using the T2000:
l

J0

J1

J2

C2

For the description of each parameter, see F Parameter Settings.

5.22.7 Technical Specifications


The technical specifications of the SF64A include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.

Parameters Specified for Optical Interfaces


Table 5-98 lists the parameters specified for the optical interfaces of the SF64A.
Table 5-98 Specifications of optical interfaces of the SF64A

5-184

Parameter

Value

Nominal bit rate

10.709 Gbit/s

Line code pattern

DRZ

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Parameter

Value

Application
codea

Ue-64.2c

Ue-64.2d

Ue-64.2e

FEC + BA (14 dB) +


PAb + DCU (60 + 80)

FEC + BA (17 dB) +


PA + DCU (80 x 2)

FEC + BA (17 dB) +


RA + PA + DCU (60
x 3)

Type of fiber

Single-mode LC

Operating
wavelength
range (nm)

1550.120.08

Launched optical -4 to -1
power range
(dBm)c
Receiver
sensitivity (dBm)

-24

Minimum
overload (dBm)

Minimum
extinction ratio
(dB)

13.5

a: The numbers in the brackets indicate the corresponding parameter values. For example,
"BA (14)" indicates that the optical power amplified by the BA is 14 dBm.
b: "FEC + BA + PA + RA" indicates that the specifications of the optical interface are
measured when the FEC, BA, PA, and Raman amplifier are used.
c: The parameters are only for the optical modules. The parameters of the amplifier are not
provided.

Table 5-99 lists the parameters specified for the colored optical interfaces of the SF64A.
Table 5-99 Parameters specified for the optical interfaces that comply with the standard
wavelengths specified in ITU-T G.692

Issue 02 (2009-07-30)

Parameter

Value

Nominal bit rate

10.709 Gbit/s

Dispersion limit (km)

80

Mean launched optical power (dBm)

-4 to -1

Receiver sensitivity (dBm)

-14

Minimum overload (dBm)

Maximum allowed dispersion (ps/


nm)

800

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Parameter

Value

Minimum extinction ratio (dB)

13.5

Laser Safety Class


The safety class of the laser on the board is Class 1. The maximum launched optical power of
the optical interfaces is less than 10 dBm (10 mW).

Mechanical Specifications
The mechanical specifications of the SF64A are as follows:
l

Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)

Weight (kg): 1.1

Power Consumption
At room temperature (25C), the maximum power consumption of the SF64 is 33 W.

5.23 SLQ41
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the SLQ41 (4xSTM-4/STM-1 optical interface board).
5.23.1 Version Description
The SLQ41 is available in one functional version, namely, N3. The SLQ41 supports the autosensing of optical interfaces.
5.23.2 Functions and Features
The SLQ41 transmits and receives STM-1 or STM-4 optical signals, performs O/E conversion
for the STM-1 or STM-4 optical signals, extracts and inserts overhead bytes, and generates alarm
signals on the line.
5.23.3 Working Principle and Signal Flow
The SLQ41 consists of the O/E converting module, CDR module, SDH overhead processing
module, logic and control module, DC/DC converter, and other modules.
5.23.4 Front Panel
The front panel of the SLQ41 has indicators, interfaces, a bar code, and a laser safety class label.
5.23.5 Valid Slots
The SLQ41 can be installed in slots 28 and 1116 in the subrack.
5.23.6 Feature Code
The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the SLQ41 indicates the type of optical interface.
5.23.7 Parameter Settings
You can set the parameters for the SLQ41 by using the T2000.
5.23.8 Technical Specifications
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The technical specifications of the SLQ41 include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.

5.23.1 Version Description


The SLQ41 is available in one functional version, namely, N3. The SLQ41 supports the autosensing of optical interfaces.

5.23.2 Functions and Features


The SLQ41 transmits and receives STM-1 or STM-4 optical signals, performs O/E conversion
for the STM-1 or STM-4 optical signals, extracts and inserts overhead bytes, and generates alarm
signals on the line.
Table 5-100 provides the functions and features of the SLQ41.
Table 5-100 Functions and features of the SLQ41
Function and
Feature

SLQ41

Basic functions

Transmits and receives 4xSTM-1 or 4xSTM-4 optical signals.

Specifications of the
optical interface

The STM-1 optical module or STM-4 optical module can be used.

Specifications of the
optical module

Service processing

Issue 02 (2009-07-30)

When the STM-1 optical module is used, the SLQ41 supports


different types of standard optical interfaces, namely, the I-1,
S-1.1, L-1.1, L-1.2, and Ve-1.2. The characteristics of the optical
interfaces of the I-1, S-1.1, L-1.1, and L-1.2 types comply with
ITU-T G.957. The characteristics of the optical interface of the
Ve-1.2 type comply with the standards defined by Huawei.

When the STM-4 optical module is used, the SLQ41 supports


different types of standard optical interfaces, namely, the I-4,
S-4.1, L-4.1, L-4.2, and Ve-4.2. The characteristics of the optical
interfaces of the I-4, S-4.1, L-4.1, and L-4.2 types comply with
ITU-T G.957. The characteristics of the optical interface of the
Ve-4.2 type comply with the standards defined by Huawei.

Supports the detection and query of the information about the


optical module.

Supports the usage and detection of the SFP optical module, which
facilitates the maintenance and upgrading of the optical module.

Provides the ALS function. The optical interface supports the


setting of the on/off state of a laser.

When the STM-1 optical module is used, the SLQ41 supports the
VC-12 services, VC-3 services, and VC-4 services.

When the STM-4 optical module is used, the SLQ41 supports the
VC-12 services, VC-3 services, VC-4 services, and VC-4-4c
concatenation services.

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Function and
Feature

SLQ41

Overhead processing

Processes the section overheads of the STM-1 signals or STM-4


signals.

Supports the transparent transmission and termination of the path


overheads.

Supports the setting and query of the J0, J1, J2, and C2 bytes.

Supports one to four channels of ECC communication.

Alarms and
performance events

Reports various alarms and performance events, which facilitates the


management and maintenance of the equipment.

Protection schemes

Supports the two-fiber ring MSP, four-fiber ring MSP, linear MSP,
SNCP, SNCTP, and SNCMP.

Maintenance
features

Supports inloops and outloops at optical interfaces.

Supports inloops and outloops on VC-4 paths.

Supports warm resets and cold resets. The warm reset does not
affect services.

Supports the query of the manufacturing information of the board.

Supports the in-service loading of the FPGA.

Supports the upgrade of the board software without affecting


services.

Supports the press-to-collect function in fault data collection.

5.23.3 Working Principle and Signal Flow


The SLQ41 consists of the O/E converting module, CDR module, SDH overhead processing
module, logic and control module, DC/DC converter, and other modules.
This topic describes the working principle and signal flow of the SLQ41 by describing how to
process STM-1/STM-4 signals.
Figure 5-53 shows the functional block diagram of the SLQ41.

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Figure 5-53 Functional block diagram of the SLQ41


Backplane
155 MHz
PLL
O/E

STM-1/
STIM-4

E/O

E/O

K1 and K2

Cross-connect
unit

High-speed
bus

....

....
O/E

STM-1/
STIM-4

Cross-connect
unit

K1 and K2
insertion/extraction

CDR

SPI

Reference clock

RST MST MSA HPT

CDR

SPI

High-speed
bus
DCC

SDH overhead
processing module

O/E converting
module
IIC
LOS

Logic and
control module

Frame header
Communication

Laser shutdown
+3.3 V
DC/DC
Converter

DC/DC
Converter

Fuse

Cross-connect
unit A
Cross-connect
unit B
SCC unit

Cross-connect
unit
SCC unit
-48 V/-60
V
-48 V/-60 V

PLL: phase-locked loop

SPI: SDH physical interface

RST: regenerator section


termination

MST: multiplex section termination MSA: multiplex section adaptation

HPT: higher order path termination IIC: inter-integrated circuit

SDH: synchronous digital hierarchy

CDR: clock and data recovery

The functional modules of the STM-1/STM-4 units are described as follows:

O/E Converting Module


l

In the receive direction, the module converts the received optical signals into electrical
signals.

In the transmit direction, the module converts the electrical signals into SDH optical signals
and sends the SDH optical signals to fibers for transmission.

The SPI detects the R_LOS alarm and provides the function of shutting down the laser.

CDR Module
This module restores the data signal and the clock signal.

SDH Overhead Processing Module


This module includes the RST, MST, MSA, and HPT sub-modules. This module provides the
inloop and outloop functions.
l

RST sub-module

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In the receive direction, the RST sub-module detects the frame alignment bytes (A1 and
A2), performs descrambling, restores the regenerator section trace byte (J0), detects a
J0 mismatch, and counts BIP-8 errored blocks.
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In the transmit direction, the RST sub-module inserts the frame alignment bytes, inserts
the J0 byte, performs scrambling, and performs BIP-8 calculation and insertion.

MST sub-module

In the receive direction, the MST sub-module counts BIP-24 errored blocks, restores
the MS_REI, and detects the MS_RDI, MS_AIS, and MS-EXC.

In the transmit direction, the MST sub-module performs BIP-24 calculation and
insertion and inserts the MS_REI, MS_RDI, and MS_AIS.

The MST sub-module extracts or inserts the K1, K2, E2, D4D12, S1, B2, and M1
bytes.

MSA sub-module

In the receive direction, the MSA sub-module interprets the AU-4 pointer, detects the
LOP and AIS, and performs pointer justifications.

In the transmit direction, the MSA sub-module assembles the AUG and generates the
AU-4 pointer and the AU_AIS.

HPT sub-module

Terminates the overheads.

Restores the J1 path trace message.

Restores the REI information.

Detects the HP_RDI (monitors the status of the path).

Detects the UNEQ and AIS (monitors the signal label).

Counts the VC-4 BIP-8 errored blocks.

Logic and Control Module


l

Manages and configures the other modules of the board.

Performs inter-board communication through the internal Ethernet interface.

Traces the clock signal from the active and standby cross-connect units.

Controls the laser.

Passes the orderwire and ECC bytes through an ADM that consists of two paired slots when
the CXL is not online.

Selects the clock signal and frame header signal from the active and standby cross-connect
units.

Controls the indicators on the board.

DC/DC Converter
It converts the 48/60 V power supply into the DC voltages that the modules of the board
require.

5.23.4 Front Panel


The front panel of the SLQ41 has indicators, interfaces, a bar code, and a laser safety class label.

Diagram of the Front Panel


Figure 5-54 shows the appearance of the front panel of the SLQ41.
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Figure 5-54 Front panel of the SLQ41

SLQ41
STAT
ACT
PROG
SRV

CLASS 1
LASER
PRODUCT

OUT1 IN1
OUT2 IN2
OUT3 IN3
OUT4 IN4

SLQ41

Indicators
The front panel of the board has the following indicators:
l

Board hardware status indicator (STAT) two colors (red and green)

Service activation status indicator (ACT) one color (green)

Board software status indicator (PROG) two colors (red and green)

Service alarm indicator (SRV) three colors (red, green, and yellow)

For the meanings of the status of the indicators, see A Indicators.

Interfaces
The front panel of the SLQ41 has four optical interfaces. Table 5-101 describes the types and
usage of the optical interfaces of the SLQ41.
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Table 5-101 Optical interfaces of the SLQ41


Interface

Type of
Interface

Usage

IN1IN4

LC

Receives optical signals.

OUT1OUT4

LC

Transmits optical signals.

5.23.5 Valid Slots


The SLQ41 can be installed in slots 28 and 1116 in the subrack.

5.23.6 Feature Code


The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the SLQ41 indicates the type of optical interface.
Table 5-102 provides the relationship between the feature code of the SLQ41 and the type of
optical interface.
Table 5-102 Relationship between the feature code of the SLQ41 and the type of optical interface
Board

Feature Code

Type of Optical Interface

SSN3SLQ414

14

I-4

SSN3SLQ410

10

S-4.1

SSN3SLQ411

11

L-4.1

SSN3SLQ412

12

L-4.2

SSN3SLQ413

13

Ve-4.2

SSN3SLQ114

14

I-1

SSN3SLQ110

10

S-1.1

SSN3SLQ111

11

L-1.1

SSN3SLQ112

12

L-1.2

SSN3SLQ113

13

Ve-1.2

5.23.7 Parameter Settings


You can set the parameters for the SLQ41 by using the T2000.
You can set the following parameters for the SLQ41 by using the T2000:
l

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l

J1

J2

C2

5 SDH Boards

For the description of each parameter, see F Parameter Settings.

5.23.8 Technical Specifications


The technical specifications of the SLQ41 include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.

Parameters Specified for Optical Interfaces


The SLQ41 supports the STM-1 and STM-4 optical modules.
Table 5-103 lists the parameters specified for the optical interfaces of the SLQ41 when the
STM-1 optical module is used.
Table 5-103 Parameters specified for the optical interfaces of the SLQ41 when the STM-1 optical module is used
Parameter

Value

Nominal bit rate

155520 kbit/s

Line code
pattern

NRZ

Application
code

I-1

S-1.1

L-1.1

L-1.2

Ve-1.2

Transmission
distance (km)

0 to 2

2 to 15

20 to 40

60 to 80

80 to 100

Type of fiber

Single-mode LC

Single-mode LC

Single-mode LC

Single-mode LC

Single-mode LC

Operating
wavelength
range (nm)

1260 to 1360

1261 to 1360

1263 to 1360

1480 to 1580

1480 to 1580

Launched
optical power
range (dBm)

-15 to -8

-15 to -8

-5 to 0

-5 to 0

-3 to 0

Receiver
sensitivity
(dBm)

-23

-28

-34

-34

-34

Minimum
overload (dBm)

-8

-8

-10

-10

-10

Minimum
extinction ratio
(dB)

8.2

8.2

10

10

10

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Table 5-104 lists the parameters specified for the optical interfaces of the SLQ41 when the
STM-4 optical module is used.
Table 5-104 Parameters specified for the optical interfaces of the SLQ41 when the STM-4
optical module is used
Parameter

Value

Nominal bit rate

622080 kbit/s

Line code pattern

NRZ

Application code

I-4

S-4.1

L-4.1

L-4.2

Ve-4.2

Transmission
distance (km)

0 to 2

2 to 15

20 to 40

50 to 80

80 to 100

Operating
wavelength range
(nm)

1261 to
1360

1274 to
1356

1280 to
1335

1480 to
1580

1480 to
1580

Type of fiber

Singlemode LC

Singlemode LC

Singlemode LC

Singlemode LC

Singlemode LC

Mean launched
optical power
(dBm)

-15 to -8

-15 to -8

-3 to -2

-3 to -2

-3 to -2

Receiver
sensitivity (dBm)

-23

-28

-28

-28

-34

Minimum
overload (dBm)

-8

-8

-8

-8

-13

Minimum
extinction ratio
(dB)

8.2

8.2

10

10

10.5

Laser Safety Class


The safety class of the laser on the board is Class 1. The maximum launched optical power of
the optical interfaces is less than 10 dBm (10 mW).

Mechanical Specifications
The mechanical specifications of the SLQ41 are as follows:
l

Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)

Weight (kg): 0.6

Power Consumption
The maximum power consumption of the SLQ41 at room temperature (25C) is 12 W.
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PDH Boards

About This Chapter


The PDH boards include the E1/T1 signal processing boards, E3/T3 signal processing boards,
E4/STM-1 signal processing boards, and DDN signal processing boards.
6.1 PQ1
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the PQ1 (63xE1 service processing board).
6.2 PO1
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the PO1 (126xE1 service processing board).
6.3 PQM
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the PQM (63xE1/T1 service processing board).
6.4 PL3
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the PL3 (3xE3/T3 service processing board).
6.5 PL3A
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the PL3A (3xE3/T3 service processing board with the interfaces on
the front panel).
6.6 PD3
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the PD3 (6xE3/T3 service processing board).
6.7 PQ3
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the PQ3 (12xE3/T3 service processing board).
6.8 DX1
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the DX1 (DDN service accessing and converging board).
6.9 DXA
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This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the DXA (DDN service converging and processing board).
6.10 SPQ4
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the SPQ4 (4xE4/STM-1 electrical processing board).

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6.1 PQ1
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the PQ1 (63xE1 service processing board).
6.1.1 Version Description
The PQ1 is available in two functional versions, namely, N1 and N2. The difference between
the two versions is with regard to their functions. The N1PQ1 is no longer manufactured.
6.1.2 Functions and Features
The PQ1 processes E1 signals, processes overhead bytes, reports alarms and performance events,
provides maintenance features, and supports the TPS protection.
6.1.3 Working Principle and Signal Flow
The PQ1 consists of the PPI module, E1 mapping/demapping module, interface converting
module, logic and control module, DC/DC converter, and other modules.
6.1.4 Front Panel
The front panel of the PQ1 has indicators.
6.1.5 Valid Slots
The PQ1 can be installed in slots 27 and 1216 in the subrack.
6.1.6 Feature Code
The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the PQ1 indicates the type of interface impedance.
6.1.7 Board Protection
The PQ1 supports the 1:N TPS protection.
6.1.8 Parameter Settings
You can set the parameters for the PQ1 by using the T2000.
6.1.9 Technical Specifications
The technical specifications of the PQ1 include the parameters specified for electrical interfaces,
mechanical specifications, and power consumption.

6.1.1 Version Description


The PQ1 is available in two functional versions, namely, N1 and N2. The difference between
the two versions is with regard to their functions. The N1PQ1 is no longer manufactured.
Table 6-1 describes the versions of the PQ1.
Table 6-1 Versions of the PQ1
Item

Description

Functional versions

The PQ1 is available in two functional versions, namely, N1 and N2.

Differences

The N2PQ1 supports the E13 function and the board version
replacement function.
The N2PQ1 does not perform the tributary re-timing function.

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Item

Description

Substitution

When the tributary re-timing function is not required, the N1PQ1A


can be replaced with the N2PQ1A.
When the tributary re-timing function is not required, the N1PQ1B
can be replaced with the N2PQ1B.

Note: The PQ1 boards are classified into the PQ1A boards (75 ohms) and PQ1B boards (120
ohms) according to the interface impedance. When the interface impedance is not considered,
the PQ1A and PQ1B are called PQ1 hereafter.

6.1.2 Functions and Features


The PQ1 processes E1 signals, processes overhead bytes, reports alarms and performance events,
provides maintenance features, and supports the TPS protection.
Table 6-2 provides the functions and features of the PQ1.
Table 6-2 Functions and features of the PQ1

6-4

Function
and
Feature

PQ1
N1PQ1

N2PQ1

Basic
functions

Processes 63xE1
signals.

Processes 63xE1 signals.

Service
processing

Processes 63xE1
electrical signals
when working with
the interface board.

Processes 63xE1 electrical signals when working


with the interface board.

Supports the E13 function, which is used to converge


E1 services into E3 services.

Overhead
processing

Supports the processing of the path overheads at the VC-12 level, such as the
J2 byte.

Alarms and
performanc
e events

Reports various alarms and performance events, which facilitates the


management and maintenance of the equipment.

Maintenan
ce features

Supports inloops and outloops at electrical interfaces.

Supports warm resets and cold resets. The warm reset does not affect
services.

Supports the query of the manufacturing information of the board.

Supports the in-service loading of the FPGA.

Supports the upgrade of the board software without affecting services.

Supports the PRBS function.

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Function
and
Feature

PQ1

Protection
schemes

Supports the TPS protection when working with the interface board.

N1PQ1

N2PQ1

The N1PQ1 supports hybrid protection. When the working board is the
N1PQ1, the protection board can be the N1PQ1, N2PQ1, or N1PQM.

The N2PQ1 does not support hybrid protection. When the working board is
the N2PQ1, the protection board can only be the N2PQ1.

6.1.3 Working Principle and Signal Flow


The PQ1 consists of the PPI module, E1 mapping/demapping module, interface converting
module, logic and control module, DC/DC converter, and other modules.
Figure 6-1 shows the functional block diagram of the PQ1.
Figure 6-1 Functional block diagram of the PQ1
2 MHz
OSC

E1
E1

LIU

LIU

P
P
I

155 MHz
PLL

63x2 Mbit/s

E1 mapping/
demapping
module
63x2 Mbit/s

LOS
Outloop/Inloop
control

155 Mbit/s

155 Mbit/s

HighInterface
speed bus
converting
module
Highspeed bus

Frame header
Communication

Logic and
control module
+3.3 V
DC/DC
converter

Reference
clock

DC/DC
converter

Fuse

Cross-connect unit

Cross-connect unit A
Cross-connect unit B

Cross-connect unit
SCC Unit
-48 V/-60 V
-48 V/-60 V

Figure 6-2 shows the functional block diagram of the E1 mapping/demapping module.

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Figure 6-2 Functional block diagram of the E1 mapping/demapping module


Mapping/demapping module
E1

LPA

PDH AIS
detector

HPA

LPT

LPOH(V5/J2/N2/
K4) insertion
LPOH(V5/J2/N2/
K4) extraction

E1
LPA

HPT

STM-1

TU-AIS/TULOP detector

LPT

HPA

HPT

STM-1

The functional modules are described as follows:

PPI Module
The PPI module consists of LIUs and provides the inloop and outloop functions. The PPI module
performs the following functions:
l

Encodes and decodes signals.

Restores the data signal and the clock signal.

Processes the PDH LOS signals.

E1 Mapping/Demapping Module

6-6

LPA sub-module

The 2 Mbit/s (1.5 Mbit/s) plesiochronous stream is inserted in a VC-12 container to be


adapted so that the stream can be transported to the synchronous network for check of the
PDH AIS.

LPT sub-module

The virtual container (VC-12) is formatted. The VC-12 is structured so that its octets are
distributed within a 125 us interval (for example, one STM1 period), and consists of the
VC-12 container and POH. The POH contains nine octets equally distributed within the
frame bytes for VC-12, namely, V5, J2, N2, and K4.

HPA sub-module

The HPA sub-module generates and processes the channel-level TU-PTR. In the receive
direction, the signals are split into VC-12s, which are located and isolated in TU-12s. The
TU-PTR is processed. TU-AIS and TU-LOP alarms are monitored. In the transmit
direction, VC-12s are located precisely and added with the TU-PTR. Sixty-three TUG-3s
are multiplexed into a VC-4 by bytes interleaving. The sequence is as follows: TUG2>TUG3->VC-4
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HPT sub-module

The virtual container (VC-4) is formatted. The VC-4 is structured so that its octets are
distributed within a 125 us interval (for example, one STM1 period), and consists of the
C4 container and POH.

MST sub-module and RST sub-module

These sub-modules are required to create a proprietary STM1 signal so that the E1
mapping/demapping module can interface with the multiplex unit.

Interface Converting Module


The interface converting module converts the 622 Mbit/s LVDS bus of the SDH system into the
parallel bus. The high-rate backplane interface is connected to the low-rate interface chip of the
transmit system through the interface converting module.

Logic and Control Module


l

Manages and configures the other modules of the board.

Performs inter-board communication through the internal Ethernet interface.

Traces the clock signal from the active and standby cross-connect units.

Selects the clock signal and frame header signal from the active and standby cross-connect
units.

Control the indicators on the board.

DC/DC Converter
It converts the 48/60 V power supply into the DC voltages that the modules of the board
require.

6.1.4 Front Panel


The front panel of the PQ1 has indicators.

Diagram of the Front Panel


Figure 6-3 shows the appearance of the front panel of the PQ1.

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Figure 6-3 Front panel of the PQ1

PQ1
STAT
ACT
PROG
SRV

PQ1

Indicators
The front panel of the board has the following indicators:
l

Board hardware status indicator (STAT) two colors (red and green)

Service activation status indicator (ACT) one color (green)

Board software status indicator (PROG) two colors (red and green)

Service alarm indicator (SRV) three colors (red, green, and yellow)

For the meanings of the status of the indicators, see A Indicators.

Interfaces
The front panel of the PQ1 does not have an interface.
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The D75S, D12S, and D12B provide 75-ohm or 120-ohm E1 interfaces for the PQ1. For details,
see the topics that describe the D75S, D12S, and D12B.

6.1.5 Valid Slots


The PQ1 can be installed in slots 27 and 1216 in the subrack.
Table 6-3 lists the slots valid for the PQ1 and the corresponding slots for the D75S, D12S, and
D12B in the main subrack.
Table 6-3 Slots valid for the PQ1 and the corresponding slots for the D75S, D12S, and D12B
in the main subrack
Slot Valid for the PQ1

Corresponding Slots for the D75S, D12S,


and D12B

Slot 2

Without the interface board

Slot 3

Slot 21 (132 channels of services)


Slot 22 (3363 channels of services)

Slot 4

Slot 23 (132 channels of services)


Slot 24 (3363 channels of services)

Slot 5

Slot 25 (132 channels of services)


Slot 26 (3363 channels of services)

Slot 6

Slot 27 (132 channels of services)


Slot 28 (3363 channels of services)

Slot 7

Slot 29 (132 channels of services)


Slot 30 (3363 channels of services)

Slot 12

Slot 31 (132 channels of services)


Slot 32 (3363 channels of services)

Slot 13

Slot 33 (132 channels of services)


Slot 34 (3363 channels of services)

Slot 14

Slot 35 (132 channels of services)


Slot 36 (3363 channels of services)

Slot 15

Slot 37 (132 channels of services)


Slot 38 (3363 channels of services)

Slot 16

Slot 39 (132 channels of services)


Slot 40 (3363 channels of services)

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NOTE

Slot 2 can house a protection board for the TPS protection. The board in slot 2 protects the boards in
slots 37 and 1216.

If the interface board for the boards in slots 37 and 1216 is the D12B, the boards in slots 37 and
1216 cannot be protected by the TPS protection scheme.

6.1.6 Feature Code


The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the PQ1 indicates the type of interface impedance.
Table 6-4 provides the relationship between the feature code of the PQ1 and the type of interface
impedance.
Table 6-4 Relationship between the feature code of the PQ1 and the type of interface impedance
Board

Feature Code

Type of Interface Impedance

SSN1PQ1A01 and SSN2PQ1A01

A01

75-ohm

SSN1PQ1B01 and SSN2PQ1B01

B01

120-ohm

6.1.7 Board Protection


The PQ1 supports the 1:N TPS protection.

Protection Principle
The PQ1 boards work with the D75S or D12S boards to realize 1:N (N10) TPS protection.
Figure 6-4 shows the TPS protection provided by the PQ1.

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Figure 6-4 TPS protection provided by the PQ1

S
L
E1 protection bus O
T
2
1

S
L
O
T
2
2

S
L
O
T
2
3

S
L
O
T
2
4

S
L
O
T
2
5

S
L
O
T
2
6

S
L
O
T
2
8

S
L
O
T
2
7

S
L
O
T
2
9

S
L
O
T
3
1

S
L
O
T
3
0

S
L
O
T
3
2

S
L
O
T
3
3

S
L
O
T
3
4

S
L
O
T
3
5

S
L
O
T
3
6

S
L
O
T
3
7

S
L
O
T
3
8

S
L
O
T
3
9

S
L
O
T
4
0

D12S
D12S

D12S
D12S

D12S
D12S

D12S
D12S

D12S
D12S

D12S
D12S

D12S
D12S

D12S
D12S

D12S
D12S

D12S
D12S

E1 service bus

Working

Working

Working

Working

S
L
O
T
1
2
Failed

S
L
O
T
1
3

S
L
O
T
1
4

S
L
O
T
1
5

S
L
O
T
1
6

Working

Protection

S
L
O
T
7

Working

S
L
O
T
6

Working

S
L
O
T
5

Working

S
L
O
T
4

Working

S
L
O
T
3

Working

S
L
O
T
2

Detecting a
board fault
Cross-connect and timing board

TPS control bus

When the cross-connect and timing board detects that a working PQ1 is faulty, the cross-connect
and timing board issues a service switching command to control the access board to switch the
services from the faulty PQ1 to the protection PQ1, which realizes the protection of the services.

Hardware Configuration
Table 6-5 shows the slot configuration for the 1:10 TPS protection of the PQ1.
Table 6-5 Slot configuration for the 1:10 TPS protection of the PQ1

Issue 02 (2009-07-30)

Working Board

Protection Board

Slot Configuration

PQ1A (75-ohm)

PQ1A (75-ohm)

PQ1B (120-ohm)

PQ1B (120-ohm) or PQM

Slot 2 can house a protection board.


The board in slot 2 protects the boards
in slots 37 and 1216. Figure 6-5
shows the slot configuration for the
1:10 TPS protection of the PQ1.

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Figure 6-5 Slot configuration for the 1:10 TPS protection of the PQ1

S
L
O
T
28

S
L
O
T
29

S
L
O
T
32

S S S S
L L L L
O O O O
T T T T
33 34 35 36

SLOT 43 EOW

S S S S
L L L L
O O O O
T T T T
13 14 15 16

SLOT 42AUX

working

working

S S
L L
O O
T T
11 12

working

S
L
O
T
10

working

S
L
O
T
9

working

working
working

S
L
O
T
8

CXL

working

S
L
O
T
7

FAN

CXL

S
L
O
T
6

working

S S
L L
O O
T T
4 5

working

SLOT 41 PIU

S
L
O
T
3

Protection

SLOT 1 PIU

S
L
O
T
2

S
L
O
T
40

D12S

FAN

S S S
L L L
O O O
T T T
37 38 39

D12S
D12S
D12S
D12S

D12S

FAN

S S
L L
O O
T T
30 31

D12S

D12S
D12S
D12S

S
L
O
T
27

D12S

D12S

S S
L L
O O
T T
25 26

D12S

D12S

S
L
O
T
24

D12S
D12S

S
L
O
T
23

D12S

S
L
O
T
22

D12S
D12S
D12S

S
L
O
T
21

Fiber routing area

6.1.8 Parameter Settings


You can set the parameters for the PQ1 by using the T2000.
You can set the following parameters for the PQ1 by using the T2000:
l

J2 byte

V5 byte

Tributary loopback

Service loading indication

For the description of each parameter, see F Parameter Settings.

6.1.9 Technical Specifications


The technical specifications of the PQ1 include the parameters specified for electrical interfaces,
mechanical specifications, and power consumption.

Parameters Specified for Electrical Interfaces


The D75S, D12S, or D12B provides electrical interfaces for the PQ1. For the parameters
specified for the electrical interfaces, see D75S, D12S and D12B.
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Mechanical Specifications
The mechanical specifications of the PQ1 are as follows:
l

Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)

Weight (kg): 1.0

Power Consumption
The maximum power consumption of the N1PQ1 at room temperature (25C) is 19 W.
The maximum power consumption of the N2PQ1 at room temperature (25C) is 13 W.

6.2 PO1
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the PO1 (126xE1 service processing board).
6.2.1 Version Description
The PO1 is available in one functional version, namely, N2.
6.2.2 Functions and Features
The PO1 processes E1 signals, processes overhead bytes, reports alarms and performance events,
provides maintenance features, and supports the TPS protection.
6.2.3 Working Principle and Signal Flow
The PO1 consists of the PPI module, E1 mapping/demapping module, interface converting
module, logic and control module, DC/DC converter, and other modules.
6.2.4 Front Panel
The front panel of the PO1 has indicators.
6.2.5 Valid Slots
The PO1 can be used with the D12S or D12B.
6.2.6 Feature Code
The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the PO1 indicates the type of interface impedance.
6.2.7 Parameter Settings
You can set the parameters for the PO1 by using the T2000.
6.2.8 Technical Specifications
The technical specifications of the PO1 include the parameters specified for electrical interfaces,
mechanical specifications, and power consumption.

6.2.1 Version Description


The PO1 is available in one functional version, namely, N2.

6.2.2 Functions and Features


The PO1 processes E1 signals, processes overhead bytes, reports alarms and performance events,
provides maintenance features, and supports the TPS protection.
Table 6-6 provides the functions and features of the PO1.
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Table 6-6 Functions and features of the PO1


Function
and
Feature

PO1

Basic
functions

Processes 126xE1 signals.

Service
processing

Processes 126xE1 electrical signals and 3xE13 signals when working with the
interface board. The interface board accesses the 1st to 63rd E1s. The PO1
accesses the 64th to 126th E1s on its front panel.

Overhead
processing

Supports the processing of the path overheads at the VC-12 level, such as the
J2 byte.

Alarms and
performanc
e events

Reports various alarms and performance events, which facilitates the


management and maintenance of the equipment.

Maintenan
ce features

Supports inloops and outloops at electrical interfaces.

Supports warm resets and cold resets. The warm reset does not affect
services.

Supports the query of the manufacturing information of the board.

Supports the in-service loading of the FPGA.

Supports the upgrade of the board software without affecting services.

Supports the PRBS function.

Supports the press-to-collect function in fault data collection.

6.2.3 Working Principle and Signal Flow


The PO1 consists of the PPI module, E1 mapping/demapping module, interface converting
module, logic and control module, DC/DC converter, and other modules.
Figure 6-6 shows the functional block diagram of the PO1.

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Figure 6-6 Functional block diagram of the PO1


2 MHz
OSC

E1

LIU

E1

LIU

P
P
I

155 MHz
PLL

63x2 Mbit/s

E1 mapping/
demapping
module
63x2 Mbit/s

LOS
Outloop/Inloop
control

155 Mbit/s

155 Mbit/s

Reference
clock

HighInterface
speed bus
converting
module
Highspeed bus

Frame header
Communication

Logic and
control module
+3.3 V
DC/DC
converter

DC/DC
converter

Fuse

Cross-connect unit

Cross-connect unit A
Cross-connect unit B

Cross-connect unit
SCC Unit
-48 V/-60 V
-48 V/-60 V

Figure 6-7 shows the functional block diagram of the E1 mapping/demapping module.
Figure 6-7 Functional block diagram of the E1 mapping/demapping module

E1 mapping/demapping module
E1

LPA

PDH AIS
detector

E1
LPA

HPA

LPT

LPOH(V5/J2/N2/
K4) insertion
LPOH(V5/J2/N2/
K4) extraction

HPT

STM-1

TU-AIS/TU-LOP
detector

LPT

HPA

HPT

STM-1

The functional modules are described as follows:

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PPI Module
The PPI module consists of LIUs and provides the inloop and outloop functions. The PPI module
performs the following functions:
l

Encodes and decodes signals.

Restores the data signal and the clock signal.

Processes the PDH LOS signals.

E1 Mapping/Demapping Module
l

LPA sub-module

The 2 Mbit/s (1.5 Mbit/s) plesiochronous stream is inserted in a VC-12 container to be


adapted so that the stream can be transported to the synchronous network for check of the
PDH AIS.

LPT sub-module

The virtual container (VC-12) is formatted. The VC-12 is structured so that its octets are
distributed within a 125 us interval (for example, one STM1 period), and consists of the
VC-12 container and POH. The POH contains nine octets equally distributed within the
frame bytes for VC-12, namely, V5, J2, N2, and K4.

HPA sub-module

The HPA sub-module generates and processes the channel-level TU-PTR. In the receive
direction, the signals are split into VC-12s, which are located and isolated in TU-12s. The
TU-PTR is processed. TU-AIS and TU-LOP alarms are monitored. In the transmit
direction, VC-12s are located precisely and added with the TU-PTR. Sixty-three TUG-3s
are multiplexed into a VC-4 by bytes interleaving. The sequence is as follows: TUG2>TUG3->VC-4

HPT sub-module

The virtual container (VC-4) is formatted. The VC-4 is structured so that its octets are
distributed within a 125 us interval (for example, one STM1 period), and consists of the
C4 container and POH.

MST sub-module and RST sub-module

These sub-modules are required to create a proprietary STM1 signal so that the E1
mapping/demapping module can interface with the multiplex unit.

Interface Converting Module


The interface converting module converts the 622 Mbit/s LVDS bus of the SDH system into the
parallel bus. The high-rate backplane interface is connected to the low-rate interface chip of the
transmit system through the interface converting module.

Logic and Control Module

6-16

Manages and configures the other modules of the board.

Performs inter-board communication through the internal Ethernet interface.

Traces the clock signal from the active and standby cross-connect units.

Selects the clock signal and frame header signal from the active and standby cross-connect
units.
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Control the indicators on the board.

DC/DC Converter
It converts the 48/60 V power supply into the DC voltages that the modules of the board
require.

6.2.4 Front Panel


The front panel of the PO1 has indicators.

Diagram of the Front Panel


Figure 6-8 shows the appearance of the front panel of the PO1.
Figure 6-8 Front panel of the PO1

PO1
STAT
ACT
PROG
SRV

64
84
85
105
106
126

PO1

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Indicators
The front panel of the board has the following indicators:
l

Board hardware status indicator (STAT) two colors (red and green)

Service activation status indicator (ACT) one color (green)

Board software status indicator (PROG) two colors (red and green)

Service alarm indicator (SRV) three colors (red, green, and yellow)

For the meanings of the status of the indicators, see A Indicators.

Interfaces
The front panel of the PO1 has three interfaces for 21xE1 96-pin connectors. Table 6-7 describes
the types and usage of the interfaces of the PO1.
Table 6-7 Interfaces of the PO1
Interface

Type of Interface

Usage

2 mm FB

Receives the 64th to 84th E1 signals.

2 mm FB

Receives the 85th to 105th E1 signals.

2 mm FB

Receives the 106th to 126th E1 signals.

The D12S and D12B provide 120-ohm E1 interfaces for the PO1. The PO1 supports only the
120-ohm interface board. For details, see the topics that describe the D12S and D12B.

6.2.5 Valid Slots


The PO1 can be used with the D12S or D12B.
The PO1 can be installed in slots 37 and 1216 in the main subrack.
The PO1 can be used with the D12S or D12B.
Table 6-8 lists the slots valid for the PO1 and the corresponding slots for the D12S and D12B
in the main subrack.
Table 6-8 Slots valid for the PO1 and the corresponding slots for the D12S and D12B in the
main subrack
Slot Valid for the PO1

Corresponding Slots for the D12S and


D12B

Slot 3

Slot 21(132 channels of services)


Slot 22 (3363 channels of services)

Slot 4

Slot 23 (132 channels of services)


Slot 24 (3363 channels of services)

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Slot Valid for the PO1

Corresponding Slots for the D12S and


D12B

Slot 5

Slot 25 (132 channels of services)


Slot 26 (3363 channels of services)

Slot 6

Slot 27 (132 channels of services)


Slot 28 (3363 channels of services)

Slot 7

Slot 29 (132 channels of services)


Slot 30 (3363 channels of services)

Slot 12

Slot 31(132 channels of services)


Slot 32 (3363 channels of services)

Slot 13

Slot 33 (132 channels of services)


Slot 34 (3363 channels of services)

Slot 14

Slot 35 (132 channels of services)


Slot 36 (3363 channels of services)

Slot 15

Slot 37 (132 channels of services)


Slot 38 (3363 channels of services)

Slot 16

Slot 39 (132 channels of services)


Slot 40 (3363 channels of services)

6.2.6 Feature Code


The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the PO1 indicates the type of interface impedance.
Table 6-9 provides the relationship between the feature code of the PO1 and the type of interface
impedance.
Table 6-9 Relationship between the feature code of the PO1 and the type of interface impedance
Board

Feature Code

Type of Interface Impedance

SSN2PO1B01

B01

120-ohm

6.2.7 Parameter Settings


You can set the parameters for the PO1 by using the T2000.
You can set the following parameters for the PO1 by using the T2000:
l

J2 byte

V5 byte

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l

Tributary loopback

Service loading indication

For the description of each parameter, see F Parameter Settings.

6.2.8 Technical Specifications


The technical specifications of the PO1 include the parameters specified for electrical interfaces,
mechanical specifications, and power consumption.

Parameters Specified for Electrical Interfaces


The D12S or D12B provides electrical interfaces for the PO1. For the parameters specified for
the electrical interfaces, see D12S and D12B.

Mechanical Specifications
The mechanical specifications of the PO1 are as follows:
l

Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)

Weight (kg): 2.0

Power Consumption
The maximum power consumption of the N2PO1 at room temperature (25C) is 32 W.

6.3 PQM
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the PQM (63xE1/T1 service processing board).
6.3.1 Version Description
The PQM is available in one functional version, namely, N1.
6.3.2 Functions and Features
The PQM processes E1/T1 signals, processes overhead bytes, reports alarms and performance
events, provides maintenance features, and supports the TPS protection.
6.3.3 Working Principle and Signal Flow
The PQM consists of the PPI module, E1/T1 mapping/demapping module, interface converting
module, logic and control module, DC/DC converter, and other modules.
6.3.4 Front Panel
The front panel of the PQM has indicators.
6.3.5 Valid Slots
The PQM can be installed in slots 27 and 1216, and must be used with the D12S or D12B.
6.3.6 Board Protection
The PQM supports the 1:N TPS protection.
6.3.7 Parameter Settings
You can set the parameters for the PQM by using the T2000.
6.3.8 Technical Specifications
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The technical specifications of the PQM include the parameters specified for electrical
interfaces, mechanical specifications, and power consumption.

6.3.1 Version Description


The PQM is available in one functional version, namely, N1.

6.3.2 Functions and Features


The PQM processes E1/T1 signals, processes overhead bytes, reports alarms and performance
events, provides maintenance features, and supports the TPS protection.
Table 6-10 provides the functions and features of the PQM.
Table 6-10 Functions and features of the PQM
Function
and Feature

PQM

Basic
functions

Processes 63xE1/T1 signals.

Service
processing

Accesses and processes 63xE1/T1 electrical signals when working with the
interface board. Each channel can be configured as E1 or T1.

Overhead
processing

Supports the processing of the path overheads at the VC-12 level, such as
the J2 byte.

Alarms and
performance
events

Reports various alarms and performance events, which facilitates the


management and maintenance of the equipment.

Maintenance
features

Supports inloops and outloops at electrical interfaces.

Supports warm resets and cold resets. The warm reset does not affect
services.

Supports the query of the manufacturing information of the board.

Supports the in-service loading of the FPGA.

Supports the upgrade of the board software without affecting services.

Supports the PRBS function.

Protection
schemes

Supports the TPS protection when working with the interface board.
l

When the working board is the N1PQ1, the protection board can be the
N1PQ1, N2PQ1 or N1PQM. In this case, the hybrid protection is
provided.

When the working board is the N1PQM, the protection board can only be
the N1PQM.

6.3.3 Working Principle and Signal Flow


The PQM consists of the PPI module, E1/T1 mapping/demapping module, interface converting
module, logic and control module, DC/DC converter, and other modules.
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Figure 6-9 shows the functional block diagram of the PQM.


Figure 6-9 Functional block diagram of the PQM
1.5 MHz/
2 MHz
OSC

E1/T1
E1/T1

LIU

LIU

155 MHz
PLL

63x1.5 Mbit/s/
63x2 Mbit/s

P
P
I

63x1.5 Mbit/
s/
63x2 Mbit/s

LOS

E1/T1
mapping/
demapping
module

155 Mbit/s

155 Mbit/s

Highspeed bus

Interface
converting
module

Highspeed bus

Frame header
Communication

Logic and
control module

Outloop/Inloop
control

Reference
clock

+3.3 V
DC/DC
converter

DC/DC
converter

Fuse

Cross-connect unit

Cross-connect unit A
Cross-connect unit B

Cross-connect unit
SCC Unit
-48 V/-60 V
-48 V/-60 V

Figure 6-10 shows the functional block diagram of the E1/T1 mapping/demapping module.
Figure 6-10 Functional block diagram of the E1/T1 mapping/demapping module
Mapping/demapping module
E1/T1

LPA

PDH AIS
detector

HPA

LPT

LPOH(V5/J2/N2/
K4) insertion
LPOH(V5/J2/N2/
K4) extraction

STM-1

TU-AIS/TULOP detector

E1/T1
LPA

HPT

LPT

HPA

HPT

STM-1

The functional modules are described as follows:

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PPI Module
The PPI module consists of LIUs and provides the inloop and outloop functions. The PPI module
performs the following functions:
l

Encodes and decodes signals.

Restores the data signal and the clock signal.

Processes the PDH LOS signals.

E1/T1 Mapping/Demapping Module


l

LPA sub-module

The 2 Mbit/s (1.5 Mbit/s) plesiochronous stream is inserted in a VC-12 container to be


adapted so that the stream can be transported to the synchronous network for check of the
PDH AIS.

LPT sub-module

The virtual container (VC-12) is formatted. The VC-12 is structured so that its octets are
distributed within a 125 us interval (for example, one STM1 period), and consists of the
VC-12 container and POH. The POH contains nine octets equally distributed within the
frame bytes for VC-12, namely, V5, J2, N2, and K4.

HPA sub-module

The HPA sub-module generates and processes the channel-level TU-PTR. In the receive
direction, the signals are split into VC-12s, which are located and isolated in TU-12s. The
TU-PTR is processed. TU-AIS and TU-LOP alarms are monitored. In the transmit
direction, VC-12s are located precisely and added with the TU-PTR. Sixty-three TUG-3s
are multiplexed into a VC-4 by bytes interleaving. The sequence is as follows: TUG2>TUG3->VC-4

HPT sub-module

The virtual container (VC-4) is formatted. The VC-4 is structured so that its octets are
distributed within a 125 us interval (for example, one STM1 period), and consists of the
C4 container and POH.

MST sub-module and RST sub-module

These sub-modules are required to create a proprietary STM1 signal so that the E1
mapping/demapping module can interface with the multiplex unit.

Interface Converting Module


The interface converting module converts the 622 Mbit/s LVDS bus of the SDH system into the
parallel bus. The high-rate backplane interface is connected to the low-rate interface chip of the
transmit system through the interface converting module.

Logic and Control Module


l

Manages and configures the other modules of the board.

Performs inter-board communication through the internal Ethernet interface.

Traces the clock signal from the active and standby cross-connect units.

Selects the clock signal and frame header signal from the active and standby cross-connect
units.

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l

Control the indicators on the board.

DC/DC Converter
It converts the 48/60 V power supply into the DC voltages that the modules of the board
require.

6.3.4 Front Panel


The front panel of the PQM has indicators.

Diagram of the Front Panel


Figure 6-11 shows the appearance of the front panel of the PQM.
Figure 6-11 Front panel of the PQM

PQM
STAT
ACT
PROG
SRV

PQM

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Indicators
The front panel of the board has the following indicators:
l

Board hardware status indicator (STAT) two colors (red and green)

Service activation status indicator (ACT) one color (green)

Board software status indicator (PROG) two colors (red and green)

Service alarm indicator (SRV) three colors (red, green, and yellow)

For the meanings of the status of the indicators, see A Indicators.

Interfaces
The front panel of the PQM does not have an interface. The D12S and D12B provide 120-ohm
E1 interfaces or 100-ohm T1 interfaces for the PQM. For details, see the topics that describe the
D12S and D12B.

6.3.5 Valid Slots


The PQM can be installed in slots 27 and 1216, and must be used with the D12S or D12B.
Table 6-11 lists the slots valid for the PQM and the corresponding slots for the D12S and D12B
in the main subrack.
Table 6-11 Slots valid for the PQM and the corresponding slots for the D12S and D12B in the
main subrack
Slot Valid for the PQM

Corresponding Slots for the D12S and


D12B

Slot 2

Without the interface board

Slot 3

Slot 21 (132 channels of services)


Slot 22 (3363 channels of services)

Slot 4

Slot 23 (132 channels of services)


Slot 24 (3363 channels of services)

Slot 5

Slot 25 (132 channels of services)


Slot 26 (3363 channels of services)

Slot 6

Slot 27 (132 channels of services)


Slot 28 (3363 channels of services)

Slot 7

Slot 29 (132 channels of services)


Slot 30 (3363 channels of services)

Slot 12

Slot 31 (132 channels of services)


Slot 32 (3363 channels of services)

Slot 13

Slot 33 (132 channels of services)


Slot 34 (3363 channels of services)

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Slot Valid for the PQM

Corresponding Slots for the D12S and


D12B

Slot 14

Slot 35 (132 channels of services)


Slot 36 (3363 channels of services)

Slot 15

Slot 37 (132 channels of services)


Slot 38 (3363 channels of services)

Slot 16

Slot 39 (132 channels of services)


Slot 40 (3363 channels of services)

NOTE

Slot 2 can house a protection board for the TPS protection. The board in slot 2 protects the boards in
slots 37 and 1216.

If the interface board for the boards in slots 37 and 1216 is the D12B, the boards in slots 37 and
1216 cannot be protected by the TPS protection scheme.

6.3.6 Board Protection


The PQM supports the 1:N TPS protection.

Protection Principle
The PQM boards work with the D12S boards to realize 1:N (N10) TPS protection. Figure
6-12 shows the TPS protection provided by the PQM.

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Figure 6-12 TPS protection provided by the PQM

E1 protection bus

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2
1

S
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2
2

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2
3

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2
4

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T
2
5

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2
6

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2
7

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2
8

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2
9

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3
0

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3
1

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3
2

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T
3
3

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3
4

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3
5

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3
6

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3
7

S
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3
8

S
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3
9

S
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4
0

D12S
D12S

D12S
D12S

D12S
D12S

D12S
D12S

D12S
D12S

D12S
D12S

D12S
D12S

D12S
D12S

D12S
D12S

D12S
D12S

E1 serv ice bus


S
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4

S
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5

S
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6

S
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7

S
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1
2
Failed

S
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1
5

S
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1
6

Working

S
L
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1
4

Working

Working

Working

Working

Working

Working

Working

Protection

S
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1
3

Working

S
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T
3

Working

S
L
O
T
2

Detecting a
board f ault
Cross-connect and timing board

TPS control bus

When the cross-connect and timing board detects that a working PQM is faulty, the cross-connect
and timing board issues a service switching command to control the access board to switch the
services from the faulty PQM to the protection PQM, which realizes the protection of the
services.

Hardware Configuration
Table 6-12 shows the slot configuration for the 1:10 TPS protection of the PQM.
Table 6-12 Slot configuration for the 1:10 TPS protection of the PQM

Issue 02 (2009-07-30)

Working
Board

Protection Board

Slot Configuration

PQM (E1)

PQM (E1)

PQM (T1)

PQM (T1)

Slot 2 can house a protection board. The


board in slot 2 protects the boards in slots
37 and 1216. Figure 6-13 shows the slot
configuration for the 1:10 TPS protection
of the PQM.

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Figure 6-13 Slot configuration for the 1:10 TPS protection of the PQM

S
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28

S
L
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T
29

S
L
O
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32

S S S S
L L L L
O O O O
T T T T
33 34 35 36

SLOT 43 EOW

S S S S
L L L L
O O O O
T T T T
13 14 15 16

SLOT 42AUX

working

working

S S
L L
O O
T T
11 12

working

S
L
O
T
10

working

S
L
O
T
9

working

working
working

S
L
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8

CXL

working

S
L
O
T
7

FAN

CXL

S
L
O
T
6

working

S S
L L
O O
T T
4 5

working

SLOT 41 PIU

S
L
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3

Protection

SLOT 11 PIU

S
L
O
T
2

S
L
O
T
40

D12S

FAN

S S S
L L L
O O O
T T T
37 38 39

D12S
D12S
D12S
D12S

D12S

FAN

S S
L L
O O
T T
30 31

D12S

D12S
D12S
D12S

S
L
O
T
27

D12S

D12S

S S
L L
O O
T T
25 26

D12S

D12S

S
L
O
T
24

D12S
D12S

S
L
O
T
23

D12S

S
L
O
T
22

D12S
D12S
D12S

S
L
O
T
21

Fiber routing area

6.3.7 Parameter Settings


You can set the parameters for the PQM by using the T2000.
You can set the following parameters for the PQM by using the T2000:
l

J2 byte

V5 byte

Tributary loopback

Service loading indication

Path service type

For the description of each parameter, see F Parameter Settings.

6.3.8 Technical Specifications


The technical specifications of the PQM include the parameters specified for electrical
interfaces, mechanical specifications, and power consumption.

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Parameters Specified for Electrical Interfaces


The D12S or D12B provides electrical interfaces for the PQM. For the parameters specified for
the electrical interfaces, see D12S and D12B.

Mechanical Specifications
The mechanical specifications of the PQM are as follows:
l

Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)

Weight (kg): 1.0

Power Consumption
The maximum power consumption of the PQM at room temperature (25C) is 22 W.

6.4 PL3
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the PL3 (3xE3/T3 service processing board).
6.4.1 Version Description
The PL3 is available in two functional versions, namely, N1 and N2. The difference between
the two versions is with regard to their functions. The N1PL3 is no longer manufactured.
6.4.2 Functions and Features
The PL3 processes E3/T3 signals, processes overhead bytes, reports alarms and performance
events, provides maintenance features, and supports the TPS protection.
6.4.3 Working Principle and Signal Flow
The PL3 consists of the PPI module, E3/T3 mapping/demapping module, interface converting
module, logic and control module, DC/DC converter, and other modules.
6.4.4 Front Panel
The front panel of the PL3 has indicators.
6.4.5 Valid Slots
The PL3 can be installed in slots 37 and 1216, and must be used with the C34S.
6.4.6 Board Protection
The PL3 supports the 1:N TPS protection.
6.4.7 Parameter Settings
You can set the parameters for the PL3 by using the T2000.
6.4.8 Technical Specifications
The technical specifications of the PL3 include the parameters specified for electrical interfaces,
mechanical specifications, and power consumption.

6.4.1 Version Description


The PL3 is available in two functional versions, namely, N1 and N2. The difference between
the two versions is with regard to their functions. The N1PL3 is no longer manufactured.
Table 6-13 describes the versions of the PL3.
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Table 6-13 Versions of the PL3


Item

Description

Functional versions

The PL3 is available in two functional versions, namely, N1 and N2.

Differences

The N1PL3 does not support the E13/M13 function.


The N2PL3 supports the E13/M13 function.
The N2PL3 supports the board version replacement function and can
replace the N1PL3. After the N2PL3 replaces the N1PL3, the
configuration and service status of the N2PL3 are the same as the
configuration and service status of the N1PL3.
The N2PL3 can replace the N1PL3.

Substitution

6.4.2 Functions and Features


The PL3 processes E3/T3 signals, processes overhead bytes, reports alarms and performance
events, provides maintenance features, and supports the TPS protection.
Table 6-14 provides the functions and features of the PL3.
Table 6-14 Functions and features of the PL3
Function and
Feature

PL3

Basic functions

Processes 3xE3/T3 signals.

Service processing

Accesses and processes 3xE3/T3 electrical signals.

Overhead
processing

Supports the setting and query of all the path overhead bytes at the VC-3
level.

Alarms and
performance
events

Reports various alarms and performance events, which facilitates the


management and maintenance of the equipment.

Maintenance
features

Supports inloops and outloops at electrical interfaces.

Supports warm resets and cold resets. The warm reset does not affect
services.

Supports the query of the manufacturing information of the board.

Supports the in-service loading of the FPGA.

Supports the upgrade of the board software without affecting


services.

Supports the PRBS function.

Protection
schemes

6-30

Supports the TPS protection when working with the interface board and
the switching and bridging board.

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6.4.3 Working Principle and Signal Flow


The PL3 consists of the PPI module, E3/T3 mapping/demapping module, interface converting
module, logic and control module, DC/DC converter, and other modules.
Figure 6-14 shows the functional block diagram of the PL3.
Figure 6-14 Functional block diagram of the PL3
34 MHz/
45 MHz
OSC

E3/T3
E3/T3

LIU

LIU

P
I

155 MHz
PLL

3x34 Mbit/s/
3x45 Mbit/s

2x155 Mbit/s
E3/T3
Interface
mapping/
converting
3x34 Mbit/s/
demapping
module
2x155 Mbit/s
3x45 Mbit/s
module

LOS

+3.3 V
DC/DC
converter

OSC: Oscillator

Cross-connect unit

Highspeed bus

Cross-connect unit A

Highspeed bus

Cross-connect unit B

Frame header
Communication

Logic and
control module

Outloop/Inloop
control

Reference
clock

DC/DC
converter

Cross-connect unit
SCC Unit

Fuse

-48 V/-60 V
-48 V/-60 V

PPI: PDH physical interface

Figure 6-15 shows the functional block diagram of the E3/T3 mapping/demapping module.
Figure 6-15 Functional block diagram of the E3/T3 mapping/demapping module
Mapping/demapping module
E3/T3

LPA

LPT

PDH AIS
detector

E3/T3
LPA

LPOH (J1/C2/
B3) insertion
LPOH (J1/C2/
B3) extraction

LPT

LPA: Low order path adaptation

Issue 02 (2009-07-30)

HPA

HPT

STM-1

TU-AIS/TULOP detector

HPA

HPT

STM-1

LPT: Low order path termination

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HPA: High order path adaptation

HPT: High order path termination

The functional modules are described as follows:

PPI Module
The PPI module consists of LIUs and provides the inloop and outloop functions. The PPI module
performs the following functions:
l

Encodes and decodes signals.

Restores the data signal and the clock signal.

Processes the P_LOS alarm.

E3/T3 Mapping/Demapping Module


l

LPA sub-module

The 45 Mbit/s (34 Mbit/s) plesiochronous stream is inserted in a C3 container to be adapted


so that the stream can be transported to the synchronous network.

LPT sub-module

The virtual container (VC-3) is formatted. The VC-3 is structured so that its octets are
distributed within a 125 us interval (for example, one STM1 period), and consists of the
VC-3 container and POH. The POH contains nine octets equally distributed within the
frame bytes for VC-3, namely, J1, B3, C2, G1, F2, H4, F3, K3, and N1.

HPA sub-module

The HPA sub-module generates and processes the channel-level TU-PTR. In the receive
direction, the signals are split into VC-3s, which are located and isolated in TU-3s. The
TU-PTR is processed. In the transmit direction, VC-3s are located precisely and added with
the TU-PTR. Three TUG-3s are multiplexed into a VC-4 by bytes interleaving. The
sequence is as follows: TU-3->TUG3->VC-4

HPT sub-module

The virtual container (VC-4) is formatted. The VC-4 is structured so that its octets are
distributed within a 125 us interval (for example, one STM1 period), and consists of the
C4 container and POH.

MST sub-module and RST sub-module

These sub-modules are required to create a proprietary STM1 signal so that the interface
converting module can be connected.

Interface Converting Module


The interface converting module converts the 622 Mbit/s LVDS bus of the SDH system into the
parallel bus. The high-rate backplane interface is connected to the low-rate interface chip of the
transmit system through the interface converting module.

Logic and Control Module

6-32

Manages and configures the other modules of the board.

Performs inter-board communication through the internal Ethernet interface.


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Traces the clock signal from the active and standby cross-connect units.

Selects the clock signal and frame header signal from the active and standby cross-connect
units.

Controls the indicators on the board.

DC/DC Converter
It converts the 48/60 V power supply into the DC voltages that the modules of the board
require.

6.4.4 Front Panel


The front panel of the PL3 has indicators.

Diagram of the Front Panel


Figure 6-16 shows the appearance of the front panel of the PL3.
Figure 6-16 Front panel of the PL3

PL3
STAT
ACT
PROG
SRV

PL3

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Indicators
The front panel of the board has the following indicators:
l

Board hardware status indicator (STAT) two colors (red and green)

Service activation status indicator (ACT) one color (green)

Board software status indicator (PROG) two colors (red and green)

Service alarm indicator (SRV) three colors (red, green, and yellow)

For the meanings of the status of the indicators, see A Indicators.

Interfaces
The front panel of the PL3 does not have an interface.
The C34S provides E3/T3 interfaces for the PL3. For details, see the topic that describes the
C34S.

6.4.5 Valid Slots


The PL3 can be installed in slots 37 and 1216, and must be used with the C34S.
Table 6-15 lists the slots valid for the PL3 and the corresponding slots for the C34S in the main
subrack.
Table 6-15 Slots valid for the PL3 and the corresponding slots for the C34S in the main subrack
Slot Valid for the PL3

Corresponding Slot for the C34S

Slot 3

Slot 21

Slot 4

Slot 23

Slot 5

Slot 25

Slot 6

Slot 27

Slot 7

Slot 29

Slot 12

Slot 31

Slot 13

Slot 33

Slot 14

Slot 35

Slot 15

Slot 37

Slot 16

Slot 39

6.4.6 Board Protection


The PL3 supports the 1:N TPS protection.
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Protection Principle
The PL3 can be configured into two 1:N (N3) TPS protection groups when the PL3 works
with the C34S and TSB8/TSB4. Figure 6-17 shows the TPS protection provided by the PL3.
Figure 6-17 TPS protection provided by the PL3
3xE3/T3

TSB8/
TSB4
3 2

3xE3/T3

C34S

3xE3/T3

Switching
control
C34S
signal

C34S
1

Crossconnect
and
timing
board
Slot 9/10

Protection
PL3

Working
PL3

Working
PL3

Working
PL3

Failed
Slot 3

Slot 4

Slot 5

Slot 6

Normal state
When each working board functions normally, the traffic signal is directly transmitted to
the PL3 through position 1 of the control switch on the C34S.

Switching state
When a working board detects a failure and requires the switching operation, the control
switch of the corresponding C34S switches from position 1 to position 2. At the same time,
the control switch of the TSB8/TSB4 switches to the corresponding position so that the
protection board can protect the failed working board.

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Hardware Configuration
Figure 6-18 Slot configuration for the two 1:3 TPS protection groups of the PL3

S
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23

S
L
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24

S
L
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25

S
L
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26

S
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27

S
L
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28

S
L
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29

FAN

S
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9

S
L
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37

S
L
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38

S
L
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39

S
L
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40

FAN

S
L
O
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10

S S
L L
O O
T T
11 12

S S S S
L L L
L
O O O O
T T T T
13 14 15 16

SLOT 43 EOW

S
L
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8

SLOT 42 AUX

Working 2

Protection 2

Working 2

Working 2

XCS

XCS

Working 1

Working 1

Working 1

SLOT 41PIU

S S S S
L L L L
O O O O
T T T T
4 5 6 7

Protection 1

SLOT 1 PIU

S
L
O
T
3

S
L
O
T
36

TSB8/TSB4

S
L
O
T
35

C34S

S S S
L L L
O O O
T T T
32 33 34

C34S

C34S

C34S

TSB8/TSB4

FAN

S
L
O
T
2

S S
L L
O O
T T
30 31

C34S

S
L
O
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22

C34S

S
L
O
T
21

Fiber routing area

In Figure 6-18, the board in slot 3 protects the boards in slots 46. The board in slot 16 protects
the boards in slots 1315.
Table 6-16 lists the slots for the PL3, C34S, and TSB8/TSB4.
Table 6-16 Slots for the PL3, C34S, and TSB8/TSB4

6-36

Board

Protection Group 1

Protection Group 2

PL3 (working board)

Slots 46

Slot 1315

PL3/PD3 (protection
board)

Slot 3

Slot 16

TSB8/TSB4

Slot 21

Slot 39

C34S

Slots 23, 25, and 27

Slots 33, 35, and 37

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6.4.7 Parameter Settings


You can set the parameters for the PL3 by using the T2000.
You can set the following parameters for the PL3 by using the T2000:
l

J1 byte

C2 byte

Tributary loopback

Service loading indication

Path service type

For the description of each parameter, see F Parameter Settings.

6.4.8 Technical Specifications


The technical specifications of the PL3 include the parameters specified for electrical interfaces,
mechanical specifications, and power consumption.

Parameters Specified for Electrical Interfaces


The C34S provides electrical interfaces for the PL3. For the parameters specified for the
electrical interfaces, see C34S.

Mechanical Specifications
The mechanical specifications of the PL3 are as follows:
l

Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)

Weight (kg): 1.0

Power Consumption
The maximum power consumption of the N1PL3 at room temperature (25C) is 15 W.
The maximum power consumption of the N2PL3 at room temperature (25C) is 12 W.

6.5 PL3A
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the PL3A (3xE3/T3 service processing board with the interfaces on
the front panel).
6.5.1 Version Description
The PL3A is available in two functional versions, namely, N1 and N2. The difference between
the two versions is with regard to whether they support the E13/M13 function. The N1PL3A is
no longer manufactured.
6.5.2 Functions and Features
The PL3A processes E3/T3 signals, processes overhead bytes, reports alarms and performance
events, provides maintenance features, and supports the TPS protection.
6.5.3 Working Principle and Signal Flow
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The PL3A consists of the PPI module, E3/T3 mapping/demapping module, interface converting
module, logic and control module, DC/DC converter, and other modules.
6.5.4 Front Panel
The front panel of the PL3A has indicators and interfaces.
6.5.5 Valid Slots
The PL3A can be installed in slots 28 and 1116 in the subrack.
6.5.6 Parameter Settings
You can set the parameters for the PL3A by using the T2000.
6.5.7 Technical Specifications
The technical specifications of the PL3A include the parameters specified for electrical
interfaces, mechanical specifications, and power consumption.

6.5.1 Version Description


The PL3A is available in two functional versions, namely, N1 and N2. The difference between
the two versions is with regard to whether they support the E13/M13 function. The N1PL3A is
no longer manufactured.
Table 6-17 describes the versions of the PL3A.
Table 6-17 Versions of the PL3A
Item

Description

Functional versions

The PL3A is available in two functional versions, namely, N1 and


N2.

Differences

The N1PL3A does not support the E13/M13 function.


The N2PL3A supports the E13/M13 function.
The N2PL3A supports the board version replacement function and
can replace the N1PL3A. After the N2PL3A replaces the N1PL3A,
the configuration and service status of the N2PL3A are the same as
the configuration and service status of the N1PL3A.

Substitution

The N2PD3A can replace the N1PD3A.

6.5.2 Functions and Features


The PL3A processes E3/T3 signals, processes overhead bytes, reports alarms and performance
events, provides maintenance features, and supports the TPS protection.
Table 6-18 provides the functions and features of the PL3A.

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Table 6-18 Functions and features of the PL3A


Function and
Feature

PL3A

Basic functions

Processes 3xE3/T3 signals.

The N2PL3A supports the E13 function, which is used to converge


E1 services into E3 services.

The N2PL3A supports the M13 function, which is used to


converge T1 services into T3 services.

Service processing

Accesses and processes 3xE3/T3 electrical signals.

Overhead
processing

Supports the setting and query of all the path overhead bytes at the
VC-3 level.

Alarms and
performance events

Reports various alarms and performance events, which facilitates the


management and maintenance of the equipment.

Maintenance
features

Supports inloops and outloops at electrical interfaces.

Supports warm resets and cold resets. The warm reset does not
affect services.

Supports the query of the manufacturing information of the board.

Supports the in-service loading of the FPGA.

Supports the upgrade of the board software without affecting


services.

Supports the PRBS function.

6.5.3 Working Principle and Signal Flow


The PL3A consists of the PPI module, E3/T3 mapping/demapping module, interface converting
module, logic and control module, DC/DC converter, and other modules.
Figure 6-19 shows the functional block diagram of the PL3A.

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Figure 6-19 Functional block diagram of the PL3A


34 MHz/
45 MHz
OSC

E3/T3
E3/T3

LIU

LIU

P
I

155 MHz
PLL

3x34 Mbit/s/
3x45 Mbit/s

2x155 Mbit/s
E3/T3
Interface
mapping/
converting
3x34 Mbit/s/
demapping
module
2x155 Mbit/s
3x45 Mbit/s
module

LOS

+3.3 V
DC/DC
converter

OSC: Oscillator

Cross-connect unit

Highspeed bus

Cross-connect unit A

Highspeed bus

Cross-connect unit B

Frame header
Communication

Logic and
control module

Outloop/Inloop
control

Reference
clock

DC/DC
converter

Cross-connect unit
SCC Unit

Fuse

-48 V/-60 V
-48 V/-60 V

PPI: PDH physical interface

Figure 6-20 shows the functional block diagram of the E3/T3 mapping/demapping module.
Figure 6-20 Functional block diagram of the E3/T3 mapping/demapping module
Mapping/demapping module
E3/T3

LPA

HPA

LPT

PDH AIS
detector

E3/T3
LPA

LPOH (J1/C2/
B3) insertion
LPOH (J1/C2/
B3) extraction

HPT

STM-1

TU-AIS/TULOP detector

HPA

LPT

HPT

STM-1

LPA: Low order path adaptation

LPT: Low order path termination

HPA: High order path adaptation

HPT: High order path termination

The functional modules are described as follows:


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PPI Module
The PPI module consists of LIUs and provides the inloop and outloop functions. The PPI module
performs the following functions:
l

Encodes and decodes signals.

Restores the data signal and the clock signal.

Processes the P_LOS alarm.

E3/T3 Mapping/Demapping Module


l

LPA sub-module

The 45 Mbit/s (34 Mbit/s) plesiochronous stream is inserted in a C3 container to be adapted


so that the stream can be transported to the synchronous network.

LPT sub-module

The virtual container (VC-3) is formatted. The VC-3 is structured so that its octets are
distributed within a 125 us interval (for example, one STM1 period), and consists of the
VC-3 container and POH. The POH contains nine octets equally distributed within the
frame bytes for VC-3, namely, J1, B3, C2, G1, F2, H4, F3, K3, and N1.

HPA sub-module

The HPA sub-module generates and processes the channel-level TU-PTR. In the receive
direction, the signals are split into VC-3s, which are located and isolated in TU-3s. The
TU-PTR is processed. In the transmit direction, VC-3s are located precisely and added with
the TU-PTR. Three TUG-3s are multiplexed into a VC-4 by bytes interleaving. The
sequence is as follows: TU-3->TUG3->VC-4

HPT sub-module

The virtual container (VC-4) is formatted. The VC-4 is structured so that its octets are
distributed within a 125 us interval (for example, one STM1 period), and consists of the
C4 container and POH.

MST sub-module and RST sub-module

These sub-modules are required to create a proprietary STM1 signal so that the interface
converting module can be connected.

Interface Converting Module


The interface converting module converts the 622 Mbit/s LVDS bus of the SDH system into the
parallel bus. The high-rate backplane interface is connected to the low-rate interface chip of the
transmit system through the interface converting module.

Logic and Control Module


l

Manages and configures the other modules of the board.

Performs inter-board communication through the internal Ethernet interface.

Traces the clock signal from the active and standby cross-connect units.

Selects the clock signal and frame header signal from the active and standby cross-connect
units.

Controls the indicators on the board.

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DC/DC Converter
It converts the 48/60 V power supply into the DC voltages that the modules of the board
require.

6.5.4 Front Panel


The front panel of the PL3A has indicators and interfaces.

Diagram of the Front Panel


Figure 6-21 shows the appearance of the front panel of the PL3A.
Figure 6-21 Front panel of the PL3A

PL3A
STAT
ACT
PROG
SRV

OUT1
IN1
OUT2
IN2
OUT3
IN3

PL3A

Indicators
The front panel of the board has the following indicators:
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Board hardware status indicator (STAT) two colors (red and green)

Service activation status indicator (ACT) one color (green)

Board software status indicator (PROG) two colors (red and green)

Service alarm indicator (SRV) three colors (red, green, and yellow)

For the meanings of the status of the indicators, see A Indicators.

Interfaces
The front panel of the PL3A has three pairs of 75-ohm unbalanced interfaces, which are of the
SMB type.

6.5.5 Valid Slots


The PL3A can be installed in slots 28 and 1116 in the subrack.

6.5.6 Parameter Settings


You can set the parameters for the PL3A by using the T2000.
You can set the following parameters for the PL3A by using the T2000:
l

J1 byte

C2 byte

Tributary loopback

Service loading indication

Path service type

For the description of each parameter, see F Parameter Settings.

6.5.7 Technical Specifications


The technical specifications of the PL3A include the parameters specified for electrical
interfaces, mechanical specifications, and power consumption.

Parameters Specified for Electrical Interfaces


Table 6-19 lists the parameters specified for the electrical interfaces of the PL3A.
Table 6-19 Parameters specified for the electrical interfaces of the PL3A

Issue 02 (2009-07-30)

Nominal Bit
Rate

Line Code
Pattern

Signal Bit
Rate at the
Output
Interface

34368 kbit/s

HDB3

Complies with ITU-T G.703.

44736 kbit/s

B3ZS

Complies with ITU-T G.703.

Allowed
Frequency
Deviation
at the
Input
Interface

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Allowed
Attenuatio
n at the
Input
Interface

Input
Jitter
Tolerance

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Mechanical Specifications
The mechanical specifications of the PL3A are as follows:
l

Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)

Weight (kg): 1.0

Power Consumption
The maximum power consumption of the N1PL3A at room temperature (25C) is 15 W.
The maximum power consumption of the N2PL3A at room temperature (25C) is 12 W.

6.6 PD3
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the PD3 (6xE3/T3 service processing board).
6.6.1 Version Description
The PD3 is available in two functional versions, namely, N1 and N2. The difference between
the two versions is with regard to whether they support the E13/M13 function. The N1PD3 is
no longer manufactured.
6.6.2 Functions and Features
The PD3 processes E3/T3 signals, processes overhead bytes, reports alarms and performance
events, provides maintenance features, and supports the TPS protection.
6.6.3 Working Principle and Signal Flow
The PD3 consists of the PPI module, E3/T3 mapping/demapping module, interface converting
module, logic and control module, DC/DC converter, and other modules.
6.6.4 Front Panel
The front panel of the PD3 has indicators.
6.6.5 Valid Slots
The PD3 can be installed in slots 37 and 1216, and must be used with the D34S.
6.6.6 Board Protection
The PD3 supports the 1:N TPS protection.
6.6.7 Parameter Settings
You can set the parameters for the PD3 by using the T2000.
6.6.8 Technical Specifications
The technical specifications of the PD3 include the parameters specified for electrical interfaces,
mechanical specifications, and power consumption.

6.6.1 Version Description


The PD3 is available in two functional versions, namely, N1 and N2. The difference between
the two versions is with regard to whether they support the E13/M13 function. The N1PD3 is
no longer manufactured.
Table 6-20 describes the versions of the PD3.
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Table 6-20 Versions of the PD3


Item

Description

Functional versions

The PD3 is available in two functional versions, namely, N1 and N2.

Differences

The N1PD3 does not support the E13/M13 function.

The N2PD3 supports the E13/M13 function.

The N2PD3 supports the board version replacement function and


can replace the N1PD3. After the N2PD3 replaces the N1PD3, the
configuration and service status of the N2PD3 are the same as the
configuration and service status of the N1PD3.

The N2PD3 can replace the N1PD3.

Substitution

6.6.2 Functions and Features


The PD3 processes E3/T3 signals, processes overhead bytes, reports alarms and performance
events, provides maintenance features, and supports the TPS protection.
Table 6-21 provides the functions and features of the PD3.
Table 6-21 Functions and features of the PD3

Issue 02 (2009-07-30)

Function
and Feature

PD3

Basic
functions

Processes 6xE3/T3 signals.

Service
processing

Accesses and processes 6xE3/T3 electrical signals.

The N2PD3 supports the E13 function, which is used to converge E1


services into E3 services.

The N2PD3 supports the M13 function, which is used to converge T1


services into T3 services.

Overhead
processing

Supports the setting and query of all the path overhead bytes at the VC-3
level.

Alarms and
performance
events

Reports various alarms and performance events, which facilitates the


management and maintenance of the equipment.

Maintenance
features

Supports inloops and outloops at electrical interfaces.

Supports warm resets and cold resets. The warm reset does not affect
services.

Supports the query of the manufacturing information of the board.

Supports the in-service loading of the FPGA.

Supports the upgrade of the board software without affecting services.

Supports the PRBS function.

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Function
and Feature

PD3

Protection
schemes

Supports the TPS protection when working with the interface board and the
switching and bridging board.

6.6.3 Working Principle and Signal Flow


The PD3 consists of the PPI module, E3/T3 mapping/demapping module, interface converting
module, logic and control module, DC/DC converter, and other modules.
Figure 6-22 shows the functional block diagram of the PD3.
Figure 6-22 Functional block diagram of the PD3
34 MHz/
45 MHz
OSC

E3/T3
E3/T3

LIU

LIU

P
I

155 MHz
PLL

6x34 Mbit/s/
6x45 Mbit/s

2x155 Mbit/s
E3/T3
Interface
mapping/
converting
6x34 Mbit/s/
demapping
module
2x155 Mbit/s
6x45 Mbit/s
module

LOS
Outloop/Inloop
control

+3.3 V

OSC: Oscillator

DC/DC
converter

Cross-connect unit

Highspeed bus

Cross-connect unit A

Highspeed bus

Cross-connect unit B

Frame header
Communication

Logic and
control module

DC/DC
converter

Reference
clock

Fuse

Cross-connect unit
SCC Unit
-48 V/-60 V
-48 V/-60 V

PPI: PDH physical interface

Figure 6-23 shows the functional block diagram of the E3/T3 mapping/demapping module.

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Figure 6-23 Functional block diagram of the E3/T3 mapping/demapping module


Mapping/demapping module
E3/T3

LPA

HPA

LPT

PDH AIS
detector

LPOH (J1/C2/
B3) insertion
LPOH (J1/C2/
B3) extraction

E3/T3
LPA

HPT

STM-1

TU-AIS/TULOP detector

HPA

LPT

HPT

STM-1

LPA: Low order path adaptation

LPT: Low order path termination

HPA: High order path adaptation

HPT: High order path termination

The functional modules are described as follows:

PPI Module
The PPI module consists of LIUs and provides the inloop and outloop functions. The PPI module
performs the following functions:
l

Encodes and decodes signals.

Restores the data signal and the clock signal.

Processes the P_LOS alarm.

E3/T3 Mapping/Demapping Module


l

LPA sub-module

The 45 Mbit/s (34 Mbit/s) plesiochronous stream is inserted in a C3 container to be adapted


so that the stream can be transported to the synchronous network.

LPT sub-module

The virtual container (VC-3) is formatted. The VC-3 is structured so that its octets are
distributed within a 125 us interval (for example, one STM1 period), and consists of the
VC-3 container and POH. The POH contains nine octets equally distributed within the
frame bytes for VC-3, namely, J1, B3, C2, G1, F2, H4, F3, K3, and N1.

HPA sub-module

The HPA sub-module generates and processes the channel-level TU-PTR. In the receive
direction, the signals are split into VC-3s, which are located and isolated in TU-3s. The
TU-PTR is processed. In the transmit direction, VC-3s are located precisely and added with
the TU-PTR. Three TUG-3s are multiplexed into a VC-4 by bytes interleaving. The
sequence is as follows: TU-3->TUG3->VC-4

HPT sub-module

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l

The virtual container (VC-4) is formatted. The VC-4 is structured so that its octets are
distributed within a 125 us interval (for example, one STM1 period), and consists of the
C4 container and POH.

MST sub-module and RST sub-module

These sub-modules are required to create a proprietary STM1 signal so that the interface
converting module can be connected.

Interface Converting Module


The interface converting module converts the 622 Mbit/s LVDS bus of the SDH system into the
parallel bus. The high-rate backplane interface is connected to the low-rate interface chip of the
transmit system through the interface converting module.

Logic and Control Module


l

Manages and configures the other modules of the board.

Performs inter-board communication through the internal Ethernet interface.

Traces the clock signal from the active and standby cross-connect units.

Selects the clock signal and frame header signal from the active and standby cross-connect
units.

Controls the indicators on the board.

DC/DC Converter
It converts the 48/60 V power supply into the DC voltages that the modules of the board
require.

6.6.4 Front Panel


The front panel of the PD3 has indicators.

Diagram of the Front Panel


Figure 6-24 shows the appearance of the front panel of the PD3.

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Figure 6-24 Front panel of the PD3

PD3
STAT
ACT
PROG
SRV

PD3

Indicators
The front panel of the board has the following indicators:
l

Board hardware status indicator (STAT) two colors (red and green)

Service activation status indicator (ACT) one color (green)

Board software status indicator (PROG) two colors (red and green)

Service alarm indicator (SRV) three colors (red, green, and yellow)

For the meanings of the status of the indicators, see A Indicators.

Interfaces
The front panel of the PD3 does not have an interface.
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The D34S provides E3/T3 interfaces for the PD3. For details, see the topic that describes the
D34S.

6.6.5 Valid Slots


The PD3 can be installed in slots 37 and 1216, and must be used with the D34S.
Table 6-22 lists the slots valid for the PD3 and the corresponding slots for the D34S in the main
subrack.
Table 6-22 Slots valid for the PD3 and the corresponding slots for the D34S in the main subrack
Slot Valid for the PD3

Corresponding Slot for the D34S

Slot 3

Slot 21

Slot 4

Slot 23

Slot 5

Slot 25

Slot 6

Slot 27

Slot 7

Slot 29

Slot 12

Slot 31

Slot 13

Slot 33

Slot 14

Slot 35

Slot 15

Slot 37

Slot 16

Slot 39

6.6.6 Board Protection


The PD3 supports the 1:N TPS protection.

Protection Principle
The PD3 can be configured into two 1:N (N3) TPS protection groups when the PD3 works
with the D34S and TSB8. Figure 6-25 shows the TPS protection provided by the PD3.

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Figure 6-25 TPS protection provided by the PD3


6xE3/T3

TSB8

6xE3/T3

D34S

6xE3/T3

Sw itching
control
D34S
signal

D34S

Crossconnect
and timing
board
Slot 9/10
Protection
PD3

Working
PD3

Working
PD3

Working
PD3

Failed
Slot 2

Slot 3

Slot 4

Slot 5

Normal state
When each working board functions normally, the traffic signal is directly transmitted to
the PD3 through position 1 of the control switch on the D34S.

Switching state
When a working board detects a failure and requires the switching operation, the control
switch of the corresponding D34S switches from position 1 to position 2. At the same time,
the control switch of the TSB8 switches to the corresponding position so that the protection
board can protect the failed working board.

Hardware Configuration
Table 6-23 shows the slot configuration for the 1:3 TPS protection of the PD3.
Table 6-23 Slot configuration for the two 1:3 TPS protection groups of the PD3

Issue 02 (2009-07-30)

Working
Board

Protection Board

Slot Configuration

PD3 (E3)

PD3 (E3)

PD3 (T3)

PD3 (T3)

Figure 6-26 shows the slot configuration for


the 1:3 TPS protection of the PD3.

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Figure 6-26 Slot configuration for the two 1:3 TPS protection groups of the PD3

S
L
O
T
23

S
L
O
T
24

S
L
O
T
28

S
L
O
T
29

S S S S
L L L L
O O O O
T T T T
33 34 35 36

S
L
O
T
6

S
L
O
T
7

S
L
O
T
8

S
L
O
T
9

S
L
O
T
38

S
L
O
T
39

S
L
O
T
40

FAN

S
L
O
T
10

S S S S S S
L
L L L L
L
O O O O O O
T T T T T T
11 12 13 14 15 16

SLOT 43 EOW

S
L
O
T
5

S
L
O
T
37

TSB8

FAN

SLOT 42 AUX

Protection 2

Working 2

Working 2

Working 2

CXL

CXL

Working 1
Working 1

Working 1

SLOT 41 PIU

S
L
O
T
4

Protection 1

SLOT 1 PIU

S
L
O
T
3

S
L
O
T
32

D34S

FAN

S
L
O
T
2

S S
L L
O O
T T
30 31

D34S

S
L
O
T
27

D34S

D34S

TSB8

S S
L L
O O
T T
25 26

D34S

S
L
O
T
22

D34S

S
L
O
T
21

Fiber routing area

In Figure 6-26, the board in slot 3 protects the boards in slots 46. The board in slot 16 protects
the boards in slots 1315.
Table 6-24 lists the slots for the PD3, D34S, and TSB8.
Table 6-24 Slots for the PD3, D34S, and TSB8
Board

Protection Group 1

Protection Group 2

PD3 (working board)

Slots 46

Slots 1315

PD3 (protection board)

Slot 3

Slot 16

TSB8

Slot 21

Slot 39

D34S

Slots 23, 25, and 27

Slots 33, 35, and 37

6.6.7 Parameter Settings


You can set the parameters for the PD3 by using the T2000.
You can set the following parameters for the PD3 by using the T2000:
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l

J1 byte

C2 byte

Tributary loopback

Service loading indication

Path service type

6 PDH Boards

For the description of each parameter, see F Parameter Settings.

6.6.8 Technical Specifications


The technical specifications of the PD3 include the parameters specified for electrical interfaces,
mechanical specifications, and power consumption.

Parameters Specified for Electrical Interfaces


The C34S provides electrical interfaces for the PD3. For the parameters specified for the
electrical interfaces, see D34S.

Mechanical Specifications
The mechanical specifications of the PD3 are as follows:
l

Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)

Weight (kg): 1.1

Power Consumption
The maximum power consumption of the N1PD3 at room temperature (25C) is 19 W.
The maximum power consumption of the N2PD3 at room temperature (25C) is 12 W.

6.7 PQ3
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the PQ3 (12xE3/T3 service processing board).
6.7.1 Version Description
The PQ3 is available in one functional version, namely, N2.
6.7.2 Functions and Features
The PQ3 processes E3/T3 signals, processes overhead bytes, reports alarms and performance
events, provides maintenance features, and supports the TPS protection.
6.7.3 Working Principle and Signal Flow
The PQ3 consists of the PPI module, E3/T3 mapping/demapping module, interface converting
module, logic and control module, DC/DC converter, and other modules.
6.7.4 Front Panel
The front panel of the PQ3 has indicators.
6.7.5 Valid Slots
The PQ3 can be installed in slots 37 and 1216, and must be used with the D34S.
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6.7.6 Board Protection


The PQ3 supports the 1:N TPS protection.
6.7.7 Parameter Settings
You can set the parameters for the PQ3 by using the T2000.
6.7.8 Technical Specifications
The technical specifications of the PQ3 include the parameters specified for electrical interfaces,
mechanical specifications, and power consumption.

6.7.1 Version Description


The PQ3 is available in one functional version, namely, N2.

6.7.2 Functions and Features


The PQ3 processes E3/T3 signals, processes overhead bytes, reports alarms and performance
events, provides maintenance features, and supports the TPS protection.
Table 6-25 provides the functions and features of the PQ3.
Table 6-25 Functions and features of the PQ3
Function and
Feature

PQ3

Basic functions

Processes 12xE3/T3 signals.

Service
processing

Accesses and processes 12xE3/T3 electrical signals.

Supports the E13 function, which is used to converge E1 services into


E3 services.

Supports the M13 function, which is used to converge T1 services into


T3 services.

Overhead
processing

Supports the setting and query of all the path overhead bytes at the VC-3
level.

Alarms and
performance
events

Reports various alarms and performance events, which facilitates the


management and maintenance of the equipment.

Maintenance
features

Supports inloops and outloops at electrical interfaces.

Supports warm resets and cold resets. The warm reset does not affect
services.

Supports the query of the manufacturing information of the board.

Supports the in-service loading of the FPGA.

Supports the upgrade of the board software without affecting services.

Supports the PRBS function.

Protection
schemes

6-54

Supports the TPS protection when working with the interface board and the
switching and bridging board.

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6.7.3 Working Principle and Signal Flow


The PQ3 consists of the PPI module, E3/T3 mapping/demapping module, interface converting
module, logic and control module, DC/DC converter, and other modules.
Figure 6-27 shows the functional block diagram of the PQ3.
Figure 6-27 Functional block diagram of the PQ3
34 MHz/
45 MHz
OSC

E3/T3
E3/T3

LIU

LIU

P
I

155 MHz
PLL

12x34 Mbit/s/
12x45 Mbit/s

2x155 Mbit/s
E3/T3
Interface
mapping/
converting
12x34 Mbit/s/
demapping
module
2x155 Mbit/s
12x45 Mbit/s
module

LOS
Outloop/Inloop
control

+3.3 V

OSC: Oscillator

Cross-connect unit

Highspeed bus

Cross-connect unit A

Highspeed bus

Cross-connect unit B

Frame header
Communication

Logic and
control module

DC/DC
converter

Reference
clock

DC/DC
converter

Cross-connect unit
SCC Unit

Fuse

-48 V/-60 V
-48 V/-60 V

PPI: PDH physical interface

Figure 6-28 shows the functional block diagram of the E3/T3 mapping/demapping module.
Figure 6-28 Functional block diagram of the E3/T3 mapping/demapping module
Mapping/demapping module
E3/T3

LPA

LPT

PDH AIS
detector

E3/T3
LPA

LPOH (J1/C2/
B3) insertion
LPOH (J1/C2/
B3) extraction

LPT

LPA: Low order path adaptation

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HPA

HPT

STM-1

TU-AIS/TULOP detector

HPA

HPT

STM-1

LPT: Low order path termination

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HPA: High order path adaptation

HPT: High order path termination

The functional modules are described as follows:

PPI Module
The PPI module consists of LIUs and provides the inloop and outloop functions. The PPI module
performs the following functions:
l

Encodes and decodes signals.

Restores the data signal and the clock signal.

Processes the P_LOS alarm.

E3/T3 Mapping/Demapping Module


l

LPA sub-module

The 45 Mbit/s (34 Mbit/s) plesiochronous stream is inserted in a C3 container to be adapted


so that the stream can be transported to the synchronous network.

LPT sub-module

The virtual container (VC-3) is formatted. The VC-3 is structured so that its octets are
distributed within a 125 us interval (for example, one STM1 period), and consists of the
VC-3 container and POH. The POH contains nine octets equally distributed within the
frame bytes for VC-3, namely, J1, B3, C2, G1, F2, H4, F3, K3, and N1.

HPA sub-module

The HPA sub-module generates and processes the channel-level TU-PTR. In the receive
direction, the signals are split into VC-3s, which are located and isolated in TU-3s. The
TU-PTR is processed. In the transmit direction, VC-3s are located precisely and added with
the TU-PTR. Three TUG-3s are multiplexed into a VC-4 by bytes interleaving. The
sequence is as follows: TU-3->TUG3->VC-4

HPT sub-module

The virtual container (VC-4) is formatted. The VC-4 is structured so that its octets are
distributed within a 125 us interval (for example, one STM1 period), and consists of the
C4 container and POH.

MST sub-module and RST sub-module

These sub-modules are required to create a proprietary STM1 signal so that the interface
converting module can be connected.

Interface Converting Module


The interface converting module converts the 622 Mbit/s LVDS bus of the SDH system into the
parallel bus. The high-rate backplane interface is connected to the low-rate interface chip of the
transmit system through the interface converting module.

Logic and Control Module

6-56

Manages and configures the other modules of the board.

Performs inter-board communication through the internal Ethernet interface.


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Traces the clock signal from the active and standby cross-connect units.

Selects the clock signal and frame header signal from the active and standby cross-connect
units.

Controls the indicators on the board.

DC/DC Converter
It converts the 48/60 V power supply into the DC voltages that the modules of the board
require.

6.7.4 Front Panel


The front panel of the PQ3 has indicators.

Diagram of the Front Panel


Figure 6-29 shows the appearance of the front panel of the PQ3.
Figure 6-29 Front panel of the PQ3

PQ3
STAT
ACT
PROG
SRV

PQ3

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Indicators
The front panel of the board has the following indicators:
l

Board hardware status indicator (STAT) two colors (red and green)

Service activation status indicator (ACT) one color (green)

Board software status indicator (PROG) two colors (red and green)

Service alarm indicator (SRV) three colors (red, green, and yellow)

For the meanings of the status of the indicators, see A Indicators.

Interfaces
The front panel of the PQ3 does not have an interface.
The D34S provides E3/T3 interfaces for the PQ3. For details, see the topic that describes the
D34S.

6.7.5 Valid Slots


The PQ3 can be installed in slots 37 and 1216, and must be used with the D34S.
Table 6-26 lists the slots valid for the PQ3 and the corresponding slots for the D34S.
Table 6-26 Slots valid for the PQ3 and the corresponding slots for the D34S
Slot Valid for the PQ3

Corresponding Slot for the D34S

Slot 3

Slots 21 and 22

Slot 4

Slots 23 and 24

Slot 5

Slots 25 and 26

Slot 6

Slots 27 and 28

Slot 7

Slots 29 and 30

Slot 12

Slots 31 and 32

Slot 13

Slots 33 and 34

Slot 14

Slots 35 and 36

Slot 15

Slots 37 and 38

Slot 16

Slots 39 and 40

6.7.6 Board Protection


The PQ3 supports the 1:N TPS protection.
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Protection Principle
The PQ3 boards can be configured into two 1:N (N3) TPS protection groups when the PQ3
boards work with two D34S boards and two TSB8 boards. Figure 6-30 shows the TPS protection
provided by the PQ3.
Figure 6-30 TPS protection provided by the PQ3
12xE3/T3 12xE3/T3 12xE3/T3 12xE3/T3 12xE3/T3 12xE3/T3

TSB8

TSB8

3 2

D34S

D34S

D34S

D34S

Sw itching
control
D34S signal

D34S

Crossconnect
and timing
board
Slot 9/10

Protection

Working

PQ3

PQ3

Slot 3

Slot 4

Working
PQ3
Failed
Slot 5

Working
PQ3

Slot 6

Normal state
When each working board functions normally, the traffic signal is directly transmitted to
the PQ3 through position 1 of the control switch on the D34S.

Switching state
When a working board detects a failure and requires the switching operation, the control
switch of the corresponding D34S switches from position 1 to position 2. At the same time,
the control switch of the TSB8 switches to the corresponding position so that the protection
board can protect the failed working board.

Hardware Configuration
NOTE

When you configure the N2PQ3 as the TPS protection board, two TSB8 boards are required.

Table 6-27 shows the slot configuration for the 1:3 TPS protection of the PQ3.

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Table 6-27 Slot configuration for the 1:3 TPS protection of the PQ3
Working
Board

Protection Board

Slot Configuration

PQ3 (E3)

PQ3 (E3)

PQ3 (T3)

PQ3 (T3)

Figure 6-31 shows the slot configuration for


the 1:3 TPS protection of the PQ3.

Figure 6-31 Slot configuration for the two 1:3 TPS protection groups of the PQ3

S
L
O
T
29

FAN

S
L
O
T
32

S S S S
L L L L
O O O O
T T T T
33 34 35 36

S
L
O
T
37

S
L
O
T
38

S
L
O
T
39

S
L
O
T
40

FAN

S
L
O
T
10

S S S S S S
L
L L L L
L
O O O O O O
T T T T T T
11 12 13 14 15 16

SLOT 43 EOW

S
L
O
T
9

SLOT 42 AUX

Protection 2

Working 2

Working 1

S
L
O
T
8

Working 2

Working 1

S
L
O
T
7

Working 2

S
L
O
T
6

FAN

CXL

S
L
O
T
5

CXL

S
L
O
T
4

Working 1

SLOT 41 PIU

S
L
O
T
3

Protection 1

SLOT 1 PIU

S
L
O
T
2

S S
L L
O O
T T
30 31

TSB8

S
L
O
T
28

TSB8

D34S
D34S

S
L
O
T
27

D34S

TSB8

S S
L L
O O
T T
25 26

D34S
D34S
D34S

TSB8

S
L
O
T
24

D34S

S
L
O
T
23

D34S

S
L
O
T
22

D34S
D34S
D34S
D34S

S
L
O
T
21

Fiber routing area

In Figure 6-31, the board in slot 3 protects the boards in slots 46. The board in slot 16 protects
the boards in slots 1315.
Table 6-28 lists the slots for the PQ3, D34S, and TSB8.
Table 6-28 Slots for the PQ3, D34S, and TSB8

6-60

Board

Protection Group 1

Protection Group 2

PQ3 (working board)

Slots 46

Slots 1315

PQ3 (protection board)

Slot 3

Slot 16

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Board

Protection Group 1

Protection Group 2

TSB8

Slots 21 and 22

Slots 39 and 40

D34S

Slots 2328

Slots 3338

6.7.7 Parameter Settings


You can set the parameters for the PQ3 by using the T2000.
You can set the following parameters for the PQ3 by using the T2000:
l

J1 byte

C2 byte

Tributary loopback

Service loading indication

Path service type

For the description of each parameter, see F Parameter Settings.

6.7.8 Technical Specifications


The technical specifications of the PQ3 include the parameters specified for electrical interfaces,
mechanical specifications, and power consumption.

Parameters Specified for Electrical Interfaces


The D34S provides electrical interfaces for the PQ3. For the parameters specified for the
electrical interfaces, see D34S.

Mechanical Specifications
The mechanical specifications of the PQ3 are as follows:
l

Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)

Weight (kg): 0.9

Power Consumption
The maximum power consumption of the PQ3 at room temperature (25C) is 13 W.

6.8 DX1
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the DX1 (DDN service accessing and converging board).
6.8.1 Version Description
The DX1 is available in one functional version, namely, N1.
6.8.2 Functions and Features
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The DX1 cross-connects 48xE1 signals at the 64 kbit/s level on the system side.
6.8.3 Working Principle and Signal Flow
The DX1 consists of the interface and frame processing module, encoding/decoding module,
timeslot cross-connect module, framing/deframing module, mapping/demapping module, logic
and control module, and power module.
6.8.4 Front Panel
The front panel of the DX1 has indicators.
6.8.5 Valid Slots
The DX1 can be installed in slots 27 and 1216, and must be used with the DM12.
6.8.6 Feature Code
The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the DX1 indicates the type of interface impedance.
6.8.7 Board Protection
The DX1 supports the 1:N TPS protection.
6.8.8 Parameter Settings
You can set the parameters for the DX1 by using the T2000.
6.8.9 Technical Specifications
The technical specifications of the DX1 include the parameters specified for electrical interfaces,
mechanical specifications, and power consumption.

6.8.1 Version Description


The DX1 is available in one functional version, namely, N1.

6.8.2 Functions and Features


The DX1 cross-connects 48xE1 signals at the 64 kbit/s level on the system side.
Table 6-29 provides the functions and features of the DX1.
Table 6-29 Functions and features of the DX1

6-62

Function
and
Feature

DX1

Basic
functions

Processes eight channels of Nx64 kbit/s services and eight channels of


framed E1 services.

Cross-connects 48 channels of Nx64 kbit/s signals on the system side.

Working
with the
interface
board

Accesses eight channels of Nx64 kbit/s and eight channels of framed E1


services and realizes the 1:N TPS protection when working with the DM12.

One DX1 board needs to work with two DM12 boards.

Alarms and
performance
events

Reports various alarms and performance events, which facilitates the


management and maintenance of the equipment.

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Function
and
Feature

DX1

Connectors

The DB28 connectors and DB44 connectors are present on the front panel of
the DM12. The DB28 connector is used for the Nx64 kbit/s signals, and the
DB44 connector is used for the framed E1 signals.

Loopback
function

Supports inloops and outloops.

PRBS selftest function

Supports this function.

6.8.3 Working Principle and Signal Flow


The DX1 consists of the interface and frame processing module, encoding/decoding module,
timeslot cross-connect module, framing/deframing module, mapping/demapping module, logic
and control module, and power module.
Figure 6-32 shows the functional block diagram of the DX1.
Figure 6-32 Functional block diagram of the DX1
Backplane

DM12
Framed E1
interface
module

8xframed E1

4xNx64 kbit/s

Nx64 kbit/s
interface
module

4xNx64 kbit/s

DM12
Nx64 kbit/s
interface
module

Power

Backplane
DX1
Framed E1
encoding/decoding
and frame
processing module
Nx64k bit/s
interface and
frame
processing
module

64 kbit/s
timeslot
crossconnect
module

Mapping/
Demapping
module for 48
channels of
signals

Framing/
Deframing
module

Logic and control


module

Power
Framed E1
interface
module

+3.3 V
Power
module

Power
module

Cross-connect
unit

SCC unit

Fuse

-48 V/-60 V
-48 V/-60 V

In the Transmit Direction


The mapping/demapping module demaps the VC-4 signals sent from the SDH cross-connect
unit and sends the demapped signals to the framing/deframing module. Then, the framing/
deframing module converts the signals into the framed E1 signals and sends the framed E1
signals to the timeslot cross-connect module. Finally, the timeslot cross-connect module crossIssue 02 (2009-07-30)

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connects and grooms the signals at the 64 kbit/s granularity, and transmits the signals that need
to be dropped on the local NE to the interface module.

In the Receive Direction


The DX1 accesses eight channels of framed E1 signals from the framed E1 interface module of
the DM12 and eight channels of Nx64 kbit/s signals from the Nx64 kbit/s interface module of
the DM12. In addition, the DX1 restores the data signal and clock signal.
In the case of the framed E1 signals, the DX1 decodes the signals and processes the frames. In
the case of the Nx64 kbit/s signals, the DX1 converts the signals and processes the frames. Then,
the DX1 transmits the signals to the 64 kbit/s timeslot cross-connect module. The timeslot crossconnect module cross-connects and grooms the signals at the 64 kbit/s granularity, and transmits
the signals to the framing/deframing module. Finally, the framing/deframing module maps the
signals into VC-4s and transmits the signals to the SDH cross-connect unit.

Logic and Control Module


The logic and control module performs the board communication, board control, and service
configuration functions. In addition, the logic and control module traces and selects the clock
signals and frame header signals sent from the active and standby cross-connect boards.

Power Module
The power module provides all the modules of the DX1 with the required DC voltages.

6.8.4 Front Panel


The front panel of the DX1 has indicators.

Diagram of the Front Panel


Figure 6-33 shows the appearance of the front panel of the DX1.

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Figure 6-33 Front panel of the DX1

DX1
STAT
ACT
PROG
SRV

DX1

Indicators
The front panel of the board has the following indicators:
l

Board hardware status indicator (STAT) two colors (red and green)

Service activation status indicator (ACT) one color (green)

Board software status indicator (PROG) two colors (red and green)

Service alarm indicator (SRV) three colors (red, green, and yellow)

For the meanings of the status of the indicators, see A Indicators.

Interfaces
The front panel of the DX1 does not have an interface.
The DX1 needs to work with the DM12 to receive and transmit the framed E1 signals and Nx64
kbit/s signals. For details, see the topic that describes the DM12.
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6.8.5 Valid Slots


The DX1 can be installed in slots 27 and 1216, and must be used with the DM12.
Table 6-30 lists the slots valid for the DX1 and the corresponding slots for the DM12.
Table 6-30 Slots valid for the DX1 and the corresponding slots for the DM12
Slot Valid for the DX1

Corresponding Slot for the DM12

Slot 3

Slots 21 and 22

Slot 4

Slots 23 and 24

Slot 5

Slots 25 and 26

Slot 6

Slots 27 and 28

Slot 7

Slots 29 and 30

Slot 12

Slots 31 and 32

Slot 13

Slots 33 and 34

Slot 14

Slots 35 and 36

Slot 15

Slots 37 and 38

slot 16

Slots 39 and 40

NOTE

Slot 2 can house a protection board for the TPS protection. The board in slot 2 protects the boards in
slots 37 and 1216.

One DX1 needs to work with two DM12 boards to access eight channels of Nx64 kbit/s signals. The
DM12 in the slot with a smaller slot number is used to access eight channels of framed E1 signals and
four channels of Nx64 kbit/s signals. The DM12 in the slot with a larger slot number is used to access
four channels of Nx64 kbit/s signals.

6.8.6 Feature Code


The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the DX1 indicates the type of interface impedance.
Table 6-31 provides the relationship between the feature code of the DX1 and the type of
interface impedance.
Table 6-31 Relationship between the feature code of the DX1 and the type of interface
impedance

6-66

Board

Feature Code

Type of Interface Impedance

SSN1DX1A01

A01

75-ohm

SSN1DX1B01

B01

120-ohm

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6.8.7 Board Protection


The DX1 supports the 1:N TPS protection.

Protection Principle
The DX1 can be configured into one 1:N (N8) TPS protection group when the DX1 works
with the DM12. Figure 6-34 shows the TPS protection provided by the DX1.
Figure 6-34 TPS protection provided by the DX1

E1protection bus

S
L
O
T
2
1

S
L
O
T
2
2

S
L
O
T
2
3

S
L
O
T
2
4

S
L
O
T
2
5

S
L
O
T
2
6

S
L
O
T
2
7

S
L
O
T
2
8

S
L
O
T
2
9

S
L
O
T
3
0

S
L
O
T
3
1

S
L
O
T
3
2

S
L
O
T
3
3

S
L
O
T
3
4

S
L
O
T
3
5

S
L
O
T
3
6

S
L
O
T
3
7

S
L
O
T
3
8

S
L
O
T
3
9

S
L
O
T
4
0

DM12
DM12

DM12
DM12

DM12
DM12

DM12
DM12

DM12
DM12

DM12
DM12

DM12
DM12

DM12
DM12

DM12
DM12

DM12
DM12

E1 service bus
S
L
O
T
2

S
L
O
T
3

S
L
O
T
4

S
L
O
T
5

S
L
O
T
6

S
L
O
T
7

S
L
O
T
1
2

S
L
O
T
1
3

S
L
O
T
1
4

S
L
O
T
1
5

S
L
O
T
1
6

Working

Working

Working

Working

Working

Working

Working

Working

Working

Working

Protection

Failed

Detecting a
board fault
Cross-connect and timing board

TPS
control
bus

NOTE

The DX1 supports only one 1:8 TPS protection group. The DX1 board in slot 2 can protect the DX1 boards
that are inserted in any eight slots of slots 37, and 1216.

When the cross-connect and timing board detects that a working DX1 is faulty, the cross-connect
and timing board issues a service switching command to control the access board to switch the
services from the faulty DX1 to the protection DX1, which realizes the protection of the services.

Hardware Configuration
Figure 6-35 shows the slot configuration for the 1:8 TPS protection of the DX1.

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Figure 6-35 Slot configuration for the 1:8 TPS protection of the DX1

S
L
O
T
21

S
L
O
T
22

S
L
O
T
23

S
L
O
T
24

S S
L L
O O
T T
25 26

S
L
O
T
27

S
L
O
T
28

S
L
O
T
29

S S S S
L L L L
O O O O
T T T T
33 34 35 36

S
L
O
T
39

S
L
O
T
40

DM12

S S
L L
O O
T T
13 14

S S
L L
O O
T T
15 16

SLOT 42 AUX

Working

Working

Working

S S
L L
O O
T T
11 12

Working

CXL

S
L
O
T
10

SLOT 43 EOW

S
L
O
T
9

Working

S
L
O
T
8

S
L
O
T
38

FAN

CXL

S
L
O
T
7

S
L
O
T
37

DM12
DM12
DM12
DM12

DM12

DM12

DM12

DM12

DM12

S
L
O
T
6

Working

S S
L L
O O
T T
4 5

Working
Working

Working
Protection

SLOT 41 PIU

S
L
O
T
3

S
L
O
T
32

FAN

Working

SLOT 1 PIU

S
L
O
T
2

DM12

DM12
DM12
DM12
DM12

DM12
DM12
DM12

DM12
DM12

FAN

S S
L L
O O
T T
30 31

Cable routing area

In Figure 6-35, the board in slot 2 protects the boards in slots 3-7 and 12-16.
Table 6-32 lists the slots for the DX1 and DM12.
Table 6-32 Slots for the DX1 and DM12
Board

Protection Group

DX1 (working board)

Slots 37 and 1216

DX1 (protection board)

Slot 2

DM12

Slots 2140

6.8.8 Parameter Settings


You can set the parameters for the DX1 by using the T2000.
You can set the following parameters for the DX1 by using the T2000:

6-68

J2 byte

Tributary loopback
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Hardware Description
l

Service loading indication

Protocol mode of serial ports

DDN clock source management

6 PDH Boards

For the description of each parameter, see F Parameter Settings.

6.8.9 Technical Specifications


The technical specifications of the DX1 include the parameters specified for electrical interfaces,
mechanical specifications, and power consumption.

Parameters Specified for Electrical Interfaces


The DM12 provides electrical interfaces for the DX1. For the parameters specified for the
electrical interfaces, see DM12.

Mechanical Specifications
The mechanical specifications of the DX1 are as follows:
l

Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)

Weight (kg): 1.0

Power Consumption
The maximum power consumption of the DX1 at room temperature (25C) is 15 W.

6.9 DXA
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the DXA (DDN service converging and processing board).
6.9.1 Version Description
The DXA is available in one functional version, namely, N1.
6.9.2 Functions and Features
The DXA cross-connects 63xE1 signals at the 64 kbit/s level on the system side.
6.9.3 Working Principle and Signal Flow
The DXA consists of the timeslot cross-connect module, framing/deframing module, mapping/
demapping module, logic and control module, and power module.
6.9.4 Front Panel
The front panel of the DXA has indicators.
6.9.5 Valid Slots
The DXA can be installed in slots 28 and 1116 in the subrack.
6.9.6 Parameter Settings
You can set the parameters for the DXA by using the T2000.
6.9.7 Technical Specifications
The technical specifications of the DXA include the mechanical specifications and power
consumption.
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6.9.1 Version Description


The DXA is available in one functional version, namely, N1.

6.9.2 Functions and Features


The DXA cross-connects 63xE1 signals at the 64 kbit/s level on the system side.
Table 6-33 provides the functions and features of the DXA.
Table 6-33 Functions and features of the DXA
Function and
Feature

DXA

Basic functions

Cross-connects 63 channels of framed E1 signals.

Alarms and
performance events

Reports various alarms and performance events, which facilitates the


management and maintenance of the equipment.

Loopback function

Supports inloops and outloops.

PRBS self-test
function

Does not support this function.

6.9.3 Working Principle and Signal Flow


The DXA consists of the timeslot cross-connect module, framing/deframing module, mapping/
demapping module, logic and control module, and power module.
Figure 6-36 shows the functional block diagram of the DXA.
Figure 6-36 Functional block diagram of the DXA
Backplane

64 kbit/s
timeslot
cross-connect
module

Framing/
Deframing
module

Signal
mapping/
demapping
module

Logic and control


module
+3.3 V
Power
module

6-70

Power
module

Crossconnect unit

SCC unit
Fuse

-48 V/-60 V
-48 V/-60 V

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In the Transmit Direction


The mapping/demapping module demaps the VC-4 signals sent from the SDH cross-connect
unit and sends the demapped signals to the framing/deframing module. Then, the framing/
deframing module converts the signals into the framed E1 signals and sends the framed E1
signals to the timeslot cross-connect module. Finally, the timeslot cross-connect module crossconnects and grooms the signals at the 64 kbit/s granularity.

In the Receive Direction


The timeslot cross-connect module cross-connects and grooms the signals at the 64 kbit/s
granularity, and transmits the signals to the framing/deframing module. Then, the framing/
deframing module maps the signals into VC-4s and transmits the signals to the SDH crossconnect unit.

Logic and Control Module


The logic and control module performs the board communication, board control, and service
configuration functions. In addition, the logic and control module traces and selects the clock
signals and frame header signals sent from the active and standby cross-connect boards.

Power Module
The power module provides all the modules of the DX1 with the required DC voltages.

6.9.4 Front Panel


The front panel of the DXA has indicators.

Diagram of the Front Panel


Figure 6-37 shows the appearance of the front panel of the DXA.

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Figure 6-37 Front panel of the DXA

DXA
STAT
ACT
PROG
SRV

DXA

Indicators
The front panel of the board has the following indicators:
l

Board hardware status indicator (STAT) two colors (red and green)

Service activation status indicator (ACT) one color (green)

Board software status indicator (PROG) two colors (red and green)

Service alarm indicator (SRV) three colors (red, green, and yellow)

For the meanings of the status of the indicators, see A Indicators.

Interfaces
The front panel of the DXA does not have an interface.
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6.9.5 Valid Slots


The DXA can be installed in slots 28 and 1116 in the subrack.

6.9.6 Parameter Settings


You can set the parameters for the DXA by using the T2000.
You can set the following parameters for the DXA by using the T2000:
l

J2 byte

Tributary loopback

Service loading indication

Protocol mode of serial ports

DDN clock source management

For the description of each parameter, see F Parameter Settings.

6.9.7 Technical Specifications


The technical specifications of the DXA include the mechanical specifications and power
consumption.

Mechanical Specifications
The mechanical specifications of the DXA are as follows:
l

Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)

Weight (kg): 0.8

Power Consumption
The maximum power consumption of the DXA at room temperature (25C) is 10 W.

6.10 SPQ4
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the SPQ4 (4xE4/STM-1 electrical processing board).
6.10.1 Version Description
The SPQ4 is available in two functional versions, namely, N1 and N2. The difference between
the two versions is with regard to their functions. The N1SPQ4 is no longer manufactured.
6.10.2 Functions and Features
The SPQ4 processes 4xE4/STM-1 electrical signals, processes overhead bytes, reports alarms
and performance events, provides maintenance features, and supports protection schemes.
6.10.3 Working Principle and Signal Flow
The SPQ4 consists of the PPI/SPI module, 140M mapping/demapping module, SDH overhead
processing module, interface converting module, logic and control module, DC/DC converter,
and other modules.
6.10.4 Front Panel
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The front panel of the SPQ4 has indicators.


6.10.5 Valid Slots
The SPQ4 can be installed in slots 37 and 1216, and must be used with the MU04.
6.10.6 Board Protection
The SPQ4 supports the 1:N TPS protection.
6.10.7 Parameter Settings
You can set the parameters for the SPQ4 by using the T2000.
6.10.8 Technical Specifications
The technical specifications of the SPQ4 include the parameters specified for electrical
interfaces, mechanical specifications, and power consumption.

6.10.1 Version Description


The SPQ4 is available in two functional versions, namely, N1 and N2. The difference between
the two versions is with regard to their functions. The N1SPQ4 is no longer manufactured.
Table 6-34 describes the versions of the SPQ4.
Table 6-34 Versions of the SPQ4
Item

Description

Functional versions

The SPQ4 is available in two functional versions, namely, N1 and


N2.

Differences

The equipment of the V100R001 and V100R002 versions supports


the N1SPQ4. The equipment of the V100R003 and later versions
supports the N2SPQ2.

Substitution

The N1SPQ4 can be replaced with the N2SPQ4. When the N1SPQ4
is replaced with the N2SPQ4, the NE software needs to be upgraded.

6.10.2 Functions and Features


The SPQ4 processes 4xE4/STM-1 electrical signals, processes overhead bytes, reports alarms
and performance events, provides maintenance features, and supports protection schemes.
Table 6-35 provides the functions and features of the SPQ4.
Table 6-35 Functions and features of the SPQ4

6-74

Function and
Feature

SPQ4

Basic functions

Processes 4xSTM-1/E4 signals.

Service
processing

Accesses and processes 4xE4/STM-1 electrical signals. The E4 signals


and STM-1 signals are compatible on each channel. Supports the VC-12
services, VC-3 services, and VC-4 services.
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Function and
Feature

SPQ4

Overhead
processing

Processes the section overheads of the STM-1 signals, such as B1, B2,
K1, K2, M1, F1, and D1D12.

Supports the transparent transmission and termination of the path


overhead bytes including J1, B3, C2, G1, and H4.

Supports the setting and query of the J0, J1, and C2 bytes.

Alarms and
performance
events

Reports various alarms and performance events, which facilitates the


management and maintenance of the equipment.

Protection
schemes

Supports the TPS protection when working with the interface board
and the switching and bridging board.

Supports the two-fiber ring MSP, linear MSP, and SNCP.

Supports inloops and outloops at optical interfaces.

Supports warm resets and cold resets. The warm reset does not affect
services.

Supports the query of the manufacturing information of the board.

Supports the in-service loading of the FPGA.

Supports the upgrade of the board software without affecting services.

Maintenance
features

6.10.3 Working Principle and Signal Flow


The SPQ4 consists of the PPI/SPI module, 140M mapping/demapping module, SDH overhead
processing module, interface converting module, logic and control module, DC/DC converter,
and other modules.
Figure 6-38 shows the functional block diagram of the SPQ4. Figure 6-39 shows the functional
block diagram of the 140M mapping/demapping module. Figure 6-40 shows the functional
block diagram of the SDH overhead processing module.

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Figure 6-38 Functional block diagram of the SPQ4


155
MHz
PLL

34 MHz
OSC

LIU

LIU

PPI/SPI

E4/STM-1

4x139
Mbit/s
4x155
Mbit/s

140M mapping/
demapping
SDH overhead
processing module

Reference clock

4x155
Mbit/s

Highspeed bus

Interface
converting
module

4x155
Mbit/s

Highspeed bus

DCC
K1 and K2
EN 140M/155M
LOS
Outloop/Inloop control

+3.3 V
DC/DC
converter

Communication

DC/DC
converter

Cross-connect unit A

Cross-connect unit B

SCC unit
Cross-connect unit
Frame header

Logic and control


module

Cross-connect unit

Fuse

Cross-connect unit
SCC unit
-48 V/-60 V
-48 V/-60 V

Figure 6-39 Functional block diagram of the 140M mapping/demapping module


Mapping/demapping module
139 Mbit/s

155 Mbit/s
LPA

PDH AIS E4 AIS


detector insertion

139 Mbit/s

6-76

SIPO

HPT

PG

J1/C2/B3

E4 AIS
insertion

LPA

HPT

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RST

MST

RST

155 Mbit/s

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Figure 6-40 Functional block diagram of the SDH overhead processing module
SDH overhead processing module
K1 and K2 insertion/
extraction

Cross-connect unit

155 Mbit/s

155 Mbit/s

155 Mbit/s
RST

MST

MSA

HPT
155 Mbit/s

DCC

SCC unit

The functional modules of the E4/STM-1 electrical interface units are described as follows:

PPI/SPI Module
The PPI module consists of LIUs and provides the inloop and outloop functions. The PPI module
performs the following functions:
l

Encodes and decodes signals.

Restores the data signal and the clock signal.

Processes the PDH LOS signals.

The SPI module consists of LIUs and provides the inloop and outloop functions. The SPI module
performs the following functions:
l

Encodes and decodes signals.

Restores the data signal and the clock signal.

Processes the R_LOS signals.

SDH Overhead Processing Module and 140M Mapping/Demapping Module


SDH Overhead Processing Module (155Mbit/s SDH Signals)
The SDH overhead processing module performs the functions that are required to manage 155
Mbit/s SDH signals.

RST Sub-Module
l

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In the receive direction, the RST sub-module detects the frame alignment bytes (A1 and
A2), restores the regenerator section trace byte (J0), detects a J0 mismatch, and counts
BIP-8 errored blocks.
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l

In the transmit direction, the RST sub-module inserts the frame alignment bytes, inserts
the J0 byte, and performs BIP-8 calculation and insertion.

MST Sub-Module
l

In the receive direction, the MST sub-module counts BIP-24 errored blocks, restores the
MS_REI, and detects the MS_RDI and MS_AIS.

In the transmit direction, the MST sub-module performs BIP-24 calculation and insertion
and inserts the MS_REI, MS_RDI, and MS_AIS.

The MST sub-module extracts or inserts the K1 byte and K2 byte.

MSA Sub-Module
l

In the receive direction, the MSA sub-module interprets the AU-4 pointer, detects the LOP
and AIS, and performs pointer justifications.

In the transmit direction, the MSA sub-module assembles the AUG and generates the AU-4
pointer and the AU_AIS.

HPT Sub-Module
l

Terminates the overheads.

Restores the J1 path trace message.

Restores the REI information.

Detects the HP_RDI (monitors the status of the path).

Detects the UNEQ and AIS (monitors the signal label).

Counts the VC-4 BIP-8 errored blocks.

140M Mapping/Demapping Module (140 Mbit/s PDH Signals)


The 140M mapping/demapping module performs the functions that are required to manage 140
Mbit/s PDH signals.

LPA Sub-Module
The 140 Mbit/s plesiochronous stream is inserted in a C4 container to be adapted so that the
stream can be transported to the synchronous network. The PDH AIS is monitored and the E4
AIS in inserted.

HPT Sub-Module
The virtual container (VC-4) is formatted. The VC-4 is structured so that its octets are distributed
within a 125 us interval (for example, one STM1 period), and consists of the C4 container and
POH. The POH contains nine octets equally distributed within the frame. The following
overhead bytes can be extracted: J1, B3. C2, G1, F2, H4, F3, K3, and N1. The E4 AIS can be
inserted in the downstream direction.
Pointer generator (PG)
A fixed pointer value is inserted in the SOH to structure the AU-4 signal.
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MST Sub-Module and RST Sub-Module


These sub-modules are required to create a proprietary STM1 signal so that the interface
converting module can be connected. In the receive direction, these sub-modules detect the frame
alignment bytes (A1 and A2).

Interface Converting Module


The interface converting module converts the 622 Mbit/s LVDS bus of the SDH system into the
parallel bus. The high-rate backplane interface is connected to the low-rate interface chip of the
transmit system through the interface converting module.

Logic and Control Module


l

Manages and configures the other modules of the board.

Performs inter-board communication through the internal Ethernet interface.

Traces the clock signal from the active and standby cross-connect units.

Passes the orderwire and ECC bytes through an ADM that consists of two paired slots when
the GSCC is not online.

Selects the clock signal and frame header signal from the active and standby cross-connect
units.

Controls the indicators on the board.

DC/DC Converter
It converts the 48/60 V power supply into the DC voltages that the modules of the board
require.

6.10.4 Front Panel


The front panel of the SPQ4 has indicators.

Diagram of the Front Panel


Figure 6-41 shows the appearance of the front panel of the SPQ4.

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Figure 6-41 Front panel of the SPQ4

SPQ4
STAT
ACT
PROG
SRV

SPQ4

Indicators
The front panel of the board has the following indicators:
l

Board hardware status indicator (STAT) two colors (red and green)

Service activation status indicator (ACT) one color (green)

Board software status indicator (PROG) two colors (red and green)

Service alarm indicator (SRV) three colors (red, green, and yellow)

For the meanings of the status of the indicators, see A Indicators.

Interfaces
The front panel of the SPQ4 does not have an interface. Hence, the SPQ4 needs to work with
the MU04 to receive and transmit the E4/STM-1 signals. For details, see the topic that describes
the MU04.
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6.10.5 Valid Slots


The SPQ4 can be installed in slots 37 and 1216, and must be used with the MU04.
Table 6-36 lists the slots valid for the SPQ4 and the corresponding slots for the MU04.
Table 6-36 Slots valid for the SPQ4 and the corresponding slots for the MU04
Slot Valid for the SPQ4

Corresponding Slot for the MU04

Slot 3

Slot 21

Slot 4

Slot 23

Slot 5

Slot 25

Slot 6

Slot 27

Slot 7

Slot 29

Slot 12

Slot 31

Slot 13

Slot 33

Slot 14

Slot 35

Slot 15

Slot 37

Slot 16

Slot 39

6.10.6 Board Protection


The SPQ4 supports the 1:N TPS protection.

Protection Principle
The SPQ4 can be configured into two 1:N (N3) TPS protection groups when the SPQ4 works
with the MU04 and TSB8/TSB4. Figure 6-42 shows the TPS protection provided by the SPQ4.

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Figure 6-42 TPS protection provided by the SPQ4


4xE4/STM-1

TSB8/
TSB4
3 2

4xE4/STM-1

MU04

4xE4/STM-1

Switching
control
MU04 signal

MU04
1

Crossconnect
and
timing
board
Slot 9/10

Protection
SPQ4

Working
SPQ4

Working
SPQ4

Working
SPQ4

Failed
Slot 3

Slot 4

Slot 5

Slot 6

Normal state
When each working board functions normally, the traffic signal is directly transmitted to
the SPQ4 through position 1 of the control switch on the MU04.

Switching state
When a working board detects a failure and requires the switching operation, the control
switch of the corresponding MU04 switches from position 1 to position 2. At the same
time, the control switch of the TSB8/TSB4 switches to the corresponding position so that
the protection board can protect the failed working board.

Hardware Configuration
Figure 6-43 shows the slot configuration for the 1:3 TPS protection of the SPQ4.

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Figure 6-43 Slot configuration for the two 1:3 TPS protection groups of the SPQ4

S
L
O
T
23

S
L
O
T
24

S
L
O
T
25

S
L
O
T
26

S
L
O
T
27

S
L
O
T
28

S
L
O
T
29

FAN

S
L
O
T
38

S
L
O
T
39

S
L
O
T
40

S S S S
L L L
L
O O O O
T T T T
13 14 15 16

SLOT 43 EOW

S S
L L
O O
T T
11 12

SLOT 42 AUX

Working 2

Protection 2

Working 2

S
L
O
T
10

Working 2

S
L
O
T
9

CXL

S
L
O
T
8

S
L
O
T
37

FAN

CXL

Working 1

Working 1

Working 1

SLOT 41 PIU

S S S S
L L L L
O O O O
T T T T
4 5 6 7

Protection 1

SLOT 1 PIU

S
L
O
T
3

S
L
O
T
36

TSB8/TSB4

S
L
O
T
35

MU04

S S S
L L L
O O O
T T T
32 33 34

MU04

MU04

MU04

TSB8/TSB4

FAN

S
L
O
T
2

S S
L L
O O
T T
30 31

MU04

S
L
O
T
22

MU04

S
L
O
T
21

Cable routing area

In Figure 6-43, the board in slot 3 protects the boards in slots 46. The board in slot 16 protects
the boards in slots 1315.
Table 6-37 lists the slots for the SPQ4, MU04, and TSB8/TSB4.
Table 6-37 Slots for the SPQ4, MU04, and TSB8/TSB4
Board

Protection Group 1

Protection Group 2

SPQ4 (working
board)

Slots 46

Slots 1315

SPQ4 (protection
board)

Slot 3

Slot 16

MU04

Slots 23, 25, and 27

Slots 33, 35, and 37

TSB8/TSB4

Slot 21

Slot 39

6.10.7 Parameter Settings


You can set the parameters for the SPQ4 by using the T2000.
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You can set the following parameters for the SPQ4 by using the T2000:
l

J1 byte

C2 byte

For the description of each parameter, see F Parameter Settings.

6.10.8 Technical Specifications


The technical specifications of the SPQ4 include the parameters specified for electrical
interfaces, mechanical specifications, and power consumption.

Parameters Specified for Electrical Interfaces


The MU04 provides electrical interfaces for the SPQ4. For the parameters specified for the
electrical interfaces, see MU04.

Mechanical Specifications
The mechanical specifications of the SPQ4 are as follows:
l

Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)

Weight (kg): 0.9

Power Consumption
The maximum power consumption of the SPQ4 at room temperature (25C) is 24 W.

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7 Data Boards

Data Boards

About This Chapter


The data boards include the boards for processing FE, GE, ATM, and SAN signals.
7.1 EFT8
This topic describes the version, functions, working principle, valid slots, and technical
specification of the EFT8 (8xFE/16xFE transparent transmission board).
7.2 EFT8A
This topic describes the version, functions, working principle, valid slots, and technical
specification of the EFT8A (8xFE transparent transmission board).
7.3 EGT2
This topic describes the version, functions, working principle, valid slots, and technical
specification of the EGT2 (2xGE transparent transmission board).
7.4 EFS0
This topic describes the version, functions, working principle, valid slots, and technical
specification of the EFS0 (8xFE switching and processing board).
7.5 EFS0A
This topic describes the version, functions, working principle, valid slots, and technical
specification of the EFS0A (16xFE switching and processing board).
7.6 EFS4
This topic describes the version, functions, working principle, valid slots, and technical
specification of the EFS4 (4xFE switching and processing board).
7.7 EGS2
This topic describes the version, functions, working principle, valid slots, and technical
specification of the EGS2 (2xGE switching and processing board).
7.8 EMS2
This topic describes the version, functions, working principle, valid slots, and technical
specification of the EMS2 (2xGE and 16xFE switching and processing board).
7.9 EMS4
This topic describes the version, functions, working principle, valid slots, and technical
specification of the EMS4 (4xGE and 16xFE switching and processing board).
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7.10 EGS4
This topic describes the version, functions, working principle, valid slots, and technical
specification of the EGS4 (4xGE switching and processing board).
7.11 EGR2
This topic describes the version, functions, working principle, valid slots, and technical
specification of the EGR2 (2xGE ring processing board).
7.12 EMR0
This topic describes the version, functions, working principle, valid slots, and technical
specification of the EMR0 (12xFE and 1xGE ring processing board).
7.13 EAS2
This topic describes the version, functions, working principle, valid slots, and technical
specification of the EAS2 (2-port 10xGE Layer 2 switching and processing board).
7.14 ADL4
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the ADL4 (1xSTM-4 ATM service processing board).
7.15 ADQ1
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the ADQ1 (4xSTM-1 ATM service processing board).
7.16 IDL4
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the IDL4 (1xSTM-4 ATM service processing board).
7.17 IDL4A
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the IDL4A (1xSTM-4 ATM service processing board).
7.18 IDQ1
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the IDQ1 (4xSTM-1 ATM service processing board).
7.19 IDQ1A
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the IDQ1A (4xSTM-1 ATM service processing board).

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7.1 EFT8
This topic describes the version, functions, working principle, valid slots, and technical
specification of the EFT8 (8xFE/16xFE transparent transmission board).
7.1.1 Version Description
The EFT8 is available in one functional version, namely, N1.
7.1.2 Functions and Features
The EFT8 supports the transparent transmission of Ethernet services, LCAS function, and test
frames.
7.1.3 Working Principle and Signal Flow
The EFT8 consists of the Ethernet access module, mapping module, interface converting
module, logic and control module, clock module, and power module.
7.1.4 Front Panel
The front panel of the EFT8 has indicators, interfaces, and a bar code.
7.1.5 Valid Slots
The slots valid for the EFT8 vary with the cross-connect capacity of the subrack and whether
the EFT8 works with an interface board.
7.1.6 Parameter Settings
You can set the parameters for the EFT8 by using the T2000.
7.1.7 Technical Specifications
The technical specifications of the EFT8 include the Ethernet performance specifications,
mechanical specifications, and power consumption.

7.1.1 Version Description


The EFT8 is available in one functional version, namely, N1.

7.1.2 Functions and Features


The EFT8 supports the transparent transmission of Ethernet services, LCAS function, and test
frames.
Table 7-1 provides the functions and features of the EFT8.
Table 7-1 Functions and features of the EFT8

Issue 02 (2009-07-30)

Function and
Feature

EFT8

Basic functions

Transmits 8xFE or 16xFE services.

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Function and
Feature

EFT8

Functions when
being used with the
interface board

Accesses 8 Ethernet signals through the electrical interface


independently.

Accesses 16 Ethernet signals through the electrical interface when


the EFT8 is used with the ETF8.

Accesses 8 Ethernet optical signals and 8 Ethernet electrical signals


when the EFT8 is used with the EFF8.

Supports 10BASE-T/100BASE-TX signals when the EFT8 is used


with the ETF8.

Supports 100BASE-FX/100BASE-TX signals when the EFT8 is


used with the EFF8. The optical interfaces comply with IEEE
802.3u.

Supports Ethernet II, IEEE 802.3, and IEEE 802.1q TAG formats.

Supports the frame with a length ranging from 64 bytes to 9600


bytes.

Supports the Jumbo frame with a length less than 9600 bytes.

Specifications of the
optical interface

Format of service
frames

Maximum uplink
bandwidth

The maximum uplink bandwidth is 1.25 Gbit/s. The EFT8 can adapt
to the bandwidth of the slot.

VCTRUNKs

Number of supported VCTRUNKs: 16


Configuration principles are as follows:

7-4

A VCTRUNK can be bound with a maximum of three VC-3s or a


maximum of 63 VC-12s.

A VCTRUNK can be bound with the VC-12 path or VC-3 path at


one time. A VCTRUNK should not be bound with VC-12 and VC-3
paths at the same time.

Different VCTRUNKs can be bound with paths at different levels.

VCTRUNK 1VCTRUNK 8 can be bound with VC-3s 112 or


VC-12s 163.

VCTRUNK 9VCTRUNK 16 can be bound with VC-3s 1324 or


VC-12s 64126.

A VCTRUNK cannot be bound with VC-12s numbered 163 and


VC-3s numbered 1012 at the same time. In addition, a VCTRUNK
cannot be bound with VC-12s numbered 64126 and VC-3s
numbered 2224 at the same time.

Encapsulation
format

Supports the HDLC, LAPS, and GFP-F protocols.

Mapping
granularities

Supports VC-12, VC-3, VC-12-Xv (X63), and VC-3-Xv (X3)


granularities.

Ethernet service type

Supports EPL services.

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Function and
Feature

EFT8

MTU

Supports the setting of the packet length, which ranges from 1518
bytes to 1535 bytes. After the setting becomes valid, the length of the
packets that enter or exit the IP ports is limited.

MPLS

Does not support the MPLS.

VLAN

Supports VLAN transparent transmission.

LPT

Supports the LPT in GFP bearer mode.

CAR

Does not support the CAR.

Flow control
function

Supports the FE port-based flow control function that complies with


IEEE 802.3x.

LCAS function

Dynamically increases or decreases the bandwidth and protects the


bandwidth in compliance with ITU-T G.7042.

ETH-OAM function

Does not support the ETH-OAM function.

Test frames

Receives and transmits GFP test frames.

Loopback function

Supports inloops on Ethernet ports (at the PHY layer or MAC


layer).

Supports inloops and outloops at the VC-3 level.

Ethernet
performance
monitoring

Supports Ethernet performance monitoring at the port level.

Alarms and
performance events

Reports various alarms and performance events, which facilitates the


management and maintenance of the equipment.

7.1.3 Working Principle and Signal Flow


The EFT8 consists of the Ethernet access module, mapping module, interface converting
module, logic and control module, clock module, and power module.
Figure 7-1 shows the functional block diagram of the EFT8 by describing how to process 1xFE
signals.

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Figure 7-1 Functional block diagram of the EFT8


Backplane

FE

Ethernet
access
module

Cross-connect unit

ENCP

Interface
converting
module

VCP
DENCP

Cross-connect unit

Mapping module
Laser
shutdown

LOS

Logic and
control module

Communication
Reference clock and frame header

+3.3 V
Clock module
50 77 125 155
MHz MHz MHz MHz

Power
module

ENCP: data encapsulation module

Power
module

SCC unit
SCC unit
Fuse

-48 V/-60 V
-48 V/-60 V

DENCP: decapsulation module

VCP: virtual concatenation processing module

Ethernet Access Module


In the receive direction, the optical signals from Ethernet equipment such as switches or routers
are converted into electrical signals. If the signals are accessed through electrical interfaces, O/
E conversion is not required. At the PHY layer, the electrical signals are decoded and the
ETH_LOS alarm is detected. The electrical signals are converted from serial signals into parallel
signals and then sent to the network processor module.
In the transmit direction, the parallel signals are converted into serial signals. At the PHY layer,
signals are encoded and converted from electrical signals to optical signals.

Mapping Module
The mapping module performs encapsulation and mapping functions.
In the upstream direction, this module first encapsulates Ethernet signals in LAPS, HDLC, or
GFP format. The concatenation is performed. Then, the Ethernet signals are converted into SDH
signals.
In the downstream direction, SDH signals are demapped. The delay of virtual concatenation is
compensated. After aligning, packets are decapsulated according to the encapsulation format.
The decapsulated data is finally transmitted to the network processor module in packets.

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Interface Converting Module


The interface converting module converts the 622 Mbit/s LVDS bus of the SDH system into the
parallel bus. The high-rate backplane interface is connected to the low-rate interface chip of the
transmit system through the interface converting module.

Logic and Control Module


The logic and control module consists of the CPU, register, oscillator, Ethernet port, and HDLC
controller. This module is connected to external circuits through the bus. The logic and control
module performs the following functions:
l

Manages and configures other modules of the board.

Implements inter-board communication through the internal Ethernet interface.

The control module also contains basic logic units. This module performs the following
functions:
l

Writes and reads the register.

Provides interfaces for the CPU.

Checks and selects the clock.

Performs phase discrimination and frequency division on the clock.

Checks the in-service state of the cross-connect, SCC, and line boards.

Controls the shutting down of the optical module.

Implements communication.

Controls indicators.

Clock Module
The clock module traces the system reference clock and generates the required working clock
for each chip. The frequency of the clock can be 50 MHz, 77 MHz, 125 MHz, or 155 MHz.

Power Module
It converts the 48 V/60 V power supply into the DC voltages that the modules of the board
require.

7.1.4 Front Panel


The front panel of the EFT8 has indicators, interfaces, and a bar code.

Diagram of the Front Panel


Figure 7-2 shows the appearance of the front panel of the EFT8.

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Figure 7-2 Front panel of the EFT8

EFT8
STAT
ACT
PROG
SRV
FE1

FE2

FE3

FE4

FE5

FE6

FE7

FE8

EFT8

Indicators
The front panel of the board has the following indicators:
l

Board hardware status indicator (STAT) two colors (red and green)

Service activation status indicator (ACT) one color (green)

Board software status indicator (PROG) two colors (red and green)

Service alarm indicator (SRV) three colors (red, green, and yellow)

Connection status indicator (LINK) one color (green)

Data receiving and transmission indicator (ACT) one color (orange)

For the meanings of the status of the indicators, see A Indicators.

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Interfaces
The front panel of the EFT8 has eight FE interfaces. Table 7-2 describes the types and usage of
the interfaces of the EFT8.
Table 7-2 Interfaces of the EFT8
Interface

Type of
Interface

Usage

FE1

RJ-45

Transmits and receives 10BASE-T/100BASE-TX


signals.

FE2

RJ-45

Transmits and receives 10BASE-T/100BASE-TX


signals.

FE3

RJ-45

Transmits and receives 10BASE-T/100BASE-TX


signals.

FE4

RJ-45

Transmits and receives 10BASE-T/100BASE-TX


signals.

FE5

RJ-45

Transmits and receives 10BASE-T/100BASE-TX


signals.

FE6

RJ-45

Transmits and receives 10BASE-T/100BASE-TX


signals.

FE7

RJ-45

Transmits and receives 10BASE-T/100BASE-TX


signals.

FE8

RJ-45

Transmits and receives 10BASE-T/100BASE-TX


signals.

Table 7-3 describes the pins of the RJ-45 connector.


Table 7-3 Pins of the RJ-45 connector

Issue 02 (2009-07-30)

Pin

Description

Positive data transmit end

Negative data transmit end

Positive data receive end

Grounding

Grounding

Negative data receive end

Grounding

Grounding

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7.1.5 Valid Slots


The slots valid for the EFT8 vary with the cross-connect capacity of the subrack and whether
the EFT8 works with an interface board.
The slots valid for the EFT8 are as follows:
l

When the EFT8 does not work with an interface board, the EFT8 can be installed in slots
27 and 1216. In this case, the bandwidth is 622 Mbit/s.

When the EFT8 works with an interface board, the EFT8 can be installed in slots 37 and
1216. In this case, the bandwidth is 1.25 Gbit/s.

7.1.6 Parameter Settings


You can set the parameters for the EFT8 by using the T2000.
You can set the following parameters for the EFT8 by using the T2000:
l

Working mode

LCAS

Maximum frame length

Mapping protocol

For the description of each parameter, see F Parameter Settings.

7.1.7 Technical Specifications


The technical specifications of the EFT8 include the Ethernet performance specifications,
mechanical specifications, and power consumption.

Ethernet Performance Specifications


Figure 7-3 shows the connection for testing the throughput specifications, packet loss ratio in
the case of overloading, and latency specifications of the EFT8.
Figure 7-3 Connection for testing the throughput specifications, packet loss ratio in the case of
overloading, and latency specifications
Port 1
Tested
equipment 1

Tested
equipment 2
Port 2

Port 1

Port 2

Data network
performance
analyzer

Figure 7-4 shows the connection for testing the back-to-back specifications of the EFT8.
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Figure 7-4 Connection for testing the back-to-back specifications


Tested
equipment 1

Port 1

Port 2

Data network
performance
analyzer

Table 7-4 lists the throughput specifications of the EFT8. Table 7-5 lists the packet loss ratio
in the case of overloading of the EFT8. Table 7-6 lists the latency specifications of the EFT8.
Table 7-7 lists the back-to-back specifications of the EFT8.
NOTE

The specifications vary according to the configuration and networking of the test environment and
the VC services bound on the VCG side. The specifications that are obtained in the actual environment
are used.

The specifications in the following tables are obtained in the following scenario: EPL services are
configured and 63 VC-12s are bound on the FE port.

The specifications of a board of a specific version are not provided because the board version has
negligible effect on the specifications.

The specifications in the following tables are obtained by using the Smart Application.

Table 7-4 Throughput specifications of the EFT8

Issue 02 (2009-07-30)

Frame Size
(Byte)

Passed Rate
(%)

(01,01,01) to
(01,01,02) (pks/
sec)

(01,01,02) to
(01,01,01) (pks/
sec)

Total (pks/
sec)

64

100.00

148810

148810

297620

128

100.00

84459

84459

168918

256

100.00

45290

45290

90580

512

100.00

23496

23496

46992

1024

100.00

11973

11973

23946

1280

100.00

9615

9615

19230

1518

100.00

8127

8127

16254

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NOTE

The specifications in the preceding table are obtained in the scenario wherein point-to-point transparent
transmission services are configured and the flow control function is disabled.

The permitted packet loss ratio is set to 0% and the resolution rate is set to 0.1%.

The test duration is set to 60 seconds.

Table 7-5 Packet loss ratio in the case of overloading of the EFT8
Frame Size
(Byte)

Rate Tested
(%)

(01,01,01) to
(01,01,02) (%)

(01,01,02) to
(01,01,01) (%)

Average (%)

64

100.00

0.000

0.000

0.000

128

100.00

0.000

0.000

0.000

256

100.00

0.000

0.000

0.000

512

100.00

0.000

0.000

0.000

1024

100.00

0.000

0.000

0.000

1280

100.00

0.000

0.000

0.000

1518

100.00

0.000

0.000

0.000

NOTE

The specifications in the preceding table are obtained in the scenario wherein point-to-point transparent
transmission services are configured and the flow control function is disabled.

The tested traffic starts from the throughput and increases to 100% in 10% steps.

The test duration is set to 60 seconds.

Table 7-6 Latency specifications of the EFT8

7-12

Frame
Size
(Byte)

Rate
Tested
(%)

(01,01,01) to
(01,01,02) (us)CT (us)

Average
(CT) (us)

(01,01,01) to
(01,01,02)
(us)-S&F (us)

Average
(S&F) (us)

64

100.00

506.4

506.4

501.2

501.2

128

100.00

518.8

518.8

508.5

508.5

256

100.00

536.2

536.2

515.8

515.8

512

100.00

578.9

578.9

538.0

538.0

1024

100.00

653.4

653.4

571.4

571.4

1280

100.00

688.1

688.1

585.6

585.6

1518

100.00

720.6

720.6

599.1

599.1

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NOTE

The specifications in the preceding table are obtained in the scenario wherein point-to-point transparent
transmission services are configured and the flow control function is disabled.

The test duration is set to 60 seconds.

The latency modes are classified into two modes, namely, cut through mode and store forward mode.
In cut through mode, the analyzer calculates the difference between the time when the first bit of the
transmitted frame reaches the output port and the time when the first bit of the transmitted frame reaches
the input port. In store forward mode, the analyzer calculates the difference between the time when the
first bit of the transmitted frame reaches the output port and the time when the last bit of the transmitted
frame reaches the input port. In the preceding table, the CT values are obtained in cut through mode
and the S&F values are obtained in store forward mode.

Table 7-7 Back-to-back specifications of the EFT8


Frame Size
(Byte)

Rate Tested
(%)

(01,01,01) to
(01,01,02) Burst
Size (Number of
Frames)

(01,01,02) to
(01,01,01)
(Number of
Frames)

Total
(Number of
Frames)

64

100.00

297620

297620

595240

128

100.00

168918

168918

337836

256

100.00

90580

90580

181160

512

100.00

46992

46992

93984

1024

100.00

23946

23946

47892

1280

100.00

19230

19230

38460

1518

100.00

16254

16254

32508

NOTE

The specifications in the preceding table are obtained in the scenario wherein point-to-point transparent
transmission services are configured and the flow control function is disabled.

The frame size is set to the range from 64 bytes to 1518 bytes, the packet transmission rate is set to
100%, the test duration is set to 2 seconds, and the number of repetitions is set to a value more than 50
on the Smart Application.

The tested traffic is set to the wire speed.

The test duration is set to 10 seconds.

Mechanical Specifications
The mechanical specifications of the EFT8 are as follows:
l

Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)

Weight (kg): 1.0

Power Consumption
The maximum power consumption of the EFT8 at room temperature (25C) is 26 W.
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7.2 EFT8A
This topic describes the version, functions, working principle, valid slots, and technical
specification of the EFT8A (8xFE transparent transmission board).
7.2.1 Version Description
The EFT8A is available in one functional version, namely, N1.
7.2.2 Functions and Features
The EFT8A supports the transparent transmission of Ethernet services, LCAS function, and test
frames.
7.2.3 Working Principle and Signal Flow
The EFT8A consists of the Ethernet access module, mapping module, interface converting
module, logic and control module, clock module, and power module.
7.2.4 Front Panel
The front panel of the EFT8A has indicators, interfaces, and a bar code.
7.2.5 Valid Slots
The EFT8A can be installed in slots 28 and 1116 in the subrack. In this case, the bandwidth
is 622 Mbit/s.
7.2.6 Parameter Settings
You can set the parameters for the EFT8A by using the T2000.
7.2.7 Technical Specifications
The technical specifications of the EFT8A include the Ethernet performance specifications,
mechanical specifications, and power consumption.

7.2.1 Version Description


The EFT8A is available in one functional version, namely, N1.

7.2.2 Functions and Features


The EFT8A supports the transparent transmission of Ethernet services, LCAS function, and test
frames.
Table 7-8 provides the functions and features of the EFT8A.
Table 7-8 Functions and features of the EFT8A

7-14

Function and
Feature

EFT8A

Basic functions

Transparently transmits 8xFE services.

Specifications of the
optical interface

Supports 10BASE-T/100BASE-TX signals.

The optical interfaces comply with IEEE 802.3u.

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Function and
Feature

EFT8A

Format of service
frames

Supports Ethernet II, IEEE 802.3, and IEEE 802.1q TAG formats.

The first four ports support the frame with a length ranging from
64 bytes to 1535 bytes and the last four ports support the frame with
a length ranging from 64 bytes to 9600 bytes.

Supports the Jumbo frame with a length less than 9600 bytes.

Maximum uplink
bandwidth

622 Mbit/s

VCTRUNKs

Number of supported VCTRUNKs: 8


Configuration principles are as follows:

Issue 02 (2009-07-30)

A VCTRUNK can be bound with a maximum of three VC-3s or a


maximum of 63 VC-12s.

A VCTRUNK can be bound with the VC-12 path or VC-3 path at


one time. A VCTRUNK should not be bound with VC-12 and VC-3
paths at the same time.

Different VCTRUNKs can be bound with paths at different levels.

A VCTRUNK cannot be bound with VC-12s numbered 163 and


VC-3s numbered 1012 at the same time.

Encapsulation
format

Supports the HDLC, LAPS, and GFP-F protocols.

Mapping
granularities

Supports VC-12, VC-3, VC-12-Xv (X63), and VC-3-Xv (X3)


granularities.

Ethernet service type

Supports EPL services.

MTU

Supports the setting of the packet length, which ranges from 1518
bytes to 1535 bytes. After the setting becomes valid, the length of the
packets that enter or exit the IP ports is limited.

MPLS

Does not support the MPLS.

VLAN

Supports VLAN transparent transmission.

LPT

Supports the LPT in GFP bearer mode.

CAR

Does not support the CAR.

Flow control
function

Supports the FE interface-based flow control function that complies


with IEEE 802.3x.

LCAS function

Dynamically increases or decreases the bandwidth and protects the


bandwidth in compliance with ITU-T G.7042.

ETH-OAM

Does not support the ETH-OAM function.

Test frames

Receives and transmits GFP test frames.

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Function and
Feature

EFT8A

Loopback function

Supports inloops on Ethernet ports (at the PHY layer or MAC


layer).

Supports inloops and outloops at the VC-3 level.

Ethernet
performance
monitoring

Supports Ethernet performance monitoring at the port level.

Alarms and
performance events

Reports various alarms and performance events, which facilitates the


management and maintenance of the equipment.

7.2.3 Working Principle and Signal Flow


The EFT8A consists of the Ethernet access module, mapping module, interface converting
module, logic and control module, clock module, and power module.
Figure 7-5 shows the functional block diagram of the EFT8A by describing how to process
1xFE signals.
Figure 7-5 Functional block diagram of the EFT8A
Backplane

FE

Ethernet
access
module

ENCP

Interface
converting
module

VCP
DENCP

Cross-connect unit
Cross-connect unit

Mapping module
LOS
Logic and
control module

Communication
Reference clock and frame header

SCC unit
SCC unit

Fuse

-48 V/-60 V

+3.3 V
Clock
module

Power
module

Power
module

-48 V/-60 V

50 77 125 155
MHz MHz MHz MHz

ENCP: data encapsulation module

DENCP: decapsulation module

VCP: virtual concatenation processing module

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Ethernet Access Module


In the receive direction, the Ethernet access module accesses the Ethernet electrical signals from
Ethernet equipment such as switches or routers. At the PHY layer, the electrical signals are
decoded and the ETH_LOS alarm is detected. The electrical signals are converted from serial
signals into parallel signals and then sent to the network processor module.
In the transmit direction, the parallel signals are converted into serial signals. At the PHY layer,
signals are encoded.

Mapping Module
The mapping module performs encapsulation and mapping functions.
In the upstream direction, this module first encapsulates Ethernet signals in LAPS, HDLC, or
GFP format. The concatenation is performed. Then, the Ethernet signals are converted into SDH
signals.
In the downstream direction, SDH signals are demapped. The delay of virtual concatenation is
compensated. After aligning, packets are decapsulated according to the encapsulation format.
The decapsulated data is finally transmitted to the network processor module in packets.

Interface Converting Module


The interface converting module converts the 622 Mbit/s LVDS bus of the SDH system into the
parallel bus. The high-rate backplane interface is connected to the low-rate interface chip of the
transmit system through the interface converting module.

Logic and Control Module


The logic and control module consists of the CPU, register, oscillator, Ethernet port, and HDLC
controller. This module is connected to external circuits through the bus. The logic and control
module performs the following functions:
l

Manages and configures other modules of the board.

Implements inter-board communication through the internal Ethernet interface.

The control module also contains basic logic units. This module performs the following
functions:
l

Writes and reads the register.

Provides interfaces for the CPU.

Checks and selects the clock.

Performs phase discrimination and frequency division on the clock.

Checks the in-service state of the cross-connect, SCC, and line boards.

Implements communication.

Controls indicators.

Clock Module
The clock module traces the system reference clock and generates the required working clock
for each chip. The frequency of the clock can be 50 MHz, 77 MHz, 125 MHz, or 155 MHz.
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Power Module
It converts the 48 V/60 V power supply into the DC voltages that the modules of the board
require.

7.2.4 Front Panel


The front panel of the EFT8A has indicators, interfaces, and a bar code.

Diagram of the Front Panel


Figure 7-6 shows the appearance of the front panel of the EFT8A.
Figure 7-6 Front panel of the EFT8A

EFT8A
STAT
ACT
PROG
SRV
FE1

FE2

FE3

FE4

FE5

FE6

FE7

FE8

EFT8A

Indicators
The front panel of the board has the following indicators:
7-18

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Board hardware status indicator (STAT) two colors (red and green)

Service activation status indicator (ACT) one color (green)

Board software status indicator (PROG) two colors (red and green)

Service alarm indicator (SRV) three colors (red, green, and yellow)

Connection status indicator (LINK) one color (green)

Data receiving and transmission indicator (ACT) one color (orange)

For the meanings of the status of the indicators, see A Indicators.

Interfaces
The front panel of the EFT8A has eight FE interfaces. Table 7-9 describes the types and usage
of the interfaces of the EFT8A.
Table 7-9 Interfaces of the EFT8A
Interface

Type of
Interface

Usage

FE1

RJ-45

Transmits and receives 10BASE-T/100BASE-TX


signals.

FE2

RJ-45

Transmits and receives 10BASE-T/100BASE-TX


signals.

FE3

RJ-45

Transmits and receives 10BASE-T/100BASE-TX


signals.

FE4

RJ-45

Transmits and receives 10BASE-T/100BASE-TX


signals.

FE5

RJ-45

Transmits and receives 10BASE-T/100BASE-TX


signals.

FE6

RJ-45

Transmits and receives 10BASE-T/100BASE-TX


signals.

FE7

RJ-45

Transmits and receives 10BASE-T/100BASE-TX


signals.

FE8

RJ-45

Transmits and receives 10BASE-T/100BASE-TX


signals.

Table 7-10 describes the pins of the RJ-45 connector.


Table 7-10 Pins of the RJ-45 connector

Issue 02 (2009-07-30)

Pin

Description

Positive data transmit end

Negative data transmit end


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Pin

Description

Positive data receive end

Grounding

Grounding

Negative data receive end

Grounding

Grounding

7.2.5 Valid Slots


The EFT8A can be installed in slots 28 and 1116 in the subrack. In this case, the bandwidth
is 622 Mbit/s.

7.2.6 Parameter Settings


You can set the parameters for the EFT8A by using the T2000.
You can set the following parameters for the EFT8A by using the T2000:
l

Working mode

LCAS

Maximum frame length

Mapping protocol

For description of each parameter, see F Parameter Settings.

7.2.7 Technical Specifications


The technical specifications of the EFT8A include the Ethernet performance specifications,
mechanical specifications, and power consumption.

Ethernet Performance Specifications


Figure 7-7 shows the connection for testing the throughput specifications, packet loss ratio in
the case of overloading, and latency specifications of the EFTA.

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Figure 7-7 Connection for testing the throughput specifications, packet loss ratio in the case of
overloading, and latency specifications
Port 1
Tested
equipment 1

Tested
equipment 2
Port 2

Port 1

Port 2

Data network
performance
analyzer

Figure 7-8 shows the connection for testing the back-to-back specifications of the EFT8A.
Figure 7-8 Connection for testing the back-to-back specifications
Tested
equipment 1

Port 1

Port 2

Data network
performance
analyzer

Table 7-11 lists the throughput specifications of the EFT8A. Table 7-12 lists the packet loss
ratio in the case of overloading of the EFT8A. Table 7-13 lists the latency specifications of the
EFT8A. Table 7-14 lists the back-to-back specifications of the EFT8A.
NOTE

Issue 02 (2009-07-30)

The specifications vary according to the configuration and networking of the test environment and
the VC services bound on the VCG side. The specifications that are obtained in the actual environment
are used.

The specifications in the following tables are obtained in the following scenario: EPL services are
configured and 63 VC-12s are bound on the FE port.

The specifications of a board of a specific version are not provided because the board version has
negligible effect on the specifications.

The specifications in the following tables are obtained by using the Smart Application.

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Table 7-11 Throughput specifications of the EFT8A


Frame Size
(Byte)

Passed Rate
(%)

(01,01,01) to
(01,01,02) (pks/
sec)

(01,01,02) to
(01,01,01) (pks/
sec)

Total (pks/
sec)

64

100.00

148810

148810

297620

128

100.00

84459

84459

168918

256

100.00

45290

45290

90580

512

100.00

23496

23496

46992

1024

100.00

11973

11973

23946

1280

100.00

9615

9615

19230

1518

100.00

8127

8127

16254

NOTE

The specifications in the preceding table are obtained in the scenario wherein point-to-point transparent
transmission services are configured and the flow control function is disabled.

The permitted packet loss ratio is set to 0% and the resolution rate is set to 0.1%.

The test duration is set to 60 seconds.

Table 7-12 Packet loss ratio in the case of overloading of the EFT8A
Frame Size
(Byte)

Rate Tested
(%)

(01,01,01) to
(01,01,02) (%)

(01,01,02) to
(01,01,01) (%)

Average (%)

64

100.00

0.000

0.000

0.000

128

100.00

0.000

0.000

0.000

256

100.00

0.000

0.000

0.000

512

100.00

0.000

0.000

0.000

1024

100.00

0.000

0.000

0.000

1280

100.00

0.000

0.000

0.000

1518

100.00

0.000

0.000

0.000

NOTE

7-22

The specifications in the preceding table are obtained in the scenario wherein point-to-point transparent
transmission services are configured and the flow control function is disabled.

The tested traffic starts from the throughput and increases to 100% in 10% steps.

The test duration is set to 60 seconds.

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Table 7-13 Latency specifications of the EFT8A


Frame
Size
(Byte)

Rate
Tested
(%)

(01,01,01) to
(01,01,02) (us)CT (us)

Average
(CT) (us)

(01,01,01) to
(01,01,02)
(us)-S&F (us)

Average
(S&F) (us)

64

100.00

506.4

506.4

501.2

501.2

128

100.00

518.8

518.8

508.5

508.5

256

100.00

536.2

536.2

515.8

515.8

512

100.00

578.9

578.9

538.0

538.0

1024

100.00

653.4

653.4

571.4

571.4

1280

100.00

688.1

688.1

585.6

585.6

1518

100.00

720.6

720.6

599.1

599.1

NOTE

The specifications in the preceding table are obtained in the scenario wherein point-to-point transparent
transmission services are configured and the flow control function is disabled.

The test duration is set to 60 seconds.

The latency modes are classified into two modes, namely, cut through mode and store forward mode.
In cut through mode, the analyzer calculates the difference between the time when the first bit of the
transmitted frame reaches the output port and the time when the first bit of the transmitted frame reaches
the input port. In store forward mode, the analyzer calculates the difference between the time when the
first bit of the transmitted frame reaches the output port and the time when the last bit of the transmitted
frame reaches the input port. In the preceding table, the CT values are obtained in cut through mode
and the S&F values are obtained in store forward mode.

Table 7-14 Back-to-back specifications of the EFT8A

Issue 02 (2009-07-30)

Frame Size
(Byte)

Rate Tested
(%)

(01,01,01) to
(01,01,02) Burst
Size (Number of
Frames)

(01,01,02) to
(01,01,01)
(Number of
Frames)

Total
(Number of
Frames)

64

100.00

297620

297620

595240

128

100.00

168918

168918

337836

256

100.00

90580

90580

181160

512

100.00

46992

46992

93984

1024

100.00

23946

23946

47892

1280

100.00

19230

19230

38460

1518

100.00

16254

16254

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NOTE

The specifications in the preceding table are obtained in the scenario wherein point-to-point transparent
transmission services are configured and the flow control function is disabled.

The frame size is set to the range from 64 bytes to 1518 bytes, the packet transmission rate is set to
100%, the test duration is set to 2 seconds, and the number of repetitions is set to a value more than 50
on the Smart Application.

The tested traffic is set to the wire speed.

The test duration is set to 10 seconds.

Mechanical Specifications
The mechanical specifications of the EFT8A are as follows:
l

Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)

Weight (kg): 1.0

Power Consumption
The maximum power consumption of the EFT8A at room temperature (25C) is 26 W.

7.3 EGT2
This topic describes the version, functions, working principle, valid slots, and technical
specification of the EGT2 (2xGE transparent transmission board).
7.3.1 Version Description
The EGT2 is available in two functional versions, namely, N1 and N2.
7.3.2 Functions and Features
The EGT2 supports the transparent transmission of Ethernet services, LCAS function, and test
frames.
7.3.3 Working Principle and Signal Flow
The EGT2 consists of the Ethernet access module, mapping module, interface converting
module, logic and control module, clock module, and power module.
7.3.4 Front Panel
The front panel of the EGT2 has indicators, interfaces, a bar code, and a laser safety class label.
7.3.5 Valid Slots
The EGT2 can be installed in slots 28 and 1116 in the subrack.
7.3.6 Feature Code
The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the EGT2 indicates the type of interface.
7.3.7 Parameter Settings
You can set the parameters for the EGT2 by using the T2000.
7.3.8 Technical Specifications
The technical specifications of the EGT2 include the parameters specified for optical interfaces,
laser safety class, Ethernet performance specifications, mechanical specifications, and power
consumption.
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7.3.1 Version Description


The EGT2 is available in two functional versions, namely, N1 and N2.

7.3.2 Functions and Features


The EGT2 supports the transparent transmission of Ethernet services, LCAS function, and test
frames.
Table 7-15 provides the functions and features of the EGT2.
Table 7-15 Functions and features of the EGT2
Function and
Feature

EGT2

Basic functions

Transparently transmits 2xGE services.

Specifications of
the optical
interface

Supports the 1000BASE-SX/LX/ZX/VX Ethernet optical interfaces.


The optical interfaces support the auto-negotiation function in
compliance with IEEE 802.3z. The optical interfaces use the SFP
optical module and support hot swapping. When the multi-mode
optical fiber is used, the maximum transmission distance is 550 m.
When the single-mode optical fiber is used, the maximum
transmission distance is 10 km. The optical modules that can meet
different requirements for the transmission distance such as 40 km
and 80 km can also be used.

The N2EGT2 also supports the 1000BASE-T RJ-45 Ethernet


electrical interface. The electrical interface supports the autonegotiation function. The negotiated rate can be 10 Mbit/s, 100 Mbit/
s, or 1000 Mbit/s. The N2EGT2 uses the SFP electrical interface and
supports hot swapping. The maximum transmission distance is 100
m.

Supports Ethernet II, IEEE 802.3, and IEEE 802.1q TAG formats.

Supports the frame with a length ranging from 64 bytes to 9600 bytes.

Supports the Jumbo frame with a length less than 9600 bytes.

Format of service
frames

Maximum uplink
bandwidth

The maximum uplink bandwidth is 2.5 Gbit/s. The EGT2 can adapt to
the bandwidth of the slot.

VCTRUNKs

Number of supported VCTRUNKs: 2


Configuration principles are as follows:

Encapsulation
format
Issue 02 (2009-07-30)

A VCTRUNK can be bound with a maximum of eight VC-4s or a


maximum of 24 VC-3s. A VCTRUNK can be bound with VC-4s
numbered 114 or VC-3s numbered 148.

The virtual concatenation modes of the two VCTRUNKs of the board


should be the same. That is, the two VCTRUNKs should be of the
VC-4 virtual concatenation or of the VC-3 virtual concatenation.

Supports the HDLC, LAPS, and GFP-F protocols.

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Function and
Feature

EGT2

Mapping
granularities

Supports VC-4, VC-3, VC3-Xv (X24), and VC4-Xv (X8)


granularities.

Ethernet service
type

Supports EPL services.

MPLS

Does not support the MPLS.

MTU

Supports the setting of the packet length, which ranges from 1518 bytes
to 9600 bytes. After the setting becomes valid, the length of the packets
that enter or exit the IP ports is limited.

VLAN

Supports the VLAN transparent transmission.

LPT

Supports the LPT in GFP bearer mode.

CAR

Does not support the CAR.

Flow control
function

Supports the GE port-based flow control function that complies with


IEEE 802.3x.

LCAS function

Dynamically increases or decreases the bandwidth and protects the


bandwidth in compliance with ITU-T G.7042.

ETH-OAM
function

Does not support the ETH-OAM function.

Test frames

Receives and transmits Ethernet test frames.

Port mirroring

Supports the ingress mirroring.

Loopback
function

Supports inloops on Ethernet ports (at the PHY layer or MAC layer).

Ethernet
performance
monitoring

Supports Ethernet performance monitoring at the port level.

Alarms and
performance
events

Reports various alarms and performance events, which facilitates the


management and maintenance of the equipment.

7.3.3 Working Principle and Signal Flow


The EGT2 consists of the Ethernet access module, mapping module, interface converting
module, logic and control module, clock module, and power module.
Figure 7-9 shows the functional block diagram of the EGT2 by describing how to process 1xGE
signals.

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Figure 7-9 Functional block diagram of the EGT2


Backplane

GE

Ethernet
access
module

ENCP

Interface
converting
module

VCP
DENCP

Cross-connect unit
Cross-connect unit

Mapping module
Laser
shutdown

LOS
Communication
Reference clock and frame header

Logic and
control module

+3.3 V
Clock module

Power
module

Power
module

Fuse

SCC unit
SCC unit
-48 V/-60 V
-48 V/-60 V

50 77 125 155
MHz MHz MHz MHz

ENCP: data encapsulation module

DENCP: decapsulation module

VCP: virtual concatenation processing module

Ethernet Access Module


In the receive direction, the optical signals from Ethernet equipment such as switches or routers
are converted into electrical signals. If the signals are accessed through electrical interfaces, O/
E conversion is not required. At the PHY layer, the electrical signals are decoded and the
ETH_LOS alarm is detected. The electrical signals are converted from serial signals into parallel
signals and then sent to the network processor module.
In the transmit direction, the parallel signals are converted into serial signals. At the PHY layer,
signals are encoded and converted from electrical signals to optical signals.

Mapping Module
The mapping module performs encapsulation and mapping functions.
In the upstream direction, this module first encapsulates Ethernet signals in LAPS, HDLC, or
GFP format. The concatenation is performed. Then, the Ethernet signals are converted into SDH
signals.
In the downstream direction, SDH signals are demapped. The delay of virtual concatenation is
compensated. After aligning, packets are decapsulated according to the encapsulation format.
The decapsulated data is finally transmitted to the network processor module in packets.

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Interface Converting Module


The interface converting module converts the 622 Mbit/s LVDS bus of the SDH system into the
parallel bus. The high-rate backplane interface is connected to the low-rate interface chip of the
transmit system through the interface converting module.

Logic and Control Module


The logic and control module consists of the CPU, register, oscillator, Ethernet port, and HDLC
controller. This module is connected to external circuits through the bus. The logic and control
module performs the following functions:
l

Manages and configures other modules of the board.

Implements inter-board communication through the internal Ethernet interface.

The control module also contains basic logic units. This module performs the following
functions:
l

Writes and reads the register.

Provides interfaces for the CPU.

Checks and selects the clock.

Performs phase discrimination and frequency division on the clock.

Checks the in-service state of the cross-connect, SCC, and line boards.

Controls the shutting down of the optical module.

Implements communication.

Controls indicators.

Clock Module
The clock module traces the system reference clock and generates the required working clock
for each chip. The frequency of the clock can be 50 MHz, 77 MHz, 125 MHz, or 155 MHz.

Power Module
It converts the 48 V/60 V power supply into the DC voltages that the modules of the board
require.

7.3.4 Front Panel


The front panel of the EGT2 has indicators, interfaces, a bar code, and a laser safety class label.

Diagram of the Front Panel


Figure 7-10 shows the appearance of the front panel of the N1EGT2/N2EGT2 that is installed
with the GE optical interface.

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Figure 7-10 Front panel of the N1EGT2/N2EGT2 that is installed with the GE optical interface

EGT2
STAT
ACT
PROG
SRV
LINK1
ACT1
LINK2
ACT2
CLASS 1
LASER
PRODUCT

OUT1
IN1
OUT2
IN2

EGT2

The N2EGT2 can also be installed with the GE electrical interface. Figure 7-11 shows the
appearance of the front panel of the N2EGT2 that is installed with the GE electrical interface.

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Figure 7-11 Front panel of the N2EGT2 that is installed with the GE electrical interface

EGT2
STAT
ACT
PROG
SRV
LINK1
ACT1
LINK2
ACT2

OUT1
IN1
OUT2
IN2

EGT2

Indicators
The front panel of the board has the following indicators:
l

Board hardware status indicator (STAT) two colors (red and green)

Service activation status indicator (ACT) one color (green)

Board software status indicator (PROG) two colors (red and green)

Service alarm indicator (SRV) three colors (red, green, and yellow)

Connection status indicator (LINK) one color (green)

Data receiving and transmission indicator (ACT) one color (orange)

For the meanings of the status of the indicators, see A Indicators.

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Interfaces
The front panel of the N1EGT2/N2EGT2 has two GE optical interfaces. Table 7-16 describes
the types and usage of the optical interfaces of the N1EGT2/N2EGT2.
Table 7-16 Optical interfaces of the N1EGT2/N2EGT2
Interface

Type of Interface

Usage

IN1/OUT1

LC (swappable)

Transmits and receives 1000BASE-SX/LX/ZX


signals.

IN2/OUT2

LC (swappable)

Transmits and receives 1000BASE-SX/LX/ZX


signals.

The two GE electrical interfaces of the N2EGT2 are of the same type and have the same usage.
Table 7-17 describes the types and usage of the electrical interfaces of the N2EGT2.
Table 7-17 Electrical interfaces of the N2EGT2
Interface

Type of Interface

Usage

GE

RJ-45 (swappable)

Transmits and receives 1000BASE-T signals.

Table 7-18 provides the pin assignments of the RJ-45 interface of the N2EGT2.
Table 7-18 Pin assignments of the RJ-45 interface of the N2EGT2
Pin

Description

BI_DA+

BI_DA

BI_DB+

BI_DC+

BI_DC

BI_DB

BI_DD+

BI_DD

7.3.5 Valid Slots


The EGT2 can be installed in slots 28 and 1116 in the subrack.
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7.3.6 Feature Code


The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the EGT2 indicates the type of interface.
Table 7-19 provides the relationship between the feature code of the EGT2 and the type of
interface.
Table 7-19 Relationship between the feature code of the EGT2 and the type of interface
Board

Feature Code

Type of Interface

SSN1EGT210 and
SSN2EGT210

10

1000BASE-SX (0.5 km)

SSN1EGT211 and
SSN2EGT211

11

1000BASE-LX (10 km)

SSN1EGT212 and
SSN2EGT212

12

1000BASE-VX (40 km)

SSN1EGT213 and
SSN2EGT213

13

1000BASE-ZX (80 km)

SSN2EGT214

14

1000BASE-T (100 m)

7.3.7 Parameter Settings


You can set the parameters for the EGT2 by using the T2000.
You can set the following parameters for the EGT2 by using the T2000:
l

Working mode

LCAS

Maximum frame length

Mapping protocol

For the description of each parameter, see F Parameter Settings.

7.3.8 Technical Specifications


The technical specifications of the EGT2 include the parameters specified for optical interfaces,
laser safety class, Ethernet performance specifications, mechanical specifications, and power
consumption.

Parameters Specified for Optical Interfaces


Table 7-20 lists the parameters specified for the optical interfaces of the EGT2.

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Table 7-20 Parameters specified for the optical interfaces of the EGT2
Parameter

Value

Type of optical
interface

1000BASEZX (80 km)

1000BASE-EX
(40 km)

1000BASELX (10 km)

1000BASE-SX
(0.5 km)

Type of fiber

Single-mode
LC

Single-mode
LC

Single-mode
LC

Multi-mode LC

Launched
optical power
range (dBm)

-2 to +5

-5.0 to 0

-9.5 to -3

-9.5 to -2.5

Operating
wavelength
range (nm)

1500 to 1580

1275 to 1350

1270 to 1355

770 to 860

Minimum
overload (dBm)

-3

-3

-3

Receiver
sensitivity
(dBm)

-23

-23

-20

-17

Minimum
extinction ratio
(dB)

Laser Safety Class


The safety class of the laser on the board is Class 1. The maximum launched optical power of
the optical interfaces is less than 10 dBm (10 mW).

Ethernet Performance Specifications


Figure 7-12 shows the connection for testing the throughput specifications, packet loss ratio in
the case of overloading, and latency specifications of the EGT2.
Figure 7-12 Connection for testing the throughput specifications, packet loss ratio in the case
of overloading, and latency specifications
Port 1
Tested
equipment 1

Tested
equipment 2
Port 2

Port 1

Port 2

Data network
performance
analyzer

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Figure 7-13 shows the connection for testing the back-to-back specifications of the EGT2.
Figure 7-13 Connection for testing the back-to-back specifications
Tested
equipment 1

Port 1

Port 2

Data network
performance
analyzer

Table 7-21 lists the throughput specifications of the EGT2. Table 7-22 lists the packet loss ratio
in the case of overloading of the EGT2. Table 7-23 lists the latency specifications of the EGT2.
Table 7-24 lists the back-to-back specifications of the EGT2.
NOTE

The specifications vary according to the configuration and networking of the test environment and
the VC services bound on the VCG side. The specifications that are obtained in the actual environment
are used.

The specifications in the following tables are obtained in the following scenario: EPL services are
configured and 24 VC-3s are bound on the GE port.

The specifications of a board of a specific version are not provided because the board version has
negligible effect on the specifications.

The specifications in the following tables are obtained by using the Smart Application.

Table 7-21 Throughput specifications of the EGT2

7-34

Frame Size
(Byte)

Passed Rate
(%)

(01,02,01) to
(01,02,02) (pks/
sec)

(01,02,02) to
(01,02,01) (pks/
sec)

Total (pks/
sec)

64

100.00

1488095

1488095

2976190

128

100.00

844595

844595

1689190

256

100.00

452899

452899

905798

512

100.00

234962

234962

469924

1024

100.00

119732

119732

239464

1280

100.00

96154

96154

192308

1518

100.00

81274

81274

162548

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NOTE

The specifications in the preceding table are obtained in the scenario wherein point-to-point transparent
transmission services are configured and the flow control function is disabled.

The permitted packet loss ratio is set to 0% and the resolution rate is set to 0.1%.

The test duration is set to 60 seconds.

Table 7-22 Packet loss ratio in the case of overloading of the EGT2
Frame Size
(Byte)

Rate Tested
(%)

(01,02,01) to
(01,02,02) (%)

(01,02,02) to
(01,02,01) (%)

Average (%)

64

100.00

0.000

0.000

0.000

128

100.00

0.000

0.000

0.000

256

100.00

0.000

0.000

0.000

512

100.00

0.000

0.000

0.000

1024

100.00

0.000

0.000

0.000

1280

100.00

0.000

0.000

0.000

1518

100.00

0.000

0.000

0.000

NOTE

The specifications in the preceding table are obtained in the scenario wherein point-to-point transparent
transmission services are configured and the flow control function is disabled.

The tested traffic starts from the throughput and increases to 100% in 10% steps.

The test duration is set to 60 seconds.

Table 7-23 Latency specifications of the EGT2

Issue 02 (2009-07-30)

Frame
Size
(Byte)

Rate
Tested
(%)

(01,02,01) to
(01,02,02) (us)CT (us)

Average
(CT) (us)

(01,02,02) to
(01,02,01)
(us)-S&F (us)

Average
(S&F) (us)

64

100.00

35.7

35.7

35.2

35.2

128

100.00

37.1

37.1

36.1

36.1

256

100.00

39.5

39.5

37.4

37.4

512

100.00

44.1

44.1

40.1

40.1

1024

100.00

53.2

53.2

45.1

45.1

1280

100.00

57.6

57.6

47.4

47.4

1518

100.00

61.9

61.9

49.7

49.7

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NOTE

The specifications in the preceding table are obtained in the scenario wherein point-to-point transparent
transmission services are configured and the flow control function is disabled.

The test duration is set to 60 seconds.

The latency modes are classified into two modes, namely, cut through mode and store forward mode.
In cut through mode, the analyzer calculates the difference between the time when the first bit of the
transmitted frame reaches the output port and the time when the first bit of the transmitted frame reaches
the input port. In store forward mode, the analyzer calculates the difference between the time when the
first bit of the transmitted frame reaches the output port and the time when the last bit of the transmitted
frame reaches the input port. In the preceding table, the CT values are obtained in cut through mode
and the S&F values are obtained in store forward mode.

Table 7-24 Back-to-back specifications of the EGT2


Frame Size
(Byte)

Rate Tested
(%)

(01,02,01) to
(01,02,02) Burst
Size (Number of
Frames)

(01,02,02) to
(01,02,01)
(Number of
Frames)

Total
(Number of
Frames)

64

100.00

2976190

2976190

5952380

128

100.00

1689190

1689190

3378380

256

100.00

905798

905798

1811596

512

100.00

469924

469924

939848

1024

100.00

239464

239464

478928

1280

100.00

192308

192308

384616

1518

100.00

162548

162548

325096

NOTE

The specifications in the preceding table are obtained in the scenario wherein point-to-point transparent
transmission services are configured and the flow control function is disabled.

The frame size is set to the range from 64 bytes to 1518 bytes, the packet transmission rate is set to
100%, the test duration is set to 2 seconds, and the number of repetitions is set to a value more than 50
on the Smart Application.

The tested traffic is set to the wire speed.

The test duration is set to 10 seconds.

Mechanical Specifications
The mechanical specifications of the EGT2 are as follows:
l

Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)

Weight (kg): 0.9

Power Consumption
The maximum power consumption of the N1EGT2 at room temperature (25C) is 29 W.
7-36

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The maximum power consumption of the N2EGT2 at room temperature (25C) is 15 W.

7.4 EFS0
This topic describes the version, functions, working principle, valid slots, and technical
specification of the EFS0 (8xFE switching and processing board).
7.4.1 Version Description
The EFS0 is available in four functional versions, namely, N1, N2, N4, and N5. The N1EFS0
and N2EFS0 are no longer manufactured.
7.4.2 Functions and Features
The EFS0 supports the Layer 2 switching, MPLS, and broadcast functions.
7.4.3 Working Principle and Signal Flow
The EFS0 consists of the Ethernet access module, network processor module, mapping module,
interface converting module, logic and control module, clock module, and power module.
7.4.4 Front Panel
The front panel of the EFS0 has indicators and a bar code.
7.4.5 Valid Slots
The EFS0 can be installed in slots 37 and 1216 in the subrack. The bandwidth of the N1EFS0
is 622 Mbit/s and the bandwidth of the N2EFS0/N4EFS0/N5EFS0 is 1.25 Gbit/s.
7.4.6 Board Protection
The EFS0 supports the 1:1 TPS protection.
7.4.7 Parameter Settings
You can set the parameters for the EFS0 by using the T2000.
7.4.8 Technical Specifications
The technical specifications of the EFS0 include the dimensions, weight, and power
consumption.

7.4.1 Version Description


The EFS0 is available in four functional versions, namely, N1, N2, N4, and N5. The N1EFS0
and N2EFS0 are no longer manufactured.
Table 7-25 describes the versions of the EFS0.
Table 7-25 Versions of the EFS0

Issue 02 (2009-07-30)

Item

Description

Functional
versions

The EFS0 is available in four functional versions, namely, N1, N2, N4,
and N5.

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Item

Description

Differences

The maximum uplink bandwidth of the N1EFS0 is 622 Mbit/s.

The maximum uplink bandwidth of the N2EFS0/N4EFS0/N5EFS0 is


1.25 Gbit/s.

The N1EFS0 supports the flow classification based on PORT, PORT


+VLAN ID, and PORT+VLAN PRI.

The N2EFS0, N4EFS0, and N5EFS0 support flow classification based


on PORT, PORT+VLAN ID, and PORT+VLAN ID+VLAN PRI.

The number of VCTRUNKs supported by the N1EFS0 is 12.

The number of VCTRUNKs supported by the N2EFS0, N4EFS0, and


N5EFS0 is 24.

The N2EFS0 supports the board version replacement function and can
substitute for the N1EFS0.

Substitution

The N4EFS0 supports the board version replacement function and can
substitute for the N2EFS0/N1EFS0.
The N5EFS0 supports the board version replacement function and can
substitute for the N4EFS0/N2EFS0/N1EFS0.

7.4.2 Functions and Features


The EFS0 supports the Layer 2 switching, MPLS, and broadcast functions.
Table 7-26 provides the functions and features of the EFS0.
Table 7-26 Functions and features of the EFS0

7-38

Function and
Feature

EFS0

Basic functions

Processes 8xFE services and supports the convergence of 60x10 Mbit/


s or 6x100 Mbit/s services.

Functions when
being used with the
interface board

Accesses 8xFE signals through the electrical interface when the


EFS0 is used with the ETF8.

Accesses 8xFE signals through the optical interface when the EFS0
is used with the EFF8.

Provides the TPS protection for the 8xFE signals through the
electrical interface when the EFS0 is used with the ETS8 and TSB8.

The N5EFS0 can access 8xFE signals through the electrical interface
when it is used with the ETF8A.

The N5EFS0 can access 8xFE signals through the optical interface
when it is used with the EFF8A.

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Function and
Feature

EFS0

Specifications of
the optical interface

Supports 10BASE-T/100BASE-TX signals when the EFS0 is used


with the ETF8.

Supports 100BASE-FX signals when the EFS0 is used with the


EFF8. The optical interfaces comply with IEEE 802.3u.

The N5EFS0 supports 10BASE-T/100BASE-TX signals when it is


used with the ETF8A.

The N5EFS0 supports 100BASE-FX signals when it is used with


the EFF8A. The optical interfaces comply with IEEE 802.3u.

Supports Ethernet II, IEEE 802.3, and IEEE 802.1 q/p formats.

Supports the frame with a length ranging from 64 bytes to 9600


bytes.

Supports the Jumbo frame with a length less than 9600 bytes.

The maximum uplink bandwidth of the N1EFS0 is 622 Mbit/s.

The maximum uplink bandwidth of the N2EFS0/N4EFS0/N5EFS0


is 1.25 Gbit/s.

The EFS0 can adapt to the bandwidth of the slot.

Format of service
frames

Maximum uplink
bandwidth

VCTRUNKs

The number of supported VCTRUNKs is as follows:


l

The number of VCTRUNKs supported by the N1EFS0 is 12.

The number of VCTRUNKs supported by the N2EFS0/N4EFS0/


N5EFS0 is 24.

Configuration principles are as follows:

Issue 02 (2009-07-30)

VCTRUNK 1VCTRUNK 12 can be bound with VC-4s numbered


14 only. VCTRUNK 13VCTRUNK 24 can be bound with VC-4s
numbered 58 only.

VC-4s numbered 4 and 8 support the binding of VC-3 and VC-12


paths. The other VC-4s support the binding of VC-3 paths only.

A VC-4 cannot be bound with VC-3 and VC-12 paths at the same
time.

Mapping
granularities

Supports VC-12, VC-3, VC-12-Xv (X63), and VC-3-Xv (X12)


granularities.

Encapsulation
format

The N1EFS0/N2EFS0 supports the GFP-F, LAPS, and HDLC


protocols. The N4EFS0/N5EFS0 supports only the GFP-F protocol.

EPL services

Supports the PORT-based transparent transmission.

EVPL services

Supports PORT+VLAN-based EVPL services that use the frame


encapsulation formats of MartinioE and stack VLAN.

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Function and
Feature

EFS0

EPLAN services

The services that are based on the IEEE 802.1d MAC bridge are
referred to as EPLAN services.

EVPLAN

7-40

Supports the Layer 2 convergence and point-to-multipoint (P2MP)


convergence.

Supports the Layer 2 forwarding function.

Supports switching on the client and SDH sides.

Supports the self-learning of the source MAC address. The capacity


of the MAC address table is 16K. The aging time of the MAC address
can be set and queried.

Supports the configuration of the static MAC route.

The N1EFS0, N2EFS0, and N5EFS0 support the query of the


dynamic MAC address.

The N4EFS0 does not support the query of the dynamic MAC
address.

Supports the creation, deletion, and query of the VB. The maximum
number of supported VBs is 16. The maximum number of logical
ports for each VB is 30.

Supports the data isolation based on VB+VLAN.

Queries the number of actually learnt MAC addresses based on VB


+VLAN or VB+LP.

Supports data isolation based on VB+VLAN.

Supports the query of the number of learned MAC addresses


according to VB+VLAN or VB+LP.

MTU

Supports the setting of the packet length, which ranges from 1518 bytes
to 9600 bytes. After the setting becomes valid, the length of the packets
that enter or exit the IP ports is limited.

MPLS

Supports the MPLS.

VLAN

Complies with IEEE 802.1q/p.

VLAN
convergence

Supports the VLAN convergence.


The number of VLANs is 4K.

RSTP

Supports the broadcast packet suppression function and rapid spanning


tree protocol (RSTP) that comply with IEEE 802.1w.

Link aggregation
function

The N1EFS0 does not support the link aggregation function.

The N2EFS0, N4EFS0, and N5EFS0 support manual link


aggregation.

Multicast function

Supports the multicast function.

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Function and
Feature

EFS0

ETH-OAM
function

The N1EFS0 and N2EFS0 do not support the ETH-OAM function.

The N4EFS0 and N5EFS0 support continuity check (CC) for the
multicast service, loopback (LB) test for the unicast service, link
trace (LT) test, loop detection (LD), auto-negotiation, fault
diagnosis, and link performance detection. The ETH-OAM function
complies with IEEE 802.1ag and IEEE 802.3ah.

CAR

Supports the CAR.


The granularity is 64 kbit/s.

Service-based

QoS flow
classification

The N1EFS0 supports the service classification based on PORT,


PORT+VLAN ID, or PORT+VLAN PRI.

The N2EFS0, N4EFS0, and N5EFS0 support the flow classification


based on PORT, PORT++VLAN ID, or PORT+VLAN ID+VLAN
PRI.

LCAS function

Dynamically increases or decreases the bandwidth and protects the


bandwidth in compliance with ITU-T G.7042.

LPT function

Supports the point-to-point (P2P) LPT and P2MP LPT.

Flow control
function

Supports the port-based flow control function that complies with IEEE
802.3x.

High-precision
time

The N1EFS0, N2EFS0, and N4EFS0 do not support the highprecision time.

The N5EFS0 supports the time synchronization feature.

Test frames

Receives and transmits Ethernet test frames.

Loopback function

Supports inloops on Ethernet ports (at the PHY layer or MAC layer).

The N1EFS0, N2EFS0, and N4EFS0 support inloops and outloops


at the VC-3 level. The N5EFS0 does not support inloops and
outloops at the VC-3 level.

Ethernet
performance
monitoring

Supports Ethernet performance monitoring at the port level.

Alarms and
performance events

Reports various alarms and performance events, which facilitates the


management and maintenance of the equipment.

7.4.3 Working Principle and Signal Flow


The EFS0 consists of the Ethernet access module, network processor module, mapping module,
interface converting module, logic and control module, clock module, and power module.
Figure 7-14 shows the functional block diagram of the EFS0 by describing how to process 1xFE
signals.
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Figure 7-14 Functional block diagram of the EFS0


Backplane

Switch
fabric

Data
Network processor module

Laser
shutdown

VCP

Control

DENCP

Network
processor

ENCP

Ethernet
FE
access
module

Interface
converting
module

Cross-connect unit

Cross-connect unit

Mapping module

LOS
Communication
Reference clock and frame header

Logic and
control module

+3.3 V
Clock module

Power Fuse
module

Power
module

SCC unit
SCC unit
-48 V/-60 V
-48 V/-60 V

50 77 125 155
MHz MHz MHz MHz

ENCP: data encapsulation module

DENCP: decapsulation module

VCP: virtual concatenation processing module

Ethernet Access Module


In the receive direction, the optical signals from Ethernet equipment such as switches or routers
are converted into electrical signals. If the signals are accessed through electrical interfaces, O/
E conversion is not required. At the PHY layer, the electrical signals are decoded and the
ETH_LOS alarm is detected. The electrical signals are converted from serial signals into parallel
signals and then sent to the network processor module.
In the transmit direction, the parallel signals are converted into serial signals. At the PHY layer,
signals are encoded and converted from electrical signals to optical signals.

Network Processor Module


The network processor module consists of the network processor and switch fabric. The network
processor first performs MAC functions, which include code conversion, framing of Ethernet
packets, CRC check, and Ethernet performance statistics.
After the striped Ethernet frames enter the core of network processor, the flow is classified
according to the service type and configuration requirement. The frames are encapsulated or
decapsulated. The following formats are supported:

7-42

Multi-protocol label switching (MPLS)

L2 MPLS VPN

Ethernet/VLAN
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In the receive direction, services are mapped and forwarded after the Tunnel and VC tags are
added according to the service configuration. In the transmit direction, the Tunnel or VC tag is
extracted based on the level (P or PE) of the equipment. Services are then routed or forwarded.
The network processor module supports the following functions:
l

Flow sense and flow classification

Unicast, multicast, and broadcast of the flow

Setting of data priorities

Weighted fair queuing (WFQ)

Four classes of service (CoSs)

Mapping Module
The mapping module performs encapsulation and mapping functions.
In the upstream direction, this module first encapsulates Ethernet signals in LAPS or GFP format.
The concatenation is performed. Then, the Ethernet signals are converted into SDH signals.
In the downstream direction, SDH signals are demapped. The delay of virtual concatenation is
compensated. After aligning, packets are decapsulated according to the encapsulation format.
The decapsulated data is finally transmitted to the network processor module in packets.

Interface Converting Module


The interface converting module converts the 622 Mbit/s LVDS bus of the SDH system into the
parallel bus. The high-rate backplane interface is connected to the low-rate interface chip of the
transmit system through the interface converting module.

Logic and Control Module


The logic and control module consists of the CPU, register, oscillator, Ethernet port, and HDLC
controller. This module is connected to external circuits through the bus. The logic and control
module performs the following functions:
l

Manages and configures other modules of the board.

Implements inter-board communication through the internal Ethernet interface.

The control module also contains basic logic units. This module performs the following
functions:
l

Writes and reads the register.

Provides interfaces for the CPU.

Checks and selects the clock.

Performs phase discrimination and frequency division on the clock.

Checks the in-service state of the cross-connect, SCC, and line boards.

Controls the shutting down of the optical module.

Implements communication.

Controls indicators.

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Clock Module
The clock module traces the system reference clock and generates the required working clock
for each chip. The frequency of the clock can be 50 MHz, 77 MHz, 125 MHz, or 155 MHz.

Power Module
It converts the 48 V/60 V power supply into the DC voltages that the modules of the board
require.

7.4.4 Front Panel


The front panel of the EFS0 has indicators and a bar code.

Diagram of the Front Panel


Figure 7-15 shows the appearance of the front panel of the EFS0.
Figure 7-15 Front panel of the EFS0

EFS0
STAT
ACT
PROG
SRV

EFS0

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Indicators
The front panel of the board has the following indicators:
l

Board hardware status indicator (STAT) two colors (red and green)

Service activation status indicator (ACT) one color (green)

Board software status indicator (PROG) two colors (red and green)

Service alarm indicator (SRV) three colors (red, green, and yellow)

For the meanings of the status of the indicators, see A Indicators.

Interfaces
The front panel of the EFS0 has no interfaces. The interfaces are available on the ETF8 or on
the EFF8. When the N5EFS0 is used with the ETF8A or EFF8A, the interfaces are available on
the ETF8A or on the EFF8A.

7.4.5 Valid Slots


The EFS0 can be installed in slots 37 and 1216 in the subrack. The bandwidth of the N1EFS0
is 622 Mbit/s and the bandwidth of the N2EFS0/N4EFS0/N5EFS0 is 1.25 Gbit/s.
The EFS0 can be used with the ETF8, EFF8, and ETS8. When the ETS8 is used as the interface
board, the TSB8 must be used as the bridging board. For the slots valid for the EFS0, ETS8, and
TSB8 when the EFS0 works with the ETS8 and TSB8, see 7.4.6 Board Protection.
The N5EFS0 can be used with the ETF8A and EFF8A. When the N5EFS0 works with the ETF8A
or EFF8A, the slots valid for the N5EFS0 are the same as the slots valid for the N5EFS0 when
the N5EFS0 works with the ETF8 or EFF8.
Table 7-27 lists the slots valid for the EFS0 and the corresponding slots for the ETF8 and EFF8.
Table 7-27 Slots valid for the EFS0 and the corresponding slots for the ETF8 and EFF8

Issue 02 (2009-07-30)

Slot Valid for the EFS0

Corresponding Slot for the ETF8 and EFF8

Slot 3

Slot 21

Slot 4

Slot 23

Slot 5

Slot 25

Slot 6

Slot 27

Slot 7

Slot 29

Slot 12

Slot 32

Slot 13

Slot 34

Slot 14

Slot 36

Slot 15

Slot 38
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Slot Valid for the EFS0

Corresponding Slot for the ETF8 and EFF8

Slot 16

Slot 40

7.4.6 Board Protection


The EFS0 supports the 1:1 TPS protection.
Figure 7-16 shows the slot configuration for the 1:1 TPS protection for the EFS0.
Figure 7-16 Slot configuration for the 1:1 TPS protection for the EFS0

S
L
O
T
21

S
L
O
T
22

S
L
O
T
23

S
L
O
T
24

S S
L L
O O
T T
25 26

S
L
O
T
27

S
L
O
T
28

S
L
O
T
29

S S
L L
O O
T T
30 31

S
L
O
T
32

S
L
O
T
33

S
L
O
T
34

S
L
O
T
35

S
L
O
T
36

S S S
L L L
O O O
T T T
37 38 39

S
L
O
T
7

S
L
O
T
8

S S
L L
O O
T T
11 12

S S
L L
O O
T T
13 14

S S
L L
O O
T T
15 16

SLOT 42 AUX

Protection 2

S
L
O
T
10

Working 2

S
L
O
T
9

SLOT 43 EOW

S
L
O
T
6

CXL

S
L
O
T
5

FA
N

CXL

S
L
O
T
4

Working 1

SLOT 41 PIU

S
L
O
T
3

Protection 1

SLOT 1 PIU

S
L
O
T
2

FA
N

TSB8

ETS8

ETS8

TSB8

FA
N

S
L
O
T
40

Fiber routing area

In Figure 7-16, the board in slot 3 protects the board in slot 4 and the board in slot 16 protects
the board in slot 15. The ETS8 is used with the working EFS0 and the TSB8 is used with the
protection EFS0. Table 7-28 lists the slots for the EFS0, ETS8, and TSB8.
Table 7-28 Slots for the EFS0, ETS8, and TSB8

7-46

Board

Protection Group 1

Protection Group 2

EFS0 (protection)

Slot 3

Slot 16

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Board

Protection Group 1

Protection Group 2

EFS0 (working)

Slot 4

Slot 15

TSB8

Slot 21

Slot 39

ETS8

Slot 23

Slot 37

7.4.7 Parameter Settings


You can set the parameters for the EFS0 by using the T2000.
You can set the following parameters for the EFS0 by using the T2000:
l

Working mode

LCAS

Maximum frame length

Mapping protocol

For the description of each parameter, see F Parameter Settings.

7.4.8 Technical Specifications


The technical specifications of the EFS0 include the dimensions, weight, and power
consumption.

Ethernet Performance Specifications


Figure 7-17 shows the connection for testing the throughput specifications, packet loss ratio in
the case of overloading, latency specifications, and back-to-back specifications of the EFS0.
Figure 7-17 Connection for testing the throughput specifications, packet loss ratio in the case
of overloading, latency specifications, and back-to-back specifications
Tested
equipment 1

Tested
equipment 2

Port 1

Port 2
Data network
performance
analyzer

Table 7-29 lists the throughput specifications of the EFS0. Table 7-30 lists the packet loss ratio
in the case of overloading of the EFS0. Table 7-31 lists the latency specifications of the EFS0.
Table 7-32 lists the back-to-back specifications of the EFS0.
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NOTE

The specifications vary according to the configuration and networking of the test environment, port
rate, and VC services bound on the VCG side. The specifications that are obtained in the actual
environment are used.

The specifications in the following tables are obtained in the following scenario: EPL services are
configured and five VC-12s are bound on the FE port.

The specifications of a board of a specific version are not provided because the board version has
negligible effect on the specifications.

The specifications in the following tables are obtained by using the Smart Application.

Table 7-29 Throughput specifications of the EFS0


Frame Size
(Byte)

Passed Rate
(%)

(01,02,03) to
(01,02,05) (pks/
sec)

(01,02,05) to
(01,02,03) (pks/
sec)

Total (pks/
sec)

64

11.48

17088

17088

34176

128

11.25

9502

9502

19004

256

11.13

5042

5042

10084

512

11.12

2613

2613

5226

1024

11.07

1326

1326

2652

1280

11.10

1067

1067

2134

1518

11.12

904

904

1808

NOTE

The specifications in the preceding table are obtained in the scenario wherein point-to-point transparent
transmission services are configured and the flow control function is disabled.

The permitted packet loss ratio is set to 0% and the resolution rate is set to 0.1%.

The test duration is set to 60 seconds.

Minimum frame size (byte): 64

Maximum frame size (byte): 1518

Step frame size (byte): custom

Number of pairs: 1

Initial rate (%): 10.00

Maximum rate (%): 12.00

Mode: bidirectional

Table 7-30 Packet loss ratio in the case of overloading of the EFS0

7-48

Frame Size
(Byte)

Rate Tested
(%)

(01,02,03) to
(01,02,05) (%)

(01,02,05) to
(01,02,03) (%)

Average (%)

64

100.00

88.507

88.507

88.507

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Frame Size
(Byte)

Rate Tested
(%)

(01,02,03) to
(01,02,05) (%)

(01,02,05) to
(01,02,03) (%)

Average (%)

128

100.00

88.730

88.745

88.737

256

100.00

88.851

88.831

88.841

512

100.00

88.876

88.846

88.861

1024

100.00

88.901

88.890

88.895

1280

100.00

88.878

88.878

88.878

1518

100.00

88.850

88.844

88.847

NOTE

The specifications in the preceding table are obtained in the scenario wherein point-to-point transparent
transmission services are configured and the flow control function is disabled.

The tested traffic starts from the throughput and increases to 100% in 10% steps.

The test duration is set to 60 seconds.

Minimum frame size (byte): 64

Maximum frame size (byte): 1518

Step frame size (byte): custom

Number of pairs: 1

Initial rate (%): 100.00

Maximum rate (%): 10.00

Resolution rate (%): none

Mode: bidirectional

Table 7-31 Latency specifications of the EFS0

Issue 02 (2009-07-30)

Frame
Size
(Byte)

Rate
Tested
(%)

(01,02,03) to
(01,02,05) (us)CT (us)

Average
(CT) (us)

(01,02,03) to
(01,02,05)
(us)-S&F (us)

Average
(S&F) (us)

64

10.00

561.4

561.4

556.2

556.2

128

10.00

644.4

644.4

634.2

634.2

256

10.00

738.4

738.4

718.0

718.0

512

10.00

948.8

948.8

907.9

907.9

1024

10.00

1371.5

1371.5

1289.6

1289.6

1280

10.00

1604.1

1604.1

1501.7

1501.7

1518

10.00

1790.4

1790.4

1669.0

1669.0

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NOTE

The specifications in the preceding table are obtained in the scenario wherein point-to-point transparent
transmission services are configured and the flow control function is disabled.

The test duration is set to 60 seconds.

The latency modes are classified into two modes, namely, cut through mode and store forward mode.
In cut through mode, the analyzer calculates the difference between the time when the first bit of the
transmitted frame reaches the output port and the time when the first bit of the transmitted frame reaches
the input port. In store forward mode, the analyzer calculates the difference between the time when the
first bit of the transmitted frame reaches the output port and the time when the last bit of the transmitted
frame reaches the input port. In the preceding table, the CT values are obtained in cut through mode
and the S&F values are obtained in store forward mode.

CT: cut through or FIFO; S&F: store forward or LIFO

Measure on one receiving card only. Mode: SmartMetrics Comp. Mode

Minimum frame size (byte): 64

Maximum frame size (byte): 1518

Step frame size (byte): custom

Number of pairs: 1

Initial rate (%): 10.00

Maximum rate (%): 10.00

Resolution rate (%): none

Mode: bidirectional

Table 7-32 Back-to-back specifications of the EFS0

7-50

Frame Size
(Byte)

Rate Tested
(%)

(01,02,03) to
(01,02,05) Burst
Size (Number of
Frames)

(01,02,05) to
(01,02,03)
(Number of
Frames)

Total
(Number of
Frames)

64

100.00

1333

1335

2668

128

100.00

848

850

1698

256

100.00

586

587

1173

512

100.00

445

447

892

1024

100.00

224

224

448

1280

100.00

211

212

423

1518

100.00

201

201

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NOTE

The specifications in the preceding table are obtained in the scenario wherein point-to-point transparent
transmission services are configured and the flow control function is disabled.

The frame size is set to the range from 64 bytes to 1518 bytes, the packet transmission rate is set to
100%, the test duration is set to 2 seconds, and the number of repetitions is set to a value more than 50
on the Smart Application.

The tested traffic is set to the wire speed.

The test duration is set to 10 seconds.

Minimum frame size (byte): 64

Maximum frame size (byte): 1518

Step frame size (byte): custom

Number of pairs: 1

Initial rate (%): 100.00

Maximum rate (%): 10.00

Resolution rate (%): none

Mode: bidirectional

Mechanical Specifications
The mechanical specifications of the EFS0 are as follows:
l

Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)

Weight of the N1EFS0 (kg): 1.0

Weight of the N2EFS0 or N4EFS0 (kg): 1.0

Weight of the N5EFS0 (kg): 0.6

Power Consumption
The maximum power consumption of the N1EFS0 at room temperature (25C) is 35 W.
The maximum power consumption of the N2EFS0 and N4EFS0 at room temperature (25C) is
35 W.
The maximum power consumption of the N5EFS0 at room temperature (25C) is 22 W.

7.5 EFS0A
This topic describes the version, functions, working principle, valid slots, and technical
specification of the EFS0A (16xFE switching and processing board).
7.5.1 Version Description
The EFS0A is available in one functional version, namely, N1.
7.5.2 Functions and Features
The EFS0A supports the Layer 2 switching, MPLS, and broadcast functions.
7.5.3 Working Principle and Signal Flow
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The EFS0A consists of the Ethernet access module, network processor module, mapping
module, interface converting module, logic and control module, clock module, and power
module.
7.5.4 Front Panel
The front panel of the EFS0A has indicators and a bar code.
7.5.5 Valid Slots
The EFS0A can be installed in slots 37 and 1216 in the subrack.
7.5.6 Board Protection
The EFS0A supports the 1:1 TPS protection.
7.5.7 Parameter Settings
You can set the parameters for the EFS0A by using the T2000.
7.5.8 Technical Specifications
The technical specifications of the EFS0A include the dimensions, weight, and power
consumption.

7.5.1 Version Description


The EFS0A is available in one functional version, namely, N1.

7.5.2 Functions and Features


The EFS0A supports the Layer 2 switching, MPLS, and broadcast functions.
Table 7-33 provides the functions and features of the EFS0A.
Table 7-33 Functions and features of the EFS0A
Function and
Feature

EFS0A

Basic functions

Processes 16xFE services and supports the convergence of 100x10


Mbit/s or 12x100 Mbit/s services.

Functions when being


used with the interface
board

Accesses 16xFE signals through the electrical interface when the


EFS0A is used with the ETF8.

Accesses 16xFE signals through the optical interface when the


EFS0A is used with the EFF8.

Provides the TPS protection for the 16xFE signals through the
electrical interface when the EFS0A is used with the ETS8 and
TSB8.

Supports 10BASE-T/100BASE-TX signals when the EFS0A is


used with the ETF8.

Supports 100BASE-FX signals when the EFS0A is used with the


EFF8. The optical interfaces comply with IEEE 802.3u.

Specifications of the
optical interface

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Function and
Feature

EFS0A

Format of service
frames

Supports Ethernet II, IEEE 802.3, and IEEE 802.1 q/p formats.

Supports the frame with a length ranging from 64 bytes to 9600


bytes.

Supports the Jumbo frame with a length less than 9600 bytes.

Maximum uplink
bandwidth

The maximum uplink bandwidth is 2.5 Gbit/s.

VCTRUNKs

Number of supported VCTRUNKs: 32

The EFS0A can adapt to the bandwidth of the slot.

Configuration principles are as follows:

Issue 02 (2009-07-30)

VC-4s numbered 4, 8, 12, and 16 support the binding of VC-3


and VC-12 paths. The other VC-4s support the binding of VC-3
paths only.

A VC-4 cannot be bound with VC-3 and VC-12 paths at the same
time.

Mapping granularities

Supports VC-12, VC-3, VC-12-Xv (X63), and VC-3-Xv (X12)


granularities.

Encapsulation format

Supports the GFP-F protocol.

EPL services

Supports the PORT-based transparent transmission.

EVPL services

Supports PORT+VLAN-based EVPL services that use the frame


encapsulation formats of MartinioE and stack VLAN.

EPLAN services

The services that are based on the IEEE 802.1d MAC bridge are
referred to as EPLAN service.
l

Supports the Layer 2 convergence and P2MP convergence.

Supports the Layer 2 forwarding function.

Supports switching on the client and SDH sides.

Supports the self-learning of the source MAC address. The


capacity of the MAC address table is 16K. The aging time of the
MAC address can be set and queried.

Supports the configuration of the static MAC route.

The N1EFS0, N2EFS0, and N5EFS0 support the query of the


dynamic MAC address.

Support the query of the dynamic MAC address.

Supports the creation, deletion, and query of the VB. The


maximum number of supported VBs is 16. The maximum
number of logical ports for each VB is 30.

Supports the data isolation based on VB+VLAN.

Queries the number of actually learnt MAC addresses based on


VB+VLAN or VB+LP.

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Function and
Feature

EFS0A

MTU

Supports the setting of the packet length, which ranges from 1518
bytes to 9600 bytes. After the setting becomes valid, the length of
the packets that enter or exit the IP ports is limited.

MPLS

Supports the MPLS.

VLAN

Complies with IEEE 802.1q/p.

VLAN convergence

Supports the VLAN convergence.


The number of VLANs is 4K.

RSTP

Supports the broadcast packet suppression function and RSTP that


comply with IEEE 802.1w.

Link aggregation
function

Supports manual link aggregation.

Multicast function

Supports the multicast function.

ETH-OAM function

Supports CC for the multicast service, LB test for the unicast service,
LT test, LD, auto-negotiation, fault diagnosis, and link performance
detection.

CAR

Supports the CAR.


The granularity is 64 kbit/s.

Service-based

Supports the flow classification based on PORT, PORT+VLAN ID,


or PORT+VLAN ID+VLAN PRI.

QoS flow
classification

7-54

LCAS function

Dynamically increases or decreases the bandwidth and protects the


bandwidth in compliance with ITU-T G.7042.

LPT function

Supports the P2P LPT and P2MP LPT.

Flow control function

Supports the port-based flow control function that complies with


IEEE 802.3x.

Test frames

Receives and transmits Ethernet test frames.

Port mirroring

Supports ingress mirroring.

Loopback function

Supports inloops on Ethernet ports (at the PHY layer or MAC layer).

Ethernet performance
monitoring

Supports Ethernet performance monitoring at the port level.

Alarms and
performance events

Reports various alarms and performance events, which facilitates


the management and maintenance of the equipment.

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7.5.3 Working Principle and Signal Flow


The EFS0A consists of the Ethernet access module, network processor module, mapping
module, interface converting module, logic and control module, clock module, and power
module.
Figure 7-18 shows the functional block diagram of the EFS0A by describing how to process
1xFE signals.
Figure 7-18 Functional block diagram of the EFS0A
Backplane

Control

Switch
fabric

Data
Network processor module

Laser
shutdown

VCP

Network
processor

DENCP

Ethernet
access
module

ENCP

FE

Interface
converting
module

Cross-connect unit

Cross-connect unit

Mapping module

LOS
Logic and
control module

Communication
Reference clock and frame header
+3.3 V

Clock module

Power Fuse
module

Power
module

SCC unit
SCC unit
-48 V/-60 V
-48 V/-60 V

50 77 125 155
MHz MHz MHz MHz

ENCP: data encapsulation module

DENCP: decapsulation module

VCP: virtual concatenation processing module

Ethernet Access Module


In the receive direction, the optical signals from Ethernet equipment such as switches or routers
are converted into electrical signals. If the signals are accessed through electrical interfaces, O/
E conversion is not required. At the PHY layer, the electrical signals are decoded and the
ETH_LOS alarm is detected. The electrical signals are converted from serial signals into parallel
signals and then sent to the network processor module.
In the transmit direction, the parallel signals are converted into serial signals. At the PHY layer,
signals are encoded and converted from electrical signals to optical signals.

Network Processor Module


The network processor module consists of the network processor and switch fabric. The network
processor first performs MAC functions, which include code conversion, framing of Ethernet
packets, CRC check, and Ethernet performance statistics.
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After the striped Ethernet frames enter the core of network processor, the flow is classified
according to the service type and configuration requirement. The frames are encapsulated or
decapsulated. The following formats are supported:
l

MPLS

L2 MPLS VPN

Ethernet/VLAN

In the receive direction, services are mapped and forwarded after the Tunnel and VC tags are
added according to the service configuration. In the transmit direction, the Tunnel or VC tag is
extracted based on the level (P or PE) of the equipment. Services are then routed or forwarded.
The network processor module supports the following functions:
l

Flow sense and flow classification

Unicast, multicast, and broadcast of the flow

Setting of data priorities

WFQ

Four CoSs

Mapping Module
The mapping module performs encapsulation and mapping functions.
In the upstream direction, this module first encapsulates Ethernet signals in LAPS or GFP format.
The concatenation is performed. Then, the Ethernet signals are converted into SDH signals.
In the downstream direction, SDH signals are demapped. The delay of virtual concatenation is
compensated. After aligning, packets are decapsulated according to the encapsulation format.
The decapsulated data is finally transmitted to the network processor module in packets.

Interface Converting Module


The interface converting module converts the 622 Mbit/s LVDS bus of the SDH system into the
parallel bus. The high-rate backplane interface is connected to the low-rate interface chip of the
transmit system through the interface converting module.

Logic and Control Module


The logic and control module consists of the CPU, register, oscillator, Ethernet port, and HDLC
controller. This module is connected to external circuits through the bus. The logic and control
module performs the following functions:
l

Manages and configures other modules of the board.

Implements inter-board communication through the internal Ethernet interface.

The control module also contains basic logic units. This module performs the following
functions:

7-56

Writes and reads the register.

Provides interfaces for the CPU.

Checks and selects the clock.


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Performs phase discrimination and frequency division on the clock.

Checks the in-service state of the cross-connect, SCC, and line boards.

Controls the shutting down of the optical module.

Implements communication.

Controls indicators.

7 Data Boards

Clock Module
The clock module traces the system reference clock and generates the required working clock
for each chip. The frequency of the clock can be 50 MHz, 77 MHz, 125 MHz, or 155 MHz.

Power Module
It converts the 48 V/60 V power supply into the DC voltages that the modules of the board
require.

7.5.4 Front Panel


The front panel of the EFS0A has indicators and a bar code.

Diagram of the Front Panel


Figure 7-19 shows the appearance of the front panel of the EFS0A.

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Figure 7-19 Front panel of the EFS0A

EFS0A
STAT
ACT
PROG
SRV

EFS0A

Indicators
The front panel of the board has the following indicators:
l

Board hardware status indicator (STAT) two colors (red and green)

Service activation status indicator (ACT) one color (green)

Board software status indicator (PROG) two colors (red and green)

Service alarm indicator (SRV) three colors (red, green, and yellow)

For the meanings of the status of the indicators, see A Indicators.

Interfaces
The front panel of the EFS0A has no interfaces. The interfaces are available on the ETF8 board
or on the EFF8 board.
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7.5.5 Valid Slots


The EFS0A can be installed in slots 37 and 1216 in the subrack.
The EFS0A can be used with the ETF8, EFF8, and ETS8. When the ETS8 is used as the interface
board, the TSB8 must be used as the bridging board. For the slots valid for the EFS0A, ETS8,
and TSB8 when the EFS0A works with the ETS8 and TSB8, see 7.5.6 Board Protection.
Table 7-34 lists the slots valid for the EFS0A and the corresponding slots for the ETF8 and
EFF8.
Table 7-34 Slots valid for the EFS0A and the corresponding slots for the ETF8 and EFF8
Slot Valid for the EFS0A

Corresponding Slot for the ETF8 and EFF8

Slot 3

Slots 21 and 22

Slot 4

Slots 23 and 24

Slot 5

Slots 25 and 26

Slot 6

Slots 27 and 28

Slot 7

Slots 29 and 30

Slot 12

Slots 31 and 32

Slot 13

Slots 33 and 34

Slot 14

Slots 35 and 36

Slot 15

Slots 37 and 38

Slot 16

Slots 39 and 40

7.5.6 Board Protection


The EFS0A supports the 1:1 TPS protection.
Figure 7-20 shows the slot configuration for the 1:1 TPS protection for the EFS0A.

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Figure 7-20 Slot configuration for the 1:1 TPS protection for the EFS0A

TSB8

TSB8

ETS8
ETS8

S
L
O
T
24

S S
L L
O O
T T
25 26

S
L
O
T
27

S
L
O
T
28

S
L
O
T
29

S S
L L
O O
T T
30 31

FA
N

S
L
O
T
33

S
L
O
T
34

FA
N

S
L
O
T
35

S
L
O
T
36

S S S
L L L
O O O
T T T
37 38 39

S
L
O
T
7

S
L
O
T
8

S S
L L
O O
T T
11 12

S S
L L
O O
T T
13 14

S S
L L
O O
T T
15 16

SLOT 42 AUX

Protection 2

S
L
O
T
10

Working 2

S
L
O
T
9

SLOT 43 EOW

S
L
O
T
6

CXL

S
L
O
T
5

S
L
O
T
40

FA
N

CXL

S
L
O
T
4

Working 1

SLOT 41 PIU

S
L
O
T
3

Protection 1

SLOT 1 PIU

S
L
O
T
2

S
L
O
T
32

TSB8

S
L
O
T
23

TSB8
ETS8

S
L
O
T
22

ETS8

S
L
O
T
21

Fiber routing area

The board in slot 3 protects the board in slot 4. The board in slot 16 protects the board in slot
15. The ETS8 is used with the working EFS0A and the TSB8 is used with the protection EFS0A.
Table 7-35 lists the slots for the EFS0A, ETS8, and TSB8.
Table 7-35 Slots for the EFS0A, ETS8, and TSB8
Board

Protection Group 1

Protection Group 2

EFS0A (protection)

Slot 3

Slot 16

EFS0A (working)

Slot 4

Slot 15

TSB8

Slots 21 and 22

Slots 39 and 40

ETS8

Slots 23 and 24

Slots 37 and 38

7.5.7 Parameter Settings


You can set the parameters for the EFS0A by using the T2000.
You can set the following parameters for the EFS0A by using the T2000:
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Working mode

LCAS

Maximum frame length

Mapping protocol

7 Data Boards

For the description of each parameter, see F Parameter Settings.

7.5.8 Technical Specifications


The technical specifications of the EFS0A include the dimensions, weight, and power
consumption.

Ethernet Performance Specifications


Figure 7-21 shows the connection for testing the throughput specifications, packet loss ratio in
the case of overloading, latency specifications, and back-to-back specifications of the EFS0A.
Figure 7-21 Connection for testing the throughput specifications, packet loss ratio in the case
of overloading, latency specifications, and back-to-back specifications
Tested
equipment 1

Tested
equipment 2

Port 1

Port 2
Data network
performance
analyzer

Table 7-36 lists the throughput specifications of the EFS0A. Table 7-37 lists the packet loss
ratio in the case of overloading of the EFS0A. Table 7-38 lists the latency specifications of the
EFS0A. Table 7-39 lists the back-to-back specifications of the EFS0A.
NOTE

Issue 02 (2009-07-30)

The specifications vary according to the configuration and networking of the test environment, port
rate, and VC services bound on the VCG side. The specifications that are obtained in the actual
environment are used.

The specifications in the following tables are obtained in the following scenario: EPL services are
configured, one VC-3 is bound on the FE port, and the MAC port is set to auto-negotiation mode.

The specifications of a board of a specific version are not provided because the board version has
negligible effect on the specifications.

The specifications in the following tables are obtained by using the Smart Application.

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Table 7-36 Throughput specifications of the EFS0A


Frame Size
(Byte)

Passed Rate
(%)

(01,11,01) to
(01,11,02) (pks/
sec)

(01,11,02) to
(01,11,01) (pks/
sec)

Total (pks/
sec)

64

53.50

79618

79618

159236

128

51.21

43253

43253

86506

256

49.95

22624

22624

45248

512

49.31

11585

11585

23170

1024

49.14

5884

5884

11768

1280

49.15

4726

4726

9452

1518

49.19

3998

3998

7996

NOTE

Test duration (sec): 3

Minimum frame size (byte): 64

Maximum frame size (byte): 1518

Step frame size (byte): custom

Number of pairs: 1

Initial rate (%): 53.33

Maximum rate (%): 54.00

Resolution rate (%): 0.01

Mode: bidirectional

Table 7-37 Packet loss ratio in the case of overloading of the EFS0A

7-62

Frame Size
(Byte)

Rate Tested
(%)

(01,11,01) to
(01,11,02) (%)

(01,11,02) to
(01,11,01) (%)

Average (%)

64

100.00

46.497

46.497

46.497

128

100.00

48.820

48.820

48.820

256

100.00

50.127

50.127

50.127

512

100.00

50.804

50.804

50.804

1024

100.00

51.115

51.115

51.115

1280

100.00

51.159

51.159

51.159

1518

100.00

51.176

51.176

51.176

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NOTE

Test duration (sec): 10

Minimum frame size (byte): 64

Maximum frame size (byte): 1518

Step frame size (byte): custom

Number of pairs: 1

Initial rate (%): 100.00

Maximum rate (%): 10.00

Resolution rate (%): none

Mode: bidirectional

Table 7-38 Latency specifications of the EFS0A

Issue 02 (2009-07-30)

Frame
Size
(Byte)

Rate
Tested
(%)

(01,11,01) to
(01,11,02) (us)CT (us)

Average
(CT) (us)

(01,11,01) to
(01,11,02)
(us)-S&F (us)

Average
(S&F) (us)

64

40.00

164.3

164.3

159.2

159.2

128

40.00

199.0

199.0

188.8

188.8

256

40.00

247.0

247.0

226.6

226.6

512

40.00

357.6

357.6

357.6

357.6

1024

40.00

514.8

514.8

432.9

432.9

1280

40.00

613.1

613.1

510.7

510.7

1518

40.00

699.4

699.4

578.0

578.0

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NOTE

The latency modes are classified into two modes, namely, cut through mode and store forward mode.
In cut through mode, the analyzer calculates the difference between the time when the first bit of the
transmitted frame reaches the output port and the time when the first bit of the transmitted frame reaches
the input port. In store forward mode, the analyzer calculates the difference between the time when the
first bit of the transmitted frame reaches the output port and the time when the last bit of the transmitted
frame reaches the input port. In the preceding table, the CT values are obtained in cut through mode
and the S&F values are obtained in store forward mode.

CT: cut through or FIFO; S&F: store forward or LIFO

Measure on one receiving card only. Mode: SmartMetrics Comp. Mode

Test duration (sec): 100

Minimum frame size (byte): 64

Maximum frame size (byte): 1518

Step frame size (byte): custom

Number of pairs: 1

Initial rate (%): 100.00

Maximum rate (%): 10.00

Resolution rate (%): none

Mode: bidirectional

Table 7-39 Back-to-back specifications of the EFS0A

7-64

Frame Size
(Byte)

Rate Tested
(%)

(01,11,01) to
(01,11,02) Burst
Size (Number of
Frames)

(01,11,02) to
(01,11,01)
(Number of
Frames)

Total
(Number of
Frames)

64

100.00

353

353

706

128

100.00

342

342

684

256

100.00

380

380

761

512

100.00

368

368

736

1024

100.00

282

282

564

1280

100.00

279

279

559

1518

100.00

291

291

582

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NOTE

Test duration (sec): 2

Minimum frame size (byte): 64

Maximum frame size (byte): 1518

Step frame size (byte): custom

Number of pairs: 1

Initial rate (%): 100.00

Maximum rate (%): 10.00

Resolution rate (%): none

Mode: bidirectional

Mechanical Specifications
The mechanical specifications of the EFS0A are as follows:
l

Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)

Weight (kg): 0.7

Power Consumption
The maximum power consumption of the EFS0A at room temperature (25C) is 32 W.

7.6 EFS4
This topic describes the version, functions, working principle, valid slots, and technical
specification of the EFS4 (4xFE switching and processing board).
7.6.1 Version Description
The EFS4 is available in three functional versions, namely, N1, N2 and N3. The difference
between the three versions is their different maximum uplink bandwidths. The N1EFS4 is no
longer manufactured.
7.6.2 Functions and Features
The EFS4 supports the Layer 2 switching, MPLS, and broadcast functions.
7.6.3 Working Principle and Signal Flow
The EFS4 consists of the Ethernet access module, network processor module, mapping module,
interface converting module, logic and control module, clock module, and power module.
7.6.4 Front Panel
The front panel of the EFS4 has indicators, interfaces, and a bar code.
7.6.5 Valid Slots
The EFS4 can be installed in slots 28 and 1116 in the subrack.
7.6.6 Parameter Settings
You can set the parameters for the EFS4 by using the T2000.
7.6.7 Technical Specifications
The technical specifications of the EFS4 include the dimensions, weight, and power
consumption.
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7.6.1 Version Description


The EFS4 is available in three functional versions, namely, N1, N2 and N3. The difference
between the three versions is their different maximum uplink bandwidths. The N1EFS4 is no
longer manufactured.
Table 7-40 describes the versions of the EFS4.
Table 7-40 Versions of the EFS4
Item

Description

Functional
version

The EFS4 is available in three functional versions, namely, N1, N2 and


N3.

Differences

The maximum uplink bandwidth of the N1EFS4 is 622 Mbit/s.

The maximum uplink bandwidth of the N2EFS4/N3EFS4 is 1.25 Gbit/


s.

The N2EFS4 and N3EFS4 support the board version replacement


function.

The N2EFS4 can substitute for the N1EFS4.

The N3EFS4 can substitute for the N2EFS4 and N1EFS4.

Substitution

7.6.2 Functions and Features


The EFS4 supports the Layer 2 switching, MPLS, and broadcast functions.
Table 7-41 provides the functions and features of the EFS4.
Table 7-41 Functions and features of the EFS4
Function and
Feature

EFS4

Basic functions

Processes 4xFE services and supports the convergence of 60x10 Mbit/


s or 4x100 Mbit/s services.

Specifications of the
optical interface

Supports 10BASE-T/100BASE-TX signals. The optical interfaces


comply with IEEE 802.3u.

Format of service
frames

Supports Ethernet II, IEEE 802.3, and IEEE 802.1 q/p formats.
Supports the frame with a length ranging from 64 bytes to 9600 bytes.
Supports the Jumbo frame with a length less than 9600 bytes.

Maximum uplink
bandwidth

7-66

The maximum uplink bandwidth of the N1EFS4 is 622 Mbit/s.

The maximum uplink bandwidth of the N2EFS4 and N3EFS4 is


1.25 Gbit/s.

The EFS4 can adapt to the bandwidth of the slot.

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Function and
Feature

EFS4

VCTRUNKs

The number of VCTRUNKs supported by the N1EFS4 is 12.

The number of VCTRUNKs supported by the N2EFS4 and N3EFS4


is 24.

Configuration principles are as follows:


VCTRUNK 1VCTRUNK 12 can be bound with VC-4s numbered
14 only. VCTRUNK 13VCTRUNK 24 can be bound with VC-4s
numbered 58 only.

VC-4s numbered 4 and 8 support the binding of VC-3 and VC-12


paths. The other VC-4s support the binding of VC-3 paths only.

A VC-4 cannot be bound with VC-3 and VC-12 paths at the same
time.

Mapping
granularities

Supports VC-12, VC-3, VC-12-Xv (X63), and VC-3-Xv (X12)


granularities.

Encapsulation
format

Supports the GFP-F protocol.

EPL services

Supports the PORT-based transparent transmission.

EVPL services

Supports PORT+VLAN-based EVPL services that use the frame


encapsulation formats of MartinioE and stack VLAN.

EPLAN services

The services that are based on the IEEE 802.1d MAC bridge are
referred to as EPLAN services.

MTU

Issue 02 (2009-07-30)

Supports the Layer 2 convergence and P2MP convergence.

Supports the Layer 2 forwarding function.

Supports switching on the client and SDH sides.

Supports the self-learning of the source MAC address. The capacity


of the MAC address table is 16K. The aging time of the MAC
address can be set and queried.

Supports the configuration of the static MAC route.

The N1EFS4 and N3EFS4 support the query of the dynamic MAC
address.

The N2EFS4 does not support the query of the dynamic MAC
address.

Supports the creation, deletion, and query of the VB. The maximum
number of supported VBs is 16. The maximum number of logical
ports for each VB is 30.

Supports the data isolation based on VB+VLAN.

Queries the number of actually learnt MAC addresses based on VB


+VLAN or VB+LP.

The packet length can be set from 1518 bytes to 9600 bytes. After the
packet length setting takes effect, the maximum length of the packets
entering or going out from the IP port are limited by the MTU setting.

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Function and
Feature

EFS4

MPLS

Supports the MPLS.

VLAN

Complies with IEEE 802.1q/p.

VLAN convergence Supports the VLAN convergence.


The maximum number of VLANs is 4K.
RSTP

Supports the broadcast packet suppression function and RSTP that


comply with IEEE 802.1w.

Link aggregation

Supports manual link aggregation.

Multicast function

Supports the multicast function.

ETH-OAM
function

The N1EFS4 does not support the ETH-OAM function.

The N2EFS4 and N3EFS4 support CC for the multicast service, LB


test for the unicast service, LT test, LD, auto-negotiation, fault
diagnosis, and link performance detection. The ETH-OAM function
complies with IEEE 802.1ag and IEEE 802.3ah.

CAR

Supports the CAR.


The granularity is 64 kbit/s.

Service-based QoS
flow classification

7-68

The N1EFS4 supports the service classification based on PORT,


PORT+VLAN ID, or PORT+VLAN PRI.

The N2EFS4 and N3EFS4 support the flow classification based on


PORT, PORT++VLAN ID, or PORT+VLAN ID+VLAN PRI.

LCAS function

Dynamically increases or decreases the bandwidth and protects the


bandwidth in compliance with ITU-T G.7042.

LPT function

The N1EFS4 supports the P2P LPT.

The N2EFS4 and N3EFS4 support the P2P LPT and P2MP LPT.

Flow control
function

Supports the port-based flow control function that complies with IEEE
802.3x.

Test frames

Receives and transmits Ethernet test frames.

Loopback function

Supports inloops on Ethernet ports (at the PHY layer or MAC layer).

Ethernet
performance
monitoring

Supports Ethernet performance monitoring at the port level.

Alarms and
performance events

Reports various alarms and performance events, which facilitates the


management and maintenance of the equipment.

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7.6.3 Working Principle and Signal Flow


The EFS4 consists of the Ethernet access module, network processor module, mapping module,
interface converting module, logic and control module, clock module, and power module.
Figure 7-22 shows the functional block diagram of the EFS4 by describing how to process 1xFE
signals.
Figure 7-22 Functional block diagram of the EFS4
Backplane

Data
Network processor module

VCP

Switch
fabric

DENCP

Network
processor

Control

ENCP

Ethernet
FE
access
module

Interface
converting
module

Cross-connect unit

Cross-connect unit

Mapping module

LOS
Logic and
control module

Communication
Reference clock and frame header
+3.3 V

Clock module

Power Fuse
module

Power
module

SCC unit
SCC unit
-48 V/-60 V
-48 V/-60 V

50 77 125 155
MHz MHz MHz MHz

ENCP: data encapsulation module

DENCP: decapsulation module

VCP: virtual concatenation processing module

Ethernet Access Module


In the receive direction, the Ethernet access module accesses the Ethernet electrical signals from
Ethernet equipment such as switches or routers. At the PHY layer, the electrical signals are
decoded and the ETH_LOS alarm is detected. The electrical signals are converted from serial
signals into parallel signals and then sent to the network processor module.
In the transmit direction, the parallel signals are converted into serial signals. At the PHY layer,
signals are encoded.

Network Processor Module


The network processor module consists of the network processor and switch fabric. The network
processor first performs MAC functions, which include code conversion, framing of Ethernet
packets, CRC check, and Ethernet performance statistics.
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After the striped Ethernet frames enter the core of network processor, the flow is classified
according to the service type and configuration requirement. The frames are encapsulated or
decapsulated. The following formats are supported:
l

MPLS

L2 MPLS VPN

Ethernet/VLAN

In the receive direction, services are mapped and forwarded after the Tunnel and VC tags are
added according to the service configuration. In the transmit direction, the Tunnel or VC tag is
extracted based on the level (P or PE) of the equipment. Services are then routed or forwarded.
The network processor module supports the following functions:
l

Flow sense and flow classification

Unicast, multicast, and broadcast of the flow

Setting of data priorities

WFQ

Four CoSs

Mapping Module
The mapping module performs encapsulation and mapping functions.
In the upstream direction, this module first encapsulates Ethernet signals in LAPS or GFP format.
The concatenation is performed. Then, the Ethernet signals are converted into SDH signals.
In the downstream direction, SDH signals are demapped. The delay of virtual concatenation is
compensated. After aligning, packets are decapsulated according to the encapsulation format.
The decapsulated data is finally transmitted to the network processor module in packets.

Interface Converting Module


The interface converting module converts the 622 Mbit/s LVDS bus of the SDH system into the
parallel bus. The high-rate backplane interface is connected to the low-rate interface chip of the
transmit system through the interface converting module.

Logic and Control Module


The logic and control module consists of the CPU, register, oscillator, Ethernet port, and HDLC
controller. This module is connected to external circuits through the bus. The logic and control
module performs the following functions:
l

Manages and configures other modules of the board.

Implements inter-board communication through the internal Ethernet interface.

The control module also contains basic logic units. This module performs the following
functions:

7-70

Writes and reads the register.

Provides interfaces for the CPU.

Checks and selects the clock.


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Performs phase discrimination and frequency division on the clock.

Checks the in-service state of the cross-connect, SCC, and line boards.

Implements communication.

Controls indicators.

7 Data Boards

Clock Module
The clock module traces the system reference clock and generates the required working clock
for each chip. The frequency of the clock can be 50 MHz, 77 MHz, 125 MHz, or 155 MHz.

Power Module
It converts the 48 V/60 V power supply into the DC voltages that the modules of the board
require.

7.6.4 Front Panel


The front panel of the EFS4 has indicators, interfaces, and a bar code.

Diagram of the Front Panel


Figure 7-23 shows the appearance of the front panel of the EFS4.

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Figure 7-23 Front panel of the EFS4

EFS4
STAT
ACT
PROG
SRV

FE1

FE2

FE3

FE4

EFS4

Indicators
The front panel of the board has the following indicators:
l

Board hardware status indicator (STAT) two colors (red and green)

Service activation status indicator (ACT) one color (green)

Board software status indicator (PROG) two colors (red and green)

Service alarm indicator (SRV) three colors (red, green, and yellow)

Connection status indicator (LINK) one color (green)

Data receiving and transmission indicator (ACT) one color (orange)

For the meanings of the status of the indicators, see A Indicators.

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Interfaces
The front panel of the EFS4 has four FE interfaces. Table 7-42 describes the types and usage
of the interfaces of the EFS4.
Table 7-42 Interfaces of the EFS4
Interface

Type of
Interface

Usage

FE1

RJ-45

Transmits and receives 10BASE-T/100BASE-TX


signals.

FE2

RJ-45

Transmits and receives 10BASE-T/100BASE-TX


signals.

FE3

RJ-45

Transmits and receives 10BASE-T/100BASE-TX


signals.

FE4

RJ-45

Transmits and receives 10BASE-T/100BASE-TX


signals.

Table 7-43 describes the pins of the RJ-45 connector.


Table 7-43 Pins of the RJ-45 connector
Pin

Description

Positive data transmit end

Negative data transmit end

Positive data receive end

Grounding

Grounding

Negative data receive end

Grounding

Grounding

7.6.5 Valid Slots


The EFS4 can be installed in slots 28 and 1116 in the subrack.
The slots valid for the EFS4 are as follows:
l

Issue 02 (2009-07-30)

When the N1EFS4 is installed in slots 28 and 1116, the bandwidth is 622 Mbit/s.

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l

When the N2EFS4 or N3EFS4 is installed in slots 28 and 1116, the bandwidth is 1.25
Gbit/s.

7.6.6 Parameter Settings


You can set the parameters for the EFS4 by using the T2000.
You can set the following parameters for the EFS4 by using the T2000:
l

Working mode

LCAS

Maximum frame length

Mapping protocol

For the description of each parameter, see F Parameter Settings.

7.6.7 Technical Specifications


The technical specifications of the EFS4 include the dimensions, weight, and power
consumption.

Ethernet Performance Specifications


Figure 7-24 shows the connection for testing the throughput specifications, packet loss ratio in
the case of overloading, latency specifications, and back-to-back specifications of the EFS4.
Figure 7-24 Connection for testing the throughput specifications, packet loss ratio in the case
of overloading, latency specifications, and back-to-back specifications
Tested
equipment 1

Tested
equipment 2

Port 1

Port 2
Data network
performance
analyzer

Table 7-44 lists the throughput specifications of the EFS4. Table 7-45 lists the packet loss ratio
in the case of overloading of the EFS4. Table 7-46 lists the latency specifications of the EFS4.
Table 7-47 lists the back-to-back specifications of the EFS4.

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NOTE

The specifications vary according to the configuration and networking of the test environment, port
rate, and VC services bound on the VCG side. The specifications that are obtained in the actual
environment are used.

The specifications in the following tables are obtained in the following scenario: EPL services are
configured and five VC-12s are bound on the FE port.

The specifications of a board of a specific version are not provided because the board version has
negligible effect on the specifications.

The specifications in the following tables are obtained by using the Smart Application.

Table 7-44 Throughput specifications of the EFS4


Frame Size
(Byte)

Passed Rate
(%)

(01,02,03) to
(01,02,05) (pks/
sec)

(01,02,05) to
(01,02,03) (pks/
sec)

Total (pks/
sec)

64

11.41

16984

16984

33968

128

11.18

9441

9441

18882

256

11.10

5026

5026

10052

512

11.09

2605

2605

5210

1024

11.00

1317

1317

2634

1280

11.09

1066

1066

2132

1518

11.07

900

900

1800

NOTE

Test duration (sec): 10

Minimum frame size (byte): 64

Maximum frame size (byte): 1518

Step frame size (byte): custom

Number of pairs: 1

Initial rate (%): 10.00

Maximum rate (%): 15.00

Resolution rate (%): 0.01

Mode: bidirectional

Table 7-45 Packet loss ratio in the case of overloading of the EFS4

Issue 02 (2009-07-30)

Frame Size
(Byte)

Rate Tested
(%)

(01,02,03) to
(01,02,05) (%)

(01,02,05) to
(01,02,03) (%)

Average (%)

64

100.00

88.510

88.513

88.512

128

100.00

88.724

88.729

88.726

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Frame Size
(Byte)

Rate Tested
(%)

(01,02,03) to
(01,02,05) (%)

(01,02,05) to
(01,02,03) (%)

Average (%)

256

100.00

88.858

88.859

88.859

512

100.00

88.858

88.861

88.859

1024

100.00

88.888

88.914

88.901

1280

100.00

88.895

88.875

88.885

1518

100.00

88.870

88.871

88.870

NOTE

Test duration (sec): 10

Minimum frame size (byte): 64

Maximum frame size (byte): 1518

Step frame size (byte): custom

Number of pairs: 1

Initial rate (%): 100.00

Maximum rate (%): 10.00

Resolution rate (%): none

Mode: bidirectional

Table 7-46 Latency specifications of the EFS4

7-76

Frame
Size
(Byte)

Rate
Tested
(%)

(01,02,03) to
(01,02,05) (us)CT (us)

Average
(CT) (us)

(01,02,03) to
(01,02,05)
(us)-S&F (us)

Average
(S&F) (us)

64

10.00

586.1

586.1

581.0

581.0

128

10.00

644.4

644.4

634.2

634.2

256

10.00

726.3

726.3

705.9

705.9

512

10.00

969.0

969.0

928.1

928.1

1024

10.00

1382.6

1382.6

1300.6

1300.6

1280

10.00

1609.0

1609.0

1506.6

1506.6

1518

10.00

1804.9

1804.9

1683.4

1683.4

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NOTE

The latency modes are classified into two modes, namely, cut through mode and store forward mode.
In cut through mode, the analyzer calculates the difference between the time when the first bit of the
transmitted frame reaches the output port and the time when the first bit of the transmitted frame reaches
the input port. In store forward mode, the analyzer calculates the difference between the time when the
first bit of the transmitted frame reaches the output port and the time when the last bit of the transmitted
frame reaches the input port. In the preceding table, the CT values are obtained in cut through mode
and the S&F values are obtained in store forward mode.

CT: cut through or FIFO; S&F: store forward or LIFO

Measure on one receiving card only. Mode: SmartMetrics Comp. Mode

Test duration (sec): 10

Minimum frame size (byte): 64

Maximum frame size (byte): 1518

Step frame size (byte): custom

Number of pairs: 1

Initial rate (%): 10.00

Maximum rate (%): 10.00

Resolution rate (%): none

Mode: bidirectional

Table 7-47 Back-to-back specifications of the EFS4

Issue 02 (2009-07-30)

Frame Size
(Byte)

Rate Tested
(%)

(01,02,03) to
(01,02,05) Burst
Size (Number of
Frames)

(01,02,05) to
(01,02,03)
(Number of
Frames)

Total
(Number of
Frames)

64

100.00

1337

1339

2676

128

100.00

852

852

1704

256

100.00

583

583

1166

512

100.00

441

441

882

1024

100.00

225

228

453

1280

100.00

210

210

420

1518

100.00

200

200

400

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NOTE

Test duration (sec): 10

Minimum frame size (byte): 64

Maximum frame size (byte): 1518

Step frame size (byte): custom

Number of pairs: 1

Initial rate (%): 100.00

Maximum rate (%): 10.00

Resolution rate (%): none

Mode: bidirectional

Mechanical Specifications
The mechanical specifications of the EFS4 are as follows:
l

Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)

Weight of the N1EFS4 or N2EFS4 (kg): 1.0

Weight of the N3EFS4 (kg): 0.6

Power Consumption
The maximum power consumption of the N1EFS4 and N2EFS4 at room temperature (25C) is
30 W.
The maximum power consumption of the N3EFS4 at room temperature (25C) is 18 W.

7.7 EGS2
This topic describes the version, functions, working principle, valid slots, and technical
specification of the EGS2 (2xGE switching and processing board).
7.7.1 Version Description
The EGS2 is available in two functional versions, namely, N2 and N3.
7.7.2 Functions and Features
The EGS2 supports the Layer 2 switching, MPLS, and broadcast functions.
7.7.3 Working Principle and Signal Flow
The EGS2 consists of the Ethernet access module, network processor module, mapping module,
interface converting module, logic and control module, clock module, and power module.
7.7.4 Front Panel
The front panel of the EGS2 has indicators, interfaces, a bar code, and a laser safety class label.
7.7.5 Valid Slots
The EGS2 can be installed in slots 28 and 1116 in the subrack.
7.7.6 Feature Code
The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the EGS2 indicates the type of interface.
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7.7.7 Parameter Settings


You can set the parameters for the EGS2 by using the T2000.
7.7.8 Technical Specifications
The technical specifications of the EGS2 include the parameters specified for optical interfaces,
laser safety class, Ethernet performance specifications, mechanical specifications, and power
consumption.

7.7.1 Version Description


The EGS2 is available in two functional versions, namely, N2 and N3.

7.7.2 Functions and Features


The EGS2 supports the Layer 2 switching, MPLS, and broadcast functions.
Table 7-48 provides the functions and features of the EGS2.
Table 7-48 Functions and features of the EGS2
Function and
Feature

EGS2

Basic functions

Processes 2xGE services and supports the convergence of 100x10 Mbit/


s or 10x100 Mbit/s services.

Specifications of
the optical
interface

Supports the 1000BASE-SX/LX/ZX/VX Ethernet optical interfaces.


The optical interfaces support the auto-negotiation function in
compliance with IEEE 802.3z. The optical interfaces use the SFP
optical module and support hot swapping. When the multi-mode
optical fiber is used, the maximum transmission distance is 550 m.
When the single-mode optical fiber is used, the maximum
transmission distance is 10 km. The optical modules that can meet
different requirements for the transmission distance such as 40 km
and 80 km can also be used.

The N3EGS2 also supports the 1000BASE-T RJ-45 Ethernet


electrical interface. The electrical interface supports the autonegotiation function. The negotiated rate can be 10 Mbit/s, 100 Mbit/
s, or 1000 Mbit/s. The N3EGS2 uses the SFP electrical interface and
supports hot swapping. The maximum transmission distance is 100
m.

Supports Ethernet II, IEEE 802.3, and IEEE 802.1q/p formats.

Supports the frame with a length ranging from 64 bytes to 9600 bytes.

Supports the Jumbo frame with a length less than 9600 bytes.

Format of service
frames

Maximum uplink
bandwidth

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The maximum uplink bandwidth is 2.5 Gbit/s. The EGS2 can adapt to
the bandwidth of the slot.

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Function and
Feature

EGS2

VCTRUNKs

Number of supported VCTRUNKs: 48


Configuration principles are as follows:

7-80

VCTRUNK 1VCTRUNK 12 can be bound with VC-4s numbered


14 only. VCTRUNK13VCTRUNK 24 can be bound with VC-4s
numbered 58 only. VCTRUNK 25VCTRUNK 36 can be bound
with VC-4s numbered 912 only. VCTRUNK 37VCTRUNK 48 can
be bound with VC-4s numbered 1316 only.

VC-4s numbered 4, 8, 12, and 16 support the binding of VC-3 and


VC-12 paths. The other VC-4s support the binding of VC-3 paths
only.

A VC-4 cannot be bound with VC-3 and VC-12 paths at the same
time.

Mapping
granularities

Supports VC-12, VC-3, VC12-Xv (X63), and VC3-Xv (X12)


granularities.

Encapsulation
format

Supports the GFP-F protocol.

EPL services

Supports the PORT-based transparent transmission.

EVPL services

Supports PORT+VLAN-based EVPL services that use the frame


encapsulation formats of MartinioE and stack VLAN.

EPLAN services

The services that are based on the IEEE 802.1d MAC bridge are referred
to as EPLAN service.
l

Supports the Layer 2 convergence and P2MP convergence.

Supports the Layer 2 forwarding function.

Supports switching on the client and SDH sides.

Supports the self-learning of the source MAC address. The capacity


of the MAC address table is 16K. The aging time of the MAC address
can be set and queried.

Supports the configuration of the static MAC route.

Supports the creation, deletion, and query of the VB. The maximum
number of supported VBs is 2. The maximum number of logical ports
for each VB is 30.

Supports the data isolation based on VB+VLAN.

MTU

Supports the setting of the packet length, which ranges from 1518 bytes
to 9600 bytes. After the setting becomes valid, the length of the packets
that enter or exit the IP ports is limited.

MPLS

Supports the MPLS.

VLAN

Complies with IEEE 802.1q/p.

VLAN
convergence

Supports the VLAN convergence.


The number of VLANs is 4K.

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Function and
Feature

EGS2

RSTP

Supports the broadcast packet suppression function and RSTP that


comply with IEEE 802.1w.

Link aggregation
function

Supports manual link aggregation.

Multicast function

Supports the multicast function.

ETH-OAM
function

The N2EGS2 does not support the ETH-OAM function.

The N3EGS2 supports CC for the multicast service, LB test for the
unicast service, LT test, LD, auto-negotiation, fault diagnosis, and
link performance detection. The ETH-OAM function complies with
IEEE 802.1ag and IEEE 802.3ah.

CAR

Supports the CAR.


The granularity is 64 kbit/s.

Service- based
QoS flow
classification

Supports the flow classification based on PORT, PORT+VLAN ID, or


PORT+VLAN ID+VLAN PRI.

LCAS function

Dynamically increases or decreases the bandwidth and protects the


bandwidth in compliance with ITU-T G.7042.

LPT function

The N2EGS2 supports the P2P LPT.

The N3EGS2 supports the P2P LPT and P2MP LPT.

Flow control
function

Supports the port-based flow control function that complies with IEEE
802.3x.

Test frames

Receives and transmits Ethernet test frames.

Loopback
function

Supports inloops on Ethernet ports (at the PHY layer or MAC layer).

The N2EGS2 supports inloops and outloops at the VC-3 level, but the
N3EGS2 does not support inloops and outloops at the VC-3 level.

Ethernet
performance
monitoring

Supports Ethernet performance monitoring at the port level.

Alarms and
performance
events

Reports various alarms and performance events, which facilitates the


management and maintenance of the equipment.

7.7.3 Working Principle and Signal Flow


The EGS2 consists of the Ethernet access module, network processor module, mapping module,
interface converting module, logic and control module, clock module, and power module.
Figure 7-25 shows the functional block diagram of the EGS2 by describing how to process
1xGE signals.
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Figure 7-25 Functional block diagram of the EGS2


Backplane

Laser
shutdown

Cross-connect unit
Interface
converting
module

VCP

Network processor module

DENCP

GE Ethernet
access
module

ENCP

Network Control Switch


processor
fabric
Data

Cross-connect unit

Mapping module

LOS

Communication

Logic and
control module

+3.3 V
Clock module
50
77
MHz MHz

SCC unit

Reference clock and frame header

Power
module

Power
module

Fuse

SCC unit

-48 V/-60 V
-48 V/-60 V

125 155
MHz MHz

ENCP: data encapsulation module

DENCP: decapsulation module

VCP: virtual concatenation processing module

Ethernet Access Module


In the receive direction, the optical signals from Ethernet equipment such as switches or routers
are converted into electrical signals. If the signals are accessed through electrical interfaces, O/
E conversion is not required. At the PHY layer, the electrical signals are decoded and the
ETH_LOS alarm is detected. The electrical signals are converted from serial signals into parallel
signals and then sent to the network processor module.
In the transmit direction, the parallel signals are converted into serial signals. At the PHY layer,
signals are encoded and converted from electrical signals to optical signals.

Network Processor Module


The network processor module consists of the network processor and switch fabric. The network
processor first performs MAC functions, which include code conversion, framing of Ethernet
packets, CRC check, and Ethernet performance statistics.
After the striped Ethernet frames enter the core of network processor, the flow is classified
according to the service type and configuration requirement. The frames are encapsulated or
decapsulated. The following formats are supported:

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MPLS

L2 MPLS VPN
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Ethernet/VLAN

In the receive direction, services are mapped and forwarded after the Tunnel and VC tags are
added according to the service configuration. In the transmit direction, the Tunnel or VC tag is
extracted based on the level (P or PE) of the equipment. Services are then routed or forwarded.
The network processor module supports the following functions:
l

Flow sense and flow classification

Unicast, multicast, and broadcast of the flow

Setting of data priorities

WFQ

Four CoSs

Mapping Module
The mapping module performs encapsulation and mapping functions.
In the upstream direction, this module first encapsulates Ethernet signals in LAPS or GFP format.
The concatenation is performed. Then, the Ethernet signals are converted into SDH signals.
In the downstream direction, SDH signals are demapped. The delay of virtual concatenation is
compensated. After aligning, packets are decapsulated according to the encapsulation format.
The decapsulated data is finally transmitted to the network processor module in packets.

Interface Converting Module


The interface converting module converts the 622 Mbit/s LVDS bus of the SDH system into the
parallel bus. The high-rate backplane interface is connected to the low-rate interface chip of the
transmit system through the interface converting module.

Logic and Control Module


The logic and control module consists of the CPU, register, oscillator, Ethernet port, and HDLC
controller. This module is connected to external circuits through the bus. The logic and control
module performs the following functions:
l

Manages and configures other modules of the board.

Implements inter-board communication through the internal Ethernet interface.

The control module also contains basic logic units. This module performs the following
functions:
l

Writes and reads the register.

Provides interfaces for the CPU.

Checks and selects the clock.

Performs phase discrimination and frequency division on the clock.

Checks the in-service state of the cross-connect, SCC, and line boards.

Controls the shutting down of the optical module.

Implements communication.

Controls indicators.

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Clock Module
The clock module traces the system reference clock and generates the required working clock
for each chip. The frequency of the clock can be 50 MHz, 77 MHz, 125 MHz, or 155 MHz.

Power Module
It converts the 48 V/60 V power supply into the DC voltages that the modules of the board
require.

7.7.4 Front Panel


The front panel of the EGS2 has indicators, interfaces, a bar code, and a laser safety class label.

Diagram of the Front Panel


Figure 7-26 shows the appearance of the front panel of the N2EGS2/N3EGS2 that is installed
with the GE optical interface.
Figure 7-26 Front panel of the N2EGS2/N3EGS2 that is installed with the GE optical interface

EGS2
STAT
ACT
PROG
SRV
LINK1
ACT1
LINK2
ACT2
CLASS 1
LASER
PRODUCT

OUT1
IN1
OUT2
IN2

EGS2

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The N3EGS2 can also be installed with the GE electrical interface. Figure 7-27 shows the
appearance of the front panel of the N3EGS2 that is installed with the GE electrical interface.
Figure 7-27 Front panel of the N3EGS2 that is installed with the GE electrical interface

EGS2
STAT
ACT
PROG
SRV
LINK1
ACT1
LINK2
ACT2

OUT1
IN1
OUT2
IN2

EGS2

Indicators
The front panel of the board has the following indicators:
l

Board hardware status indicator (STAT) two colors (red and green)

Service activation status indicator (ACT) one color (green)

Board software status indicator (PROG) two colors (red and green)

Service alarm indicator (SRV) three colors (red, green, and yellow)

Connection status indicator (LINK) one color (green)

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l

Data receiving and transmission indicator (ACT) one color (orange)

For the meanings of the status of the indicators, see A Indicators.

Interfaces
The front panel of the N2EGS2/N3EGS2 has two GE optical interfaces. Table 7-49 describes
the types and usage of the optical interfaces of the N2EGS2/N3EGS2.
Table 7-49 Optical interfaces of the N2EGS2/N3EGS2
Interface

Type of
Interface

Usage

OUT1/IN1

LC (swappable)

Transmits and receives 1000BASE-SX/LX/ZX


signals.

OUT2/IN2

LC (swappable)

Transmits and receives 1000BASE-SX/LX/ZX


signals.

When the N3EGS2 is installed with the electrical interfaces, the two GE electrical interfaces are
of the same type and have the same usage. Table 7-50 describes the types and usage of the
electrical interfaces of the N3EGS2.
Table 7-50 Electrical interfaces of the N3EGS2
Interface

Type of
Interface

Usage

GE

RJ-45 (swappable)

Transmits and receives 1000BASE-T signals.

Table 7-51 provides the pin assignments of the RJ-45 interface of the N3EGS2.
Table 7-51 Pin assignments of the RJ-45 interface of the N3EGS2

7-86

Pin

Description

BI_DA+

BI_DA

BI_DB+

BI_DC+

BI_DC

BI_DB

BI_DD+

BI_DD
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7.7.5 Valid Slots


The EGS2 can be installed in slots 28 and 1116 in the subrack.

7.7.6 Feature Code


The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the EGS2 indicates the type of interface.
Table 7-52 provides the relationship between the feature code of the EGS2 and the type of
interface.
Table 7-52 Relationship between the feature code of the EGS2 and the type of interface
Board

Feature Code

Type of Interface

SSN2EGS210 and
SSN2EGS310

10

1000BASE-SX (0.5 km)

SSN2EGS211 and
SSN2EGS311

11

1000BASE-LX (10 km)

SSN2EGS212 and
SSN2EGS312

12

1000BASE-VX (40 km)

SSN2EGS213 and
SSN2EGS213

13

1000BASE-ZX (80 km)

SSN3EGS214

14

1000BASE-T (100 m)

7.7.7 Parameter Settings


You can set the parameters for the EGS2 by using the T2000.
You can set the following parameters for the EGS2 by using the T2000:
l

Working mode

LCAS

Maximum frame length

Mapping protocol

For the description of each parameter, see F Parameter Settings.

7.7.8 Technical Specifications


The technical specifications of the EGS2 include the parameters specified for optical interfaces,
laser safety class, Ethernet performance specifications, mechanical specifications, and power
consumption.
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Parameter Specified for Optical Interfaces


Table 7-53 lists the parameters specified for the optical interfaces of the EGS2.
Table 7-53 Parameters specified for the optical interfaces of the EGS2
Parameter

Value

Type of optical
interface

1000BASE-ZX
(80 km)

1000BASEEX (40 km)

1000BASELX (10 km)

1000BASE-SX
(0.5 km)

Type of fiber

Single-mode LC

Single-mode
LC

Single-mode
LC

Multi-mode LC

Launched optical
power range
(dBm)

-2 to +5

-5.0 to 0

-9.5 to -3

-9.5 to -2.5

Operating
wavelength range
(nm)

1500 to 1580

1275 to 1350

1270 to 1355

770 to 860

Minimum
overload (dBm)

-3

-3

-3

Receiver
sensitivity (dBm)

-23

-23

-20

-17

Minimum
extinction ratio
(dB)

Laser Safety Class


The safety class of the laser on the board is Class 1. The maximum launched optical power of
the optical interfaces is less than 10 dBm (10 mW).

Ethernet Performance Specifications


Figure 7-28 shows the connection for testing the throughput specifications, packet loss ratio in
the case of overloading, latency specifications, and back-to-back specifications of the EGS2.
Figure 7-28 Connection for testing the throughput specifications, packet loss ratio in the case
of overloading, latency specifications, and back-to-back specifications
Tested
equipment 1

Tested
equipment 2

Port 1

Port 2
Data network
performance
analyzer

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Table 7-54 lists the throughput specifications of the EGS2. Table 7-55 lists the packet loss ratio
in the case of overloading of the EGS2. Table 7-56 lists the latency specifications of the EGS2.
Table 7-57 lists the back-to-back specifications of the EGS2.
NOTE

The specifications vary according to the configuration and networking of the test environment and
the VC services bound on the VCG side. The specifications that are obtained in the actual environment
are used.

The specifications in the following tables are obtained in the following scenario: EPL services are
configured and five VC-12s are bound on the GE port.

The specifications of a board of a specific version are not provided because the board version has
negligible effect on the specifications.

The specifications in the following tables are obtained by using the Smart Application.

Table 7-54 Throughput specifications of the EGS2


Frame Size
(Byte)

Passed Rate
(%)

(01,01,01) to
(01,01,02) (pks/
sec)

(01,01,02) to
(01,01,01) (pks/
sec)

Total (pks/
sec)

64

1.15

17086

17086

34172

128

1.12

9501

9501

19002

256

1.12

5094

5094

10188

512

1.13

2660

2660

5320

1024

1.12

1346

1346

2692

1280

1.13

1088

1088

2176

1518

1.14

925

925

1850

NOTE

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Test duration (sec): 10

Minimum frame size (byte): 64

Maximum frame size (byte): 1518

Step frame size (byte): custom

Number of pairs: 1

Initial rate (%): 1.00

Maximum rate (%): 2.00

Resolution rate (%): 0.01

Mode: bidirectional

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Table 7-55 Packet loss ratio in the case of overloading of the EGS2
Frame Size
(Byte)

Rate Tested
(%)

(01,01,01) to
(01,01,02) (%)

(01,01,02) to
(01,01,01) (%)

Average (%)

64

100.00

98.846

98.846

98.846

128

100.00

98.869

98.868

98.868

256

100.00

98.874

98.875

98.874

512

100.00

98.866

98.863

98.865

1024

100.00

98.870

98.870

98.870

1280

100.00

98.863

98.861

98.862

1518

100.00

98.855

98.855

98.855

NOTE

Test duration (sec): 10

Minimum frame size (byte): 64

Maximum frame size (byte): 1518

Step frame size (byte): custom

Number of pairs: 1

Initial rate (%): 100.00

Maximum rate (%): 10.00

Resolution rate (%): none

Mode: bidirectional

Table 7-56 Latency specifications of the EGS2

7-90

Frame
Size
(Byte)

Rate
Tested
(%)

(01,01,01) to
(01,01,02) (us)CT (us)

Average
(CT) (us)

(01,01,01) to
(01,01,02)
(us)-S&F (us)

Average
(S&F) (us)

64

1.00

555.8

555.8

555.3

555.3

128

1.00

615.2

615.2

614.2

614.2

256

1.00

734.6

734.6

732.6

732.6

512

1.00

914.0

914.0

909.9

909.9

1024

1.00

1313.7

1313.7

1305.6

1305.6

1280

1.00

1523.1

1523.1

1512.9

1512.9

1518

1.00

1706.6

1706.6

1694.4

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NOTE

The latency modes are classified into two modes, namely, cut through mode and store forward mode.
In cut through mode, the analyzer calculates the difference between the time when the first bit of the
transmitted frame reaches the output port and the time when the first bit of the transmitted frame reaches
the input port. In store forward mode, the analyzer calculates the difference between the time when the
first bit of the transmitted frame reaches the output port and the time when the last bit of the transmitted
frame reaches the input port. In the preceding table, the CT values are obtained in cut through mode
and the S&F values are obtained in store forward mode.

CT: cut through or FIFO; S&F: store forward or LIFO

Measure on one receiving card only. Mode: SmartMetrics Comp. Mode

Test duration (sec): 10

Minimum frame size (byte): 64

Maximum frame size (byte): 1518

Step frame size (byte): custom

Number of pairs: 1

Initial rate (%): 1.00

Maximum rate (%): 10.00

Resolution rate (%): none

Mode: bidirectional

Table 7-57 Back-to-back specifications of the EGS2

Issue 02 (2009-07-30)

Frame Size
(Byte)

Rate Tested
(%)

(01,01,01) to
(01,01,02) Burst
Size (Number of
Frames)

(01,01,02) to
(01,01,01)
(Number of
Frames)

Total
(Number of
Frames)

64

100.00

1236

1236

2472

128

100.00

1321

1323

2644

256

100.00

1070

1070

2140

512

100.00

934

934

1868

1024

100.00

468

468

936

1280

100.00

458

458

916

1518

100.00

450

453

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NOTE

Test duration (sec): 10

Minimum frame size (byte): 64

Maximum frame size (byte): 1518

Step frame size (byte): custom

Number of pairs: 1

Initial rate (%): 100.00

Maximum rate (%): 10.00

Resolution rate (%): none

Mode: bidirectional

Mechanical Specifications
The mechanical specifications of the EGS2 are as follows:
l

Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)

Weight of the N2EGS2 (kg): 1.0

Weight of the N3EGS2 (kg): 0.6

Power Consumption
The maximum power consumption of the N2EGS2 at room temperature (25C) is 43 W.
The maximum power consumption of the N3EGS2 at room temperature (25C) is 25 W.

7.8 EMS2
This topic describes the version, functions, working principle, valid slots, and technical
specification of the EMS2 (2xGE and 16xFE switching and processing board).
7.8.1 Version Description
The EMS2 is available in one functional version, namely, N1.
7.8.2 Functions and Features
The EMS2 supports the Layer 2 switching, link convergence, and multicast functions.
7.8.3 Working Principle and Signal Flow
The EMS2 consists of the Ethernet access module, network processor module, mapping module,
interface converting module, logic and control module, clock module, and power module.
7.8.4 Front Panel
The front panel of the EMS2 has indicators, interfaces, a bar code, and a laser safety class label.
7.8.5 Valid Slots
The EMS2 can be installed in slots 27 and 1216 in the subrack.
7.8.6 Feature Code
The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the EMS2 indicates the type of interface.
7.8.7 Parameter Settings
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You can set the parameters for the EMS2 by using the T2000.
7.8.8 Technical Specifications
The technical specifications of the EMS2 include the parameters specified for optical interfaces,
laser safety class, dimensions, weight, and power consumption.

7.8.1 Version Description


The EMS2 is available in one functional version, namely, N1.

7.8.2 Functions and Features


The EMS2 supports the Layer 2 switching, link convergence, and multicast functions.
Table 7-58 provides the functions and features of the EMS2.
Table 7-58 Functions and features of the EMS2
Function and
Feature

EMS2

Basic functions

Accesses and processes 2xGE services.


Processes 16xFE services

Functions when being


used with the interface
board

Specifications of the
optical interface

Issue 02 (2009-07-30)

Accesses 16xFE signals through the electrical interface when the


EMS2 is used with the ETF8.

Accesses 16xFE signals through the optical interface when the


EMS2 is used with the EFF8.

Accesses 8xFE signals through the electrical interface and 8xFE


signals through the optical interface when the EMS2 is used with
the ETF8 and EFF8.

Supports the 1000BASE-SX/LX/ZX/VX Ethernet optical


interfaces. The optical interfaces support the auto-negotiation
function in compliance with IEEE 802.3z. The optical interfaces
use the SFP optical module and support hot swapping. When the
multi-mode optical fiber is used, the maximum transmission
distance is 550 m. When the single-mode optical fiber is used, the
maximum transmission distance is 10 km. The optical modules
that can meet different requirements for the transmission distance
such as 40 km and 80 km can also be used.

Supports the 1000BASE-T RJ-45 Ethernet electrical interface.


The electrical interface supports the auto-negotiation function.
The negotiated rate can be 10 Mbit/s, 100 Mbit/s, or 1000 Mbit/
s. The board uses the SFP electrical interface and supports hot
swapping. The maximum transmission distance is 100 m.

Supports 10BASE-T/100BASE-TX signals when the EMS2 is


used with the ETF8 and supports 100BASE-FX signals when the
EMS2 is used with the EFF8.

The optical interfaces comply with IEEE 802.3u.

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Function and
Feature

EMS2

Format of service
frames

Supports Ethernet II, IEEE 802.3, IEEE 802.1q/p formats.

Supports the frame with a length ranging from 64 bytes to 9600


bytes.

Supports the Jumbo frame with a length less than 9600 bytes.

Maximum uplink
bandwidth

2.5 Gbit/s

Mapping granularities

Supports the following virtual concatenation granularities: VC-12,


VC-3, VC12-Xv (X63), and VC3-Xv (X12).

VCTRUNKs

Number of supported VCTRUNKs: 48

Encapsulation format

Supports the GFP-F protocol.

EPL services

Supports PORT-based transparent transmission.

EVPL services

The services that are based on the IEEE 802.1d MAC bridge are
referred to as EPLAN service.
l

EPLAN

EVPLAN

7-94

Supports EVPL services based on PORT+VLAN.

Supports a maximum of 4000 services that are accessed


through IP ports.

Supports a maximum of 4000 services that are accessed


through VCTRUNKs.

Supports a maximum of 8000 links.

Supports QinQ-based EVPL services.

Supports PORT-based service forwarding.

The services that are based on the IEEE 802.1d MAC bridge are
referred to as EPLAN service.
l

Supports the Layer 2 forwarding function.

Supports switching on the client and SDH sides.

Supports the blacklist with a capacity of 2K bytes and the static


MAC address table with a capacity of 2K bytes. They share 2K
bytes.

Supports the self-learning of the source MAC address. The


capacity of the MAC address table is 16K. The aging time of the
MAC address can be set and queried.

Supports the configuration of the static MAC route.

Supports the creation, deletion, and query of the VB. The


maximum number of supported VBs is 2.

Does not support EVPLAN services.

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Function and
Feature

EMS2

VLAN

Supports VLAN and QinQ.

7 Data Boards

Supports the addition, deletion, and exchanging of VLAN tags.


The function complies with IEEE 802.1q/p.
MTU

Supports the setting of the packet length, which ranges from 1518
bytes to 9600 bytes. After the setting becomes valid, the length of
the packets that enter or exit the IP ports is limited.

RSTP

Supports the RSTP, which complies with IEEE 802.1w.

Multicast function

Supports the multicast function.

ETH-OAM function

Supports CC for the multicast service, LB test for the unicast service,
LT test, LD, auto-negotiation, fault diagnosis, and link performance
detection. The ETH-OAM function complies with IEEE 802.1ag and
IEEE 802.3ah.

Test frames

Supports test frames.

Port mirroring

Supports ingress mirroring.

Link aggregation
function

Supports manual link aggregation.

VLAN convergence

Supports 4096 VLANs (04095) in the case of QinQ services.

Supports 4095 VLANs (14095) in the case of EVPL services.

Protection

Does not support the BPS protection or PPS protection.

CAR

Supports the CAR.


The granularity is 64 kbit/s.

Issue 02 (2009-07-30)

Flow classification

Supports the flow classification based on PORT, PORT+VLAN ID,


or PORT+VLAN ID+PRI.

LCAS function

Dynamically increases or decreases the bandwidth and protects the


bandwidth in compliance with ITU-T G.7042.

LPT function

Supports the P2P LPT and P2MP LPT.

Inter-board link
aggregation

Does not support inter-board link aggregation.

Flow control function

Supports the port-based flow control function that complies with


IEEE 802.3x.

Loopback function

Supports inloops on Ethernet ports (on the PHY layer).

Ethernet performance
monitoring

Supports RMON of the Ethernet performance at the PORT level and


the VCTRUNK level.

Alarms and
performance events

Reports various alarms and performance events, which facilitates the


management and maintenance of the equipment.

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7.8.3 Working Principle and Signal Flow


The EMS2 consists of the Ethernet access module, network processor module, mapping module,
interface converting module, logic and control module, clock module, and power module.
Figure 7-29 shows the functional block diagram of the EMS2 by describing how to process
1xGE/FE signals.
Figure 7-29 Functional block diagram of the EMS2
Backplane

Cross-connect unit
Interface
converting
module

VCP

Laser
shutdown

DENCP

Network processor module

ENCP

Network Control Switch


processor
fabric
Data

GE/FE Ethernet
access
module

Cross-connect unit

Mapping module

LOS

Communication

Logic and
control module

+3.3 V
Clock module
77
50
MHz MHz

SCC unit

Reference clock and frame header

Power
module

Power
module

Fuse

SCC unit

-48 V/-60 V
-48 V/-60 V

125 155
MHz MHz

ENCP: data encapsulation module

DENCP: decapsulation module

VCP: virtual concatenation processing module

Ethernet Access Module


In the receive direction, the optical signals from Ethernet equipment such as switches or routers
are converted into electrical signals. If the signals are accessed through electrical interfaces, O/
E conversion is not required. At the PHY layer, the electrical signals are decoded and the
ETH_LOS alarm is detected. The electrical signals are converted from serial signals into parallel
signals and then sent to the network processor module.
In the transmit direction, the parallel signals are converted into serial signals. At the PHY layer,
signals are encoded and converted from electrical signals to optical signals.
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Network Processor Module


The network processor module consists of the network processor and switch fabric. The network
processor first performs MAC functions, which include code conversion, framing of Ethernet
packets, CRC check, and Ethernet performance statistics.
After the striped Ethernet frames enter the core of network processor, the flow is classified
according to the service type and configuration requirement. The frames are encapsulated or
decapsulated. The Ethernet/VLAN format is supported.
The network processor module supports the following functions:
l

Flow sense and flow classification

Unicast, multicast, and broadcast of the flow

Setting of data priorities

WFQ

Four CoSs

Mapping Module
The mapping module performs encapsulation and mapping functions.
In the upstream direction, this module first encapsulates Ethernet signals in LAPS, GFP-F, or
HDLC format. The concatenation is performed. The LCAS function is supported. Then, the
Ethernet signals are converted into SDH signals.
In the downstream direction, SDH signals are demapped. The delay of virtual concatenation is
compensated. After aligning, packets are decapsulated according to the encapsulation format.
The decapsulated data is finally transmitted to the network processor module in packets.

Interface Converting Module


The interface converting module converts the 622 Mbit/s LVDS bus of the SDH system into the
parallel bus. The high-rate backplane interface is connected to the low-rate interface chip of the
transmit system through the interface converting module.

Logic and Control Module


The logic and control module consists of the CPU, register, oscillator, Ethernet port, and HDLC
controller. This module is connected to external circuits through the bus. The logic and control
module performs the following functions:
l

Manages and configures other modules of the board.

Implements inter-board communication through the internal Ethernet interface.

The control module also contains basic logic units. This module performs the following
functions:
l

Writes and reads the register.

Provides interfaces for the CPU.

Checks and selects the clock.

Performs phase discrimination and frequency division on the clock.

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l

Checks the in-service state of the cross-connect, SCC, and line boards.

Controls the shutting down of the optical module.

Implements communication.

Controls indicators.

Clock Module
The clock module traces the system reference clock and generates the required working clock
for each chip. The frequency of the clock can be 50 MHz, 77 MHz, 125 MHz, or 155 MHz.

Power Module
It converts the 48 V/60 V power supply into the DC voltages that the modules of the board
require.

7.8.4 Front Panel


The front panel of the EMS2 has indicators, interfaces, a bar code, and a laser safety class label.

Diagram of the Front Panel


Figure 7-30 shows the appearance of the front panel of the EMS2 that is installed with the GE
optical interface.

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Figure 7-30 Front panel of the EMS2 that is installed with the GE optical interface

EMS2
STAT
ACT
PROG
SRV
LINK1
ACT1
LINK2
ACT2
CLASS 1
LASER
PRODUCT

OUT1
IN1
OUT2
IN2

EMS2

Figure 7-31 shows the appearance of the front panel of the EMS2 that is installed with the GE
electrical interface.

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Figure 7-31 Front panel of the EMS2 that is installed with the GE electrical interface

EMS2
STAT
ACT
PROG
SRV
LINK1
ACT1
LINK2
ACT2

OUT1
IN1
OUT2
IN2

EMS2

Indicators
The front panel of the board has the following indicators:
l

Board hardware status indicator (STAT) two colors (red and green)

Service activation status indicator (ACT) one color (green)

Board software status indicator (PROG) two colors (red and green)

Service alarm indicator (SRV) three colors (red, green, and yellow)

Connection status indicator (LINK) one color (green)

Data receiving and transmission indicator (ACT) one color (orange)

For the meanings of the status of the indicators, see A Indicators.

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Interfaces
The front panel of the EMS2 has two interfaces. Table 7-59 describes the types and usage of
the interfaces of the EMS2 when the EMS2 is installed with the optical interfaces. When the
EMS2 is installed with the electrical interfaces, the two GE electrical interfaces are of the same
type and have the same usage. Table 7-60 describes the types and usage of the electrical
interfaces of the EMS2.
Table 7-59 Optical interfaces of the EMS2
Interface

Type of
Interface

Usage

OUT1/IN1

LC (swappable)

Transmits and receives 1000BASE-SX/LX/ZX


signals.

OUT2/IN2

LC (swappable)

Transmits and receives 1000BASE-SX/LX/ZX


signals.

Table 7-60 Electrical interfaces of the EMS2


Interface

Type of
Interface

Usage

GE

RJ-45
(swappable)

Transmits and receives 1000BASE-T signals.

Table 7-61 provides the pin assignments of the RJ-45 interface of the EMS2.
Table 7-61 Pin assignments of the RJ-45 interface of the EMS2

Issue 02 (2009-07-30)

Pin

Description

BI_DA+

BI_DA

BI_DB+

BI_DC+

BI_DC

BI_DB

BI_DD+

BI_DD

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7.8.5 Valid Slots


The EMS2 can be installed in slots 27 and 1216 in the subrack.
The EMS2 can be used with the ETF8 and EFF8.
Table 7-62 lists the slots valid for the EMS2 and the corresponding slots for the ETF8 and EFF8.
Table 7-62 Slots valid for the EMS2 and the corresponding slots for the ETF8 and EFF8
Slot Valid for the EMS2

Corresponding Slots for the ETF8 and EFF8

Slot 2

Without the interface board

Slot 3

Slots 21 and 22

Slot 4

Slots 23 and 24

Slot 5

Slots 25 and 26

Slot 6

Slots 27 and 28

Slot 7

Slots 28 and 29

Slot 12

Slots 31 and 32

Slot 13

Slots 33 and 34

Slot 14

Slots 35 and 36

Slot 15

Slots 37 and 38

Slot 16

Slots 39 and 40

7.8.6 Feature Code


The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the EMS2 indicates the type of interface.
Table 7-63 provides the relationship between the feature code of the EMS2 and the type of
interface.
Table 7-63 Relationship between the feature code of the EMS2 and the type of interface

7-102

Board

Feature Code

Type of Interface

SSN1EMS210

10

1000BASE-SX (0.5 km)

SSN1EMS211

11

1000BASE-LX (10 km)

SSN1EMS212

12

1000BASE-VX (40 km)

SSN1EMS213

13

1000BASE-ZX (80 km)

SSN1EMS214

14

1000BASE-T (100 m)

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7.8.7 Parameter Settings


You can set the parameters for the EMS2 by using the T2000.
You can use set the following parameters for the EMS2 by using the T2000:
l

Working mode

LCAS

Maximum frame length

Mapping protocol

For the description of each parameter, see F Parameter Settings.

7.8.8 Technical Specifications


The technical specifications of the EMS2 include the parameters specified for optical interfaces,
laser safety class, dimensions, weight, and power consumption.

Parameters Specified for Optical Interfaces


Table 7-64 lists the parameters specified for the optical interfaces of the EMS2.
Table 7-64 Parameters specified for the optical interfaces of the EMS2
Parameter

Value

Type of optical
interface

1000BASE-ZX
(80 km)

1000BASEEX (40 km)

1000BASELX (10 km)

1000BASE-SX
(0.5 km)

Type of fiber

Single-mode LC

Single-mode
LC

Single-mode
LC

Multi-mode LC

Launched optical
power range
(dBm)

-2 to +5

-5.0 to 0

-9.5 to -3

-9.5 to -2.5

Operating
wavelength range
(nm)

1500 to 1580

1275 to 1350

1270 to 1355

770 to 860

Minimum
overload (dBm)

-3

-3

-3

Receiver
sensitivity (dBm)

-23

-23

-20

-17

Minimum
extinction ratio
(dB)

Laser Safety Class


The safety class of the laser on the board is Class 1. The maximum launched optical power of
the optical interfaces is less than 10 dBm (10 mW).
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Mechanical Specifications
The mechanical specifications of the EMS2 are as follows:
l

Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)

Weight (kg): 0.7

Power Consumption
The maximum power consumption of the EMS2 at room temperature (25C) is 40 W.

7.9 EMS4
This topic describes the version, functions, working principle, valid slots, and technical
specification of the EMS4 (4xGE and 16xFE switching and processing board).
7.9.1 Version Description
The EMS4 is available in one functional version, namely, N1.
7.9.2 Functions and Features
The EMS4 supports the Layer 2 switching, link convergence, and multicast functions.
7.9.3 Working Principle and Signal Flow
The EMS4 consists of the Ethernet access module, network processor module, mapping module,
interface converting module, logic and control module, clock module, and power module.
7.9.4 Front Panel
The front panel of the EMS4 has indicators, interfaces, a bar code, and a laser safety class label.
7.9.5 Valid Slots
The EMS4 can be installed in slots 27 and 1216 in the subrack.
7.9.6 Feature Code
The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the EMS4 indicates the type of interface.
7.9.7 Board Protection
The EMS4 supports the BPS and PPS.
7.9.8 Parameter Settings
You can set the parameters for the EMS4 by using the T2000.
7.9.9 Technical Specifications
The technical specifications of the EMS4 include the parameters specified for optical interfaces,
laser safety class, Ethernet performance specifications, mechanical specifications, and power
consumption.

7.9.1 Version Description


The EMS4 is available in one functional version, namely, N1.

7.9.2 Functions and Features


The EMS4 supports the Layer 2 switching, link convergence, and multicast functions.
Table 7-65 provides the functions and features of the EMS4.
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Table 7-65 Functions and features of the EMS4


Function and
Feature

EMS4

Basic functions

Accesses and processes 4xGE services


Processes 16xFE services.

Functions when being


used with the interface
board

Specifications of the
optical interface

Format of service
frames

Issue 02 (2009-07-30)

Accesses 16xFE signals through the electrical interface when the


EMS4 is used with the ETF8.

Accesses 16xFE signals through the optical interface when the


EMS4 is used with the EFF8.

Accesses 8xFE signals through the electrical interface and 8xFE


signals through the optical interface when the EMS4 is used with
the ETF8 and EFF8.

Supports the 1000BASE-SX/LX/ZX/VX Ethernet optical


interfaces. The optical interfaces support the auto-negotiation
function in compliance with IEEE 802.3z. The optical interfaces
use the SFP optical module and support hot swapping. When the
multi-mode optical fiber is used, the maximum transmission
distance is 550 m. When the single-mode optical fiber is used, the
maximum transmission distance is 10 km. The optical modules
that can meet different requirements for the transmission distance
such as 40 km and 80 km can also be used.

Supports the 1000BASE-T RJ-45 Ethernet electrical interface.


The electrical interface supports the auto-negotiation function.
The negotiated rate can be 10 Mbit/s, 100 Mbit/s, or. 1000 Mbit/
s. The EMS4 uses the SFP electrical interface and supports hot
swapping. The maximum transmission distance is 100 m.

Supports 10BASE-T/100BASE-TX signals when the EMS4 is


used with the ETF8 and supports 100BASE-FX signals when the
EMS4 is used with the EFF8.

The optical interfaces comply with IEEE 802.3u.

Supports Ethernet II, IEEE 802.3, IEEE 802.1q/p formats.

Supports the frame with a length ranging from 64 bytes to 9216


bytes.

Supports the Jumbo frame with a length less than 9216 bytes.

Maximum uplink
bandwidth

2.5 Gbit/s.

Mapping granularities

Supports the following virtual concatenation granularities: VC-12,


VC-3, VC-4, VC12-Xv (X64), VC3-Xv (X24), and VC4-Xv
(X8).

Number of supported
VCTRUNKs

64

Encapsulation format

Supports the GFP-F, LAPS, and HDLG protocols.

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Function and
Feature

EMS4

EPL services

Supports PORT-based transparent transmission.


Supports 4000 bidirectional services.

EVPL services

EPLAN services

EVPLAN services

VLAN

Supports EVPL services based on PORT+VLAN.

Supports a maximum of 4000 services that are accessed


through IP ports.

Supports a maximum of 4000 services that are accessed


through VCTRUNKs.

Supports a maximum of 8000 links.

Supports QinQ-based EVPL services.

Supports PORT-based service forwarding.

The services that are based on the IEEE 802.1d MAC bridge are
referred to as EPLAN service.
l

Supports the Layer 2 forwarding function.

Supports switching on the client and SDH sides.

Supports the blacklist with a capacity of 512 bytes and the static
MAC address table with a capacity of 512 bytes.

Supports the self-learning of the source MAC address. The


capacity of the MAC address table is 128K. The aging time of the
MAC address can be set and queried.

Supports the configuration of the static MAC route.

Supports the creation, deletion, and query of the VB. The


maximum number of supported VBs is 2.

The services that are based on the IEEE 802.1q virtual bridge and
IEEE 802.1ad provider bridge are referred to as EVPLAN services.
l

Supports data isolation based on VB+VLAN.

Supports the setting of a maximum of 4000 VLAN services.

Supports VLAN and QinQ.


Supports the addition, deletion, and exchanging of VLAN tags.
The function complies with IEEE 802.1q/p.

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MTU

Supports the setting of the packet length, which ranges from 1518
bytes to 9216 bytes. After the setting becomes valid, the length of
the packets that enter or exit the IP ports is limited.

RSTP

Supports the RSTP, which complies with IEEE 802.1w.

Multicast function

Supports the multicast function.

ETH-OAM function

Supports CC for the multicast service, LB test for the unicast service,
remote loopback, auto-negotiation, LD, fault diagnosis, and link
performance detection. The ETH-OAM function complies with
IEEE 802.1ag and IEEE 802.3ah.

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Function and
Feature

EMS4

Test frames

Supports test frames.

Service mirroring

Does not support service mirroring.

Link aggregation
function

Supports manual link aggregation and static link aggregation.

VLAN convergence

Supports 4096 VLANs (04095) in the case of QinQ services.

Supports 4095 VLANs (14095) in the case of EVPL services.

Protection

Supports the BPS and PPS.

CAR

Supports the CAR.


The granularity is 64 kbit/s.

Flow classification

Supports the flow classification based on PORT, PORT+VLAN, or


PORT+SVLAN.

LCAS function

Dynamically increases or decreases the bandwidth and protects the


bandwidth in compliance with ITU-T G.7042.

LPT function

Supports the P2P LPT.

Inter-board link
aggregation

Supports inter-board link aggregation.

Flow control function

Supports the port-based flow control function that complies with


IEEE 802.3x.

Loopback function

Supports inloops on Ethernet ports (at the PHY layer).

Ethernet performance
monitoring

Supports RMON of the Ethernet performance at the PORT level and


the VCTRUNK level.

Alarms and
performance events

Reports various alarms and performance events, which facilitates


management and maintenance of the equipment.

7.9.3 Working Principle and Signal Flow


The EMS4 consists of the Ethernet access module, network processor module, mapping module,
interface converting module, logic and control module, clock module, and power module.
Figure 7-32 shows the functional block diagram of the EMS4 by describing how to process
1xGE/FE signals.

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Figure 7-32 Functional block diagram of the EMS4


Backplane

Cross-connect unit
Interface
converting
module

VCP

Laser
shutdown

DENCP

Network processor module

ENCP

Network Control Switch


processor
fabric
Data

GE/FE Ethernet
access
module

Cross-connect unit

Mapping module

LOS

Communication

Logic and
control module

+3.3 V
Clock module
77
50
MHz MHz

SCC unit

Reference clock and frame header

Power
module

Power
module

Fuse

SCC unit

-48 V/-60 V
-48 V/-60 V

125 155
MHz MHz

ENCP: data encapsulation module

DENCP: decapsulation module

VCP: virtual concatenation processing module

Ethernet Access Module


In the receive direction, the optical signals from Ethernet equipment such as switches or routers
are converted into electrical signals. If the signals are accessed through electrical interfaces, O/
E conversion is not required. At the PHY layer, the electrical signals are decoded and the
ETH_LOS alarm is detected. The electrical signals are converted from serial signals into parallel
signals and then sent to the network processor module.
In the transmit direction, the parallel signals are converted into serial signals. At the PHY layer,
signals are encoded and converted from electrical signals to optical signals.

Network Processor Module


The network processor module consists of the network processor and switch fabric. The network
processor first performs MAC functions, which include code conversion, framing of Ethernet
packets, CRC check, and Ethernet performance statistics.
After the striped Ethernet frames enter the core of network processor, the flow is classified
according to the service type and configuration requirement. The frames are encapsulated or
decapsulated. The Ethernet/VLAN format is supported.
The network processor module supports the following functions:
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l

Flow sense and flow classification

Unicast, multicast, and broadcast of the flow

Setting of data priorities

WFQ

Four CoSs

7 Data Boards

Mapping Module
The mapping module performs encapsulation and mapping functions.
In the upstream direction, this module first encapsulates Ethernet signals in LAPS, GFP-F, or
HDLC format. The concatenation is performed. The LCAS function is supported. Then, the
Ethernet signals are converted into SDH signals.
In the downstream direction, SDH signals are demapped. The delay of virtual concatenation is
compensated. After aligning, packets are decapsulated according to the encapsulation format.
The decapsulated data is finally transmitted to the network processor module in packets.

Interface Converting Module


The interface converting module converts the 622 Mbit/s LVDS bus of the SDH system into the
parallel bus. The high-rate backplane interface is connected to the low-rate interface chip of the
transmit system through the interface converting module.

Logic and Control Module


The logic and control module consists of the CPU, register, oscillator, Ethernet port, and HDLC
controller. This module is connected to external circuits through the bus. The logic and control
module performs the following functions:
l

Manages and configures other modules of the board.

Implements inter-board communication through the internal Ethernet interface.

The control module also contains basic logic units. This module performs the following
functions:
l

Writes and reads the register.

Provides interfaces for the CPU.

Checks and selects the clock.

Performs phase discrimination and frequency division on the clock.

Checks the in-service state of the cross-connect, SCC, and line boards.

Controls the shutting down of the optical module.

Implements communication.

Controls indicators.

Clock Module
The clock module traces the system reference clock and generates the required working clock
for each chip. The frequency of the clock can be 50 MHz, 77 MHz, 125 MHz, or 155 MHz.
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Power Module
It converts the 48 V/60 V power supply into the DC voltages that the modules of the board
require.

7.9.4 Front Panel


The front panel of the EMS4 has indicators, interfaces, a bar code, and a laser safety class label.

Diagram of the Front Panel


Figure 7-33 shows the appearance of the front panel of the EMS4 that is installed with the GE
optical interface.
Figure 7-33 Front panel of the EMS4 that is installed with the GE optical interface

EMS4
STAT
ACT
PROG
SRV

CLASS 1
LASER
PRODUCT

OUT1
IN1
OUT2
IN2
OUT3
IN3
OUT4
IN4
LINK ACT
1
2
3
4

EMS4

Figure 7-34 shows the appearance of the front panel of the EMS4 that is installed with the GE
electrical interface.
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Figure 7-34 Front panel of the EMS4 that is installed with the GE electrical interface

EMS4
STAT
ACT
PROG
SRV

OUT1
IN1
OUT2
IN2
OUT3
IN3
OUT4
IN4
LINK ACT
1
2
3
4

EMS4

Indicators
The front panel of the board has the following indicators:
l

Board hardware status indicator (STAT) two colors (red and green)

Service activation status indicator (ACT) one color (green)

Board software status indicator (PROG) two colors (red and green)

Service alarm indicator (SRV) three colors (red, green, and yellow)

Connection status indicator (LINK) one color (green)

Data receiving and transmission indicator (ACT) one color (orange)

For the meanings of the status of the indicators, see A Indicators.

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Interfaces
The front panel of the EMS4 has four interfaces. Table 7-66 describes the types and usage of
the optical interfaces of the EMS4. When the EMS4 is installed with the electrical interfaces,
the four GE electrical interfaces are of the same type and have the same usage. Table 7-67
describes the types and usage of the electrical interfaces of the EMS4.
Table 7-66 Optical interfaces of the EMS4
Interface

Type of
Interface

Usage

OUT1/IN1

LC (swappable)

Transmits and receives 1000BASE-SX/LX/ZX


signals.

OUT2/IN2

LC (swappable)

Transmits and receives 1000BASE-SX/LX/ZX


signals.

OUT3/IN3

LC (swappable)

Transmits and receives 1000BASE-SX/LX/ZX


signals.

OUT4/IN4

LC (swappable)

Transmits and receives 1000BASE-SX/LX/ZX


signals.

Table 7-67 Electrical interfaces of the EMS4


Interface

Type of
Interface

Usage

GE

RJ-45
(swappable)

Transmits and receives 1000BASE-T signals.

Table 7-68 provides the pin assignments of the RJ-45 interface of the EMS4.
Table 7-68 Pin assignments of the RJ-45 interface of the EMS4

7-112

Pin

Description

BI_DA+

BI_DA

BI_DB+

BI_DC+

BI_DC

BI_DB

BI_DD+

BI_DD
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7.9.5 Valid Slots


The EMS4 can be installed in slots 27 and 1216 in the subrack.
The EMS4 can be used with the ETF8 and EFF8.
Table 7-69 lists the slots valid for the EMS4 and the corresponding slots for the ETF8 and EFF8.
Table 7-69 Slots valid for the EMS4 and the corresponding slots for the ETF8 and EFF8
Slot Valid for the EMS4

Corresponding Slots for the ETF8


and EFF8

Slot 2

Without the interface board

Slot 3

Slots 21 and 22

Slot 4

Slots 23 and 24

Slot 5

Slots 25 and 26

Slot 65

Slots 27 and 28

Slot 7

Slots 29 and 30

Slot 12

Slots 31 and 32

Slot 13

Slots 33 and 34

Slot 14

Slots 35 and 36

Slot 15

Slots 37 and 38

Slot 16

Slots 39 and 40

7.9.6 Feature Code


The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the EMS4 indicates the type of interface.
Table 7-70 provides the relationship between the feature code of the EMS4 and the type of
interface.
Table 7-70 Relationship between the feature code of the EMS4 and the type of interface

Issue 02 (2009-07-30)

Board

Feature Code

Type of Interface

SSN1EMS410

10

1000BASE-LX (0.5 km)

SSN1EMS411

11

1000BASE-SX (10 km)

SSN1EMS412

12

1000BASE-VX (40 km)

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Board

Feature Code

Type of Interface

SSN1EMS413

13

1000BASE-ZX (80 km)

SSN1EMS414

14

1000BASE-T (100 m)

7.9.7 Board Protection


The EMS4 supports the BPS and PPS.

Protection Principle
When the BPS protection is provided for the EMS4, the GE and FE ports are protected by using
the single-fed and selective-receiving scheme. The EMS4 has four GE ports and 16 FE ports
and hence may be connected to many sets of communication equipment. Normally, the active
board is working and services are transmitted in two directions of the active link. On the backup
link, the EMS4 disables the transmission of all ports. In this case, the ports of the opposite board
are in the linkdown state. In addition, the opposite board enables the transmission but does not
transmit services. In this manner, the receive ports of the backup EMS4 are not in the linkdown
state. The solid lines in Figure 7-35 show how the EMS4 normally works.
Figure 7-35 Normal working of the EMS4

No.1

Active
EMS4

Active
communication
equipment

Standby
communication
equipment

No.2

No.3

Active
communication
equipment

XCS

B
Standby
communication
equipment

No.1
No.2

Standby
EMS4

No.3

Active
communication
equipment
Standby
communication
equipment

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l

7 Data Boards

BPS Protection

When the BPS protection is provided, if the active board detects the linkdown state of any link
or any fault in the board, the cross-connect board switches all the services to the standby board.
In this manner, services are protected. The solid lines in Figure 7-36 show how the BPS
protection functions. The services numbered 1, 2 and 3 are all switched to the standby EMS4
and the corresponding communication equipment.
Figure 7-36 Principle of the BPS protection for the EMS4

No.1

Active
EMS4

Active
communication
equipment
Standby
communication
equipment

No.2

No.3

Active
communication
equipment

XCS

B
Standby
communication
equipment

No.1
No.2

Standby
EMS4

No.3

Active
communication
equipment
Standby
communication
equipment

PPS Protection

When the PPS protection is provided, if the active board detects the linkdown state of any link,
any fault in the board, or the offline state of any board, the cross-connect board switches all the
services to the standby board. In this manner, services are protected. The solid lines in Figure
7-37 show how the PPS protection functions. Only the service numbered 1 is switched to the
standby EMS4 and the standby communication equipment.

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Figure 7-37 Principle of the PPS protection for the EMS4

No.1

Active
communication
equipment

Active
EMS4

Standby
communication
equipment

No.2

No.3
Active
communication
equipment

XCS

B
Standby
communication
equipment

No.1
No.2

Standby
EMS4

No.3

Active
communication
equipment

Standby
communication
equipment

The conditions that trigger the protection for the EMS4 are as follows:
l

Fault at the PHY layer of the MAC port, that is, linkdown state

Fault in key hardware units of the board, such as the power module, optical module, and
clock

Offline state of the board

WARNING
When the board-level protection is performed, the FE ports support only the 100M full-duplex
mode and the GE ports support the auto-negotiation and 1000M full-duplex mode.

Board Configuration
Two EMS4 boards should be configured to provide the board-level protection. One EMS4 is the
active board and the other is the standby board. When you configure the EMS4 board protection,
ensure that the access capacity of the slot that houses the standby board must not be less than
the access capacity of the slot that houses the active board.
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7.9.8 Parameter Settings


You can set the parameters for the EMS4 by using the T2000.
You can set the following parameters for the EMS4 by using the T2000:
l

Working mode

LCAS

Maximum frame length

Mapping protocol

For the description of each parameter, see F Parameter Settings.

7.9.9 Technical Specifications


The technical specifications of the EMS4 include the parameters specified for optical interfaces,
laser safety class, Ethernet performance specifications, mechanical specifications, and power
consumption.

Parameters Specified for Optical Interfaces


Table 7-71 lists the parameters specified for the optical interfaces of the EMS4.
Table 7-71 Parameters specified for the optical interfaces of the EMS4

Issue 02 (2009-07-30)

Parameter

Value

Type of optical
interface

1000BASE-ZX
(80 km)

1000BASEEX (40 km)

1000BASELX (10 km)

1000BASE-SX
(0.5 km)

Type of fiber

Single-mode LC

Single-mode
LC

Single-mode
LC

Multi-mode LC

Launched optical
power range
(dBm)

-2 to +5

-5.0 to 0

-9.5 to -3

-9.5 to -2.5

Operating
wavelength range
(nm)

1500 to 1580

1275 to 1350

1270 to 1355

770 to 860

Minimum
overload (dBm)

-3

-3

-3

Receiver
sensitivity (dBm)

-23

-23

-20

-17

Minimum
extinction ratio
(dB)

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Laser Safety Class


The safety class of the laser on the board is Class 1. The maximum launched optical power of
the optical interfaces is less than 10 dBm (10 mW).

Ethernet Performance Specifications


Figure 7-38 shows the connection for testing the throughput specifications, packet loss ratio in
the case of overloading, and latency specifications of the EMS4.
Figure 7-38 Connection for testing the throughput specifications, packet loss ratio in the case
of overloading, and latency specifications
Port 1
Tested
equipment 1

Tested
equipment 2
Port 2

Port 1

Port 2

Data network
performance
analyzer

Figure 7-39 shows the connection for testing the back-to-back specifications of the EMS4.
Figure 7-39 Connection for testing the back-to-back specifications
Tested
equipment 1

Port 1

Port 2

Data network
performance
analyzer

Table 7-72 and Table 7-73 list the throughput specifications of the EMS4. Table 7-74 and
Table 7-75 list the packet loss ratio in the case of overloading of the EMS4. Table 7-76 and
Table 7-77 list the latency specifications of the EMS4. Table 7-78 and Table 7-79 list the backto-back specifications of the EMS4.
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NOTE

The specifications vary according to the configuration and networking of the test environment and
the VC services bound on the VCG side. The specifications that are obtained in the actual environment
are used.

The specifications in the following tables are obtained in the following scenario: EPL services are
configured and one VC-4 is bound on the FE port, or EPL services are configured and 24 VC-3s are
bound on the GE port.

The specifications of a board of a specific version are not provided because the board version has
negligible effect on the specifications.

The specifications in the following tables are obtained by using the Smart Application.

Table 7-72 Throughput specifications of the EMS4 (one VC-4 is bound on the FE port)
Frame Size
(Byte)

Passed Rate (%)

(01,01,03) to (01,01,06)
(pks/sec)

Total (pks/sec)

64

100.00

148810

148810

128

100.00

84459

84459

256

100.00

45290

45290

512

100.00

23496

23496

1024

100.00

11973

11973

1280

100.00

9615

9615

1518

100.00

8127

8127

NOTE

The specifications in the preceding table are obtained in the scenario wherein point-to-point transparent
transmission services are configured and the flow control function is disabled.

The permitted packet loss ratio is set to 0% and the resolution rate is set to 0.1%.

The test duration is set to 60 seconds.

Minimum frame size (byte): 64

Maximum frame size (byte): 1518

Step frame size (byte): custom

Number of pairs: 1

Initial rate (%): 100.00

Maximum rate (%): none

Mode: unidirectional

Table 7-73 Throughput specifications of the EMS4 (24 VC-3s are bound on the GE port)

Issue 02 (2009-07-30)

Frame Size
(Byte)

Passed Rate (%)

(01,03,01) to (01,03,02)
(pks/sec)

Total (pks/sec)

64

100.00

1488095

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Frame Size
(Byte)

Passed Rate (%)

(01,03,01) to (01,03,02)
(pks/sec)

Total (pks/sec)

128

100.00

844595

844595

256

100.00

452899

452899

512

100.00

234962

234962

1024

100.00

119732

119732

1280

100.00

96154

96154

1518

100.00

81274

81274

NOTE

The specifications in the preceding table are obtained in the scenario wherein point-to-point transparent
transmission services are configured and the flow control function is disabled.

The permitted packet loss ratio is set to 0% and the resolution rate is set to 0.1%.

The test duration is set to 60 seconds.

Minimum frame size (byte): 64

Maximum frame size (byte): 1518

Step frame size (byte): custom

Number of pairs: 1

Initial rate (%): 100.00

Maximum rate (%): 100.00

Resolution rate (%): 1.00

Mode: unidirectional

Table 7-74 Packet loss ratio in the case of overloading of the EMS4 (one VC-4 is bound on the
FE port)

7-120

Frame Size
(Byte)

Rate Tested (%)

(01,01,03) to (01,01,06)
(%)

Average (%)

64

100.00

0.000

0.000

128

100.00

0.000

0.000

256

100.00

0.000

0.000

512

100.00

0.000

0.000

1024

100.00

0.000

0.000

1518

100.00

0.000

0.000

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NOTE

The specifications in the preceding table are obtained in the scenario wherein point-to-point transparent
transmission services are configured and the flow control function is disabled.

The tested traffic starts from the throughput and increases to 100% in 10% steps.

The test duration is set to 60 seconds.

Minimum frame size (byte): 64

Maximum frame size (byte): 1518

Step frame size (byte): custom

Number of pairs: 1

Initial rate (%): 100.00

Maximum rate (%): 10.00

Resolution rate (%): none

Mode: unidirectional

Table 7-75 Packet loss ratio in the case of overloading of the EMS4 (24 VC-3s are bound on
the GE port)

Issue 02 (2009-07-30)

Frame Size
(Byte)

Rate Tested (%)

(01,03,01) to (01,03,02)
(%)

Average (%)

64

100.00

0.000

0.000

128

100.00

0.000

0.000

256

100.00

0.000

0.000

512

100.00

0.000

0.000

1024

100.00

0.000

0.000

1280

100.00

0.000

0.000

1518

100.00

0.000

0.000

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NOTE

The specifications in the preceding table are obtained in the scenario wherein point-to-point transparent
transmission services are configured and the flow control function is disabled.

The tested traffic starts from the throughput and increases to 100% in 10% steps.

The test duration is set to 60 seconds.

Minimum frame size (byte): 64

Maximum frame size (byte): 1518

Step frame size (byte): custom

Number of pairs: 1

Initial rate (%): 100.00

Maximum rate (%): 10.00

Resolution rate (%): none

Mode: unidirectional

Table 7-76 Latency specifications of the EMS4 (one VC-4 is bound on the FE port)

7-122

Frame
Size
(Byte)

Rate
Tested
(%)

(01,01,03) to
(01,01,06) (us)CT (us)

Average
(CT) (us)

(01,01,03) to
(01,01,06)
(us)-S&F (us)

Average
(S&F) (us)

64

100.00

110.6

110.6

105.5

105.5

128

100.00

123.8

123.8

113.6

113.6

256

100.00

149.2

149.2

128.8

128.8

512

100.00

195.5

195.5

154.6

154.6

1024

100.00

285.6

285.6

203.7

203.7

1518

100.00

373.1

373.1

251.7

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NOTE

The specifications in the preceding table are obtained in the scenario wherein point-to-point transparent
transmission services are configured and the flow control function is disabled.

The test duration is set to 60 seconds.

The latency modes are classified into two modes, namely, cut through mode and store forward mode.
In cut through mode, the analyzer calculates the difference between the time when the first bit of the
transmitted frame reaches the output port and the time when the first bit of the transmitted frame reaches
the input port. In store forward mode, the analyzer calculates the difference between the time when the
first bit of the transmitted frame reaches the output port and the time when the last bit of the transmitted
frame reaches the input port. In the preceding table, the CT values are obtained in cut through mode
and the S&F values are obtained in store forward mode.

CT: cut through or FIFO; S&F: store forward or LIFO

Measure on one receiving card only. Mode: SmartMetrics Comp. Mode

Minimum frame size (byte): 64

Maximum frame size (byte): 1518

Step frame size (byte): custom

Number of pairs: 1

Initial rate (%): 100.00

Maximum rate (%): 10.00

Resolution rate (%): none

Mode: unidirectional

Table 7-77 Latency specifications of the EMS4 (24 VC-3s are bound on the GE port)

Issue 02 (2009-07-30)

Frame
Size
(Byte)

Rate
Tested
(%)

(01,03,01) to
(01,03,02) (us)CT (us)

Average
(CT) (us)

(01,03,01) to
(01,03,02)
(us)-S&F (us)

Average
(S&F) (us)

64

100.00

80.9

80.9

80.4

80.4

128

100.00

83.0

83.0

82.0

82.0

256

100.00

86.9

86.9

84.9

84.9

512

100.00

94.9

94.9

90.9

90.9

1024

100.00

108.8

108.8

100.7

100.7

1280

100.00

115.2

115.2

105.0

105.0

1518

100.00

120.7

120.7

108.6

108.6

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NOTE

The specifications in the preceding table are obtained in the scenario wherein point-to-point transparent
transmission services are configured and the flow control function is disabled.

The test duration is set to 60 seconds.

The latency modes are classified into two modes, namely, cut through mode and store forward mode.
In cut through mode, the analyzer calculates the difference between the time when the first bit of the
transmitted frame reaches the output port and the time when the first bit of the transmitted frame reaches
the input port. In store forward mode, the analyzer calculates the difference between the time when the
first bit of the transmitted frame reaches the output port and the time when the last bit of the transmitted
frame reaches the input port. In the preceding table, the CT values are obtained in cut through mode
and the S&F values are obtained in store forward mode.

CT: cut through or FIFO; S&F: store forward or LIFO

Measure on one receiving card only. Mode: SmartMetrics Comp. Mode

Minimum frame size (byte): 64

Maximum frame size (byte): 1518

Step frame size (byte): custom

Number of pairs: 1

Initial rate (%): 100.00

Maximum rate (%): 10.00

Resolution rate (%): none

Mode: unidirectional

Table 7-78 Back-to-back specifications of the EMS4 (one VC-4 is bound on the FE port)

7-124

Frame Size
(Byte)

Rate Tested (%)

(01,01,03) to (01,01,06)
Burst Size (Number of
Frames)

Total (Number of
Frames)

64

100.00

1488100

1488100

128

100.00

844590

844590

256

100.00

452900

452900

512

100.00

234960

234960

1024

100.00

119730

119730

1518

100.00

81270

81270

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NOTE

The specifications in the preceding table are obtained in the scenario wherein point-to-point transparent
transmission services are configured and the flow control function is disabled.

The frame size is set to the range from 64 bytes to 1518 bytes, the packet transmission rate is set to
100%, the test duration is set to 2 seconds, and the number of repetitions is set to a value more than 50
on the Smart Application.

The tested traffic is set to the wire speed.

The test duration is set to 10 seconds.

Minimum frame size (byte): 64

Maximum frame size (byte): 1518

Step frame size (byte): custom

Number of pairs: 1

Initial rate (%): 100.00

Maximum rate (%): 10.00

Resolution rate (%): none

Mode: unidirectional

Table 7-79 Back-to-back specifications of the EMS4 (24 VC-3s are bound on the GE port)

Issue 02 (2009-07-30)

Frame Size
(Byte)

Rate Tested (%)

(01,03,01) to (01,03,02)
Burst Size (Number of
Frames)

Total (Number of
Frames)

64

100.00

2976190

2976190

128

100.00

1689190

1689190

256

100.00

905798

905798

512

100.00

469924

469924

1024

100.00

239464

239464

1280

100.00

192308

192308

1518

100.00

162548

162548

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NOTE

The specifications in the preceding table are obtained in the scenario wherein point-to-point transparent
transmission services are configured and the flow control function is disabled.

The frame size is set to the range from 64 bytes to 1518 bytes, the packet transmission rate is set to
100%, the test duration is set to 2 seconds, and the number of repetitions is set to a value more than 50
on the Smart Application.

The tested traffic is set to the wire speed.

The test duration is set to 10 seconds.

Minimum frame size (byte): 64

Maximum frame size (byte): 1518

Step frame size (byte): custom

Number of pairs: 1

Initial rate (%): 100.00

Maximum rate (%): 10.00

Resolution rate (%): none

Mode: unidirectional

Mechanical Specifications
The mechanical specifications of the EMS4 are as follows:
l

Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)

Weight (kg): 1.1

Power Consumption
The maximum power consumption of the EMS4 at room temperature (25C) is 65 W.

7.10 EGS4
This topic describes the version, functions, working principle, valid slots, and technical
specification of the EGS4 (4xGE switching and processing board).
7.10.1 Version Description
The EGS4 is available in three functional versions, namely, N1, N3 and N4. The N1EGS4 is no
longer manufactured.
7.10.2 Functions and Features
The EGS4 supports the Layer 2 switching, link aggregation, and multicast functions.
7.10.3 Working Principle and Signal Flow
The EGS4 consists of the Ethernet access module, network processor module, mapping module,
interface converting module, logic and control module, clock module, and power module.
7.10.4 Front Panel
The front panel of the EGS4 has indicators, interfaces, a bar code, and a laser safety class label.
7.10.5 Valid Slots
The EGS4 can be installed in slot 28 and 1116 in the subrack.
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7.10.6 Feature Code


The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the EGS4 indicates the type of interface.
7.10.7 Board Protection
The EGS4 supports the BPS and PPS.
7.10.8 Parameter Settings
You can set the parameters for the EGS4 by using the T2000.
7.10.9 Technical Specifications
The technical specifications of the EGS4 include the parameters specified for optical interfaces,
laser safety class, Ethernet performance specifications, mechanical specifications, and power
consumption.

7.10.1 Version Description


The EGS4 is available in three functional versions, namely, N1, N3 and N4. The N1EGS4 is no
longer manufactured.
Table 7-80 describes the versions of the EGS4.
Table 7-80 Versions of the EGS4
Item

Description

Functional versions

The EGS4 is available in three functional versions, namely, N1, N3


and N4.

Differences

The N1EGS4 supports the binding of a maximum of 1008 VC-12s.


The N3EGS4 and N4EGS4 support the binding of a maximum of 504
VC-12s. The restrictions that exist in the case of the VC-4/VC-3
binding and VC-12 binding are as follows:

Substitution

VC-4/VC-3 binding: VC-4s are divided into two areas, namely,


VC-4-1 to VC-4-8 and VC-4-9 to VC-4-16. The VC-4s/VC-3s in
these two areas cannot be bound at one time.

VC-12 binding: VC-4s are divided into two areas, namely, VC-4-1
to VC-4-4 and VC-4-9 to VC-4-12. The VC-12s in these two areas
cannot be bound at one time.

The N4EGS4 can substitute for the N3EGS4.

7.10.2 Functions and Features


The EGS4 supports the Layer 2 switching, link aggregation, and multicast functions.
Table 7-81 provides the functions and features of the EGS4.

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Table 7-81 Functions and features of the EGS4


Function and
Feature

EGS4

Basic functions

Accesses and processes 4xGE services and supports the convergence


of 100x10 Mbit/s or 10x100 Mbit/s services..

Specifications of the
optical interface

Supports the 1000BASE-SX/LX/ZX/VX Ethernet optical


interfaces. The optical interfaces support the auto-negotiation
function in compliance with IEEE 802.3z. The optical interfaces
use the SFP optical module and support hot swapping. When the
multi-mode optical fiber is used, the maximum transmission
distance is 550 m. When the single-mode optical fiber is used, the
maximum transmission distance is 10 km. The optical modules that
can meet different requirements for the transmission distance such
as 40 km and 80 km can also be used.

The N1EGS4 and N4EGS4 also support the 1000BASE-T RJ-45


Ethernet electrical interface. The electrical interface supports the
auto-negotiation function. The negotiated rate can be 10 Mbit/s,
100 Mbit/s, or 1000 Mbit/s. The N1EGS4 and N4EGS4 use the
SFP electrical interface and support hot swapping. The maximum
transmission distance is 100 m.

Supports Ethernet II, IEEE 802.3, IEEE 802.1q/p formats.

Supports the frame with a length ranging from 64 bytes to 9216


bytes.

Supports the Jumbo frame with a length less than 9216 bytes.

Format of service
frames

7-128

Maximum uplink
bandwidth

2.5 Gbit/s

Mapping
granularities

Supports the following virtual concatenation granularities: VC-12,


VC-3, VC-4, VC12-Xv (X64), VC3-Xv (X24), and VC4-Xv
(X8).

Number of supported
VCTRUNKs

64

Encapsulation format

Supports the GFP-F, LAPS, and HDLG protocols.

EPL services

Supports PORT-based transparent transmission.

EVPL services

Supports EVPL services based on PORT+VLAN.

Supports a maximum of 4000 services that are accessed through


IP ports.

Supports a maximum of 4000 services that are accessed through


VCTRUNKs.

Supports a maximum of 8000 links.

Supports QinQ-based EVPL services.

Supports PORT-based service forwarding.

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Function and
Feature

EGS4

EPLAN services

Supports the Layer 2 forwarding function.

Supports switching on the client and SDH sides.

Supports the self-learning of the source MAC address. The


capacity of the MAC address table is 128K. The aging time of the
MAC address can be set and queried.

Supports the configuration of the static MAC route.

Supports the creation, deletion, and query of the VB. The


maximum number of supported VBs is 12.

Supports data isolation based on VB+VLAN.

Supports the setting of a maximum of 4000 VLAN services.

EVPLAN

VLAN

Supports VLAN and QinQ.


Supports the addition, deletion, and exchanging of VLAN tags.
The function complies with IEEE 802.1q/p.

MTU

Supports the setting of the packet length, which ranges from 1518
bytes to 9216 bytes. After the setting becomes valid, the length of the
packets that enter or exit the IP ports is limited.

RSTP

Supports the RSTP, which complies with IEEE 802.1w.

Multicast function

Supports the multicast function.

ETH-OAM function

Supports CC for the multicast service, LB test for the unicast


service, and LD.

Supports the initiation of remote loopbacks, auto-negotiation,


status query in the case of a severe fault in the board, and link
performance detection functions, which comply with IEEE
802.3ah.

Test frames

Supports test frames. .

Service mirroring

Does not support service mirroring.

Link aggregation
function

Supports manual link aggregation and static link aggregation.

VLAN convergence

Supports 4096 VLANs (04095) in the case of QinQ services.

Supports 4095 VLANs (14095) in the case of EVPL services.

Protection

Supports the BPS and PPS.

CAR

Supports the CAR.


The granularity is 64 kbit/s.
The N1EGS4 supports 512 rate modes, and the N3EGS4 and N4EGS4
support 60 rate modes.

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Function and
Feature

EGS4

Flow classification

The N3EGS4/N4EGS4 supports the flow classification based on


PORT, PORT+VLAN, or PORT+SVLAN.

LCAS function

Dynamically increases or decreases the bandwidth and protects the


bandwidth in compliance with ITU-T G.7042.

LPT function

The N3EGS4 supports the P2P LPT.

The N4EGS4 supports the P2P LPT and the P2MP LPT.

Inter-board link
aggregation

Supports inter-board link aggregation.

Flow control
function

Supports the port-based flow control function that complies with


IEEE 802.3x.

Loopback function

Supports inloops on Ethernet ports (at the PHY layer).

Ethernet
performance
monitoring

Supports RMON of the Ethernet performance at the port level and the
VCTRUNK level.

Alarms and
performance events

Reports various alarms and performance events, which facilitates


management and maintenance of the equipment.

7.10.3 Working Principle and Signal Flow


The EGS4 consists of the Ethernet access module, network processor module, mapping module,
interface converting module, logic and control module, clock module, and power module.
Figure 7-40 shows the functional block diagram of the EGS4 by describing how to process
1xGE signals.

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Figure 7-40 Functional block diagram of the EGS4


Backplane

Laser
shutdown

Cross-connect unit
Interface
converting
module

VCP

Network processor module

DENCP

GE Ethernet
access
module

ENCP

Network Control Switch


processor
fabric
Data

Cross-connect unit

Mapping module

LOS

Communication

Logic and
control module

Reference clock and frame header

+3.3 V
Clock module
50
77
MHz MHz

Power
module

Power
module

Fuse

SCC unit
SCC unit

-48 V/-60 V
-48 V/-60 V

125 155
MHz MHz

Ethernet Access Module


In the receive direction, the optical signals from Ethernet equipment such as switches or routers
are converted into electrical signals. If the signals are accessed through electrical interfaces, O/
E conversion is not required. At the PHY layer, the electrical signals are decoded and the
ETH_LOS alarm is detected. The electrical signals are converted from serial signals into parallel
signals and then sent to the network processor module.
In the transmit direction, the parallel signals are converted into serial signals. At the PHY layer,
signals are encoded and converted from electrical signals to optical signals.

Network Processor Module


The network processor module consists of the network processor and switch fabric. The network
processor first performs MAC functions, which include code conversion, framing of Ethernet
packets, CRC check, and Ethernet performance statistics.
After the striped Ethernet frames enter the core of network processor, the flow is classified
according to the service type and configuration requirement. The frames are encapsulated or
decapsulated. The Ethernet/VLAN format is supported.
The network processor module supports the following functions:
l

Flow sense and flow classification

Unicast, multicast, and broadcast of the flow

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l

Setting of data priorities

WFQ

Three CoSs

Mapping Module
The mapping module performs encapsulation and mapping functions.
In the upstream direction, this module first encapsulates Ethernet signals in LAPS, GFP-F, or
HDLC format. The concatenation is processed. The LCAS function is supported. Then, the
Ethernet signals are converted into SDH signals.
In the downstream direction, SDH signals are demapped. The delay of virtual concatenation is
compensated. After aligning, packets are decapsulated according to the encapsulation format.
The decapsulated data is finally transmitted to the network processor module in packets.

Interface Converting Module


The interface converting module converts the 622 Mbit/s LVDS bus of the SDH system into the
parallel bus. The high-rate backplane interface is connected to the low-rate interface chip of the
transmit system through the interface converting module.

Logic and Control Module


The logic and control module consists of the CPU, register, oscillator, Ethernet port, and HDLC
controller. This module is connected to external circuits through the bus. The logic and control
module performs the following functions:
l

Manages and configures other modules of the board.

Implements inter-board communication through the internal Ethernet interface.

The control module also contains basic logic units. This module has the following functions:
l

Writes and reads the register.

Provides interfaces for the CPU.

Checks and selects the clock.

Performs phase discrimination and frequency division on the clock.

Checks the in-service state of the cross-connect, SCC, and line boards.

Controls the shutting down of the optical module.

Implements communication.

Controls indicators.

Clock Module
The clock module traces the system reference clock and generates the required working clock
for each chip. The frequency of the clock can be 50 MHz, 77 MHz, 125 MHz, or 155 MHz.

Power Module
It converts the 48 V/60 V power supply into the DC voltages that the modules of the board
require.
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7.10.4 Front Panel


The front panel of the EGS4 has indicators, interfaces, a bar code, and a laser safety class label.

Diagram of the Front Panel


Figure 7-41 shows the appearance of the front panel of the N1EGS4/N3EGS4/N4EGS4 that is
installed with the optical interface.
Figure 7-41 Front panel of the N1EGS4/N3EGS4/N4EGS4 that is installed with the optical
interface

EGS4
STAT
ACT
PROG
SRV

CLASS 1
LASER
PRODUCT

OUT1
IN1
OUT2
IN2
OUT3
IN3
OUT4
IN4
LINK ACT
1
2
3
4

EGS4

The N1EGS4/N4EGS4 can also be installed with the GE electrical interface. Figure 7-42 shows
the appearance of the front panel of the N1EGS4/N4EGS4 that is installed with the GE electrical
interface.

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Figure 7-42 front panel of the N1EGS4/N4EGS4 that is installed with the GE electrical interface

EGS4
STAT
ACT
PROG
SRV

CLASS 1
LASER
PRODUCT

OUT1
IN1
OUT2
IN2
OUT3
IN3
OUT4
IN4
LINK ACT
1
2
3
4

EGS4

Indicators
The front panel of the board has the following indicators:
l

Board hardware status indicator (STAT) two colors (red and green)

Service activation status indicator (ACT) one color (green)

Board software status indicator (PROG) two colors (red and green)

Service alarm indicator (SRV) three colors (red, green, and yellow)

Connection status indicator (LINK) one color (green)

Data receiving and transmission indicator (ACT) one color (orange)

For the meanings of the status of the indicators, see A Indicators.

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Interfaces
The front panel of the N1EGS4/N3EGS4/N4EGS4 has four GE optical interfaces. Table 7-82
describes the types and usage of the optical interfaces of the N1EGS4/N3EGS4/N4EGS4.
Table 7-82 Optical interfaces of the N1EGS4/N3EGS4/N4EGS4
Interface

Type of
Interface

Usage

OUT1/IN1

LC (swappable)

Transmits and receives 1000BASE-SX/LX/ZX


signals.

OUT2/IN2

LC (swappable)

Transmits and receives 1000BASE-SX/LX/ZX


signals.

OUT3/IN3

LC (swappable)

Transmits and receives 1000BASE-SX/LX/ZX


signals.

OUT4/IN4

LC (swappable)

Transmits and receives 1000BASE-SX/LX/ZX


signals.

The four GE electrical interfaces of the N1EGS4/N4EGS4 are of the same type and have the
same usage. Table 7-83 describes the types and usage of the electrical interfaces of the N1EGS4/
N4EGS4.
Table 7-83 Electrical interfaces of the N1EGS4/N4EGS4
Interface

Type of
Interface

Usage

GE

RJ-45
(swappable)

Transmits and receives 1000BASE-T signals.

Table 7-84 provides the pin assignments of the RJ-45 interface of the N1EGS4/N4EGS4.
Table 7-84 Pin assignments of the RJ-45 interface of the N1EGS4/N4EGS4

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Pin

Description

BI_DA+

BI_DA

BI_DB+

BI_DC+

BI_DC

BI_DB
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Pin

Description

BI_DD+

BI_DD

7.10.5 Valid Slots


The EGS4 can be installed in slot 28 and 1116 in the subrack.

7.10.6 Feature Code


The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the EGS4 indicates the type of interface.
Table 7-85 provides the relationship between the feature code of the EGS4 and the type of
interface.
Table 7-85 Relationship between the feature code of the EGS4 and the type of interface
Board

Feature Code

Type of Interface

SSN1EGS410,
SSN3EGS41O, and
SSN4EGS10

10

1000BASE-SX (0.5 km)

SSN1EGS411,
SSN3EGS411, and
SSN4EGS411

11

1000BASE-LX (10 km)

SSN1EGS412,
SSN3EGS412, and
SSN4EGS412

12

1000BASE-VX (40 km)

SSN1EGS413,
SSN3EGS413, and
SSN4EGS413

13

1000BASE-ZX (80 km)

SSN1EGS414 and
SSN4EGS414

14

1000BASE-T (100 m)

7.10.7 Board Protection


The EGS4 supports the BPS and PPS.

Protection Principle
When the BPS protection is provided for the EGS4, the GE and FE ports are protected by using
the single-fed and selective-receiving scheme. The EGS4 may be connected to many sets of
communication equipment. Normally, the active board is working and services are transmitted
in two directions of the active link. On the backup link, the EGS4 disables the transmission of
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all ports. In this case, the ports of the opposite board are in the linkdown state. In addition, the
opposite board enables the transmission but does not transmit services. In this manner, the
receive ports of the backup EGS4 are not in the linkdown state. The solid lines in Figure 7-43
show how the EGS4 normally works.
Figure 7-43 Normal working of the EGS4

No.1

Active
EGS4

Active
communication
equipment
Standby
communication
equipment

No.2

No.3

Active
communication
equipment

XCS

B
Standby
communication
equipment

No.1
No.2

Standby
EGS4

No.3

Active
communication
equipment
Standby
communication
equipment

BPS Protection

When the BPS protection is provided, if the active board detects the linkdown state of any link
or any fault in the board, the cross-connect board switches all the services to the standby board.
In this manner, services are protected. The solid lines in Figure 7-44 show how the BPS
protection functions. The services numbered 1, 2 and 3 are all switched to the standby EGS4
and the corresponding communication equipment.

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Figure 7-44 Principle of the BPS protection for the EGS4

No.1

Active
EGS4

Active
communication
equipment
Standby
communication
equipment

No.2

No.3

Active
communication
equipment

XCS

B
Standby
communication
equipment

No.1
No.2

Standby
EGS4

No.3

Active
communication
equipment
Standby
communication
equipment

PPS Protection

When the PPS protection is provided, if the active board detects the linkdown state of any link,
any fault in the board, or the offline state of any board, the cross-connect board switches all the
services to the standby board. In this manner, services are protected. The solid lines in Figure
7-45 show how the PPS protection functions. Only the service numbered 1 is switched to the
standby EGS4 and the standby communication equipment.

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Figure 7-45 Principle of the PPS protection for the EGS4

No.1

Active
communication
equipment

Active
EGS4

Standby
communication
equipment

No.2

No.3
Active
communication
equipment

XCS

B
Standby
communication
equipment

No.1
No.2

Standby
EGS4

No.3

Active
communication
equipment

Standby
communication
equipment

The conditions that trigger the protection for the EGS4 are as follows:
l

Fault at the PHY layer of the MAC port, that is, linkdown state

Fault in key hardware units of the board, such as the power module, optical module, and
clock

Offline state of the board

WARNING
When the board-level protection is performed, the GE ports support the auto-negotiation and
1000M full-duplex mode.

Board Configuration
Two EGS4 boards should be configured to provide the board-level protection. One EGS4 is the
active board and the other is the standby board. When you configure the EGS4 board protection,
ensure that the access capacity of the slot that houses the standby board must not be less than
the access capacity of the slot that houses the active board.
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7.10.8 Parameter Settings


You can set the parameters for the EGS4 by using the T2000.
You can set the following parameters for the EGS4 by using the T2000:
l

Working mode

LCAS

Maximum frame length

Mapping protocol

For the description of each parameter, see F Parameter Settings.

7.10.9 Technical Specifications


The technical specifications of the EGS4 include the parameters specified for optical interfaces,
laser safety class, Ethernet performance specifications, mechanical specifications, and power
consumption.

Parameters Specified for Optical Interfaces


Table 7-86 lists the parameters specified for the optical interfaces of the EGS4.
Table 7-86 Parameters specified for the optical interfaces of the EGS4

7-140

Parameter

Value

Type of optical
interface

1000BASE-ZX
(80 km)

1000BASEEX (40 km)

1000BASELX (10 km)

1000BASE-SX
(0.5 km)

Type of fiber

Single-mode LC

Single-mode
LC

Single-mode
LC

Multi-mode LC

Launched optical
power range
(dBm)

-2 to +5

-5.0 to 0

-9.5 to -3

-9.5 to -2.5

Operating
wavelength range
(nm)

1500 to 1580

1275 to 1350

1270 to 1355

770 to 860

Minimum
overload (dBm)

-3

-3

-3

Receiver
sensitivity (dBm)

-23

-23

-20

-17

Minimum
extinction ratio
(dB)

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Laser Safety Class


The safety class of the laser on the board is Class 1. The maximum launched optical power of
the optical interfaces is less than 10 dBm (10 mW).

Ethernet Performance Specifications


Figure 7-46 shows the connection for testing the throughput specifications, packet loss ratio in
the case of overloading, and latency specifications of the EGS4.
Figure 7-46 Connection for testing the throughput specifications, packet loss ratio in the case
of overloading, and latency specifications
Port 1
Tested
equipment 1

Tested
equipment 2
Port 2

Port 1

Port 2

Data network
performance
analyzer

Figure 7-47 shows the connection for testing the back-to-back specifications of the EGS4.
Figure 7-47 Connection for testing the back-to-back specifications
Tested
equipment 1

Port 1

Port 2

Data network
performance
analyzer

Table 7-87 and Table 7-88 list the throughput specifications of the EGS4. Table 7-89 and Table
7-90 list the packet loss ratio in the case of overloading of the EGS4. Table 7-91 and Table
7-92 list the latency specifications of the EGS4. Table 7-93 and Table 7-94 list the back-toback specifications of the EGS4.
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NOTE

The specifications vary according to the configuration and networking of the test environment and
the VC services bound on the VCG side. The specifications that are obtained in the actual environment
are used.

The specifications in the following tables are obtained in the following scenario: EPL services are
configured and one VC-4 is bound on the FE port, or EPL services are configured and 24 VC-3s are
bound on the GE port.

The specifications of a board of a specific version are not provided because the board version has
negligible effect on the specifications.

The specifications in the following tables are obtained by using the Smart Application.

Table 7-87 Throughput specifications of the EGS4 (one VC-4 is bound on the FE port)
Frame Size
(Byte)

Passed Rate (%)

(01,01,03) to (01,01,06)
(pks/sec)

Total (pks/sec)

64

100.00

148810

148810

128

100.00

84459

84459

256

100.00

45290

45290

512

100.00

23496

23496

1024

100.00

11973

11973

1280

100.00

9615

9615

1518

100.00

8127

8127

NOTE

The specifications in the preceding table are obtained in the scenario wherein point-to-point transparent
transmission services are configured and the flow control function is disabled.

The permitted packet loss ratio is set to 0% and the resolution rate is set to 0.1%.

The test duration is set to 60 seconds.

Minimum frame size (byte): 64

Maximum frame size (byte): 1518

Step frame size (byte): custom

Number of pairs: 1

Initial rate (%): 100.00

Maximum rate (%): none

Mode: unidirectional

Table 7-88 Throughput specifications of the EGS4 (24 VC-3s are bound on the GE port)

7-142

Frame Size
(Byte)

Passed Rate (%)

(01,03,01) to (01,03,02)
(pks/sec)

Total (pks/sec)

64

100.00

1488095

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Frame Size
(Byte)

Passed Rate (%)

(01,03,01) to (01,03,02)
(pks/sec)

Total (pks/sec)

128

100.00

844595

844595

256

100.00

452899

452899

512

100.00

234962

234962

1024

100.00

119732

119732

1280

100.00

96154

96154

1518

100.00

81274

81274

NOTE

The specifications in the preceding table are obtained in the scenario wherein point-to-point transparent
transmission services are configured and the flow control function is disabled.

The permitted packet loss ratio is set to 0% and the resolution rate is set to 0.1%.

The test duration is set to 60 seconds.

Minimum frame size (byte): 64

Maximum frame size (byte): 1518

Step frame size (byte): custom

Number of pairs: 1

Initial rate (%): 100.00

Maximum rate (%): 100.00

Resolution rate (%): 1.00

Mode: unidirectional

Table 7-89 Packet loss ratio in the case of overloading of the EGS4 (one VC-4 is bound on the
FE port)

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Frame Size
(Byte)

Rate Tested (%)

(01,01,03) to (01,01,06)
(%)

Average (%)

64

100.00

0.000

0.000

128

100.00

0.000

0.000

256

100.00

0.000

0.000

512

100.00

0.000

0.000

1024

100.00

0.000

0.000

1518

100.00

0.000

0.000

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NOTE

The specifications in the preceding table are obtained in the scenario wherein point-to-point transparent
transmission services are configured and the flow control function is disabled.

The tested traffic starts from the throughput and increases to 100% in 10% steps.

The test duration is set to 60 seconds.

Minimum frame size (byte): 64

Maximum frame size (byte): 1518

Step frame size (byte): custom

Number of pairs: 1

Initial rate (%): 100.00

Maximum rate (%): 10.00

Resolution rate (%): none

Mode: unidirectional

Table 7-90 Packet loss ratio in the case of overloading of the EGS4 (24 VC-3s are bound on the
GE port)

7-144

Frame Size
(Byte)

Rate Tested (%)

(01,03,01) to (01,03,02)
(%)

Average (%)

64

100.00

0.000

0.000

128

100.00

0.000

0.000

256

100.00

0.000

0.000

512

100.00

0.000

0.000

1024

100.00

0.000

0.000

1280

100.00

0.000

0.000

1518

100.00

0.000

0.000

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NOTE

The specifications in the preceding table are obtained in the scenario wherein point-to-point transparent
transmission services are configured and the flow control function is disabled.

The tested traffic starts from the throughput and increases to 100% in 10% steps.

The test duration is set to 60 seconds.

Minimum frame size (byte): 64

Maximum frame size (byte): 1518

Step frame size (byte): custom

Number of pairs: 1

Initial rate (%): 100.00

Maximum rate (%): 10.00

Resolution rate (%): none

Mode: unidirectional

Table 7-91 Latency specifications of the EGS4 (one VC-4 is bound on the FE port)

Issue 02 (2009-07-30)

Frame
Size
(Byte)

Rate
Tested
(%)

(01,01,03) to
(01,01,06) (us)CT (us)

Average
(CT) (us)

(01,01,03) to
(01,01,06)
(us)-S&F (us)

Average
(S&F) (us)

64

100.00

110.6

110.6

105.5

105.5

128

100.00

123.8

123.8

113.6

113.6

256

100.00

149.2

149.2

128.8

128.8

512

100.00

195.5

195.5

154.6

154.6

1024

100.00

285.6

285.6

203.7

203.7

1518

100.00

373.1

373.1

251.7

251.7

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NOTE

The specifications in the preceding table are obtained in the scenario wherein point-to-point transparent
transmission services are configured and the flow control function is disabled.

The test duration is set to 60 seconds.

The latency modes are classified into two modes, namely, cut through mode and store forward mode.
In cut through mode, the analyzer calculates the difference between the time when the first bit of the
transmitted frame reaches the output port and the time when the first bit of the transmitted frame reaches
the input port. In store forward mode, the analyzer calculates the difference between the time when the
first bit of the transmitted frame reaches the output port and the time when the last bit of the transmitted
frame reaches the input port. In the preceding table, the CT values are obtained in cut through mode
and the S&F values are obtained in store forward mode.

CT: cut through or FIFO; S&F: store forward or LIFO

Measure on one receiving card only. Mode: SmartMetrics Comp. Mode

Minimum frame size (byte): 64

Maximum frame size (byte): 1518

Step frame size (byte): custom

Number of pairs: 1

Initial rate (%): 100.00

Maximum rate (%): 10.00

Resolution rate (%): none

Mode: unidirectional

Table 7-92 Latency specifications of the EGS4 (24 VC-3s are bound on the GE port)

7-146

Frame
Size
(Byte)

Rate
Tested
(%)

(01,03,01) to
(01,03,02) (us)CT (us)

Average
(CT) (us)

(01,03,01) to
(01,03,02)
(us)-S&F (us)

Average
(S&F) (us)

64

100.00

80.9

80.9

80.4

80.4

128

100.00

83.0

83.0

82.0

82.0

256

100.00

86.9

86.9

84.9

84.9

512

100.00

94.9

94.9

90.9

90.9

1024

100.00

108.8

108.8

100.7

100.7

1280

100.00

115.2

115.2

105.0

105.0

1518

100.00

120.7

120.7

108.6

108.6

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NOTE

The specifications in the preceding table are obtained in the scenario wherein point-to-point transparent
transmission services are configured and the flow control function is disabled.

The test duration is set to 60 seconds.

The latency modes are classified into two modes, namely, cut through mode and store forward mode.
In cut through mode, the analyzer calculates the difference between the time when the first bit of the
transmitted frame reaches the output port and the time when the first bit of the transmitted frame reaches
the input port. In store forward mode, the analyzer calculates the difference between the time when the
first bit of the transmitted frame reaches the output port and the time when the last bit of the transmitted
frame reaches the input port. In the preceding table, the CT values are obtained in cut through mode
and the S&F values are obtained in store forward mode.

CT: cut through or FIFO; S&F: store forward or LIFO

Measure on one receiving card only. Mode: SmartMetrics Comp. Mode

Minimum frame size (byte): 64

Maximum frame size (byte): 1518

Step frame size (byte): custom

Number of pairs: 1

Initial rate (%): 100.00

Maximum rate (%): 10.00

Resolution rate (%): none

Mode: unidirectional

Table 7-93 Back-to-back specifications of the EGS4 (one VC-4 is bound on the FE port)

Issue 02 (2009-07-30)

Frame Size
(Byte)

Rate Tested (%)

(01,01,03) to (01,01,06)
Burst Size (Number of
Frames)

Total (Number of
Frames)

64

100.00

1488100

1488100

128

100.00

844590

844590

256

100.00

452900

452900

512

100.00

234960

234960

1024

100.00

119730

119730

1518

100.00

81270

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NOTE

The specifications in the preceding table are obtained in the scenario wherein point-to-point transparent
transmission services are configured and the flow control function is disabled.

The frame size is set to the range from 64 bytes to 1518 bytes, the packet transmission rate is set to
100%, the test duration is set to 2 seconds, and the number of repetitions is set to a value more than 50
on the Smart Application.

The tested traffic is set to the wire speed.

The test duration is set to 10 seconds.

Minimum frame size (byte): 64

Maximum frame size (byte): 1518

Step frame size (byte): custom

Number of pairs: 1

Initial rate (%): 100.00

Maximum rate (%): 10.00

Resolution rate (%): none

Mode: unidirectional

Table 7-94 Back-to-back specifications of the EGS4 (24 VC-3s are bound on the GE port)

7-148

Frame Size
(Byte)

Rate Tested (%)

(01,03,01) to (01,03,02)
Burst Size (Number of
Frames)

Total (Number of
Frames)

64

100.00

2976190

2976190

128

100.00

1689190

1689190

256

100.00

905798

905798

512

100.00

469924

469924

1024

100.00

239464

239464

1280

100.00

192308

192308

1518

100.00

162548

162548

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NOTE

The specifications in the preceding table are obtained in the scenario wherein point-to-point transparent
transmission services are configured and the flow control function is disabled.

The frame size is set to the range from 64 bytes to 1518 bytes, the packet transmission rate is set to
100%, the test duration is set to 2 seconds, and the number of repetitions is set to a value more than 50
on the Smart Application.

The tested traffic is set to the wire speed.

The test duration is set to 10 seconds.

Minimum frame size (byte): 64

Maximum frame size (byte): 1518

Step frame size (byte): custom

Number of pairs: 1

Initial rate (%): 100.00

Maximum rate (%): 10.00

Resolution rate (%): none

Mode: unidirectional

Mechanical Specifications
The mechanical specifications of the EGS4 are as follows:
l

Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)

Weight of the N1EGS4 or N3EGS4 (kg): 1.1

Weight of the N4EGS4 (kg): 0.7

Power Consumption
The maximum power consumption of the N1EGS4 and N3EGS4 at room temperature (25C) is
70 W.
The maximum power consumption of the N4EGS4 at room temperature (25C) is 34 W.

7.11 EGR2
This topic describes the version, functions, working principle, valid slots, and technical
specification of the EGR2 (2xGE ring processing board).
7.11.1 Version Description
The EGR2 is available in one functional version, namely, N2.
7.11.2 Functions and Features
The EGR2 supports the Layer 2 switching, port aggregation, and RPR functions.
7.11.3 Working Principle and Signal Flow
The EGR2 consists of the Ethernet access module, network processor module, RPR protocol
processing module, mapping module, interface converting module, logic and control module,
clock module, and power module.
7.11.4 Front Panel
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The front panel of the EGR2 has indicators, interfaces, a bar code, and a laser safety class label.
7.11.5 Valid Slots
The EGR2 can be installed in slots 28 and 1116 in the subrack.
7.11.6 Feature Code
The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the EGR2 indicates the type of optical interface.
7.11.7 Parameter Settings
You can set the parameters for the EGR2 by using the T2000.
7.11.8 Technical Specifications
The technical specifications of the EGR2 include the parameters specified for optical interfaces,
laser safety class, Ethernet performance specifications, mechanical specifications, and power
consumption.

7.11.1 Version Description


The EGR2 is available in one functional version, namely, N2.

7.11.2 Functions and Features


The EGR2 supports the Layer 2 switching, port aggregation, and RPR functions.
Table 7-95 provides the functions and features of the EGR2.
Table 7-95 Functions and features of the EGR2
Function and
Feature

EGR2

Basic functions

Accesses and processes 2xGE services.


Supports the RPR feature.

Specifications of the
optical interface

Format of service
frames

7-150

The optical interfaces are 1000BASE-SX/LX/ZX/VX Ethernet


optical interfaces.

The optical interfaces support the auto-negotiation function in


compliance with IEEE 802.3z.

The optical interfaces use the SFP optical module and support hot
swapping.

When the multi-mode optical fiber is used, the maximum


transmission distance is 550 m.

When the single-mode optical fiber is used, the maximum


transmission distance is 10 km.

The optical modules that can meet different requirements for the
transmission distance such as 40 km and 80 km can also be used.

Supports Ethernet II, IEEE 802.3, and IEEE 802.1q TAG formats.

Supports the frame with a length ranging from 64 bytes to 9600


bytes.

Supports the Jumbo frame with a length less than 9600 bytes.

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Function and
Feature

EGR2

Maximum uplink
bandwidth

2.5 Gbit/s
The EGR2 can adapt to the bandwidth of the slot.

Mapping
granularities

Supports VC-3, VC3-2v, VC-4, and VC4-Xv (X8) granularities.

Encapsulation
format

Supports the GFP-F and LAPS protocols.

EVPL services

Supports EVPL services. The frame format can be Ethernet II,


IEEE 802.3, IEEE 802.1q TAG, or MPLS Martini.

Supports the MPLS encapsulation and forwarding based on PORT


or PORT+VLAN.

Supports five types of LSPs, including ingress LSP, egress LSP,


transit LSP, RPR ingress LSP, and RPR transit LSP.

Supports a maximum of 512 LSPs.

Supports EVPLAN services that use the stack VLAN


encapsulation.

Supports the self-learning of the source MAC address. The capacity


of the MAC address table in the N2 functional version is 64K. The
aging time of the MAC address can be set and queried.

Supports the configuration of the static MAC routes. A maximum


of 4K static MAC routes can be configured.

Supports data isolation based on VB+VLAN.

Supports the creation, deletion, and query of the VB. The maximum
number of supported VBs is 16. The maximum number of logical
ports for each VB is 32.

EVPLAN services

Issue 02 (2009-07-30)

7 Data Boards

MTU

Supports the setting of the packet length, which ranges from 1518
bytes to 9600 bytes. After the setting becomes valid, the length of the
packets that enter or exit the IP ports is limited.

MPLS

Supports MartinioE.

Stack VLAN

Supports the stack VLAN.

VLAN

Supports 4096 VLAN tags, and the addition, deletion, and exchanging
of VLAN tags in compliance with IEEE 802.1q.

VLAN convergence

Supports the VLAN convergence.


The maximum number of VLANs is 4K.

VLAN tag
exchanging

Supports the replacement of VLAN tags in Ethernet signal frames.

Port aggregation

Supports the aggregation of a maximum of two GE ports.

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Function and
Feature

EGR2

RPR

Supports the RPR feature that complies with IEEE 802.17.

Supports a maximum of 255 nodes on the ring network, and


supports stripping at the destination node and weighted fairness
algorithm.

Supports five priority levels, including A0, A1, B_EIR, B_CIR,


and C, and supports automatic discovery of topologies, which can
display the network status in real time.

Supports three protection modes, including Steering, Wrapping,


and Wrapping+Steering. Hence, the signal failure time is less than
50 ms.

Supports the manual configuration of routes for the services on the


RPR ring network.

Supports the self-learning of routes on the ring, that is, supports the
learning of mapping relationship between MAC addresses and
node numbers.

RSTP

Supports the broadcast packet suppression and RSTP, which comply


with IEEE 802.1w.

Multicast function

Supports the multicast function.

CAR

Supports the CAR.


The granularity is 64 kbit/s.

7-152

Flow classification

Supports the flow classification based on PORT, PORT+VLAN ID,


or PORT+VLAN ID+VLAN PRI.

LCAS function

Dynamically increases or decreases the bandwidth and protects the


bandwidth in compliance with ITU-T G.7042.

Flow control
function

Supports the port-based flow control function that complies with


IEEE 802.3x.

Echo test frames

Supports the echo function specified in the RPR OAM function, which
is used to test the connectivity of the link.

Loopback function

Supports inloops on Ethernet ports (at the PHY layer or MAC layer).

Ethernet
performance
monitoring

Supports Ethernet performance monitoring at the port level.

Alarms and
performance events

Reports various alarms and performance events, which facilitates the


management and maintenance of the equipment.

Weighted fairness
algorithm

Supports the weighted fairness algorithm.

Automatic discovery
of topologies

Supports the automatic discovery of topologies.

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Function and
Feature

EGR2

Maximum number of
supported nodes

255

Service priority
levels

Supports A0, A1, B_CIR, B_EIR, and C.

7.11.3 Working Principle and Signal Flow


The EGR2 consists of the Ethernet access module, network processor module, RPR protocol
processing module, mapping module, interface converting module, logic and control module,
clock module, and power module.
Figure 7-48 shows the functional block diagram of the EGR2 by describing how to process
1xGE/FE signals.
Figure 7-48 Functional block diagram of the EGR2
Backplane

RPR protocol
processing module

Cross-connect
unit

Communication

Logic and
control module

SCC unit

Reference clock and frame header

50 MHz
77 MHz
125 MHz Clock module
100 MHz

Crossconnect unit

Mapping module

Laser shutdown
LOS

Interface
converting
module

VCP

RPR
MAC
(west)

DENCP

Network processor module

RPR
MAC
(east)

ENCP

GE/FE Ethernet
access
module

Control
Network signal Switch
processor
fabric
Data

+3.3 V
Power
module

Power
module

Fuse

Cross-connect
unit

-48 V/-60 V
-48 V/-60 V

RPR: resilient package ring

Ethernet Access Module


In the receive direction, the optical signals from Ethernet equipment such as switches or routers
are converted into electrical signals. If the signals are accessed through electrical interfaces, O/
E conversion is not required. At the PHY layer, the electrical signals are decoded and the
ETH_LOS alarm is detected. The electrical signals are converted from serial signals into parallel
signals and then sent to the network processor module.
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In the transmit direction, the parallel signals are converted into serial signals. At the PHY layer,
signals are encoded and converted from electrical signals to optical signals.

Network Processor Module


The network processor module consists of the network processor and switch fabric. The network
processor first performs MAC functions, which include code conversion, framing of Ethernet
packets, CRC check, and Ethernet performance statistics.
After the striped Ethernet frames enter the core of network processor, the flow is classified
according to the service type and configuration requirement. The frames are encapsulated or
decapsulated. The following formats are supported:
l

MPLS

L2 MPLS VPN

Ethernet/VLAN

In the receive direction, services are mapped and forwarded after the Tunnel and VC tags are
added according to the service configuration. In the transmit direction, the Tunnel or VC tag is
extracted based on the level (P or PE) of the equipment. Services are then routed or forwarded.
The network processor module supports the following functions:
l

Flow sense and flow classification

Unicast, multicast, and broadcast of the flow

Setting of data priorities

WFQ

Four CoSs

RPR Protocol Processing Module


The RPR implements the weighted fairness algorithm and statistical multiplexing for the ring
bandwidth. In addition, the RPR provides protection switching schemes. By using the RPR
protocol and RPR weighted fairness algorithm, the RPR protocol processing module controls
the bandwidth of each node accessed by the ring network. In addition, the RPR ring has the
features of spatial reuse and statistical multiplexing. Hence, the bandwidth utilization is
improved.
Topology auto-discovery ensures the plug-and-play feature of the RPR. The protocol for
topology auto-discovery provides correct and reliable ways of discovering topologies of all
nodes and changes occurring on these topologies.
RPR unicast frames are striped at the destination node and thus the bandwidth on the ring is
reused spatially.
The RPR ring supports a maximum of 255 nodes.

Mapping Module
The mapping module performs encapsulation and mapping functions.
In the upstream direction, virtual concatenation services support the LCAS function. The
encapsulation formats are LAPS and GFP-F.
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In the downstream direction, SDH signals are demapped. The delay of virtual concatenation is
compensated. After aligning, packets are decapsulated according to the encapsulation format.
The decapsulated data is finally transmitted to the RPR protocol processing module in packets.

Interface Converting Module


The interface converting module converts the 622 Mbit/s LVDS bus of the SDH system into the
parallel bus. The high-rate backplane interface is connected to the low-rate interface chip of the
transmit system through the interface converting module.

Logic and Control Module


The logic and control module consists of the CPU, register, oscillator, Ethernet port, and HDLC
controller. This module is connected to external circuits through the bus. The logic and control
module performs the following functions:
l

Manages and configures other modules of the board.

Implements inter-board communication through the internal Ethernet interface.

The control module also contains basic logic units. This module performs the following
functions:
l

Writes and reads the register.

Provides interfaces for the CPU.

Checks and selects the clock.

Performs phase discrimination and frequency division on the clock.

Checks the in-service state of the cross-connect, SCC, and line boards.

Controls the shutting down of the optical module.

Implements communication.

Controls indicators.

Clock Module
The clock module traces the system reference clock and generates the required working clock
for each chip. The frequency of the clock can be 50 MHz, 77 MHz, 125 MHz, or 100 MHz.

Power Module
It converts the 48 V/60 V power supply into the DC voltages that the modules of the board
require.

7.11.4 Front Panel


The front panel of the EGR2 has indicators, interfaces, a bar code, and a laser safety class label.

Diagram of the Front Panel


Figure 7-49 shows the appearance of the front panel of the EGR2.
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Figure 7-49 Front panel of the EGR2

EGR2
STAT
ACT
PROG
SRV
LINK1
ACT1
LINK2
ACT2
CLASS 1
LASER
PRODUCT

OUT1
IN1
OUT2
IN2

EGR2

Indicators
The front panel of the board has the following indicators:
l

Board hardware status indicator (STAT) two colors (red and green)

Service activation status indicator (ACT) one color (green)

Board software status indicator (PROG) two colors (red and green)

Service alarm indicator (SRV) three colors (red, green, and yellow)

Connection status indicator (LINK) one color (green)

Data receiving and transmission indicator (ACT) one color (orange)

For the meanings of the status of the indicators, see A Indicators.

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Interfaces
The front panel of the EGR2 has two optical interfaces. Table 7-96 describes the types and usage
of the optical interfaces of the EGR2.
Table 7-96 Optical interfaces of the EGR2
Interface

Type of Interface

Usage

OUT1/IN1

LC (swappable)

Transmits and receives 1000BASE-SX/LX/ZX


signals.

OUT2/IN2

LC (swappable)

Transmits and receives 1000BASE-SX/LX/ZX


signals.

7.11.5 Valid Slots


The EGR2 can be installed in slots 28 and 1116 in the subrack.

7.11.6 Feature Code


The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the EGR2 indicates the type of optical interface.
Table 7-97 provides the relationship between the feature code of the EGR2 and the type of
optical interface.
Table 7-97 Relationship between the feature code of the EGR2 and the type of optical interface
Board

Feature Code

Type of Optical Interface

SSN2EGR210

10

1000BASE-SX (0.5 km)

SSN2EGR211

11

1000BASE-LX (10 km)

SSN2EGR212

12

1000BASE-VX (40 km)

SSN2EGR213

13

1000BASE-ZX (80 km)

7.11.7 Parameter Settings


You can set the parameters for the EGR2 by using the T2000.
You can set the following parameters for the EGR2 by using the T2000:
l

Working mode

LCAS

Maximum frame length

Mapping protocol

For the description of each parameter, see F Parameter Settings.


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7.11.8 Technical Specifications


The technical specifications of the EGR2 include the parameters specified for optical interfaces,
laser safety class, Ethernet performance specifications, mechanical specifications, and power
consumption.

Parameters Specified for Optical Interfaces


Table 7-98 lists the parameters specified for the optical interfaces of the EGR2.
Table 7-98 Parameters specified for the optical interfaces of the EGR2
Parameter

Value

Type of optical
interface

1000BASE-ZX
(80 km)

1000BASEEX (40 km)

1000BASELX (10 km)

1000BASE-SX
(0.5 km)

Type of fiber

Single-mode LC

Single-mode
LC

Single-mode
LC

Multi-mode LC

Launched optical
power range
(dBm)

-2 to +5

-5.0 to 0

-9.5 to -3

-9.5 to -2.5

Operating
wavelength range
(nm)

1500 to 1580

1275 to 1350

1270 to 1355

770 to 860

Minimum
overload (dBm)

-3

-3

-3

Receiver
sensitivity (dBm)

-23

-23

-20

-17

Minimum
extinction ratio
(dB)

Laser Safety Class


The safety class of the laser on the board is Class 1. The maximum launched optical power of
the optical interfaces is less than 10 dBm (10 mW).

Ethernet Performance Specifications


Figure 7-50 shows the connection for testing the throughput specifications, packet loss ratio in
the case of overloading, latency specifications, and back-to-back specifications of the EGR2.

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Figure 7-50 Connection for testing the throughput specifications, packet loss ratio in the case
of overloading, latency specifications, and back-to-back specifications
Tested
equipment 1

Tested
equipment 2

Port 1

Port 2
Data network
performance
analyzer

Table 7-99 lists the throughput specifications of the EGR2. Table 7-100 lists the packet loss
ratio in the case of overloading of the EGR2. Table 7-101 lists the latency specifications of the
EGR2. Table 7-102 lists the back-to-back specifications of the EGR2.
NOTE

The specifications vary according to the configuration and networking of the test environment and
the VC services bound on the VCG side. The specifications that are obtained in the actual environment
are used.

The specifications in the following tables are obtained in the following scenario: EVPL bidirectional
unicast services are configured and eight VC-4s are bound on the GE port.

The specifications of a board of a specific version are not provided because the board version has
negligible effect on the specifications.

The specifications in the following tables are obtained by using the Smart Application.

Table 7-99 Throughput specifications of the EGR2

Issue 02 (2009-07-30)

Frame Size
(Byte)

Passed Rate
(%)

(01,08,01) to
(01,08,02) (pks/
sec)

(01,08,02) to
(01,08,01) (pks/
sec)

Total (pks/
sec)

64

80.77

1201923

1201923

2403846

128

94.87

801282

801282

1602564

256

100.00

452899

452899

905798

512

100.00

234962

234962

469924

1024

100.00

119732

119732

239464

1280

100.00

196154

96154

192308

1518

100.00

81274

81274

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NOTE

Test duration (sec): 3

Minimum frame size (byte): 64

Maximum frame size (byte): 1518

Step frame size (byte): custom

Number of pairs: 1

Initial rate (%): 90.00

Maximum rate (%): 100.00

Resolution rate (%): 1.00

Mode: bidirectional

Table 7-100 Packet loss ratio in the case of overloading of the EGR2
Frame Size
(Byte)

Rate Tested
(%)

(01,08,01) to
(01,08,02) (%)

(01,08,02) to
(01,08,01) (%)

Average (%)

64

100.00

16.719

16.720

16.719

128

100.00

4.315

4.328

4.321

256

100.00

0.000

0.000

0.000

512

100.00

0.000

0.000

0.000

1024

100.00

0.000

0.000

0.000

1280

100.00

0.000

0.000

0.000

1518

100.00

0.000

0.000

0.000

NOTE

7-160

Test duration (sec): 4

Minimum frame size (byte): 64

Maximum frame size (byte): 1518

Step frame size (byte): custom

Number of pairs: 1

Initial rate (%): 100.00

Maximum rate (%): 10.00

Resolution rate (%): none

Mode: bidirectional

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Table 7-101 Latency specifications of the EGR2


Frame
Size
(Byte)

Rate
Tested
(%)

(01,08,01) to
(01,08,02) (us)CT (us)

Average
(CT) (us)

(01,08,01) to
(01,08,02)
(us)-S&F (us)

Average
(S&F) (us)

64

80.77

117.8

117.8

117.3

117.3

128

94.87

121.2

121.2

120.2

120.2

256

100.00

126.6

126.6

124.6

124.6

512

100.00

137.7

137.7

133.7

133.7

1024

100.00

159.9

159.9

151.8

151.8

1280

100.00

170.2

170.2

160.0

160.0

1518

100.00

182.9

182.9

170.8

170.8

NOTE

The latency modes are classified into two modes, namely, cut through mode and store forward mode.
In cut through mode, the analyzer calculates the difference between the time when the first bit of the
transmitted frame reaches the output port and the time when the first bit of the transmitted frame reaches
the input port. In store forward mode, the analyzer calculates the difference between the time when the
first bit of the transmitted frame reaches the output port and the time when the last bit of the transmitted
frame reaches the input port. In the preceding table, the CT values are obtained in cut through mode
and the S&F values are obtained in store forward mode.

CT: cut through or FIFO; S&F: store forward or LIFO

Measure on one receiving card only. Mode: SmartMetrics Comp. Mode

Test duration (sec): 4

Minimum frame size (byte): 64

Maximum frame size (byte): 1518

Step frame size (byte): custom

Number of pairs: 1

Initial rate (%): 80.77

Maximum rate (%): 10.00

Resolution rate (%): none

Mode: bidirectional

Table 7-102 Back-to-back specifications of the EGR2

Issue 02 (2009-07-30)

Frame Size
(Byte)

Rate Tested
(%)

(01,08,01) to
(01,08,02) Burst
Size (Number of
Frames)

(01,08,02) to
(01,08,01)
(Number of
Frames)

Total
(Number of
Frames)

64

100.00

298

300

598

128

100.00

650

650

1300

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Frame Size
(Byte)

Rate Tested
(%)

(01,08,01) to
(01,08,02) Burst
Size (Number of
Frames)

(01,08,02) to
(01,08,01)
(Number of
Frames)

Total
(Number of
Frames)

256

100.00

905798

905798

1811596

512

100.00

469924

469924

939848

1024

100.00

239464

239464

478928

1280

100.00

192308

192308

384616

1518

100.00

162548

162548

325096

NOTE

Test duration (sec): 2

Minimum frame size (byte): 64

Maximum frame size (byte): 1518

Step frame size (byte): custom

Number of pairs: 1

Initial rate (%): 100.00

Maximum rate (%): 10.00

Resolution rate (%): none

Mode: bidirectional

Mechanical Specifications
The mechanical specifications of the EGR2 are as follows:
l

Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)

Weight (kg): 1.1

Power Consumption
The maximum power consumption of the EGR2 at room temperature (25C) is 40 W.

7.12 EMR0
This topic describes the version, functions, working principle, valid slots, and technical
specification of the EMR0 (12xFE and 1xGE ring processing board).
7.12.1 Version Description
The EMR0 is available in one functional versions, namely, N2.
7.12.2 Functions and Features
The EMR0 supports the Layer 2 switching, port aggregation, and RPR functions.
7.12.3 Working Principle and Signal Flow
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The EMR0 consists of the Ethernet access module, network processor module, RPR protocol
processing module, mapping module, interface converting module, logic and control module,
clock module, and power module.
7.12.4 Front Panel
The front panel of the EMR0 has indicators, interfaces, a bar code, and a laser safety class label.
7.12.5 Valid Slots
Without the interface board, the EMR0 can be installed in slots 28 and 1116 in the subrack.
With the interface board, the EMR0 can be installed in slots 37 and 1216 in the subrack. In
this case, the bandwidth is 2.5 Gbit/s.
7.12.6 Feature Code
The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the EMR0 indicates the type of optical interface.
7.12.7 Parameter Settings
You can set the parameters for the EMR0 by using the T2000.
7.12.8 Technical Specifications
The technical specifications of the EMR0 include the parameters specified for optical interfaces,
laser safety class, Ethernet performance specifications, mechanical specifications, and power
consumption.

7.12.1 Version Description


The EMR0 is available in one functional versions, namely, N2.

7.12.2 Functions and Features


The EMR0 supports the Layer 2 switching, port aggregation, and RPR functions.
Table 7-103 provides the functions and features of the EMR0.
Table 7-103 Functions and features of the EMR0
Function and
Feature

EMR0

Basic functions

Accesses and processes 12xFE services and 1xGE services.


Supports the RPR feature.

Functions when
being used with the
interface board

Specifications of the
optical interface

Issue 02 (2009-07-30)

Supports four FE ports and one GE ports.

Accesses 12xFE signals through the electrical interface when the


EMR0 is used with the ETF8.

Accesses 8xFE signals through the optical interface when the


EMR0 is used with the EFF8.

Supports 10BASE-T/100BASE-TX signals when the EMR0 is


used with the ETF8. The maximum transmission distance is 100
m.

Supports 100BASE-FX signals in compliance with IEEE 802.3u


when the EMR0 is used with the EFF8.

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Function and
Feature

EMR0

Format of service
frames

Supports Ethernet II, IEEE 802.3, and IEEE 802.1q TAG formats.

Supports the frame with a length ranging from 64 bytes to 9600


bytes.

Supports the Jumbo frame with a length less than 9600 bytes.

Maximum uplink
bandwidth

2.5 Gbit/s
The EMR0 can adapt to the bandwidth of the slot.

Mapping
granularities

Supports VC-3, VC3-2v, VC-4, and VC4-Xv (X8) granularities.

Encapsulation format

Supports the GFP-F and LAPS protocols.

EVPL services

Supports EVPL services. The frame format can be Ethernet II,


IEEE 802.3, IEEE 802.1q TAG, or MPLS Martini.

Supports the MPLS encapsulation and forwarding based on PORT


or PORT+VLAN.

Supports five types of LSPs, including ingress LSP, egress LSP,


transit LSP, RPR ingress LSP, and RPR transit LSP.

Supports a maximum of 512 LSPs.

Supports EVPLAN services that use the stack VLAN


encapsulation.

Supports the configuration of the static MAC routes. A maximum


of 4K static MAC routes can be configured.

Supports data isolation based on VB+VLAN.

EVPLAN services

7-164

MTU

Supports the setting of the packet length, which ranges from 1518
bytes to 9600 bytes. After the setting becomes valid, the length of the
packets that enter or exit the IP ports is limited.

MPLS

Supports MartinioE.

Stack VLAN

Supports the stack VLAN.

VLAN

Supports 4096 VLAN tags, and the addition, deletion, and


exchanging of VLAN tags in compliance with IEEE 802.1q.

VLAN convergence

Supports the VLAN convergence.


The maximum number of VLANs is 4K.

VLAN tag
exchanging

Supports the replacement of VLAN tags in Ethernet signal frames.

Port aggregation

Supports the aggregation of a maximum of eight FE ports.

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Function and
Feature

EMR0

RPR

Supports the RPR feature that complies with IEEE 802.17.

Supports a maximum of 255 nodes on the ring network, and


supports stripping at the destination node and weighted fairness
algorithm.

Supports five priority levels, including A0, A1, B_EIR, B_CIR,


and C, and supports automatic discovery of topologies, which can
display the network status in real time.

Supports three protection modes, including Steering, Wrapping,


and Wrapping+Steering. Hence, the signal failure time is less than
50 ms.

Supports the self-learning of routes on the ring, that is, supports


the learning of mapping relationship between MAC addresses and
node numbers.

The N2EMR0 supports the manual configuration of routes for the


services on the RPR ring network.

RSTP

Supports the broadcast packet suppression and RSTP, which comply


with IEEE 802.1w.

Multicast function

Supports the multicast function.

CAR

Supports the CAR.


The granularity is 64 kbit/s.

Issue 02 (2009-07-30)

Flow classification

The N2EMR0 supports the flow classification based on PORT, PORT


+VLAN ID, or PORT+VLAN ID+VLAN PRI.

LCAS function

Dynamically increases or decreases the bandwidth and protects the


bandwidth in compliance with ITU-T G.7042.

Flow control function

Supports the port-based flow control function that complies with


IEEE 802.3x.

Echo test frames

Supports the echo function specified in the RPR OAM function,


which is used to test the connectivity of the link.

Loopback function

Supports inloops on Ethernet ports (at the PHY layer or MAC layer).

Ethernet
performance
monitoring

Supports Ethernet performance monitoring at the port level.

Alarms and
performance events

Reports various alarms and performance events, which facilitates the


management and maintenance of the equipment.

Weighted fairness
algorithm

Supports the weighted fairness algorithm.

Automatic discovery
of topologies

Supports the automatic discovery of topologies.

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Function and
Feature

EMR0

Maximum number of 255


supported nodes
Service priority
levels

Supports A0, A1, B_CIR, B_EIR, and C.

7.12.3 Working Principle and Signal Flow


The EMR0 consists of the Ethernet access module, network processor module, RPR protocol
processing module, mapping module, interface converting module, logic and control module,
clock module, and power module.
Figure 7-51 shows the functional block diagram of the EMR0 by describing how to process
1xGE/FE signals.
Figure 7-51 Functional block diagram of the EMR0
Backplane

RPR protocol
processing module

Cross-connect
unit

Communication

Logic and
control module

SCC unit

Reference clock and frame header

50 MHz
77 MHz
125 MHz Clock module
100 MHz

Crossconnect unit

Mapping module

Laser shutdown
LOS

Interface
converting
module

VCP

RPR
MAC
(west)

DENCP

Network processor module

RPR
MAC
(east)

ENCP

GE/FE Ethernet
access
module

Control
Network signal Switch
processor
fabric
Data

+3.3 V
Power
module

Power
module

Fuse

Cross-connect
unit

-48 V/-60 V
-48 V/-60 V

RPR: resilient package ring

Ethernet Access Module


In the receive direction, the optical signals from Ethernet equipment such as switches or routers
are converted into electrical signals. If the signals are accessed through electrical interfaces, O/
E conversion is not required. At the PHY layer, the electrical signals are decoded and the
ETH_LOS alarm is detected. The electrical signals are converted from serial signals into parallel
signals and then sent to the network processor module.
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In the transmit direction, the parallel signals are converted into serial signals. At the PHY layer,
signals are encoded and converted from electrical signals to optical signals.

Network Processor Module


The network processor module consists of the network processor and switch fabric. The network
processor first performs MAC functions, which include code conversion, framing of Ethernet
packets, CRC check, and Ethernet performance statistics.
After the striped Ethernet frames enter the core of network processor, the flow is classified
according to the service type and configuration requirement. The frames are encapsulated or
decapsulated. The following formats are supported:
l

MPLS

L2 MPLS VPN

Ethernet/VLAN

In the receive direction, services are mapped and forwarded after the Tunnel and VC tags are
added according to the service configuration. In the transmit direction, the Tunnel or VC tag is
extracted based on the level (P or PE) of the equipment. Services are then routed or forwarded.
The network processor module supports the following functions:
l

Flow sense and flow classification

Unicast, multicast, and broadcast of the flow

Setting of data priorities

WFQ

Three CoSs

RPR Protocol Processing Module


The RPR implements the weighted fairness algorithm and statistical multiplexing for the ring
bandwidth. In addition, the RPR provides protection switching schemes. By using the RPR
protocol and RPR weighted fairness algorithm, the RPR protocol processing module controls
the bandwidth of each node accessed by the ring network. In addition, the RPR ring has the
features of spatial reuse and statistical multiplexing. Hence, the bandwidth utilization is
improved.
Topology auto-discovery ensures the plug-and-play feature of the RPR. The protocol for
topology auto-discovery provides correct and reliable ways of discovering topologies of all
nodes and changes occurring on these topologies.
RPR unicast frames are striped at the destination node and thus the bandwidth on the ring is
reused spatially.
The RPR ring supports a maximum of 255 nodes.

Mapping Module
The mapping module performs encapsulation and mapping functions.
In the upstream direction, virtual concatenation services support the LCAS function. The
encapsulation formats are LAPS and GFP-F.
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In the downstream direction, virtual concatenation services are received. The delay of virtual
concatenation is compensated. After aligning, packets are decapsulated according to the
encapsulation format. The decapsulated data is finally transmitted to the RPR protocol
processing module in packets.

Interface Converting Module


The interface converting module converts the 622 Mbit/s LVDS bus of the SDH system into the
parallel bus. The high-rate backplane interface is connected to the low-rate interface chip of the
transmit system through the interface converting module.

Logic and Control Module


The logic and control module consists of the CPU, register, oscillator, Ethernet port, and HDLC
controller. This module is connected to external circuits through the bus. The logic and control
module performs the following functions:
l

Manages and configures other modules of the board.

Implements inter-board communication through the internal Ethernet interface.

The control module also contains basic logic units. This module performs the following
functions:
l

Writes and reads the register.

Provides interfaces for the CPU.

Checks and selects the clock.

Performs phase discrimination and frequency division on the clock.

Checks the in-service state of the cross-connect, SCC, and line boards.

Controls the shutting down of the optical module.

Implements communication.

Controls indicators.

Clock Module
The clock module traces the system reference clock and generates the required working clock
for each chip. The frequency of the clock can be 50 MHz, 77 MHz, 125 MHz, or 100 MHz.

Power Module
It converts the 48 V/60 V power supply into the DC voltages that the modules of the board
require.

7.12.4 Front Panel


The front panel of the EMR0 has indicators, interfaces, a bar code, and a laser safety class label.

Diagram of the Front Panel


Figure 7-52 shows the appearance of the front panel of the EMR0.
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Figure 7-52 Front panel of the EMR0

EMR0
STAT
ACT
PROG
SRV
LINK
ACT

CLASS 1
LASER
PRODUCT

OUT1
IN1
FE1

FE2

FE3

FE4

EMR0

Indicators
The front panel of the board has the following indicators:
l

Board hardware status indicator (STAT) two colors (red and green)

Service activation status indicator (ACT) one color (green)

Board software status indicator (PROG) two colors (red and green)

Service alarm indicator (SRV) three colors (red, green, and yellow)

Connection status indicator (LINK) one color (green)

Data receiving and transmission indicator (ACT) one color (orange)

For the meanings of the status of the indicators, see A Indicators.

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Interfaces
The front panel of the EMR0 has five interfaces. Table 7-104 describes the types and usage of
the interfaces of EMR0.
Table 7-104 Interfaces of the EMR0
Interface

Type of
Interface

Usage

OUT1/IN1

LC (swappable)

Transmits and receives 1000BASE-SX/LX/ZX


signals.

FE1

RJ-45

Transmits and receives 10BASE-T/100BASE-TX


signals.

FE2

RJ-45

Transmits and receives 10BASE-T/100BASE-TX


signals.

FE3

RJ-45

Transmits and receives 10BASE-T/100BASE-TX


signals.

FE4

RJ-45

Transmits and receives 10BASE-T/100BASE-TX


signals.

7.12.5 Valid Slots


Without the interface board, the EMR0 can be installed in slots 28 and 1116 in the subrack.
With the interface board, the EMR0 can be installed in slots 37 and 1216 in the subrack. In
this case, the bandwidth is 2.5 Gbit/s.
The EMR0 can be used with the ETF8 and EFF8.
Table 7-105 lists the slots valid for the EMR0 and the corresponding slots for the ETF8 and
EFF8.
Table 7-105 Slots valid for the EMR0 and the corresponding slots for the ETF8 and EFF8

7-170

Slot Valid for the EMR0

Corresponding Slot for the ETF8 and


EFF8

Slot 2

Without the interface board

Slot 3

Slot 21

Slot 4

Slot 23

Slot 5

Slot 25

Slot 6

Slot 27

Slot 7

Slot 29

lot 8

Without the interface board


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Slot Valid for the EMR0

Corresponding Slot for the ETF8 and


EFF8

Slot 11

Without the interface board

Slot 12

Slot 32

Slot 13

Slot 34

Slot 14

Slot 36

Slot 15

Slot 38

Slot 16

Slot 40

7.12.6 Feature Code


The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the EMR0 indicates the type of optical interface.
Table 7-106 provides the relationship between the feature code of the EMR0 and the type of
optical interface.
Table 7-106 Relationship between the feature code of the EMR0 and the type of optical interface
Board

Feature Code

Type of Optical Interface

SSN2EMR010

10

1000BASE-SX (0.5 km)

SSN2EMR011

11

1000BASE-LX (10 km)

SSN2EMR012

12

1000BASE-VX (40 km)

SSN2EMR013

13

1000BASE-ZX (80 km)

7.12.7 Parameter Settings


You can set the parameters for the EMR0 by using the T2000.
You can set the following parameters for the EMR0 by using the T2000:
l

Working mode

LCAS

Maximum frame length

Mapping protocol

For the description of each parameter, see F Parameter Settings.

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7.12.8 Technical Specifications


The technical specifications of the EMR0 include the parameters specified for optical interfaces,
laser safety class, Ethernet performance specifications, mechanical specifications, and power
consumption.

Parameters Specified for Optical Interfaces


Table 7-107 lists the parameters specified for the optical interfaces of the EMR0.
Table 7-107 Parameters specified for the optical interfaces of the EMR0
Parameter

Value

Type of optical
interface

1000BASE-ZX
(80 km)

1000BASE-EX
(40 km)

1000BASELX (10 km)

1000BASE-SX
(0.55 km)

Type of fiber

Single-mode
LC

Single-mode LC

Single-mode
LC

Multi-mode LC

Launched optical
power range
(dBm)

-2 to +5

-5.0 to 0

-9.5 to -3

-9.5 to -2.5

Operating
wavelength
range (nm)

1500 to 1580

1275 to 1350

1270 to 1355

770 to 860

Minimum
overload (dBm)

-3

-3

-3

Receiver
sensitivity (dBm)

-23

-23

-20

-17

Minimum
extinction ratio
(dB)

Laser Safety Class


The safety class of the laser on the board is Class 1. The maximum launched optical power of
the optical interfaces is less than 10 dBm (10 mW).

Ethernet Performance Specifications


Figure 7-53 shows the connection for testing the throughput specifications, packet loss ratio in
the case of overloading, latency specifications, and back-to-back specifications of the EMR0.

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Figure 7-53 Connection for testing the throughput specifications, packet loss ratio in the case
of overloading, latency specifications, and back-to-back specifications
Tested
equipment 1

Tested
equipment 2

Port 1

Port 2
Data network
performance
analyzer

Table 7-108 and Table 7-109 list the throughput specifications of the EMR0. Table 7-110 and
Table 7-111 list the packet loss ratio in the case of overloading of the EMR0. Table 7-112 and
Table 7-113 list the latency specifications of the EMR0. Table 7-114 and Table 7-115 list the
back-to-back specifications of the EMR0.
NOTE

The specifications vary according to the configuration and networking of the test environment and
the VC services bound on the VCG side. The specifications that are obtained in the actual environment
are used.

The specifications in the following tables are obtained in the following scenario: EVPL bidirectional
unicast services are configured and eight VC-4s are bound on the FE port, or EVPL bidirectional
unicast services are configured and eight VC-4s are bound on the GE port.

The specifications of a board of a specific version are not provided because the board version has
negligible effect on the specifications.

The specifications in the following tables are obtained by using the Smart Application.

Table 7-108 Throughput specifications of the EMR0 (eight VC-4s are bound on the FE port)

Issue 02 (2009-07-30)

Frame Size
(Byte)

Passed Rate
(%)

(01,06,05) to
(01,06,06) (pks/
sec)

(01,06,06) to
(01,06,05) (pks/
sec)

Total (pks/
sec)

64

100.00

148810

148810

297620

128

100.00

84459

84459

168918

256

100.00

45290

45290

90580

512

100.00

23496

23496

46992

1024

100.00

11973

11973

23946

1280

100.00

9615

9615

19230

1518

100.00

8127

8127

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NOTE

Test duration (sec): 5

Minimum frame size (byte): 64

Maximum frame size (byte): 1518

Step frame size (byte): custom

Number of pairs: 1

Initial rate (%): 100.00

Maximum rate (%): 100.00

Resolution rate (%): 1.00

Mode: bidirectional

Table 7-109 Throughput specifications of the EMR0 (eight VC-4s are bound on the GE port)
Frame Size
(Byte)

Passed Rate
(%)

(01,01,01) to
(01,04,01) (pks/
sec)

(01,04,01) to
(01,01,01) (pks/
sec)

Total (pks/
sec)

64

72.41

1077586

1077586

2155172

128

94.87

801282

801282

1602564

256

100.00

452899

452899

905798

512

100.00

234962

234962

469924

1024

100.00

119732

119732

239464

1280

100.00

96154

96154

192308

1518

100.00

81274

81274

162548

NOTE

7-174

Test duration (sec): 20

Minimum frame size (byte): 64

Maximum frame size (byte): 1518

Step frame size (byte): custom

Number of pairs: 1

Initial rate (%): 100.00

Maximum rate (%): 100.00

Resolution rate (%): 1.00

Mode: bidirectional

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Table 7-110 Packet loss ratio in the case of overloading of the EMR0 (eight VC-4s are bound
on the FE port)
Frame Size
(Byte)

Rate Tested
(%)

(01,06,05) to
(01,06,06) (%)

(01,06,06) to
(01,06,05) (%)

Average (%)

64

100.00

0.000

0.000

0.000

128

100.00

0.000

0.000

0.000

256

100.00

0.000

0.000

0.000

512

100.00

0.000

0.000

0.000

1024

100.00

0.000

0.000

0.000

1280

100.00

0.000

0.000

0.000

1518

100.00

0.000

0.000

0.000

NOTE

Test duration (sec): 5

Minimum frame size (byte): 64

Maximum frame size (byte): 1518

Step frame size (byte): custom

Number of pairs: 1

Initial rate (%): 100.00

Step rate: 10.00

Resolution rate (%): none

Mode: bidirectional

Table 7-111 Packet loss ratio in the case of overloading of the EMR0 (eight VC-4s are bound
on the GE port)

Issue 02 (2009-07-30)

Frame Size
(Byte)

Rate Tested
(%)

(01,01,01) to
(01,04,01) (%)

(01,04,01) to
(01,01,01) (%)

Average (%)

64

100.00

29.833

29.827

29.830

128

100.00

4.306

4.309

4.307

256

100.00

0.000

0.000

0.000

512

100.00

0.000

0.000

0.000

1024

100.00

0.000

0.000

0.000

1280

100.00

0.000

0.000

0.000

1518

100.00

0.000

0.000

0.000

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NOTE

Test duration (sec): 5

Minimum frame size (byte): 64

Maximum frame size (byte): 1518

Step frame size (byte): custom

Number of pairs: 1

Initial rate (%): 100.00

Step rate: 10.00

Resolution rate (%): none

Mode: bidirectional

Table 7-112 Latency specifications of the EMR0 (eight VC-4s are bound on the FE port)

7-176

Frame
Size
(Byte)

Rate
Tested
(%)

(01,06,05) to
(01,06,06) (us)CT (us)

Average
(CT) (us)

(01,06,05) to
(01,06,06)
(us)-S&F (us)

Average
(S&F) (us)

64

100.00

126.1

126.1

121.0

121.0

128

100.00

131.0

131.0

120.8

120.8

256

100.00

149.2

149.2

128.8

128.8

512

100.00

176.9

176.9

136.0

136.0

1024

100.00

237.0

237.0

155.1

155.1

1280

100.00

266.7

266.7

164.3

164.3

1518

100.00

289.3

289.3

167.9

167.9

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NOTE

The latency modes are classified into two modes, namely, cut through mode and store forward mode.
In cut through mode, the analyzer calculates the difference between the time when the first bit of the
transmitted frame reaches the output port and the time when the first bit of the transmitted frame reaches
the input port. In store forward mode, the analyzer calculates the difference between the time when the
first bit of the transmitted frame reaches the output port and the time when the last bit of the transmitted
frame reaches the input port. In the preceding table, the CT values are obtained in cut through mode
and the S&F values are obtained in store forward mode.

Test duration (sec): 5

Minimum frame size (byte): 64

Maximum frame size (byte): 1518

Step frame size (byte): custom

Number of pairs: 1

Initial rate (%): 100.00

Step rate: 10.00

Resolution rate (%): none

Mode: bidirectional

Table 7-113 Latency specifications of the EMR0 (eight VC-4s are bound on the GE port)

Issue 02 (2009-07-30)

Frame
Size
(Byte)

Rate
Tested
(%)

(01,01,01) to
(01,04,01) (us)CT (us)

Average
(CT) (us)

(01,01,01) to
(01,04,01)
(us)-S&F (us)

Average
(S&F) (us)

64

72.41

130.1

130.1

129.6

129.6

128

94.87

143.1

143.1

142.1

142.1

256

100.00

123.4

123.4

121.4

121.4

512

100.00

130.7

130.7

126.7

126.7

1024

100.00

154.4

154.4

146.3

146.3

1280

100.00

164.6

164.6

154.4

154.4

1518

100.00

174.4

174.4

162.3

162.3

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NOTE

The latency modes are classified into two modes, namely, cut through mode and store forward mode.
In cut through mode, the analyzer calculates the difference between the time when the first bit of the
transmitted frame reaches the output port and the time when the first bit of the transmitted frame reaches
the input port. In store forward mode, the analyzer calculates the difference between the time when the
first bit of the transmitted frame reaches the output port and the time when the last bit of the transmitted
frame reaches the input port. In the preceding table, the CT values are obtained in cut through mode
and the S&F values are obtained in store forward mode.

Test duration (sec): 20

Minimum frame size (byte): 64

Maximum frame size (byte): 1518

Step frame size (byte): custom

Number of pairs: 1

Initial rate (%): 72.41

Step rate: 10.00

Resolution rate (%): none

Mode: bidirectional

Table 7-114 Back-to-back specifications of the EMR0 (eight VC-4s are bound on the FE port)

7-178

Frame Size
(Byte)

Rate Tested
(%)

(01,06,05) to
(01,06,06) Burst
Size (Number of
Frames)

(01,06,06) to
(01,06,05)
(Number of
Frames)

Total
(Number of
Frames)

64

100.00

297620

297620

595240

128

100.00

168918

168918

337836

256

100.00

90580

90580

181160

512

100.00

46992

46992

93984

1024

100.00

23946

23946

47892

1280

100.00

19230

19230

38460

1518

100.00

16254

16254

32508

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NOTE

Test duration (sec): 2

Minimum frame size (byte): 64

Maximum frame size (byte): 1518

Step frame size (byte): custom

Number of pairs: 1

Initial rate (%): 100.00

Step rate: 10.00

Resolution rate (%): none

Mode: bidirectional

Table 7-115 Back-to-back specifications of the EMR0 (eight VC-4s are bound on the GE port)
Frame Size
(Byte)

Rate Tested
(%)

(01,01,01) to
(01,04,01) Burst
Size (Number of
Frames)

(01,04,01) to
(01,01,01)
(Number of
Frames)

Total
(Number of
Frames)

64

100.00

3410

3410

6820

128

100.00

29054

29054

58108

256

100.00

905798

905798

1811596

512

100.00

469924

469924

939848

1024

100.00

239464

239464

478928

1280

100.00

192308

192308

384616

1518

100.00

162548

162548

325096

NOTE

Test duration (sec): 2

Minimum frame size (byte): 64

Maximum frame size (byte): 1518

Step frame size (byte): custom

Number of pairs: 1

Initial rate (%): 100.00

Step rate: 10.00

Resolution rate (%): none

Mode: bidirectional

Mechanical Specifications
The mechanical specifications of the EMR0 are as follows:
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l

Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)

Weight (kg): 1.2

Power Consumption
The maximum power consumption of the EMR0 at room temperature (25C) is 50 W.

7.13 EAS2
This topic describes the version, functions, working principle, valid slots, and technical
specification of the EAS2 (2-port 10xGE Layer 2 switching and processing board).
7.13.1 Version Description
The EAS2 is available in one functional version, namely, N1.
7.13.2 Functions and Features
The EAS2 supports the access of 10 GE Ethernet services, LCAS, and test frame functions.
7.13.3 Working Principle and Signal Flow
The EAS2 consists of the interface processing module, mapping module, interface converting
module, logic and control module, clock module, and power module.
7.13.4 Front Panel
The front panel of the EAS2 has indicators, interfaces, a bar code, and a laser safety class label.
7.13.5 Valid Slots
The valid slots for the EAS2 board vary with the cross-connect capacity of the subrack.
7.13.6 Parameter Settings
You can set the parameters for the EAS2 by using the T2000.
7.13.7 Technical Specifications
The technical specifications of the EAS2 include the parameters specified for optical interfaces,
dimensions, weight, and power consumption.

7.13.1 Version Description


The EAS2 is available in one functional version, namely, N1.

7.13.2 Functions and Features


The EAS2 supports the access of 10 GE Ethernet services, LCAS, and test frame functions.
Table 7-116 provides the functions and features of the EAS2.
Table 7-116 Functions and features of the EAS2 board
Function and
Feature

EAS2

Basic functions

Accesses 2x10 GE Ethernet services.

Specifications of the The optical interfaces are 10GBASE-LR and 10GBASE-LW Ethernet
optical interface
optical interfaces, which comply with IEEE 802.3ae.
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Function and
Feature

EAS2

Format of service
frames

Supports Ethernet II, IEEE 802.3, and IEEE 802.1qTAG formats.

Supports the frame with a length ranging from 64 bytes to 9600


bytes.

Supports the Jumbo frame with a length less than 9600 bytes.

Maximum uplink
bandwidth

10 Gbit/s
The EAS2 can adapt to the bandwidth of the slot.

Number of
supported
VCTRUNKs

24

Encapsulation
format

Supports the GFP-F protocol, which meets ITU-T G.7041.

Mapping
granularities

Supports the following adjacent concatenation granularities: VC4-Xv


(X8), VC3-Xv (X24), and VC4-4c.

EPL services

Supports the PORT-based transparent transmission.

EVPL services

Supports EVPL services based on PORT+VLAN.

Supports QinQ-based EVPL services.

Supports the port-based service forwarding.

Supports a maximum of 2048 links.

Supports the creation, deletion, and query of the VB. The maximum
number of supported VBs is 1.

Supports the setting and query of the aging time of the MAC address

Supports the configuration of static MAC routes.

Supports EVPLAN services that use the stack VLAN


encapsulation.

Supports data isolation based on VB+VLAN.

EPLAN services

EVPLAN services

MTU

Supports the setting of the packet length, which ranges from 1518
bytes to 9600 bytes. After the setting becomes valid, the length of the
packets that enter or exit the IP ports is limited.

MPLS

Does not support the MPLS.

VLAN

Supports VLAN and QinQ, which comply with IEEE 802.1q/p.

LPT function

Supports the P2P LPT and P2MP LPT.

CAR

Supports the CAR.


The granularity is 64kbit/s.

Flow control
function

Issue 02 (2009-07-30)

Supports the port-based flow control function that complies with IEEE
802.3x.

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Function and
Feature

EAS2

LCAS function

Dynamically increases or decreases the bandwidth and protects the


bandwidth in compliance with ITU-T G.7042.

Multicast function

Supports the enabling of the IGMP Snooping protocol. Supports a


maximum of 1024 multicast groups.

Supports the query of the enabling status of the IGMP Snooping


protocol.

Supports the setting and query of the IGMP Snooping protocol


parameters.

Supports a maximum of 512 static multicast groups.

RSTP

Supports the broadcast packet suppression and RSTP, which comply


with IEEE 802.1w.

ETH-OAM function

Supports CC for the multicast service, LB test for the unicast service,
and LT test. The ETH-OAM function complies with IEEE 802.1ag.

Link aggregation

Supports manual link aggregation and static link aggregation for


Ethernet links and VCTRUNKs.

Inter-board link
aggregation

Supports inter-board link aggregation.

Test frames

Supports test frames in ETH and GFP bearer modes.

Ethernet
performance
monitoring
(RMON)

Supports the Ethernet performance monitoring at the port level.

Supports the query of the rate of a port.

Alarms and
performance events

Provides various alarm and performance events, which facilitates the


management and maintenance of the equipment.

7.13.3 Working Principle and Signal Flow


The EAS2 consists of the interface processing module, mapping module, interface converting
module, logic and control module, clock module, and power module.
Figure 7-54 shows the functional block diagram of the EAS2 by describing how to process 1x10
GE signals.

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Figure 7-54 Functional block diagram of the EAS2


Backplane

10GE

Interface
processing
module

Laser
shutdown

Service
processing
module

Interface
converting
module

Encapsulation
module
Digital encapsulation module
Mapping module

Virtual
concatenation
processing
module

Cross-connect unit

Cross-connect unit

LOS

Logic and
control module

Communication
Clock reference and frame delimitation

+3.3 V
Clock module

Power
module

Power
module

Fuse

SCC unit
SCC unit
-48 V/-60 V
-48 V/-60 V

In the Transmit Direction


The encapsulation or conversion module demaps and decapsulates the signals received from the
cross-connect unit. Then, the interface converting module performs the interface converting
operations and transmits the signals to the service processing module. The service processing
module implements the functions of the Layer 2 switching and private line service. After the
interface processing module converts parallel signals to serial signals and encodes the serial
signals, the Ethernet interface module transmits the serial signals.

In the Receive Direction


The XFP optical module performs O/E conversion on the 10 GE Ethernet signals, and then
transmits the signals to the Ethernet interface module. The Ethernet interface module transmits
the parallel signals to the service processing module to realize the functions of the Layer 2
switching and private line service. The encapsulation module encapsulates and maps the Ethernet
GFP-F frames, and then transmits the signals to the cross-connect unit.

Logic and Control Module


The logic and control module provides the communication, control, and service configuration
functions of the board.

Clock Module
The clock module traces the system reference clock, and generates the required clock signals
when the board is working.

Power Module
It converts the 48 V/60 V power supply into the DC voltages that the modules of the board
require.
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7.13.4 Front Panel


The front panel of the EAS2 has indicators, interfaces, a bar code, and a laser safety class label.

Diagram of the Front Panel


Figure 7-55 shows the appearance of the front panel of the EAS2.
Figure 7-55 Front panel of the EAS2

EAS2
STAT
ACT
PROG
SRV
LINK1
ACT1
LINK2
ACT2
CLASS 1
LASER
PRODUCT

OUT1

IN1
OUT2

IN2

EAS2

Indicators
The front panel of the board has the following indicators:

7-184

Board hardware status indicator (STAT) two colors (red and green)

Service activation status indicator (ACT) one color (green)

Board software status indicator (PROG) two colors (red and green)
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Service alarm indicator (SRV) three colors (red, green, and yellow)

Connection status indicator (LINK) one color (green)

Data receiving and transmission indicator (ACT) one color (orange)

For the meanings of the status of the indicators, see A Indicators.

Interfaces
The front panel of the EAS2 has two 10 GE interfaces. Table 7-117 describes the types and
usage of the interfaces of the EAS2.
Table 7-117 Interfaces of the EAS2
Interface

Type of Interface

Usage

IN1IN2

LC

Receives 10 GE signals.

OUT1OUT2

LC

Transmits 10 GE signals.

7.13.5 Valid Slots


The valid slots for the EAS2 board vary with the cross-connect capacity of the subrack.
l

When the cross-connect capacity is 60 Gbit/s, the EAS2 is not supported.

When the cross-connect capacity is 110 Gbit/s, the EAS2 can be installed in slots 7, 8, 11,
and 12 in the subrack. In this case, the bandwidth is 10 Gbit/s.

7.13.6 Parameter Settings


You can set the parameters for the EAS2 by using the T2000.
You can set the following parameters for the EAS2 by using the T2000:
l

Working mode

LCAS

Maximum frame length

Mapping protocol

For the description of each parameter, see F Parameter Settings.

7.13.7 Technical Specifications


The technical specifications of the EAS2 include the parameters specified for optical interfaces,
dimensions, weight, and power consumption.

Parameters Specified for Optical Interfaces


Table 7-118 lists the parameters specified for the optical interfaces of the EAS2.
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Table 7-118 Parameters specified for the optical interfaces of the EAS2
Parameter

Value

Transmission rate

10.3125 Gbit/s or 9.953 Gbit/s

Processing capability

2x10GE signals

Type of optical interface

10GBASE-LR/LX

Type of fiber

Single-mode LC

Operating wavelength
range (nm)

1290 to 1330

Transmission distance (km)

10

Maximum mean launched


power (dBm)

-1

Minimum mean launched


power (dBm)

-6

Receiver sensitivity (dBm)

-11

Minimum extinction ratio


(dB)

Connector type

LC

Laser Safety Class


The safety class of the laser on the board is Class 1. The maximum launched optical power of
the optical interfaces is less than 10 dBm (10 mW).

Ethernet Performance Specifications


Figure 7-56 shows the connection for testing the throughput specifications, packet loss ratio in
the case of overloading, latency specifications, and back-to-back specifications of the EAS2.
Figure 7-56 Connection for testing the throughput specifications, packet loss ratio in the case
of overloading, latency specifications, and back-to-back specifications
Tested
equipment 1

Tested
equipment 2

Port 1

Port 2
Data network
performance
analyzer

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Table 7-119 lists the throughput specifications of the EAS2. Table 7-120 lists the packet loss
ratio in the case of overloading of the EAS2. Table 7-121 lists the latency specifications of the
EAS2.
NOTE

The specifications vary according to the configuration and networking of the test environment and
the VC services bound on the VCG side. The specifications that are obtained in the actual environment
are used.

The specifications in the following tables are obtained in the following scenario: EPL services are
configured and 64 VC-4s are bound on the 10xGE port.

The specifications of a board of a specific version are not provided because the board version has
negligible effect on the specifications.

The specifications in the following tables are obtained by using the Smart Flow software.

Table 7-119 Throughput specifications of the EAS2


Frame Size
(Byte)

Passed Rate
(%)

Number of Tx
Frames (pks/sec)

Number of Rx
Frames (pks/sec)

Total (%)

64

100.00000

148809440

148613326

99.29688

128

100.00000

84459360

84457314

99.29688

256

99.29687

44974080

44719807

98.59375

512

97.89062

23001600

22892340

97.1875

1024

96.48437

11552000

11552000

96.48438

1280

96.48437

9277280

9277280

96.48438

1518

96.48437

7841440

7831693

95.78125

Table 7-120 Packet loss ratio in the case of overloading of the EAS2

Issue 02 (2009-07-30)

Frame Size
(Byte)

Rate Tested
(%)

Number of Tx
Frames (pks/sec)

Number of Rx
Frames (pks/sec)

Total (%)

64

100.00000

148809440

148614523

0.13

128

100.00000

84459360

84457396

0.00

256

100.00000

45289760

44709723

1.28

512

100.00000

23496160

22868728

2.67

1024

100.00000

11973120

11566750

3.39

1280

100.00000

9615360

9274900

3.54

1518

100.00000

8127360

7832064

3.63

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Table 7-121 Latency specifications of the EAS2


Frame
Size
(Byte)

Rate
Tested
(%)

Number
of Tx
Frames
(pks/sec)

Number of
Rx Frames
(pks/sec)

Minimum
Latency
(ms)

Average
Latency
(ms)

Maximu
m
Latency
(ms)

64

100.0000
0

14880950

14880950

59.7

90.798

98.2

128

100.0000
0

8445940

8445940

55.9

92.201

99.5

256

100.0000
0

4528980

4528980

61

96.178

103.7

512

100.0000
0

2349620

2349620

72.7

102.403

109.9

1024

100.0000
0

1197310

1197310

81.8

116.101

123.7

1280

100.0000
0

961530

961530

88.2

122.479

130.2

1518

100.0000
0

812740

812740

99.1

128.928

136.3

Mechanical Specifications
The mechanical specifications of the EAS2 board are as follows:
l

Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)

Weight (kg): 1.2

Power Consumption
The maximum power consumption of the EAS2 at room temperature (25C) is 70 W.

7.14 ADL4
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the ADL4 (1xSTM-4 ATM service processing board).
7.14.1 Version Description
The ADL4 is available in one functional version, namely, N1.
7.14.2 Functions and Features
The ADL4 supports the ATM switching and ATM protection.
7.14.3 Working Principle and Signal Flow
The ADL4 consists of the O/E converting module, physical layer module, ATM module, E3
module, mapping module, logic and control module, clock module, and power module.
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7.14.4 Front Panel


The front panel of the ADL4 has indicators, interfaces, a bar code, and a laser safety class label.
7.14.5 Valid Slots
The ADL4 can be installed in slots 28 and 1116 in the subrack. In this case, the bandwidth is
1.25 Gbit/s.
7.14.6 Feature Code
The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the ADL4 indicates the type of optical interface.
7.14.7 Parameter Settings
You can set the parameters for the ADL4 by using the T2000.
7.14.8 Technical Specifications
The technical specifications of the ADL4 include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.

7.14.1 Version Description


The ADL4 is available in one functional version, namely, N1.

7.14.2 Functions and Features


The ADL4 supports the ATM switching and ATM protection.
Table 7-122 provides the functions and features of the ADL4.
Table 7-122 Functions and features of the ADL4

Issue 02 (2009-07-30)

Function and
Feature

ADL4

Basic functions

Accesses and processes 1xSTM-4 ATM services.

Type of optical
interface

Supports the following types of optical interfaces: S-4.1, L-4.1,


L-4.2 and Ve-4.2.

Connector type

LC

Type of optical module

SFP

E3 ATM interface

Supports 12xE3 signals, which are accessed through the PD3, PL3,
or N1PL3A.

IMA function

Does not support the IMA function.

Maximum uplink
bandwidth

Supports a bandwidth of 8xVC-4s, or a bandwidth of 12xVC-3s


and 4xVC-4s.

ATM switching
capability

1.2 Gbit/s

Mapping granularities

Supports VC-3, VC-4, and VC4-Xv (X = 14) granularities.

Service types

Supports the CBR, rt-VBR, nrt-VBR, and UBR.

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Function and
Feature

ADL4

Number of supported
ATM connections

2048

Statistical multiplexing

Supports the statistical multiplexing.

Flow types and QoS

Complies with IETF RFC2514 and ATM forum TM4.0.

ATM multicast
connection

Supports the spatial multicast and logical multicast.

ATM protection (ITUT I.630)

Supports the unidirectional/bidirectional 1+1, unidirectional/


bidirectional 1:1, VP-Ring, and VC-Ring protection schemes.

OAM functions (ITU-T


I.610)

Supports the AIS, RDI, LB , and CC.

Maintenance features

Supports inloops at the ATM layer and on optical interfaces.


Supports outloops at the ATM layer.
These features can be used to locate faults quickly.

Alarms and
performance events

Reports various alarms and performance events, which can be used


to locate faults and maintain the equipment.

7.14.3 Working Principle and Signal Flow


The ADL4 consists of the O/E converting module, physical layer module, ATM module, E3
module, mapping module, logic and control module, clock module, and power module.
Figure 7-57 shows the functional block diagram of the ADL4 by describing how to process
1xSTM-4 signals.

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Figure 7-57 Functional block diagram of the ADL4


Backplane
622
Mbit/s

E/O

622
Mbit/s

622
Mbit/s

High-speed
bus

Physical
layer
622 module
Mbit/s

O/E

Cross-connect unit

Mapping
module

ATM
module
E3
module

High-speed
bus

Cross-connect unit

O/E converting
module

Reference clock and frame header

LOS
Laser shutdown

Logic and
control module

Communication

Cross-connect unit
SCC unit

50 MHz
77 MHz
100 MHz

Clock
module

+3.3 V

Power
module

Fuse

-48 V/-60 V
-48 V/-60 V

Power
module

O/E Converting Module


In the receive direction, optical signals are converted into electrical signals. In the transmit
direction, electrical signals are converted into optical signals.

Physical Layer Module


The physical layer module mainly performs the following functions:
l

Maps ATM cells into SDH frames.

Demaps SDH frames to ATM cells.

Implements the following functions at the ATM service physical layer: cell delimitation,
and test and generation of header error control (HEC) sequence.

ATM Module
The ATM module mainly performs the following ATM layer functions that are specified in
ATM protocols:
l

Flow control

Extraction and generation of cell headers

ATM switching

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E3 Module
The E3 module mainly processes ATM services at the E3 rate. This module performs the
following functions:
l

Maps the ATM cells into E3 containers.

Demaps E3 containers to ATM cells.

Implements functions at the ATM physical layer for ATM services at the E3 rate.

Mapping Module
The mapping module performs the following functions:
l

Maps ATM cells into SDH frame payloads.

Demaps SDH frame payloads to ATM cells.

Implements functions at the ATM physical layer.

Implements the VC4-Xv (X4) virtual concatenation.

Logic and Control Module


The logic and control module performs the following functions:
l

Controls writing and reading of each chip.

Communicates with the NE.

Issues configured services.

Reports alarms of each functional module.

Detects R_LOS alarms of optical modules.

Controls the shutting down of the laser.

Clock Module
This module mainly generates the required working clock for each chip. The frequency of the
clock can be 50 MHz, 77 MHz, or 100 MHz.

Power Module
It converts the 48 V/60 V power supply into the DC voltages that the modules of the board
require.

7.14.4 Front Panel


The front panel of the ADL4 has indicators, interfaces, a bar code, and a laser safety class label.

Diagram of the Front Panel


Figure 7-58 shows the appearance of the front panel of the ADL4.
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Figure 7-58 Front panel of the ADL4

ADL4
STAT
ACT
PROG
SRV

CLASS 1
LASER
PRODUCT

OUT1 IN1

ADL4

Indicators
The front panel of the board has the following indicators:
l

Board hardware status indicator (STAT) two colors (red and green)

Service activation status indicator (ACT) one color (green)

Board software status indicator (PROG) two colors (red and green)

Service alarm indicator (SRV) three colors (red, green, and yellow)

For the meanings of the status of the indicators, see A Indicators.

Interfaces
The front panel of the ADL4 has one optical interface. Table 7-123 describes the type and usage
of the optical interface of the ADL4.
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Table 7-123 Optical interface of the ADL4


Interface

Type of
Interface

Usage

OUT1/IN1

LC
(swappable)

Transmits and receives STM-4 optical signals.

7.14.5 Valid Slots


The ADL4 can be installed in slots 28 and 1116 in the subrack. In this case, the bandwidth is
1.25 Gbit/s.

7.14.6 Feature Code


The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the ADL4 indicates the type of optical interface.
Table 7-124 provides the relationship between the feature code of the ADL4 and the type of
optical interface.
Table 7-124 Relationship between the feature code of the ADL4 and the type of optical interface
Board

Feature Code

Type of Optical Interface

SSN1ADL410

10

S-4.1

SSN1ADL411

11

L-4.1

SSN1ADL412

12

L-4.2

SSN1ADL413

13

Ve-4.2

7.14.7 Parameter Settings


You can set the parameters for the ADL4 by using the T2000.
You can set the following parameters for the ADL4 by using the T2000:
l

Port type

Flow type

Service type

Peak cell rate (PCR)

Sustainable cell rate (SCR)

Maximum cell burst size

Cell delay variation tolerance (CDVT)

For the description of each parameter, see F Parameter Settings.


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7.14.8 Technical Specifications


The technical specifications of the ADL4 include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.

Parameters Specified for Optical Interfaces


Table 7-125 lists the parameters specified for the optical interfaces of the ADL4.
Table 7-125 Parameters specified for the optical interfaces of the ADL4
Parameter

Value

Type of optical
interface

S-4.1

L-4.1

L-4.2

Ve-4.2

Type of fiber

Single-mode LC

Single-mode
LC

Single-mode
LC

Single-mode
LC

Operating
wavelength range
(nm)

1274 to 1356

1280 to 1335

1480 to 1580

1480 to 1580

Launched optical
power range
(dBm)

-15 to -8

-3 to +2

-3 to +2

-3 to +2

Minimum
overload (dBm)

-8

-8

-8

-13

Receiver
sensitivity (dBm)

-28

-28

-28

-34

Minimum
extinction ratio
(dB)

8.2

10

10

10.5

Laser Safety Class


The safety class of the laser on the board is Class 1. The maximum launched optical power of
the optical interfaces is less than 10 dBm (10 mW).

Mechanical Specifications
The mechanical specifications of the ADL4 are as follows:
l

Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)

Weight (kg): 0.9

Power Consumption
The maximum power consumption of the ADL4 at room temperature (25C) is 41 W.
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7.15 ADQ1
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the ADQ1 (4xSTM-1 ATM service processing board).
7.15.1 Version Description
The ADQ1 is available in one functional version, namely, N1.
7.15.2 Functions and Features
The ADQ1 supports the ATM switching and ATM protection.
7.15.3 Working Principle and Signal Flow
The ADQ1 consists of the O/E converting module, physical layer module, ATM module, E3
module, mapping module, logic and control module, clock module, and power module.
7.15.4 Front Panel
The front panel of the ADQ1 has indicators, interfaces, a bar code, and a laser safety class label.
7.15.5 Valid Slots
The ADQ1 can be installed in slots 28 and 1116. In this case, the bandwidth is 1.25 Gbit/s.
7.15.6 Feature Code
The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the ADQ1 indicates the type of optical interface.
7.15.7 Parameter Settings
You can set the parameters for the ADQ1 by using the T2000.
7.15.8 Technical Specifications
The technical specifications of the ADQ1 include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.

7.15.1 Version Description


The ADQ1 is available in one functional version, namely, N1.

7.15.2 Functions and Features


The ADQ1 supports the ATM switching and ATM protection.
Table 7-126 provides the functions and features of the ADQ1.
Table 7-126 Functions and features of the ADQ1

7-196

Function and
Feature

ADQ1

Basic functions

Accesses and processes 4xSTM-1 ATM services.

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Function and
Feature

ADQ1

Type of optical
interface

Supports different types of standard optical interfaces, namely, the


Ie-1, S-1.1, L-1.1, L-1.2, and Ve-1.2. The characteristics of the
optical interfaces of the I-1, S-1.1, L-1.1, and L-1.2 types comply
with ITU-T G.957. The characteristics of the optical interfaces of
the Ie-1 and Ve-1.2 types comply with the standards defined by
Huawei.

Connector type

LC

Optical module type

SFP

E3 ATM interface

Supports 12xE3 signals, which are accessed through the PD3, PL3,
or N1PL3A.

IMA function

Does not support the IMA function.

Maximum uplink
bandwidth

Supports a bandwidth of 8xVC-4s, or a bandwidth of 12xVC-3s and


4xVC-4s.

ATM switching
capability

1.2 Gbit/s

Mapping granularities

Supports VC-3, VC-4, and VC4-Xv (X = 14) granularities.

Service types

Supports the CBR, rt-VBR, nrt-VBR and UBR.

Number of supported
ATM connections

2048

Statistical
multiplexing

Supports the statistical multiplexing.

Flow types and QoS

Complies with IETF RFC2514 and ATM forum TM4.0.

ATM multicast
connection

Supports the spatial multicast and logical multicast.

ATM protection (ITUT I.630)

Supports the unidirectional/bidirectional 1+1, unidirectional/


bidirectional 1:1, VP-Ring, and VC-Ring protection schemes.

OAM functions (ITUT I.610)

Supports the AIS, RDI, LB , and CC.

Maintenance features

Supports inloops at the ATM layer and on optical interfaces.


Supports outloops at the ATM layer.
These features can be used to locate faults quickly.

Alarms and
performance events

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Reports various alarms and performance events, which can be used


to locate faults and maintain the equipment.

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7.15.3 Working Principle and Signal Flow


The ADQ1 consists of the O/E converting module, physical layer module, ATM module, E3
module, mapping module, logic and control module, clock module, and power module.
Figure 7-59 shows the functional block diagram of the ADQ1.
Figure 7-59 Functional block diagram of the ADQ1
Backplane
4x155
Mbit/s

4x155
Mbit/s

E/O

4x155
Mbit/s

O/E

Physical
layer
4x155 module
Mbit/s

ATM
module

High-speed
bus

Cross-connect unit

High-speed
bus

Cross-connect unit

Mapping
module
E3
module

O/E converting
module

Reference clock and frame header

LOS
Laser shutdown

Logic and
control module

Communication

Cross-connect unit
SCC unit

50 MHz
77 MHz
100 MHz

Clock
module

+3.3 V

Power
module

Fuse

-48 V/-60 V
-48 V/-60 V

Power
module

O/E Converting Module


In the receive direction, optical signals are converted into electrical signals. In the transmit
direction, electrical signals are converted into optical signals.

Physical Layer Module


The physical layer module mainly performs the following functions:
l

Maps ATM cells into SDH frames.

Demaps SDH frames to ATM cells.

Implements the following functions at the ATM service physical layer: cell delimitation,
and test and generation of HEC sequence.

ATM Module
The ATM module mainly performs the following ATM layer functions that are specified in
ATM protocols:
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l

Flow control

Extraction and generation of cell headers

ATM switching

7 Data Boards

E3 Module
The E3 module mainly processes ATM services at the E3 rate. This module performs the
following functions:
l

Maps the ATM cells into E3 containers.

Demaps E3 containers to ATM cells.

Implements functions at the ATM physical layer for ATM services at the E3 rate.

Mapping Module
The mapping module performs the following functions:
l

Maps ATM cells into SDH frame payloads.

Demaps SDH frame payloads to ATM cells.

Implements functions at the ATM physical layer.

Implements the VC4-Xv (X4) virtual concatenation.

Logic and Control Module


The logic and control module performs the following functions:
l

Controls writing and reading of each chip.

Communicates with the NE.

Issues configured services.

Reports alarms of each functional module.

Detects R_LOS alarms of optical modules.

Controls the shutting down of the laser.

Clock Module
This module mainly generates the required working clock for each chip. The frequency of the
clock can be 50 MHz, 77 MHz, or 100 MHz.

Power Module
It converts the 48 V/60 V power supply into the DC voltages that the modules of the board
require.

7.15.4 Front Panel


The front panel of the ADQ1 has indicators, interfaces, a bar code, and a laser safety class label.
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Diagram of the Front Panel


Figure 7-60 shows the appearance of the front panel of the ADQ1.
Figure 7-60 Front panel of the ADQ1

ADQ1
STAT
ACT
PROG
SRV

CLASS 1
LASER
PRODUCT

OUT1
IN1
OUT2
IN2
OUT3
IN3
OUT4
IN4

ADQ1

Indicators
The front panel of the board has the following indicators:
l

Board hardware status indicator (STAT) two colors (red and green)

Service activation status indicator (ACT) one color (green)

Board software status indicator (PROG) two colors (red and green)

Service alarm indicator (SRV) three colors (red, green, and yellow)

For the meanings of the status of the indicators, see A Indicators.


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Interfaces
The front panel of the ADQ1 has four optical interfaces. Table 7-127 describes the types and
usage of the optical interfaces of the ADQ1.
Table 7-127 Optical interfaces of the ADQ1
Interface

Type of
Interface

Usage

OUT1/IN1

LC (swappable)

Transmits and receives STM-1 optical signals.

OUT2/IN2

LC (swappable)

Transmits and receives STM-1 optical signals.

OUT3/IN3

LC (swappable)

Transmits and receives STM-1 optical signals.

OUT4/IN4

LC (swappable)

Transmits and receives STM-1 optical signals.

7.15.5 Valid Slots


The ADQ1 can be installed in slots 28 and 1116. In this case, the bandwidth is 1.25 Gbit/s.

7.15.6 Feature Code


The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the ADQ1 indicates the type of optical interface.
Table 7-128 provides the relationship between the feature code of the ADQ1 and the type of
optical interface.
Table 7-128 Relationship between the feature code of the ADQ1 and the type of optical interface
Board

Feature Code

Type of Optical Interface

SSN1ADQ110

10

S-1.1

SSN1ADQ111

11

L-1.1

SSN1ADQ112

12

L-1.2

SSN1ADQ113

13

Ve-1.2

SSN1ADQ114

14

Ie-1

7.15.7 Parameter Settings


You can set the parameters for the ADQ1 by using the T2000.
You can set the following parameters for the ADQ1 by using the T2000:
l

Port type

Flow type

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l

Service type

PCR

SCR

Maximum cell burst size

CDVT

For the description of each parameter, see F Parameter Settings.

7.15.8 Technical Specifications


The technical specifications of the ADQ1 include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.

Parameters Specified for Optical Interfaces


Table 7-129 lists the parameters specified for the optical interfaces of the ADQ1.
Table 7-129 Parameters specified for the optical interfaces of the ADQ1
Parameter

Value

Type of optical
interface

Ie-1

S-1.1

L-1.1

L-1.2

Ve-1.2

Type of fiber

Multimode LC

Single-mode
LC

Single-mode
LC

Singlemode LC

Single-mode
LC

Operating
wavelength
range (nm)

1270 to
1380

1261 to 1360

1263 to 1360

1480 to
1580

1480 to 1580

Transmission
distance (km)

0 to 0.5

2 to 15

15 to 40

40 to 80

80 to 100

Launched
optical power
range (dBm)

-19 to -14

-15 to -8

-5 to 0

-5 to 0

-3 to 0

Receive optical
power (dBm)

-30

-28

-34

-34

-34

Minimum
overload (dBm)

-14

-8

-10

-10

-10

Minimum
extinction ratio
(dB)

10

8.2

10

10

10

Laser Safety Class


The safety class of the laser on the board is Class 1. The maximum launched optical power of
the optical interfaces is less than 10 dBm (10 mW).
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Mechanical Specifications
The mechanical specifications of the ADQ1 are as follows:
l

Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)

Weight (kg): 1.0

Power Consumption
The maximum power consumption of the ADQ1 at room temperature (25C) is 41 W.

7.16 IDL4
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the IDL4 (1xSTM-4 ATM service processing board).
7.16.1 Version Description
The IDL4 is available in one functional version, namely, N1.
7.16.2 Functions and Features
The IDL4 supports the ATM switching, IMA, and ATM protection.
7.16.3 Working Principle and Signal Flow
The IDL4 consists of the O/E converting module, physical layer module, ATM module, IMA
module, mapping module, logic and control module, clock module, and power module.
7.16.4 Front Panel
The front panel of the IDL4 has indicators, interfaces, a bar code, and a laser safety class label.
7.16.5 Valid Slots
The IDL4 can be installed in slots 28 and 1116 in the subrack. In this case, the bandwidth is
1.25 Gbit/s.
7.16.6 Feature Code
The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the SL1 indicates the type of optical interface.
7.16.7 Board Protection
The IDL4 supports the 1+1 board-level protection. The working IDL4 and protection IDL4
should be installed in paired slots.
7.16.8 Parameter Settings
You can set the parameters for the IDL4 by using the T2000.
7.16.9 Technical Specifications
The technical specifications of the IDL4 include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.

7.16.1 Version Description


The IDL4 is available in one functional version, namely, N1.

7.16.2 Functions and Features


The IDL4 supports the ATM switching, IMA, and ATM protection.
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Table 7-130 provides the functions and features of the IDL4.


Table 7-130 Functions and features of the IDL4

7-204

Function and
Feature

IDL4

Basic functions

Accesses and processes 1xSTM-4 ATM services.

Type of optical
interface

Supports the following types of optical interfaces: S-4.1, L-4.1, L-4.2


and Ve-4.2.

Connector type

LC

Optical module type

SFP

E3 ATM interface

Does not support the E3 ATM interface.

IMA functions
(ATM Forum IMA
1.1)

Accesses and processes IMA services when the IDL4 is used with
the E1 service processing board N1PQ1 or N1PQM.

Supports a maximum of 63 IMA E1 services.

Supports the mapping between ATM ports and a maximum of 16


IMA groups. Each IMA group supports 132 E1 signals.

Supports the mapping between ATM ports and a maximum of 16


E1 links that belong to non-IMA groups.

Supports the maximum IMA multichannel delay of 226 ms.

Maximum uplink
bandwidth

Supports a bandwidth of 8xVC-4s, or a bandwidth of 63xVC-12s and


7xVC-4s.

ATM switching
capability

1.0 Gbit/s
The IDL4 can adapt to the bandwidth of the slot.

Mapping
granularities

Supports VC-12, VC-4, VC4-Xc (X = 14), and VC12-Xv (X = 1


32) granularities.

Service types

Supports the CBR, rt-VBR, nrt-VBR and UBR.

Number of supported
ATM connections

2048

Statistical
multiplexing

Supports the statistical multiplexing.

Flow types and QoS

Complies with IETF RFC2514 and ATM forum TM4.0.

ATM multicast
connection

Supports the spatial multicast and logical multicast.

ATM protection
(ITU-T I.630)

Supports the unidirectional/bidirectional 1+1, unidirectional/


bidirectional 1:1, VP-Ring, and VC-Ring protection schemes.

Board-level 1+1
protection

Supports the board-level 1+1 protection.

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Function and
Feature

IDL4

OAM functions
(ITU-T I.610)

Supports the AIS, RDI, LB , and CC.

Maintenance
features

Supports inloops at the ATM layer and on optical interfaces.


Supports outloops at the ATM layer.
These features can be used to locate faults quickly.

Alarms and
performance events

Reports various alarms and performance events, which can be used


to locate faults and maintain the equipment.

Note: The IMA function can encapsulate ATM cells into E1 signals. The IMA group can
coexist with a single E1 signal. The IMA group can dynamically increase or decrease the
bandwidth to improve the bandwidth utilization. The IMA group can also be used to converge
2 Mbit/s services and to interconnect with other IMA equipment.

7.16.3 Working Principle and Signal Flow


The IDL4 consists of the O/E converting module, physical layer module, ATM module, IMA
module, mapping module, logic and control module, clock module, and power module.
Figure 7-61 shows the functional block diagram of the IDL4 by describing how to process
1xSTM-4 signals.
Figure 7-61 Functional block diagram of the IDL4
Backplane
622
Mbit/s

622
Mbit/s

622
Mbit/s

E/O

622
Mbit/s

O/E

Physical
layer
module

ATM
module

High-speed
bus

Cross-connect unit A

High-speed
bus

Cross-connect unit B

Mapping
module
IMA
module

O/E converting
module

Reference clock and frame header

LOS
Laser shutdown

Logic and
control module

Communication

Cross-connect unit
SCC unit

50 MHz
77 MHz
100 MHz

Clock
module

+3.3 V

Power
module

Fuse

-48 V/-60 V
-48 V/-60 V

Power
module

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O/E Converting Module


In the receive direction, optical signals are converted into electrical signals. In the transmit
direction, electrical signals are converted into optical signals.

Physical Layer Module


The physical layer module mainly performs the following functions:
l

Maps ATM cells into SDH frames.

Demaps SDH frames to ATM cells.

Implements the following functions at the ATM service physical layer: cell delimitation,
and test and generation of HEC sequence.

ATM Module
The ATM module mainly performs the following ATM layer functions that are specified in
ATM protocols:
l

Flow control

Extraction and generation of cell headers

ATM switching

IMA Module
This module mainly performs the following functions that are specified in IMA protocols:
l

Separation and re-creation of ATM cells

Frame synchronization

Insertion and extraction of IMA control protocol (ICP) cells

Management of IMA groups

Mapping Module
The mapping module performs the following functions:
l

Maps ATM cells into SDH frame payloads.

Demaps SDH frame payloads to ATM cells.

Implements functions at the ATM physical layer.

Implements the VC4-Xv (X4) virtual concatenation.

Logic and Control Module


The logic and control module performs the following functions:

7-206

Controls writing and reading of each chip.

Communicates with the NE.


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l

Issues configured services.

Reports alarms of each functional module.

Detects R_LOS alarms of optical modules.

Controls the shutting down of the laser.

7 Data Boards

Clock Module
This module mainly generates the required working clock for each chip. The frequency of the
clock can be 50 MHz, 77 MHz, or 100 MHz.

Power Module
It converts the 48 V/60 V power supply into the DC voltages that the modules of the board
require.

7.16.4 Front Panel


The front panel of the IDL4 has indicators, interfaces, a bar code, and a laser safety class label.

Diagram of the Front Panel


Figure 7-62 shows the appearance of the front panel of the IDL4.

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Figure 7-62 Front panel of the IDL4

IDL4
STAT
ACT
PROG
SRV

CLASS 1
LASER
PRODUCT

OUT1
IN1

IDL4

Indicators
The front panel of the board has the following indicators:
l

Board hardware status indicator (STAT) two colors (red and green)

Service activation status indicator (ACT) one color (green)

Board software status indicator (PROG) two colors (red and green)

Service alarm indicator (SRV) three colors (red, green, and yellow)

For the meanings of the status of the indicators, see A Indicators.

Interfaces
The front panel of the IDL4 has one optical interface. Table 7-131 describes the type and usage
of the optical interface of the IDL4.
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Table 7-131 Optical interface of the IDL4


Interface

Type of
Interface

Usage

OUT1/IN1

LC
(swappable)

Transmits and receives STM-4 optical signals.

7.16.5 Valid Slots


The IDL4 can be installed in slots 28 and 1116 in the subrack. In this case, the bandwidth is
1.25 Gbit/s.

7.16.6 Feature Code


The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the SL1 indicates the type of optical interface.
Table 7-132 provides the relationship between the feature code of the IDL4 and the type of
optical interface.
Table 7-132 Relationship between the feature code of the IDL4 and the type of optical interface
Board

Feature Code

Type of Optical Interface

SSN1IDL410

10

S-4.1

SSN1IDL411

11

L-4.1

SSN1IDL412

12

L-4.2

SSN1IDL413

13

Ve-4.2

7.16.7 Board Protection


The IDL4 supports the 1+1 board-level protection. The working IDL4 and protection IDL4
should be installed in paired slots.
The IDL4 can be installed in the following paired slots: (slot 8, slot 11), (slot 7, slot 12), (slot
1, slot 13), (slot 5, slot 14), (slot 4, slot 15), and (slot 3, slot 16)

7.16.8 Parameter Settings


You can set the parameters for the IDL4 by using the T2000.
You can set the following parameters for the IDL4 by using the T2000:
l

Port type

Flow type

Service type

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l

PCR

SCR

Maximum cell burst size

CDVT

For the description of each parameter, see F Parameter Settings.

7.16.9 Technical Specifications


The technical specifications of the IDL4 include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.

Parameters Specified for Optical Interfaces


Table 7-133 lists the parameters specified for the optical interfaces of the IDL4.
Table 7-133 Parameters specified for the optical interfaces of the IDL4
Parameter

Value

Type of optical
interface

S-4.1

L-4.1

L-4.2

Ve-4.2

Type of fiber

Single-mode
LC

Single-mode
LC

Single-mode
LC

Single-mode
LC

Operating
wavelength range
(nm)

1274 to 1356

1280 to 1335

1480 to 1580

1480 to 1580

Launched optical
power range (dBm)

-15 to -8

-3 to +2

-3 to +2

-3 to +2

Receiver sensitivity
(dBm)

-28

-28

-28

-34

Minimum overload
(dBm)

-8

-8

-8

-13

Minimum extinction
ratio (dB)

8.2

10

10

10.5

Laser Safety Class


The safety class of the laser on the board is Class 1. The maximum launched optical power of
the optical interfaces is less than 10 dBm (10 mW).

Mechanical Specifications
The mechanical specifications of the IDL4 are as follows:
l

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Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)


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Weight (kg): 1.0

Power Consumption
The maximum power consumption of the IDL4 at room temperature (25C) is 41 W.

7.17 IDL4A
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the IDL4A (1xSTM-4 ATM service processing board).
7.17.1 Version Description
The IDL4A is available in one functional version, namely, N1.
7.17.2 Functions and Features
The IDL4A supports the ATM switching, IMA, and ATM protection.
7.17.3 Working Principle and Signal Flow
The IDL4A consists of the O/E converting module, physical layer module, ATM module, IMA
module, mapping module, logic and control module, clock module, and power module.
7.17.4 Front Panel
The front panel of the IDL4A has indicators, interfaces, a bar code, and a laser safety class label.
7.17.5 Valid Slots
The IDL4A must be installed in a valid slot in the subrack. Otherwise, the IDL4A cannot work
normally.
7.17.6 Feature Code
The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the IDL4A indicates the type of optical interface.
7.17.7 Board Protection
The IDL4A supports the intra-board PPS protection and inter-board PPS protection. The interboard PPS protection does not have specific restrictions on the available paired slots for the
IDL4A.
7.17.8 Parameter Settings
You can set the parameters for the IDL4A by using the T2000.
7.17.9 Technical Specifications
The technical specifications of the IDL4A include the parameters specified for optical interfaces,
laser safety class, dimensions, weight, and power consumption.

7.17.1 Version Description


The IDL4A is available in one functional version, namely, N1.

7.17.2 Functions and Features


The IDL4A supports the ATM switching, IMA, and ATM protection.
Table 7-134 provides the functions and features of the IDL4A.

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Table 7-134 Functions and features of the IDL4A


Function and
Feature

IDL4A

Basic functions

Accesses and processes 1xSTM-4 ATM services.

Type of optical
interface

Supports the following types of optical interfaces: S-4.1, L-4.1, L-4.2


and Ve-4.2.

Connector type

LC/PC, which is applicable to the long-distance and short-distance


lasers.

Optical module
type

SFP and ESFP

E3 ATM interface

Does not support the E3 ATM interface.

IMA functions
(ATM Forum
IMA 1.1)

Accesses and processes IMA services when the IDL4A is used with
the E1 service processing board N1PQ1 or N1PQM.

Supports a maximum of 189 IMA E1 services.

Supports the mapping between ATM ports and a maximum of 93


IMA groups. Each IMA group supports 132 E1 signals.

Supports the mapping between ATM ports and a maximum of 93 E1


links that belong to non-IMA groups.

Supports the IMA multichannel delay ranging from 25 ms to 226 ms.

Supports a bandwidth of 8xVC-4s, or a bandwidth of 189xVC-12s


and 5xVC-4s.

Supports an SDH bandwidth of 8xVC-4s on the TDM cross-connect


side and thus ensures the access bandwidth of 4xVC-4s of the 622
Mbit/s slot.

The IDL4A can adapt to the bandwidth of the slot.

Maximum uplink
bandwidth

7-212

ATM switching
capability

Bidirectional: 900 Mbit/s

Capacity of the
ATM ring

600 Mbit/s

Mapping
granularities

Supports VC-12, VC-4, and VC4-Xv (X = 14) granularities.

Service types

Supports the CBR, rt-VBR, nrt-VBR, UBR, and UBR+.

Number of
supported ATM
connections

8192

Statistical
multiplexing

Supports the statistical multiplexing.

Flow types and


QoS

Complies with IETF RFC2514 and ATM forum TM4.0.

Unidirectional: 1.8 Gbit/s

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Function and
Feature

IDL4A

ATM multicast
connection

Does not support the ATM multicast connection.

ATM protection
(ITU-T I.630)

Supports the unidirectional/bidirectional 1:1, VP-Ring, and VC-Ring


protection schemes.

PPS protection

Supports the intra-board PPS protection and inter-board PPS


protection.

OAM functions
(ITU-T I.610)

Supports the AIS, RDI, LB , and CC.

Clock tracing

When the optical interface is connected to the RNC, the optical interface
supports the input and output of the clock source.

Maintenance
features

Supports inloops at the ATM layer and on optical interfaces.


Supports outloops at the ATM layer.
These features can be used to locate faults quickly.

Alarms and
performance
events

Reports various alarms and performance events, which can be used to


locate faults and maintain the equipment.

Note: The IMA function can encapsulate ATM cells into E1 signals. The IMA group can
coexist with a single E1 signal. The IMA group can dynamically increase or decrease the
bandwidth to improve the bandwidth utilization. The IMA group can also be used to converge
2 Mbit/s services and to interconnect with other IMA equipment.

7.17.3 Working Principle and Signal Flow


The IDL4A consists of the O/E converting module, physical layer module, ATM module, IMA
module, mapping module, logic and control module, clock module, and power module.
Figure 7-63 shows the functional block diagram of the IDL4A by describing how to process
1xSTM-4 signals.

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Figure 7-63 Functional block diagram of the IDL4A

622 Mbit/s

E/O

High-rate bus

622 Mbit/s

PHY
module

Mapping

ATM
module

module
High-rate bus

IMA
module

O/E
622 Mbit/s

622 Mbit/s

LOS

Logic and
control module

Laser shutdown

Cross-connect unit
A

Cross-connect unit B

Reference clock and frame header


Communication

Cross-connect unit
SCC unit

50 MHz
77 MHz
100 MHz

Clock
module
+3.3 V

Power
module

Fuse

-48 V/ -60 V
-48 V/ -60 V

Power
module

O/E Converting Module


In the receive direction, optical signals are converted into electrical signals. In the transmit
direction, electrical signals are converted into optical signals.

Physical Layer Module


The physical layer module mainly performs the following functions:
l

Maps ATM cells into SDH frames.

Demaps SDH frames to ATM cells.

Implements the following functions at the ATM service physical layer: cell delimitation,
and test and generation of HEC sequence.

ATM Module
The ATM module mainly performs the following ATM layer functions that are specified in
ATM protocols:

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Flow control

Extraction and generation of cell headers

ATM switching
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IMA Module
This module mainly performs the following functions that are specified in IMA protocols:
l

Separation and re-creation of ATM cells

Frame synchronization

Insertion and extraction of IMA control protocol (ICP) cells

Management of IMA groups

Mapping Module
The mapping module performs the following functions:
l

Maps ATM cells into SDH frame payloads.

Demaps SDH frame payloads to ATM cells.

Implements functions at the ATM physical layer.

Implements the VC4-Xv (X4) virtual concatenation.

Logic and Control Module


The logic and control module performs the following functions:
l

Controls writing and reading of each chip.

Communicates with the NE.

Issues configured services.

Reports alarms of each functional module.

Detects R_LOS alarms of optical modules.

Controls the shutting down of the laser.

Clock Module
This module mainly generates the required working clock for each chip. The frequency of the
clock can be 50 MHz, 77 MHz, or 100 MHz.

Power Module
It converts the 48 V/60 V power supply into the DC voltages that the modules of the board
require.

7.17.4 Front Panel


The front panel of the IDL4A has indicators, interfaces, a bar code, and a laser safety class label.

Diagram of the Front Panel


Figure 7-64 shows the appearance of the front panel of the IDL4A.
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Figure 7-64 Front panel of the IDL4A

IDL4A
STA
AC
T
T
PROG
SRV

CLASS 1
LASER
PRODUCT

OUT1 IN1
IDL4A

Indicators
The front panel of the board has the following indicators:
l

Board hardware status indicator (STAT) two colors (red and green)

Service activation status indicator (ACT) one color (green)

Board software status indicator (PROG) two colors (red and green)

Service alarm indicator (SRV) three colors (red, green, and yellow)

For the meanings of the status of the indicators, see A Indicators.

Interfaces
The front panel of the IDL4A has one optical interface. Table 7-135 describes the type and usage
of the optical interface of the IDL4A.

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Table 7-135 Optical interface of the IDL4A


Interface

Type of
Interface

Usage

OUT1/IN1

LC
(swappable)

Transmits and receives STM-4 optical signals.

7.17.5 Valid Slots


The IDL4A must be installed in a valid slot in the subrack. Otherwise, the IDL4A cannot work
normally.
The IDL4A can be installed in slots 28 and 1116 in the subrack.

7.17.6 Feature Code


The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the IDL4A indicates the type of optical interface.
Table 7-136 provides the relationship between the feature code of the IDL4A and the type of
optical interface.
Table 7-136 Relationship between the feature code of the IDL4A and the type of optical interface
Board

Feature Code

Type of Optical Interface

SSN1IDL4A10

10

S-4.1

SSN1IDL4A11

11

L-4.1

SSN1IDL4A12

12

L-4.2

SSN1IDL4A13

13

Ve-4.2

7.17.7 Board Protection


The IDL4A supports the intra-board PPS protection and inter-board PPS protection. The interboard PPS protection does not have specific restrictions on the available paired slots for the
IDL4A.

7.17.8 Parameter Settings


You can set the parameters for the IDL4A by using the T2000.
You can set the following parameters for the IDL4A by using the T2000:
l

Port type

Flow type

Service type

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l

PCR

SCR

Maximum cell burst size

CDVT

MCR

For the description of each parameter, see F Parameter Settings.

7.17.9 Technical Specifications


The technical specifications of the IDL4A include the parameters specified for optical interfaces,
laser safety class, dimensions, weight, and power consumption.

Parameters Specified for Optical Interfaces


Table 7-137 lists the parameters specified for the optical interfaces of the IDL4A.
Table 7-137 Parameters specified for the optical interfaces of the IDL4A
Parameter

Value

Type of optical
interface

S-4.1

L-4.1

L-4.2

Ve-4.2

Type of fiber

Single-mode
LC

Single-mode
LC

Single-mode
LC

Single-mode
LC

Operating
wavelength range
(nm)

1274 to 1356

1280 to 1335

1480 to 1580

1480 to 1580

Launched optical
power range (dBm)

15 to 8

3 to +2

3 to +2

3 to +2

Receiver sensitivity
(dBm)

28

28

28

34

Minimum overload
(dBm)

13

Minimum extinction 8.2


ratio (dB)

10

10

10.5

Laser Safety Class


The safety class of the laser on the board is Class 1. The maximum launched optical power of
the optical interfaces is less than 10 dBm (10 mW).

Mechanical Specifications
The mechanical specifications of the IDL4A are as follows:
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Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)

Weight (kg): 1.5

7 Data Boards

Power Consumption
The maximum power consumption of the IDL4A at room temperature (25C) is 60 W.

7.18 IDQ1
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the IDQ1 (4xSTM-1 ATM service processing board).
7.18.1 Version Description
The IDQ1 is available in one functional version, namely, N1.
7.18.2 Functions and Features
The IDQ1 supports the ATM switching, IMA, and ATM protection.
7.18.3 Working Principle and Signal Flow
The IDQ1 consists of the O/E converting module, physical layer module, ATM module, IMA
module, mapping module, logic and control module, clock module, and power module.
7.18.4 Front Panel
The front panel of the IDQ1 has indicators, interfaces, a bar code, and a laser safety class label.
7.18.5 Valid Slots
The IDQ1 can be installed in slots 28 and 1116. In this case, the bandwidth is 1.25 Gbit/s.
7.18.6 Feature Code
The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the IDQ1 indicates the type of optical interface.
7.18.7 Board Protection
The IDQ1 supports the 1+1 board-level protection. The active and standby IDQ1 should be
housed in paired slots.
7.18.8 Parameter Settings
You can set the parameters for the IDQ1 by using the T2000.
7.18.9 Technical Specifications
The technical specifications of the IDQ1 include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.

7.18.1 Version Description


The IDQ1 is available in one functional version, namely, N1.

7.18.2 Functions and Features


The IDQ1 supports the ATM switching, IMA, and ATM protection.
Table 7-138 provides the functions and features of the IDQ1.

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Table 7-138 Functions and features of the IDQ1

7-220

Function and
Feature

IDQ1

Basic functions

Accesses and processes 4xSTM-1 ATM services.

Type of optical
interface

Supports different types of standard optical interfaces, namely, the Ie-1,


S-1.1, L-1.1, L-1.2, and Ve-1.2. The characteristics of the optical
interfaces of the I-1, S-1.1, L-1.1, and L-1.2 types comply with ITU-T
G.957. The characteristics of the optical interfaces of the Ie-1 and
Ve-1.2 types comply with the standards defined by Huawei.

Connector type

LC

Optical module
type

SFP

E3 ATM interface

Does not support the E3 ATM interface.

IMA functions
(ATM Forum
IMA 1.1)

Accesses and processes IMA services when the IDQ1 is used with
the E1 service processing board N1PQ1 or N1PQM.

Supports a maximum of 63 IMA E1 services.

Supports the mapping between ATM ports and a maximum of 93


IMA groups. Each IMA group supports 132 E1 signals.

Supports the mapping between ATM ports and a maximum of 16 E1


links that belong to non-IMA groups.

Supports the maximum IMA multichannel delay of 226 ms.

Maximum uplink
bandwidth

Supports a bandwidth of 8xVC-4s, or a bandwidth of 63xVC-12s and


7xVC-4s.
The IDQ1 can adapt to the bandwidth of the slot.

ATM switching
capability

1.0 Gbit/s

Mapping
granularities

Supports VC-12, VC-4, VC4-Xc (X = 14), and VC12-Xv (X = 132)


granularities.

Service types

Supports the CBR, rt-VBR, nrt-VBR, and UBR.

Number of
supported ATM
connections

2048

Statistical
multiplexing

Supports the statistical multiplexing.

Flow types and


QoS

Complies with IETF RFC2514 and ATM forum TM4.0.

ATM multicast
connection

Supports the spatial multicast and logical multicast.

ATM protection
(ITU-T I.630)

Supports unidirectional/bidirectional 1+1, unidirectional/bidirectional


1:1, VP-Ring, and VC-Ring protection schemes.

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Function and
Feature

IDQ1

Board-level 1+1
protection

Supports the board-level 1+1 protection.

OAM functions
(ITU-T I.610)

Supports the AIS, RDI, LB , and CC.

Maintenance
features

Supports inloops at the ATM layer and on optical interfaces.


Supports outloops at the ATM layer.
These features can be used to locate faults quickly.

Alarm and
performance event

Reports various alarms and performance events, which can be used to


locate faults and maintain the equipment.

Note: The IMA function can encapsulate ATM cells into E1 signals. The IMA group can
coexist with a single E1 signal. The IMA group can dynamically increase or decrease the
bandwidth to improve the bandwidth utilization. The IMA group can also be used to converge
2 Mbit/s services and to interconnect with other IMA equipment.

7.18.3 Working Principle and Signal Flow


The IDQ1 consists of the O/E converting module, physical layer module, ATM module, IMA
module, mapping module, logic and control module, clock module, and power module.
Figure 7-65 shows the functional block diagram of the IDQ1.
Figure 7-65 Functional block diagram of the IDQ1
Backplane
4x155
Mbit/s

4x155
Mbit/s

E/O

4x155
Mbit/s

O/E

Physical
layer
4x155 module
Mbit/s

ATM
module

High-speed
bus

Cross-connect unit A

High-speed
bus

Cross-connect unit B

Mapping
module
IMA
module

O/E converting
module

Reference clock and frame header

LOS
Laser shutdown

Logic and
control module

Communication

Cross-connect unit
SCC unit

50 MHz
77 MHz
100 MHz

Clock
module

+3.3 V

Power
module

Fuse

-48 V/-60 V
-48 V/-60 V

Power
module

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O/E Converting Module


In the receive direction, optical signals are converted into electrical signals. In the transmit
direction, electrical signals are converted into optical signals.

Physical Layer Module


The physical layer module mainly performs the following functions:
l

Maps ATM cells into SDH frames.

Demaps SDH frames to ATM cells.

Implements the following functions at the ATM service physical layer: cell delimitation,
and test and generation of HEC sequence.

ATM Module
The ATM module mainly performs the following ATM layer functions that are specified in
ATM protocols:
l

Flow control

Extraction and generation of cell headers

ATM switching

IMA Module
This module mainly performs the following functions that are specified in IMA protocols:
l

Separation and re-creation of ATM cells

Frame synchronization

Insertion and extraction of IMA control protocol (ICP) cells

Management of IMA groups

Mapping Module
The mapping module performs the following functions:
l

Maps ATM cells into SDH frame payloads.

Demaps SDH frame payloads to ATM cells.

Implements functions at the ATM physical layer.

Implements the VC4-Xv (X4) virtual concatenation.

Logic and Control Module


The logic and control module performs the following functions:

7-222

Controls writing and reading of each chip.

Communicates with the NE.


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Issues configured services.

Reports alarms of each functional module.

Detects R_LOS alarms of optical modules.

Controls the shutting down of the laser.

7 Data Boards

Clock Module
This module mainly generates the required working clock for each chip. The frequency of the
clock can be 50 MHz, 77 MHz, or 100 MHz.

Power Module
It converts the 48 V/60 V power supply into the DC voltages that the modules of the board
require.

7.18.4 Front Panel


The front panel of the IDQ1 has indicators, interfaces, a bar code, and a laser safety class label.

Diagram of the Front Panel


Figure 7-66 shows the appearance of the front panel of the IDQ1.

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Figure 7-66 Front panel of the IDQ1

IDQ1
STAT
ACT
PROG
SRV

CLASS 1
LASER
PRODUCT

OUT1
IN1
OUT2
IN2
OUT3
IN3
OUT4
IN4

IDQ1

Indicators
The front panel of the board has the following indicators:
l

Board hardware status indicator (STAT) two colors (red and green)

Service activation status indicator (ACT) one color (green)

Board software status indicator (PROG) two colors (red and green)

Service alarm indicator (SRV) three colors (red, green, and yellow)

For the meanings of the status of the indicators, see A Indicators.

Interfaces
The front panel of the IDQ1 has four optical interfaces. Table 7-139 describes the types and
usage of the optical interfaces of the IDQ1.
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Table 7-139 Optical interfaces of the IDQ1


Interface

Type of
Interface

Usage

OUT1/IN1

LC (swappable)

Transmits and receives STM-1 optical signals.

OUT2/IN2

LC (swappable)

Transmits and receives STM-1 optical signals.

OUT3/IN3

LC (swappable)

Transmits and receives STM-1 optical signals.

OUT4/IN4

LC (swappable)

Transmits and receives STM-1 optical signals.

7.18.5 Valid Slots


The IDQ1 can be installed in slots 28 and 1116. In this case, the bandwidth is 1.25 Gbit/s.

7.18.6 Feature Code


The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the IDQ1 indicates the type of optical interface.
Table 7-140 provides the relationship between the feature code of the IDQ1 and the type of
optical interface.
Table 7-140 Relationship between the feature code of the IDQ1 and the type of optical interface
Board

Feature Code

Type of Optical Interface

SSN1IDQ110

10

S-1.1

SSN1IDQ111

11

L-1.1

SSN1IDQ112

12

L-1.2

SSN1IDQ113

13

Ve-1.2

SSN1IDQ114

14

Ie-1

7.18.7 Board Protection


The IDQ1 supports the 1+1 board-level protection. The active and standby IDQ1 should be
housed in paired slots.

7.18.8 Parameter Settings


You can set the parameters for the IDQ1 by using the T2000.
You can set the following parameters for the IDQ1 by using the T2000:
l

Port type

Flow type

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l

Service type

PCR

SCR

Maximum cell burst size

CDVT

For the description of each parameter, see F Parameter Settings.

7.18.9 Technical Specifications


The technical specifications of the IDQ1 include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.

Parameters Specified for Optical Interfaces


Table 7-141 lists the parameters specified for the optical interfaces of the IDQ1.
Table 7-141 Parameters specified for the optical interfaces of the IDQ1
Parameter

Value

Type of optical
interface

Ie-1

S-1.1

L-1.2

Ve-1.2

L-1.1

Type of fiber

Multimode LC

Singlemode LC

Singlemode LC

Single-mode
LC

Single-mode
LC

Operating
wavelength
range (nm)

1270 to
1380

1261 to
1360

1480 to
1580

1480 to 1580

1263 to 1360

Transmission
distance (km)

0 to 0.5

2 to 15

40 to 80

80 to 100

15 to 40

Launched optical
power range
(dBm)

-19 to -14

-15 to -8

-5 to 0

-3 to 0

-5 to 0

Receiver
sensitivity
(dBm)

-30

-28

-34

-34

-34

Minimum
overload (dBm)

-14

-8

-10

-10

-10

Minimum
extinction ratio
(dB)

10

8.2

10

10

10

Laser Safety Class


The safety class of the laser on the board is Class 1. The maximum launched optical power of
the optical interfaces is less than 10 dBm (10 mW).
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Mechanical Specifications
The mechanical specifications of the IDQ1 are as follows:
l

Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)

Weight (kg): 1.0

Power Consumption
The maximum power consumption of the IDQ1 at room temperature (25C) is 41 W.

7.19 IDQ1A
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the IDQ1A (4xSTM-1 ATM service processing board).
7.19.1 Version Description
The IDQ1A is available in one functional version, namely, N1.
7.19.2 Functions and Features
The IDQ1A supports the ATM switching, IMA, and ATM protection.
7.19.3 Working Principle and Signal Flow
The IDQ1A consists of the O/E converting module, physical layer module, ATM module, IMA
module, mapping module, logic and control module, clock module, and power module.
7.19.4 Front Panel
The front panel of the IDQ1A has indicators, interfaces, a bar code, and a laser safety class label.
7.19.5 Valid Slots
The IDQ1A must be installed in a valid slot in the subrack. Otherwise, the IDQ1A cannot work
normally.
7.19.6 Feature Code
The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the IDQ1A indicates the type of optical interface.
7.19.7 Board Protection
The IDQ1A supports the intra-board PPS protection and inter-board PPS protection. The interboard PPS protection does not have specific restrictions on the available paired slots for the
IDL4A.
7.19.8 Parameter Settings
You can set the parameters for the IDQ1A by using the T2000.
7.19.9 Technical Specifications
The technical specifications of the IDQ1A include the parameters specified for optical interfaces,
laser safety class, dimensions, weight, and power consumption.

7.19.1 Version Description


The IDQ1A is available in one functional version, namely, N1.

7.19.2 Functions and Features


The IDQ1A supports the ATM switching, IMA, and ATM protection.
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Table 7-142 provides the functions and features of the IDQ1A.


Table 7-142 Functions and features of the IDQ1A

7-228

Function and
Feature

IDQ1A

Basic functions

Accesses and processes 4xSTM-1 ATM services.

Type of optical
interface

Supports different types of standard optical interfaces, namely, the Ie-1,


S-1.1, L-1.1, L-1.2, and Ve-1.2. The characteristics of the optical
interfaces of the I-1, S-1.1, L-1.1, and L-1.2 types comply with ITU-T
G.957. l The characteristics of the optical interfaces of the Ie-1 and
Ve-1.2 types comply with the standards defined by Huawei.

Connector type

LC/PC, which is applicable to the long-distance and short-distance


lasers.

Optical module
type

SFP and ESFP

E3 ATM interface

Does not support the E3 ATM interface.

IMA functions
(ATM Forum
IMA 1.1 standard)

Accesses and processes IMA services when the IDQ1A is used with
the E1 service processing board N1PQ1 or N1PQM.

Supports a maximum of 189 IMA E1 services.

Supports the mapping between ATM ports and a maximum of 93


IMA groups. Each IMA group supports 132 E1 signals.

Supports the mapping between ATM ports and a maximum of 93 E1


links that belong to non-IMA groups.

Supports the IMA multichannel delay ranging from 25 ms to 226 ms.

Maximum uplink
bandwidth

Supports a bandwidth of 8xVC-4s, or a bandwidth of 189xVC-12s and


5xVC-4s.
The IDQ1A can adapt to the bandwidth of the slot.

ATM switching
capability

Bidirectional: 900 Mbit/s

Capacity of the
ATM ring

600 Mbit/s

Mapping
granularities

Supports VC-12, VC-4, and VC4-Xc (X = 14) granularities.

Service types

Supports the CBR, rt-VBR, nrt-VBR, UBR, and UBR+.

Number of
supported ATM
connections

8192

Statistical
multiplexing

Supports the statistical multiplexing.

Unidirectional: 1.8 Gbit/s

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Function and
Feature

IDQ1A

Flow types and


QoS

Complies with IETF RFC2514 and ATM forum TM4.0.

ATM multicast
connection

Does not support the ATM multicast connection.

ATM protection
(ITU-T I.630)

Supports the unidirectional/bidirectional 1:1, VP-Ring, and VC-Ring


protection schemes.

PPS protection

Supports the inter-board PPS protection and intra-board PPS


protection.

OAM functions
(ITU-T I.610)

Supports the AIS, RDI, LB , and CC.

Clock tracing
function

When the optical interface is interconnected with the RNC, the optical
interface supports the input and output of the clock source.

Maintenance
features

Supports inloops at the ATM layer and on optical interfaces.


Supports outloops at the ATM layer.
These features can be used to locate faults quickly.

Alarms and
performance
events

Reports various alarms and performance events, which can be used to


locate faults and maintain the equipment.

Note: The IMA function can encapsulate ATM cells into E1 signals. The IMA group can
coexist with a single E1 signal. The IMA group can dynamically increase or decrease the
bandwidth to improve the bandwidth utilization. The IMA group can also be used to converge
2 Mbit/s services and to interconnect with other IMA equipment.

7.19.3 Working Principle and Signal Flow


The IDQ1A consists of the O/E converting module, physical layer module, ATM module, IMA
module, mapping module, logic and control module, clock module, and power module.
Figure 7-67 shows the functional block diagram of the IDQ1A by describing how to process
1xSTM-1 signals.

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Figure 7-67 Functional block diagram of the IDQ1A

155 Mbit/s

E/O

High-rate bus

155 Mbit/s

PHY
module

Mapping

ATM
module

module
High-rate bus

IMA
module

O/E
155 Mbit/s

155 Mbit/s

LOS

Logic and
control module

Laser shutdown

Cross-connect unit
A

Cross-connect unit B

Reference clock and frame header


Communication

Cross-connect unit
SCC unit

50 MHz
77 MHz
100 MHz

Clock
module
+3.3 V

Power
module

Fuse

-48 V/ -60 V
-48 V/ -60 V

Power
module

O/E Converting Module


In the receive direction, optical signals are converted into electrical signals. In the transmit
direction, electrical signals are converted into optical signals.

Physical Layer Module


The physical layer module mainly performs the following functions:
l

Maps ATM cells into SDH frames.

Demaps SDH frames to ATM cells.

Implements the following functions at the ATM service physical layer: cell delimitation,
and test and generation of HEC sequence.

ATM Module
The ATM module mainly performs the following ATM layer functions that are specified in
ATM protocols:

7-230

Flow control

Extraction and generation of cell headers

ATM switching
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IMA Module
This module mainly performs the following functions that are specified in IMA protocols:
l

Separation and re-creation of ATM cells

Frame synchronization

Insertion and extraction of IMA control protocol (ICP) cells

Management of IMA groups

Mapping Module
The mapping module performs the following functions:
l

Maps ATM cells into SDH frame payloads.

Demaps SDH frame payloads to ATM cells.

Implements functions at the ATM physical layer.

Implements the VC4-Xv (X4) virtual concatenation.

Logic and Control Module


The logic and control module performs the following functions:
l

Controls writing and reading of each chip.

Communicates with the NE.

Issues configured services.

Reports alarms of each functional module.

Detects R_LOS alarms of optical modules.

Controls the shutting down of the laser.

Clock Module
This module mainly generates the required working clock for each chip. The frequency of the
clock can be 50 MHz, 77 MHz, or 100 MHz.

Power Module
It converts the 48 V/60 V power supply into the DC voltages that the modules of the board
require.

7.19.4 Front Panel


The front panel of the IDQ1A has indicators, interfaces, a bar code, and a laser safety class label.

Diagram of the Front Panel


Figure 7-68 shows the appearance of the front panel of the IDQ1A.
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Figure 7-68 Front panel of the IDQ1A

IDQ1A
STAT
ACT
PROG
SRV
CLASS 1
LASER
PRODUCT

OUT1
IN1
OUT2
IN2
OUT3
IN3
OUT4
IN4
IDQ1A

Indicators
The front panel of the board has the following indicators:
l

Board hardware status indicator (STAT) two colors (red and green)

Service activation status indicator (ACT) one color (green)

Board software status indicator (PROG) two colors (red and green)

Service alarm indicator (SRV) three colors (red, green, and yellow)

For the meanings of the status of the indicators, see A Indicators.

Interfaces
The front panel of the IDQ1A has four optical interfaces. Table 7-143 describes the types and
usage of the optical interfaces of the IDQ1A.

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Table 7-143 Optical interfaces of the IDQ1A


Interface

Type of
Interface

Usage

OUT1/IN1

LC (swappable)

Transmits and receives STM-1 optical signals.

OUT2/IN2

LC (swappable)

Transmits and receives STM-1 optical signals.

OUT3/IN3

LC (swappable)

Transmits and receives STM-1 optical signals.

OUT4/IN4

LC (swappable)

Transmits and receives STM-1 optical signals.

7.19.5 Valid Slots


The IDQ1A must be installed in a valid slot in the subrack. Otherwise, the IDQ1A cannot work
normally.
The IDQ1A can be installed in slots 28 and 1116 in the subrack.

7.19.6 Feature Code


The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the IDQ1A indicates the type of optical interface.
Table 7-144 provides the relationship between the feature code of the IDQ1A and the type of
optical interface.
Table 7-144 Relationship between the feature code of the IDQ1A and the type of optical interface
Board

Feature Code

Type of Optical Interface

SSN1IDQ1A10

10

S-1.1

SSN1IDQ1A11

11

L-1.1

SSN1IDQ1A12

12

L-1.2

SSN1IDQ1A13

13

Ve-1.2

SSN1IDQ1A14

14

Ie-1

7.19.7 Board Protection


The IDQ1A supports the intra-board PPS protection and inter-board PPS protection. The interboard PPS protection does not have specific restrictions on the available paired slots for the
IDL4A.

7.19.8 Parameter Settings


You can set the parameters for the IDQ1A by using the T2000.
You can set the following parameters for the IDQ1A by using the T2000:
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l

Port type

Flow type

Service type

PCR

SCR

Maximum cell burst size

CDVT

MCR

For the description of each parameter, see F Parameter Settings.

7.19.9 Technical Specifications


The technical specifications of the IDQ1A include the parameters specified for optical interfaces,
laser safety class, dimensions, weight, and power consumption.

Parameters Specified for Optical Interfaces


Table 7-145 lists the parameters specified for the optical interfaces of the IDQ1A.
Table 7-145 Parameters specified for the optical interfaces of the IDQ1A

7-234

Parameter

Value

Type of optical
interface

Ie-1

S-1.1

L-1.2

Ve-1.2

L-1.1

Type of fiber

Singlemode LC

Singlemode LC

Singlemode LC

Single-mode
LC

Single-mode
LC

Operating
wavelength
range (nm)

1260 to
1360

1261 to
1360

1480 to
1580

1480 to 1580

1280 to 1335

Transmission
distance (km)

0 to 0.5

2 to 15

40 to 80

80 to 100

15 to 40

Launched optical
power range
(dBm)

19 to 14

15 to 8

5 to 0

3 to 0

5 to 0

Receiver
sensitivity
(dBm)

31

28

34

34

34

Minimum
overload (dBm)

14

10

10

10

Minimum
extinction ratio
(dB)

10

8.2

10

10

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Laser Safety Class


The safety class of the laser on the board is Class 1. The maximum launched optical power of
the optical interfaces is less than 10 dBm (10 mW).

Mechanical Specifications
The mechanical specifications of the IDQ1A are as follows:
l

Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)

Weight (kg): 1.5

Power Consumption
The maximum power consumption of the IDQ1A at room temperature (25C) is 46 W.

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8 Interface Boards and Switching and Bridging Boards

Interface Boards and Switching and


Bridging Boards

About This Chapter


This topic describes the interface boards and the switching and bridging boards. The interface
boards are used to access cables and optical fibers. The switching and bridging boards are used
for the TPS.
8.1 D12B
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the D12B (32xE1/T1 access board).
8.2 D12S
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the D12S (32xE1/T1 switching access board).
8.3 D75S
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the D75S (32xE1 switching access board).
8.4 D34S
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the D34S (6xE3/T3 switching access board).
8.5 C34S
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the C34S (3xE3/T3 switching access board).
8.6 EU04
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the EU04 (4xSTM-1 electrical interface board).
8.7 EU08
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the EU08 (8xSTM-1 electrical interface board).
8.8 OU08
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the OU08 (8xSTM-1 optical interface board).
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8.9 MU04
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the MU04 (4xE4/STM-1 electrical interface board).
8.10 TSB4
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the TSB4 (4-channel electrical interface protection switching board).
8.11 TSB8
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the TSB8 (8-channel electrical interface protection switching board).
8.12 EFF8
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the EFF8 (8x100M Ethernet optical interface board).
8.13 EFF8A
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the EFF8A (8x100M Ethernet optical interface board).
8.14 ETF8
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the ETF8 (8x100M Ethernet twisted pair interface board).
8.15 ETF8A
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the ETF8A (8x100M Ethernet twisted pair interface board).
8.16 ETS8
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the ETS8 (8x10/100M Ethernet twisted pair interface switching
board).
8.17 DM12
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the DM12 (DDN service interface board).

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8.1 D12B
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the D12B (32xE1/T1 access board).
8.1.1 Version Description
The D12B is available in one functional version, namely, N1.
8.1.2 Functions and Features
The D12B receives and transmits 32xE1/T1 electrical signals. The D12B must work with the
PQ1, PO1, or PQM.
8.1.3 Working Principle and Signal Flow
The D12B has the interface module.
8.1.4 Front Panel
The front panel of the D12B has interfaces and a bar code.
8.1.5 Valid Slots
The D12B can be installed in slots 2140 in the subrack and works as the interface board of the
PQ1, PO1 or PQM.
8.1.6 Technical Specifications
The technical specifications of the D12B include the parameters specified for the electrical
interfaces, mechanical specifications and power consumption.

8.1.1 Version Description


The D12B is available in one functional version, namely, N1.

8.1.2 Functions and Features


The D12B receives and transmits 32xE1/T1 electrical signals. The D12B must work with the
PQ1, PO1, or PQM.

8.1.3 Working Principle and Signal Flow


The D12B has the interface module.
Figure 8-1 shows the functional block diagram of the D12B by describing how to process 1xE1/
T1 signals.
Figure 8-1 Functional block diagram of the D12B
Backplane

PQ1/PQM/PO1

E1/T1 electrical signal


Interface
module
E1/T1 electrical signal

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Interface Module
The interface module receives and transmits the E1/T1 electrical signals.

8.1.4 Front Panel


The front panel of the D12B has interfaces and a bar code.

Diagram of the Front Panel


Figure 8-2 shows the appearance of the front panel of the D12B.
Figure 8-2 Front panel of the D12B

D12B

1~8
9~16
17~24
25~32

D12B

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Interfaces
The front panel of the D12B has four DB44 interfaces. Table 8-1 describes the types and usage
of the interfaces of the D12B.
Table 8-1 Interfaces of the D12B
Interface

Type of
Interface

Usage

18

DB44

Receives the 1st to the 8th channels of E1/T1


signals.

916

DB44

Receives the 9th to the 16th channels of E1/T1


signals.

1724

DB44

Receives the 17th to the 24th channels of E1/T1


signals.

2532

DB44

Receives the 25th to the 32nd channels of E1/T1


signals.

Table 8-2 provides the pin assignments of the DB44 interface.


Table 8-2 Pin assignments of the DB44 interface
Front View
30

15

44

Pin

Usage

Pin

Usage

38

Receives the 1st


channel of signals
(R1).

34

Receives the 5th


channel of signals
(R5).

Receives the 2nd


channel of signals
(R2).

33

Receives the 3rd


channel of signals
(R3).

32

Receives the 4th


channel of signals
(R4).

31

Transmits the 1st


channel of signals
(T1).

11

Transmits the 2nd


channel of signals
(T2).

10

23
37
22
36
21
35

31
16

20
15
30
14
29

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19

18

17

16

26

25

Receives the 6th


channel of signals
(R6).
Receives the 7th
channel of signals
(R7).
Receives the 8th
channel of signals
(R8).
Transmits the 5th
channel of signals
(T5).
Transmits the 6th
channel of signals
(T6).

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Front View

Pin

Usage

Pin

Usage

13

Transmits the 3rd


channel of signals
(T3).

Transmits the 7th


channel of signals
(T7).

Transmits the 4th


channel of signals
(T4).

28
12
27

24

Transmits the 8th


channel of signals
(T8).

8.1.5 Valid Slots


The D12B can be installed in slots 2140 in the subrack and works as the interface board of the
PQ1, PO1 or PQM.
Table 8-3 lists the slots valid for the PQ1/PQM/PO1 and the corresponding slots for the D12B.
The D12B installed in the slot with a smaller number accesses the 1st to the 32nd channels of
E1/T1 electrical signals. The D12B installed in the slot with a larger number accesses the 33rd
to the 63rd channels of E1/T1 electrical signals.
Table 8-3 Slots valid for the PQ1/PQM/PO1 and the corresponding slots for the D12B
Slot Valid for the PQ1/PQM/PO1

Corresponding Slot for the D12B

Slot 3

Slots 21 and 22

Slot 4

Slots 23 and 24

Slot 5

Slots 25 and 26

Slot 6

Slots 27 and 28

Slot 7

Slots 29 and 30

Slot 12

Slots 31 and 32

Slot 13

Slots 33 and 34

Slot 14

Slots 35 and 36

Slot 15

Slots 37 and 38

Slot 16

Slots 39 and 40

8.1.6 Technical Specifications


The technical specifications of the D12B include the parameters specified for the electrical
interfaces, mechanical specifications and power consumption.

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Parameters Specified for Electrical Interfaces


Table 8-4 Parameters specified for the electrical interfaces of the D12B
Parameter

Value

Type of electrical
interface

1544 kbit/s

2048 kbit/s

Line code pattern

B8ZS and
AMI

HDB3

Signal bit rate at the


output interface

Complies with ITU-T G.703.

Allowed frequency
deviation at the
input interface
Allowed attenuation
at the input interface
Input jitter tolerance

Mechanical Specifications
The mechanical specifications of the D12B are as follows:
l

Dimensions (mm): 22 (W) x 110 (D) x 262.05 (H)

Weight (kg): 0.3

Power Consumption
The maximum power consumption of the D12B at room temperature (25C) is 0 W.

8.2 D12S
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the D12S (32xE1/T1 switching access board).
8.2.1 Version Description
The D12S is available in one functional version, namely, N1.
8.2.2 Functions and Features
The D12S receives and transmits 32xE1/T1 electrical signals. The D12S must work with the
PQ1, PD1, PO1, or PQM.
8.2.3 Working Principle and Signal Flow
The D12S consists of the interface module, switch matrix module, and power access circuit.
8.2.4 Front Panel
The front panel of the D12S has interfaces and a bar code.
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8.2.5 Valid Slots


The D12S can be installed in slots 2140 in the subrack and works as the interface board of the
PQ1, PO1, or PQM.
8.2.6 Technical Specifications
The technical specifications of the D12S include the parameters specified for the electrical
interfaces, mechanical specifications and power consumption.

8.2.1 Version Description


The D12S is available in one functional version, namely, N1.

8.2.2 Functions and Features


The D12S receives and transmits 32xE1/T1 electrical signals. The D12S must work with the
PQ1, PD1, PO1, or PQM.

8.2.3 Working Principle and Signal Flow


The D12S consists of the interface module, switch matrix module, and power access circuit.
Figure 8-3 shows the functional block diagram of the D12S by describing how to process 1xE1/
T1 signals.
Figure 8-3 Functional block diagram of the D12S
Backplane
Cross-connect board
E1/T1 electrical
signal

Interfac
e
module

Switch
matrix
module

E1/T1 electrical
signal

PQ1/PD1/PQM

PQ1/PD1/PQM

+3.3 V

Fuse

+3.3 V power

Interface Module
The interface module receives and transmits the E1/T1 electrical signals.

Switch Matrix Module


In the receive direction, the switch matrix module receives the signal sent from the interface
module and selects the output direction of the signal according to the TPS protection control
signal sent from the cross-connect board. When the TPS is not performed, the switch matrix
module transmits the signal to the PQ1/PD1/PO1 or PQM. When the TPS is performed, the
switch matrix module transmits the signal to the protection board for bridging.
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In the transmit direction, the switch matrix module performs the reverse process.

Power Access Circuit


The power access circuit provides all the modules of the D12S with the required DC voltages.

8.2.4 Front Panel


The front panel of the D12S has interfaces and a bar code.

Diagram of the Front Panel


Figure 8-4 shows the appearance of the front panel of the D12S.
Figure 8-4 Front panel of the D12S

D12S

1~8
9~16
17~24
25~32

D12S

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Interfaces
The front panel of the D12S has four DB44 interfaces. Table 8-5 describes the types and usage
of the interfaces of the D12S.
Table 8-5 Interfaces of the D12S
Interface

Type of
Interface

Usage

18

DB44

Receives the 1st to the 8th channels of E1/T1


signals.

916

DB44

Receives the 9th to the 16th channels of E1/T1


signals.

1724

DB44

Receives the 17th to the 24th channels of E1/T1


signals.

2532

DB44

Receives the 25th to the 32nd channels of E1/T1


signals.

Table 8-6 provides the pin assignments of the DB44 interface.


Table 8-6 Pin assignments of the DB44 interface
Front View
30

15

44

Pin

Usage

Pin

Usage

38

Receives the 1st


channel of signals
(R1).

34

Receives the 5th


channel of signals
(R5).

Receives the 2nd


channel of signals
(R2).

33

Receives the 3rd


channel of signals
(R3).

32

Receives the 4th


channel of signals
(R4).

31

Transmits the 1st


channel of signals
(T1).

11

Transmits the 2nd


channel of signals
(T2).

10

23
37
22
36
21
35

31
16

20
15
30
14
29

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19

18

17

16

26

25

Receives the 6th


channel of signals
(R6).
Receives the 7th
channel of signals
(R7).
Receives the 8th
channel of signals
(R8).
Transmits the 5th
channel of signals
(T5).
Transmits the 6th
channel of signals
(T6).

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Front View

8 Interface Boards and Switching and Bridging Boards

Pin

Usage

Pin

Usage

13

Transmits the 3rd


channel of signals
(T3).

Transmits the 7th


channel of signals
(T7).

Transmits the 4th


channel of signals
(T4).

28
12
27

24

Transmits the 8th


channel of signals
(T8).

8.2.5 Valid Slots


The D12S can be installed in slots 2140 in the subrack and works as the interface board of the
PQ1, PO1, or PQM.
Table 8-7 lists the slots valid for the PQ1/PQM/PO1 and the corresponding slots for the D12S.
The D12S installed in the slot with a smaller number accesses the 1st to the 32nd channels of
E1/T1 electrical signals. The D12S installed in the slot with a larger number accesses the 33rd
to the 63rd channels of E1/T1 electrical signals.
Table 8-7 Slots valid for the PQ1/PQM/PO1 and the corresponding slots for the D12S
Slot Valid for the PQ1/PQM/PO1

Corresponding Slot for the D12S

Slot 3

Slots 21 and 22

Slot 4

Slots 23 and 24

Slot 5

Slots 25 and 26

Slot 6

Slots 27 and 28

Slot 7

Slots 29 and 30

Slot 12

Slots 31 and 32

Slot 13

Slots 33 and 34

Slot 14

Slots 35 and 36

Slot 15

Slots 37 and 38

Slot 16

Slots 39 and 40

8.2.6 Technical Specifications


The technical specifications of the D12S include the parameters specified for the electrical
interfaces, mechanical specifications and power consumption.

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Parameters Specified for Electrical Interfaces


Table 8-8 Parameters specified for the electrical interfaces of the D12S
Parameter

Value

Type of electrical
interface

1544 kbit/s

2048 kbit/s

Line code pattern

B8ZS and
AMI

HDB3

Signal bit rate at the


output interface

Complies with ITU-T G.703.

Allowed frequency
deviation at the
input interface
Allowed attenuation
at the input interface
Input jitter tolerance

Mechanical Specifications
The mechanical specifications of the D12S are as follows:
l

Dimensions (mm): 22 (W) x 110 (D) x 262.05 (H)

Weight (kg): 0.4

Power Consumption
At room temperature (25C), the maximum power consumption of the D12S is 0 W.

8.3 D75S
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the D75S (32xE1 switching access board).
8.3.1 Version Description
The D75S is available in one functional version, namely, N1.
8.3.2 Functions and Features
The D75S receives and transmits 32xE1 electrical signals. The D75S must work with the PQ1/
PD1.
8.3.3 Working Principle and Signal Flow
The D75S consists of the interface module, switch matrix module, and power access circuit.
8.3.4 Front Panel
The front panel of the D75S has interfaces and a bar code.
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8.3.5 Valid Slots


The D75S can be installed in slots 2140 in the subrack and works as the interface board of the
PQ1.
8.3.6 Technical Specifications
The technical specifications of the D75S include the parameters specified for the electrical
interfaces, mechanical specifications and power consumption.

8.3.1 Version Description


The D75S is available in one functional version, namely, N1.

8.3.2 Functions and Features


The D75S receives and transmits 32xE1 electrical signals. The D75S must work with the PQ1/
PD1.

8.3.3 Working Principle and Signal Flow


The D75S consists of the interface module, switch matrix module, and power access circuit.
Figure 8-5 shows the functional block diagram of the D75S by describing how to process 1xE1
signals.
Figure 8-5 Functional block diagram of the D75S
Backplane
Cross-connect board
E1 electrical signal
Interface
module

Switch
matrix
module

E1 electrical signal

PQ1/PD1

PQ1/PD1

+3.3 V

Fuse

+3.3 V power

Interface Module
The interface module receives and transmits the E1 electrical signals.

Switch Matrix Module


In the receive direction, the switch matrix module receives the signal sent from the interface
module and selects the output direction of the signal according to the TPS protection control
signal sent from the cross-connect board. When the TPS is not performed, the switch matrix
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module transmits the signal to the PQ1/PD1. When the TPS is performed, the switch matrix
module transmits the signal to the protection board for bridging.
In the transmit direction, the switch matrix module performs the reverse process.

Power Access Circuit


The power access circuit provides all the modules of the D75S with the required DC voltages.

8.3.4 Front Panel


The front panel of the D75S has interfaces and a bar code.

Diagram of the Front Panel


Figure 8-6 shows the appearance of the front panel of the D75S.
Figure 8-6 Front panel of the D75S

D75S

1~8
9~16
17~24
25~32

D75S

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Interfaces
The front panel of the D75S has four DB44 interfaces. Table 8-9 describes the types and usage
of the interfaces of the D75S.
Table 8-9 Interfaces of the D75S
Interface

Type of
Interface

Usage

18

DB44

Receives the 1st to the 8th channels of E1 signals.

916

DB44

Receives the 9th to the 16th channels of E1


signals.

1724

DB44

Receives the 17th to the 24th channels of E1


signals.

2532

DB44

Receives the 25th to the 32nd channels of E1


signals.

Table 8-10 provides the pin assignments of the DB44 interface.


Table 8-10 Pin assignments of the DB44 interface
Front View
30

15

44

Pin

Usage

Pin

Usage

38

Receives the 1st


channel of signals
(R1).

34

Receives the 5th


channel of signals
(R5).

Receives the 2nd


channel of signals
(R2).

33

Receives the 3rd


channel of signals
(R3).

32

Receives the 4th


channel of signals
(R4).

31

Transmits the 1st


channel of signals
(T1).

11

Transmits the 2nd


channel of signals
(T2).

10

Transmits the 3rd


channel of signals
(T3).

23
37
22
36
21
35

31
16

20
15
30
14
29
13
28

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19

18

17

16

26

25

24

Receives the 6th


channel of signals
(R6).
Receives the 7th
channel of signals
(R7).
Receives the 8th
channel of signals
(R8).
Transmits the 5th
channel of signals
(T5).
Transmits the 6th
channel of signals
(T6).
Transmits the 7th
channel of signals
(T7).
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Front View

Pin

Usage

Pin

Usage

12

Transmits the 4th


channel of signals
(T4).

Transmits the 8th


channel of signals
(T8).

27

8.3.5 Valid Slots


The D75S can be installed in slots 2140 in the subrack and works as the interface board of the
PQ1.
Table 8-11 lists the slots valid for the PQ1 and the corresponding slots for the D75S. The D75S
installed in the slot with a smaller number accesses the 1st to the 32nd channels of E1 electrical
signals. The D75S installed in the slot with a larger number accesses the 33rd to the 63rd channels
of E1 electrical signals.
Table 8-11 Slots valid for the PQ1 and the corresponding slots for the D75S
Slot Valid for the PQ1

Corresponding Slot for the D75S

Slot 3

Slots 21 and 22

Slot 4

Slots 23 and 24

Slot 5

Slots 25 and 26

Slot 6

Slots 27 and 28

Slot 7

Slots 29 and 30

Slot 12

Slots 31 and 32

Slot 13

Slots 33 and 34

Slot 14

Slots 35 and 36

Slot 15

Slots 37 and 38

Slot 16

Slots 39 and 40

8.3.6 Technical Specifications


The technical specifications of the D75S include the parameters specified for the electrical
interfaces, mechanical specifications and power consumption.

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Parameters Specified for Electrical Interfaces


Table 8-12 Parameters specified for the electrical interfaces of the D75S
Parameter

Value

Type of electrical
interface

2048 kbit/s

Line code pattern

HDB3

Signal bit rate at the


output interface

Complies with ITU-T G.703.

Allowed frequency
deviation at the
input interface
Allowed attenuation
at the input interface
Input jitter tolerance

Mechanical Specifications
The mechanical specifications of the D75S are as follows:
l

Dimensions (mm): 22 (W) x 110 (D) x 262.05 (H)

Weight (kg): 0.4

Power Consumption
At room temperature (25C), the maximum power consumption of the D75S is 0 W.

8.4 D34S
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the D34S (6xE3/T3 switching access board).
8.4.1 Version Description
The D34S is available in one functional version, namely, N1.
8.4.2 Functions and Features
The D34S receives and transmits 6xE3/T3 electrical signals. The D34S must work with the PD3
or PQ3.
8.4.3 Working Principle and Signal Flow
The D34S consists of the interface module, switch matrix module, and power access circuit.
8.4.4 Front Panel
The front panel of the D34S has interfaces and a bar code.
8.4.5 Valid Slots
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Hardware Description

The D34S can be installed in slots 2140 in the subrack.


8.4.6 Technical Specifications
The technical specifications of the D34S include the parameters specified for electrical
interfaces, mechanical specifications, and power consumption.

8.4.1 Version Description


The D34S is available in one functional version, namely, N1.

8.4.2 Functions and Features


The D34S receives and transmits 6xE3/T3 electrical signals. The D34S must work with the PD3
or PQ3.

8.4.3 Working Principle and Signal Flow


The D34S consists of the interface module, switch matrix module, and power access circuit.
Figure 8-7 shows the functional block diagram of the D34S by describing how to process 1xE3/
T3 signals.
Figure 8-7 Functional block diagram of the D34S
Backplane
Cross-connect board
E3/T3 electrical
signal

Interface
module

Switch
matrix
module

+3.3 V

Fuse

E3/T3 electrical
signal

PD3/PQ3
TSB8
TSB8
PD3/PQ3

+3.3 V power

Interface Module
The interface module receives and transmits the E3/T3 electrical signals.

Switch Matrix Module


In the receive direction, the switch matrix module receives the signal sent from the interface
module and selects the output direction of the signal according to the TPS protection control
signal sent from the cross-connect board. When the TPS is not performed, the switch matrix
module transmits the signal to the PD3 or PQ3. When the TPS is performed, the switch matrix
module transmits the signal to the TSB8 for bridging.
In the transmit direction, the switch matrix module performs the reverse process.
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Power Access Circuit


The power access circuit provides all the modules of the D34S with the required DC voltages.

8.4.4 Front Panel


The front panel of the D34S has interfaces and a bar code.

Diagram of the Front Panel


Figure 8-8 shows the appearance of the front panel of the D34S.
Figure 8-8 Front panel of the D34S

D34S

OUT1
IN1
OUT2
IN2
OUT3
IN3
OUT4
IN4
OUT5
IN5
OUT6
IN6

D34S

Interfaces
The front panel of the D34S has six pairs of electrical interfaces.
Table 8-13 describes the types and usage of the interfaces of the D34S.
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Table 8-13 Interfaces of the D34S


Interface

Type of
Interface

Usage

IN1IN6

SMB

Receives the 1st to the 6th channels of E3/T3


electrical signals.

OUT1OUT6

SMB

Transmits the 1st to the 6th channels of E3/T3


electrical signals.

8.4.5 Valid Slots


The D34S can be installed in slots 2140 in the subrack.

8.4.6 Technical Specifications


The technical specifications of the D34S include the parameters specified for electrical
interfaces, mechanical specifications, and power consumption.

Parameters Specified for Electrical Interfaces


Table 8-14 lists the parameters specified for the electrical interfaces of the D34S.
Table 8-14 Parameters specified for the electrical interfaces of the D34S
Parameter

Value

Nominal bit rate

34368 kbit/s and 44736 kbit/s

Line code pattern

HDB3 (E3) and B3ZS (T3)

Signal bit rate at the output interface

Complies with ITU-T G.703.

Allowed frequency deviation at the input


interface
Allowed attenuation at the input
interface
Input jitter tolerance

Mechanical Specifications
The mechanical specifications of the D34S are as follows:
l

Dimensions (mm): 22 (W) x 110 (D) x 262.05 (H)

Weight (kg): 0.4

Power Consumption
At room temperature (25C), the maximum power consumption of the D34S is 0 W.
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8.5 C34S
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the C34S (3xE3/T3 switching access board).
8.5.1 Version Description
The C34S is available in one functional version, namely, N1.
8.5.2 Functions and Features
The C34S receives and transmits 3xE3/T3 electrical signals. The C34S must work with the PL3.
8.5.3 Working Principle and Signal Flow
The C34S consists of the interface module, switch matrix module, and power access circuit.
8.5.4 Front Panel
The front panel of the C34S has interfaces and a bar code.
8.5.5 Valid Slots
The C34S can be installed in slots 21, 23, 25, 27, 29, 31, 33, 35, 37, and 39 in the subrack and
works as the interface board of the PL3.
8.5.6 Technical Specifications
The technical specifications of the C34S include the parameters specified for electrical
interfaces, mechanical specifications, and power consumption.

8.5.1 Version Description


The C34S is available in one functional version, namely, N1.

8.5.2 Functions and Features


The C34S receives and transmits 3xE3/T3 electrical signals. The C34S must work with the PL3.

8.5.3 Working Principle and Signal Flow


The C34S consists of the interface module, switch matrix module, and power access circuit.
Figure 8-9 shows the functional block diagram of the C34S by describing how to process 1xE3/
T3 signals.
Figure 8-9 Functional block diagram of the C34S
Backplane
Cross-connect board
E3/T3 electrical
signal

Interface
module

Switch
matrix
module

E3/T3 electrical
signal
+3.3 V

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PL3
TSB4/TSB8
TSB4/TSB8
PL3

+3.3 V power

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Hardware Description

Interface Module
The interface module receives and transmits the E3/T3 electrical signals.

Switch Matrix Module


In the receive direction, the switch matrix module receives the signal sent from the interface
module and selects the output direction of the signal according to the TPS protection control
signal sent from the cross-connect board. When the TPS is not performed, the switch matrix
module transmits the signal to the PL3. When the TPS is performed, the switch matrix module
transmits the signal to the TSB4 or TSB8 for bridging.
In the transmit direction, the switch matrix module performs the reverse process.

Power Access Circuit


The power access circuit provides all the modules of the C34S with the required DC voltages.

8.5.4 Front Panel


The front panel of the C34S has interfaces and a bar code.

Diagram of the Front Panel


Figure 8-10 shows the appearance of the front panel of the C34S.

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Figure 8-10 Front panel of the C34S

C34S

OUT1
IN1
OUT2
IN2
OUT3
IN3

C34S

Interfaces
The front panel of the C34S has three pairs of electrical interfaces.
Table 8-15 describes the type and usage of the interface of the C34S.
Table 8-15 Interfaces of the C34S

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Interface

Type of Interface

Usage

IN1IN3

SMB

Receives the 1st to the 3rd channels of E3/T3


electrical signals.

OUT1OUT3

SMB

Transmits the 1st to the 3rd channels of E3/T3


electrical signals.

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8.5.5 Valid Slots


The C34S can be installed in slots 21, 23, 25, 27, 29, 31, 33, 35, 37, and 39 in the subrack and
works as the interface board of the PL3.
Table 8-16 lists the slots valid for the PL3 and the corresponding slots for the C34S.
Table 8-16 Slots valid for the PL3 and the corresponding slots for the C34S
Slot Valid for the PL3

Corresponding Slot for the C34S

Slot 3

Slot 21

Slot 4

Slot 23

Slot 5

Slot 25

Slot 6

Slot 27

Slot 7

Slot 29

Slot 8

Slot 31

Slot 13

Slot 33

Slot 14

Slot 35

Slot 15

Slot 37

slot 16

Slot 39

8.5.6 Technical Specifications


The technical specifications of the C34S include the parameters specified for electrical
interfaces, mechanical specifications, and power consumption.

Parameters Specified for Electrical Interfaces


Table 8-17 lists the parameters specified for the electrical interfaces of the C34S.
Table 8-17 Parameters specified for the electrical interfaces of the C34S
Parameter

Value

Nominal bit rate

34368 kbit/s and 44736 kbit/s

Line code pattern

HDB3 (E3) and B3ZS (T3)

Signal bit rate at the output


interface

Complies with ITU-T G.703.

Allowed frequency
deviation at the input
interface
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Parameter

8 Interface Boards and Switching and Bridging Boards

Value

Allowed attenuation at the


input interface
Input jitter tolerance

Mechanical Specifications
The mechanical specifications of the C34S are as follows:
l

Dimensions (mm): 22 (W) x 110 (D) x 262.05 (H)

Weight (kg): 0.3

Power Consumption
At room temperature (25C), the maximum power consumption of the C34S is 0 W.

8.6 EU04
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the EU04 (4xSTM-1 electrical interface board).
8.6.1 Version Description
The EU04 is available in one functional version, namely, N1.
8.6.2 Functions and Features
The EU04 receives and transmits 4xSTM-1 electrical signals. The EU04 must work with the
SEP.
8.6.3 Working Principle and Signal Flow
The EU04 consists of the interface module, switch matrix module, and power module.
8.6.4 Front Panel
The front panel of the EU04 has interfaces and a bar code.
8.6.5 Valid Slots
The EU04 can be installed in slots 21, 23, 25, 27, 29, 31, 33, 35, 37, and 39 in the subrack and
works as the interface board of the SEP.
8.6.6 Technical Specifications
The technical specifications of the EU04 include the parameters specified for electrical
interfaces, mechanical specifications, and power consumption.

8.6.1 Version Description


The EU04 is available in one functional version, namely, N1.

8.6.2 Functions and Features


The EU04 receives and transmits 4xSTM-1 electrical signals. The EU04 must work with the
SEP.
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8.6.3 Working Principle and Signal Flow


The EU04 consists of the interface module, switch matrix module, and power module.
Figure 8-11 shows the functional block diagram of the EU04 by describing how to process
1xSTM-1 signals.
Figure 8-11 Functional block diagram of the EU04
Backplane
Cross-connect board
STM-1 electrical
signal

Interface
module

Switch
matrix
module

STM-1 electrical
signal

+3.3 V

Power
module

Fuse

SEP
TSB4/TSB8
TSB4/TSB8
SEP

+3.3 V power

Interface Module
The interface module receives and transmits the STM-1 electrical signals.

Switch Matrix Module


In the receive direction, the switch matrix module receives the signal sent from the interface
module and selects the output direction of the signal according to the TPS protection control
signal sent from the cross-connect board. When the TPS is not performed, the switch matrix
module transmits the signal to the SEP. When the TPS is performed, the switch matrix module
transmits the signal to the TSB4 or TSB8 for bridging.
In the transmit direction, the switch matrix module performs the reverse process.

Power Module
The power module provides all the modules of the EU04 with the required DC voltages.

8.6.4 Front Panel


The front panel of the EU04 has interfaces and a bar code.

Diagram of the Front Panel


Figure 8-12 shows the appearance of the front panel of the EU04.
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Figure 8-12 Front panel of the EU04

EUO4

OUT1
IN1
OUT2
IN2
OUT3
IN3
OUT4
IN4

EUO4

Interfaces
The front panel of the EU04 has four pairs of electrical interfaces.
Table 8-18 describes the types and usage of the interfaces of the EU04.
Table 8-18 Interfaces of the EU04

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Interface

Type of Interface

Usage

IN1IN4

SMB

Receives the 1st to the 4th channels of STM-1


electrical signals.

OUT1OUT4

SMB

Transmits the 1st to the 4th channels of STM-1


electrical signals.

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8.6.5 Valid Slots


The EU04 can be installed in slots 21, 23, 25, 27, 29, 31, 33, 35, 37, and 39 in the subrack and
works as the interface board of the SEP.
Table 8-19 lists the slots valid for the SEP and the corresponding slots for the EU04.
Table 8-19 Slots valid for the SEP and the corresponding slots for the EU04
Slot Valid for the SEP

Corresponding Slot for the EU04

Slot 3

Slot 21

Slot 4

Slot 23

Slot 5

Slot 25

Slot 6

Slot 27

Slot 7

Slot 29

Slot 12

Slot 31

Slot 13

Slot 33

Slot 14

Slot 35

Slot 15

Slot 37

Slot 16

Slot 39

8.6.6 Technical Specifications


The technical specifications of the EU04 include the parameters specified for electrical
interfaces, mechanical specifications, and power consumption.

Parameters Specified for Electrical Interfaces


Table 8-20 lists the parameters specified for the electrical interfaces of the EU04.
Table 8-20 Parameters specified for the electrical interfaces of the EU04
Parameter

Value

Nominal bit rate

155520 kbit/s

Line code pattern

CMI

Signal bit rate at the output interface

Complies with ITU-T G.703.

Allowed frequency deviation at the input


interface
Allowed attenuation at the input interface

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Mechanical Specifications
The mechanical specifications of the EU04 are as follows:
l

Dimensions (mm): 22 (W) x 110 (D) x 262.05 (H)

Weight (kg): 0.4

Power Consumption
The maximum power consumption of the EU04 at room temperature (25C) is 6 W.

8.7 EU08
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the EU08 (8xSTM-1 electrical interface board).
8.7.1 Version Description
The EU08 is available in one functional version, namely, N1.
8.7.2 Functions and Features
The EU08 receives and transmits 8xSTM-1 electrical signals. The EU08 must work with the
SLH1B or SEP1.
8.7.3 Working Principle and Signal Flow
The EU08 consists of the interface module, switch matrix module, and power module.
8.7.4 Front Panel
The front panel of the EU08 has interfaces and a bar code.
8.7.5 Valid Slots
The EU08 can be installed in slots 2140 in the subrack and works as the interface board of the
SLH1B or SEP1.
8.7.6 Technical Specifications
The technical specifications of the EU08 include the parameters specified for electrical
interfaces, mechanical specifications, and power consumption.

8.7.1 Version Description


The EU08 is available in one functional version, namely, N1.

8.7.2 Functions and Features


The EU08 receives and transmits 8xSTM-1 electrical signals. The EU08 must work with the
SLH1B or SEP1.

8.7.3 Working Principle and Signal Flow


The EU08 consists of the interface module, switch matrix module, and power module.
Figure 8-13 shows the functional block diagram of the EU08.

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Figure 8-13 Functional block diagram of the EU08


Backplane
Cross-connect board
STM-1 electrical
signal

Interface
module

Switch
matrix
module

STM-1 electrical
signal
+3.3 V

Power
module

Fuse

SEP/SLH1
TSB8
TSB8
SEP/SLH1

+3.3 V power

Interface Module
The interface module receives and transmits the STM-1 electrical signals.

Switch Matrix Module


In the receive direction, the switch matrix module receives the signal sent from the interface
module and selects the output direction of the signal according to the TPS protection control
signal sent from the cross-connect board. When the TPS is not performed, the switch matrix
module transmits the signal to the SLH1B or SEP1. When the TPS is performed, the switch
matrix module transmits the signal to the TSB8 for bridging.
In the transmit direction, the switch matrix module performs the reverse process.

Power Module
The power module provides all the modules of the EU08 with the required DC voltages.

8.7.4 Front Panel


The front panel of the EU08 has interfaces and a bar code.

Diagram of the Front Panel


Figure 8-14 shows the appearance of the front panel of the EU08.

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Figure 8-14 Front panel of the EU08

EUO8
OUT1
IN1
OUT2
IN2
OUT3
IN3
OUT4
IN4
OUT5
IN5
OUT6
IN6
OUT7
IN7
OUT8
IN8

EUO8

Interfaces
The front panel of the EU08 has eight pairs of electrical interfaces.
Table 8-21 describes the types and usage of the interfaces of the EU08.
Table 8-21 Interfaces of the EU08

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Interface

Type of
Interface

Usage

IN1IN8

SMB

Receives the 1st to the 8th channels of STM-1


electrical signals.

OUT1OUT8

SMB

Transmits the 1st to the 8th channels of STM-1


electrical signals.

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8.7.5 Valid Slots


The EU08 can be installed in slots 2140 in the subrack and works as the interface board of the
SLH1B or SEP1.
Table 8-22 lists the slots valid for the SLH1B and the corresponding slots for the EU08. The
EU08 installed in the slot with a smaller number accesses the 1st to the 8th channels of STM-1
electrical signals. The EU08 installed in the slot with a larger number accesses the 9th to the
16th channels of STM-1 electrical signals.
Table 8-22 Slots valid for the SLH1B and the corresponding slots for the EU08
Slot Valid for the SLH1B

Corresponding Slot for the EU08

Slot 3

Slots 21 and 22

Slot 4

Slots 23 and 24

Slot 5

Slots 25 and 26

Slot 6

Slots 27 and 28

Slot 7

Slots 29 and 30

Slot 12

Slots 31 and 32

Slot 13

Slots 33 and 34

Slot 14

Slots 35 and 36

Slot 15

Slots 37 and 38

Slot 16

Slots 39 and 40

Table 8-23 lists the slots valid for the SEP and the corresponding slots for the EU08.
Table 8-23 Slots valid for the SEP and the corresponding slots for the EU08

8-32

Slot Valid for the SEP

Corresponding Slot for the EU08

Slot 3

Slot 21

Slot 4

Slot 23

Slot 5

Slot 25

Slot 6

Slot 27

Slot 7

Slot 29

Slot 12

Slot 31

Slot 13

Slot 33

Slot 14

Slot 35

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Slot Valid for the SEP

Corresponding Slot for the EU08

Slot 15

Slot 37

Slot 16

Slot 39

8.7.6 Technical Specifications


The technical specifications of the EU08 include the parameters specified for electrical
interfaces, mechanical specifications, and power consumption.

Parameters Specified for Electrical Interfaces


Table 8-24 lists the parameters specified for the electrical interfaces of the EU08.
Table 8-24 Parameters specified for the electrical interfaces of the EU08
Parameter

Value

Nominal bit rate

155520 kbit/s

Line code pattern

CMI

Signal bit rate at the


output interface

Complies with ITU-T G.703.

Allowed frequency
deviation at the input
interface
Allowed attenuation at
the input interface
Input jitter tolerance

Mechanical Specifications
The mechanical specifications of the EU08 are as follows:
l

Dimensions (mm): 22 (W) x 110 (D) x 262.05 (H)

Weight (kg): 0.4

Power Consumption
The maximum power consumption of the EU08 at room temperature (25C) is 11 W.

8.8 OU08
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the OU08 (8xSTM-1 optical interface board).
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8.8.1 Version Description


The OU08 is available in two functional versions, namely, N1 and N2. The difference between
the two versions is with regard to the connector type for the optical interfaces and whether the
optical module is swappable.
8.8.2 Functions and Features
The OU08 receives and transmits 8xSTM-1 optical signals. The OU08 must work with the SLH1
or SLH1B or SEP1.
8.8.3 Working Principle and Signal Flow
The OU08 consists of the interface module and power module.
8.8.4 Front Panel
The front panel of the OU08 has interfaces and a bar code.
8.8.5 Valid Slots
The OU08 can be installed in slots 2140 in the subrack and works as the interface board of the
SLH1B or SEP1.
8.8.6 Technical Specifications
The technical specifications of the OU08 include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.

8.8.1 Version Description


The OU08 is available in two functional versions, namely, N1 and N2. The difference between
the two versions is with regard to the connector type for the optical interfaces and whether the
optical module is swappable.
Table 8-25 describes the versions of the OU08.
Table 8-25 Versions of the OU08
Item

Description

Functional
versions

The OU08 is available in two functional versions, namely, N1 and


N2.

Common points

The working principle of the N1OU08 is the same as the working


principle of the N2OU08.

Differences

The optical interface of the N1OU08 uses the LC connector, whereas


the optical interface of the N2OU08 uses the SC connector. The
N1OU08 uses the swappable optical module, whereas the N2OU08
does not use the swappable optical module.

Substitution

None.

8.8.2 Functions and Features


The OU08 receives and transmits 8xSTM-1 optical signals. The OU08 must work with the SLH1
or SLH1B or SEP1.

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8.8.3 Working Principle and Signal Flow


The OU08 consists of the interface module and power module.
Figure 8-15 shows the functional block diagram of the OU08.
Figure 8-15 Functional block diagram of the OU08
Backplane
STM-1 optical
signal

SEP/SLH1

Interface
module

STM-1 optical
signal

SEP/SLH1

+3.3 V

Power
module

Fuse

+3.3 V power

Interface Module
In the receive direction, the interface module performs O/E conversion for the STM-1 signals
and transmits the signals to the SLH1 or SLH1B or SEP1.
In the transmit direction, the interface module performs E/O conversion for the STM-1 signals
and transmits the signals to the optical interface.

Power Module
The power module provides all the modules of the OU08 with the required DC voltages.

8.8.4 Front Panel


The front panel of the OU08 has interfaces and a bar code.

Diagram of the Front Panel


Figure 8-16 shows the appearance of the front panel of the N1OU08.Figure 8-17 shows the
appearance of the front panel of the N2OU08.

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Figure 8-16 Front panel of the N1OU08

OU08

OUT1 IN1
OUT2 IN2
OUT3 IN3
OUT4 IN4
OUT5 IN5
OUT6 IN6
OUT7 IN7
OUT8 IN8
CLASS 1
LASER
PRODUCT

OU08

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Figure 8-17 Front panel of the N2OU08

OU08
OUT1
IN1
OUT2
IN2
OUT3
IN3
OUT4
IN4
OUT5
IN5
OUT6
IN6
OUT7
IN7
OUT8
IN8

OU08

Interfaces
The front panel of the N1OU08/N2OU08 has eight optical interfaces.
Table 8-26 describes the types and usage of the interfaces of the N1OU08. Table 8-27 describes
the types and usage of the interfaces of the N2OU08.
Table 8-26 Interfaces of the N1OU08

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Interface

Type of
Interface

Usage

IN1IN8

LC

Receives the 1st to the 8th channels of STM-1


optical signals.

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Interface

Type of
Interface

Usage

OUT1OUT8

LC

Transmits the 1st to the 8th channels of STM-1


optical signals.

Table 8-27 Interfaces of the N2OU08


Interface

Type of
Interface

Usage

IN1IN8

SC

Receives the 1st to the 8th channels of STM-1


optical signals.

OUT1OUT8

SC

Transmits the 1st to the 8th channels of STM-1


optical signals.

8.8.5 Valid Slots


The OU08 can be installed in slots 2140 in the subrack and works as the interface board of the
SLH1B or SEP1.
Table 8-28 lists the slots valid for the SLH1B and the corresponding slots for the OU08. The
OU08 installed in the slot with a smaller number accesses the 1st to the 8th channels of STM-1
optical signals. The OU08 installed in the slot with a larger number accesses the 9th to the 16th
channels of STM-1 optical signals.
Table 8-28 Slots valid for the SLH1B and the corresponding slots for the OU08

8-38

Slot Valid for the SLH1B

Corresponding Slot for the OU08

Slot 3

Slots 21 and 22

Slot 4

Slots 23 and 24

Slot 5

Slots 25 and 26

Slot 6

Slots 27 and 28

Slot 7

Slots 29 and 30

Slot 12

Slots 31 and 32

Slot 13

Slots 33 and 34

Slot 14

Slots 35 and 36

Slot 15

Slots 37 and 38

Slot 16

Slots 39 and 40

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Table 8-29 lists the slots valid for the SEP1 and the corresponding slots for the OU08.
Table 8-29 Slots valid for the SEP1 and the corresponding slots for the OU08
Slot Valid for the SEP1

Corresponding Slot for the OU08

Slot 3

Slot 21

Slot 4

Slot 23

Slot 5

Slot 25

Slot 6

Slot 27

Slot 7

Slot 29

Slot 12

Slot 31

Slot 13

Slot 33

Slot 14

Slot 35

Slot 15

Slot 37

Slot 16

Slot 39

8.8.6 Technical Specifications


The technical specifications of the OU08 include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.

Parameters Specified for Optical Interfaces


Table 8-30 lists the parameters specified for the optical interfaces of the OU08.
Table 8-30 Parameters specified for the optical interfaces of the OU08

Issue 02 (2009-07-30)

Parameter

Value

Nominal bit rate

155520 kbit/s

Line code pattern

NRZ

Application code

S-1.1

Operating wavelength
range (nm)

N1OU08: 1260-1360

Type of fiber

Single-mode LC

Mean launched optical


power (dBm)

-15 to -8

Receiver sensitivity
(dBm)

-28

N2OU08: 1261-1360

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Laser Safety Class


The safety class of the laser on the board is Class 1. The maximum launched optical power of
the optical interfaces is less than 10 dBm (10 mW).

Mechanical Specifications
The mechanical specifications of the OU08 are as follows:
l

Dimensions (mm): 22 (W) x 110 (D) x 262.05 (H)

Weight (kg): 0.4

Power Consumption
The maximum power consumption of the OU08 at room temperature (25C) is 6 W.

8.9 MU04
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the MU04 (4xE4/STM-1 electrical interface board).
8.9.1 Version Description
The MU04 is available in one functional version, namely, N1.
8.9.2 Functions and Features
The MU04 receives and transmits 4xE4/STM-1 electrical signals. The MU04 must work with
the SPQ4.
8.9.3 Working Principle and Signal Flow
The MU04 consists of the interface module, switch matrix module, and power module.
8.9.4 Front Panel
The front panel of the MU04 has interfaces and a bar code.
8.9.5 Valid Slots
The MU04 can be installed in slots 21, 23, 25, 27, 29, 31, 33, 35, 37, and 39 in the subrack and
works as the interface board of the SPQ4.
8.9.6 Technical Specifications
The technical specifications of the MU04 include the parameters specified for electrical
interfaces, mechanical specifications, and power consumption.

8.9.1 Version Description


The MU04 is available in one functional version, namely, N1.

8.9.2 Functions and Features


The MU04 receives and transmits 4xE4/STM-1 electrical signals. The MU04 must work with
the SPQ4.

8.9.3 Working Principle and Signal Flow


The MU04 consists of the interface module, switch matrix module, and power module.
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Figure 8-18 shows the functional block diagram of the MU04 by describing how to process
1xE4/STM-1 signals.
Figure 8-18 Functional block diagram of the MU04
Backplane
Cross-connect board
E4/STM-1 electrical
signal
Interface
module
E4/STM-1 electrical
signal
+3.3 V

Switch
matrix
module

Power
module

Fuse

SPQ4
TSB4/TSB8
TSB4/TSB8
SPQ4

+3.3 V power

Interface Module
The interface module receives and transmits the E4/STM-1 electrical signals.

Switch Matrix Module


In the receive direction, the switch matrix module receives the signal sent from the interface
module and selects the output direction of the signal according to the TPS protection control
signal sent from the cross-connect board. When the TPS is not performed, the switch matrix
module transmits the signal to the SPQ4. When the TPS is performed, the switch matrix module
transmits the signal to the TSB4 or TSB8 for bridging.
In the transmit direction, the switch matrix module performs the reverse process.

Power Module
The power module provides all the modules of the MU04 with the required DC voltages.

8.9.4 Front Panel


The front panel of the MU04 has interfaces and a bar code.

Diagram of the Front Panel


Figure 8-19 shows the appearance of the front panel of the MU04.

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Figure 8-19 Front panel of the MU04

MUO4

OUT1
IN1
OUT2
IN2
OUT3
IN3
OUT4
IN4

MUO4

Interfaces
The front panel of the MU04 has four pairs of electrical interfaces.
Table 8-31 describes the types and usage of the interfaces of the MU04.
Table 8-31 Interfaces of the MU04

8-42

Interface

Type of
Interface

Usage

IN1IN4

SMB

Receives the 1st to the 4th channels of E4/STM-1


electrical signals.

OUT1OUT4

SMB

Transmits the 1st to the 4th channels of E4/STM-1


electrical signals.

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8.9.5 Valid Slots


The MU04 can be installed in slots 21, 23, 25, 27, 29, 31, 33, 35, 37, and 39 in the subrack and
works as the interface board of the SPQ4.
Table 8-32 lists the slots valid for the SPQ4 and the corresponding slots for the MU04.
Table 8-32 Slots valid for the SPQ4 and the corresponding slots for the MU04
Slot Valid for the SPQ4

Corresponding Slot for the MU04

Slot 3

Slot 21

Slot 4

Slot 23

Slot 5

Slot 25

Slot 6

Slot 27

Slot 7

Slot 29

Slot 12

Slot 31

Slot 13

Slot 33

Slot 14

Slot 35

Slot 15

Slot 37

Slot 16

Slot 39

8.9.6 Technical Specifications


The technical specifications of the MU04 include the parameters specified for electrical
interfaces, mechanical specifications, and power consumption.

Parameters Specified for Electrical Interfaces


Table 8-33 lists the parameters specified for the electrical interfaces of the MU04.
Table 8-33 Parameters specified for the electrical interfaces of the MU04
Parameter

Value

Nominal bit rate

139264 kbit/s and 155520 kbit/s

Line code pattern

CMI

Signal bit rate at the output


interface

Complies with ITU-T G.703.

Allowed frequency
deviation at the input
interface
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Parameter

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Hardware Description

Value

Allowed attenuation at the


input interface

Mechanical Specifications
The mechanical specifications of the MU04 are as follows:
l

Dimensions (mm): 22 (W) x 110 (D) x 262.05 (H)

Weight (kg): 0.4

Power Consumption
The maximum power consumption of the MU04 at room temperature (25C) is 2 W.

8.10 TSB4
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the TSB4 (4-channel electrical interface protection switching board).
8.10.1 Version Description
The TSB4 is available in one functional version, namely, N1.
8.10.2 Functions and Features
The TSB4 is used to provide the TPS protection.
8.10.3 Working Principle and Signal Flow
The TSB4 consists of the switch matrix module and power module.
8.10.4 Front Panel
The front panel of the TSB4 has a bar code.
8.10.5 Valid Slots
When the TSB4 works with different processing boards and interface boards to realize the TPS
protection, the TSB4 can be installed in different slots.
8.10.6 Technical Specifications
The technical specifications of the TSB4 include the mechanical specifications and power
consumption.

8.10.1 Version Description


The TSB4 is available in one functional version, namely, N1.

8.10.2 Functions and Features


The TSB4 is used to provide the TPS protection.
The TSB4 can work with the MU04, C34S, or EU04 to realize the TPS protection on different
processing boards.
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The TSB4 can work with the MU04 to realize the TPS protection on the SPQ4.

The TSB4 can work with the C34S to realize the TPS protection on the PL3.

The TSB4 can work with the EU04 to realize the TPS protection on the SEP.

8.10.3 Working Principle and Signal Flow


The TSB4 consists of the switch matrix module and power module.
Figure 8-20 shows the functional block diagram of the TSB4.
Figure 8-20 Functional block diagram of the TSB4
Backplane

Backplane
Cross-connect board

Interface board 1
Interface board 2

Standby processing board

Interface board 3
Switch matrix
module
+3.3 V

Power
module

Fuse

+3.3 V backup power

Switch Matrix Module


In the receive direction, the switch matrix module selects signals from one of the three interface
boards according to the TPS protection control signal sent from the cross-connect board, and
transmits the signals to the standby processing board.
In the transmit direction, the switch matrix module performs the reverse process.

Power Module
The power module provides all the modules of the TSB4 with the required DC voltages.

8.10.4 Front Panel


The front panel of the TSB4 has a bar code.

Diagram of the Front Panel


Figure 8-21 shows the appearance of the front panel of the TSB4.

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Figure 8-21 Front panel of the TSB4

TSB4

TSB4

8.10.5 Valid Slots


When the TSB4 works with different processing boards and interface boards to realize the TPS
protection, the TSB4 can be installed in different slots.
Table 8-34 lists the slots valid for the TSB4 and the corresponding slots for the SPQ4 and MU04.
Table 8-34 Slots valid for the TSB4 and the corresponding slots for the SPQ4 and MU04

8-46

Slot Valid for the TSB4

Slot Valid for the SPQ4

Corresponding Slot for the


MU04

Slot 21

Slot 4

Slot 23

Slot 5

Slot 25

Slot 6

Slot 27

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Slot Valid for the TSB4

Slot Valid for the SPQ4

Corresponding Slot for the


MU04

Slot 39

Slot 13

Slot 33

Slot 14

Slot 35

Slot 15

Slot 37

Table 8-35 lists the slots valid for the TSB4 and the corresponding slots for the SEP1 and EU04.
Table 8-35 Slots valid for the TSB4 and the corresponding slots for the SEP1 and EU04
Slot Valid for the TSB4

Slot Valid for the SEP1

Corresponding Slot for


the EU04

Slot 21

Slot 4

Slot 23

Slot 5

Slot 25

Slot 6

Slot 27

Slot 13

Slot 33

Slot 14

Slot 35

Slot 15

Slot 37

Slot 39

Table 8-36 lists the slots valid for the TSB4 and the corresponding slots for the PL3 and C34S.
Table 8-36 Slots valid for the TSB4 and the corresponding slots for the PL3 and C34S
Slot Valid for the TSB4

Slot Valid for the PL3

Corresponding Slot for


the C34S

Slot 21

Slot 4

Slot 23

Slot 5

Slot 25

Slot 6

Slot 27

Slot 13

Slot 33

Slot 14

Slot 35

Slot 15

Slot 37

Slot 39

8.10.6 Technical Specifications


The technical specifications of the TSB4 include the mechanical specifications and power
consumption.
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Mechanical Specifications
The mechanical specifications of the TSB4 are as follows:
l

Dimensions (mm): 22 (W) x 110 (D) x 262.05 (H)

Weight (kg): 0.3

Power Consumption
The maximum power consumption of the TSB4 at room temperature (25C) is 3 W.

8.11 TSB8
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the TSB8 (8-channel electrical interface protection switching board).
8.11.1 Version Description
The TSB8 is available in one functional version, namely, N1.
8.11.2 Functions and Features
The TSB8 is used to provide the TPS protection.
8.11.3 Working Principle and Signal Flow
The TSB8 consists of the switch matrix module and power module.
8.11.4 Front Panel
The front panel of the TSB8 has a bar code.
8.11.5 Valid Slots
The TSB8 can be installed in slots 21, 22, 39, and 40 in the subrack
8.11.6 Technical Specifications
The technical specifications of the TSB8 include the mechanical specifications and power
consumption.

8.11.1 Version Description


The TSB8 is available in one functional version, namely, N1.

8.11.2 Functions and Features


The TSB8 is used to provide the TPS protection.
The TSB8 can work with the MU04, C34S, D34S, EU04,, EU08, or ETS8 to realize the TPS
protection on different processing boards.

8-48

The TSB8 can work with the MU04 to realize the TPS protection on the SPQ4.

The TSB8 can work with the C34S to realize the TPS protection on the PL3.

The TSB8 can work with the D34S to realize the TPS protection on the PD3.

The TSB8 can work with the D34S to realize the TPS protection on the PQ3.

The TSB8 can work with the EU04 to realize the TPS protection on the SEP1.
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The TSB8 can work with the EU08 to realize the TPS protection on the SLH1B/SEP1.

The TSB8 can work with the ETS8 to realize the TPS protection on the EFS0.

8.11.3 Working Principle and Signal Flow


The TSB8 consists of the switch matrix module and power module.
Figure 8-22 shows the functional block diagram of the TSB8 by describing how to process one
channel of signals.
Figure 8-22 Functional block diagram of the TSB8
Backplane

Backplane
Cross-connect board

Interface board 1
Interface board 2

Standby processing board

Interface board 3
Switch matrix
module
+3.3 V

Power
module

Fuse

+3.3 V backup power

Switch Matrix Module


In the receive direction, the switch matrix module selects signals from one of the three interface
boards according to the TPS protection control signal sent from the cross-connect board, and
transmits the signals to the standby processing board.
In the transmit direction, the switch matrix module performs the reverse process.

Power Module
The power module provides all the modules of the TSB8 with the required DC voltages.

8.11.4 Front Panel


The front panel of the TSB8 has a bar code.

Diagram of the Front Panel


Figure 8-23 shows the appearance of the front panel of the TSB8.

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Figure 8-23 Front panel of the TSB8

TSB8

TSB8

8.11.5 Valid Slots


The TSB8 can be installed in slots 21, 22, 39, and 40 in the subrack
Table 8-37 lists the slots valid for the TSB8 and the corresponding slots for the SPQ4 and MU04.
Table 8-37 Slots valid for the TSB8 and the corresponding slots for the SPQ4 and MU04

8-50

Slot Valid for the TSB8

Slot Valid for the SPQ4

Corresponding Slot for the


MU04

Slots 21

Slot 4

Slot 23

Slot 5

Slot 25

Slot 6

Slot 27

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Slot Valid for the TSB8

Slot Valid for the SPQ4

Corresponding Slot for the


MU04

Slots 39

Slot 13

Slot 33

Slot 14

Slot 35

Slot 15

Slot 37

Table 8-38 lists the slots valid for the TSB8 and the corresponding slots for the PL3 and C34S.
Table 8-38 Slots valid for the TSB8 and the corresponding slots for the PL3 and C34S
Slot Valid for the TSB8

Slot Valid for the PL3

Corresponding Slot for


the C34S

Slots 21

Slot 4

Slot 23

Slot 5

Slot 25

Slot 6

Slot 27

Slot 13

Slot 33

Slot 14

Slot 35

Slot 15

Slot 37

Slots 39

Table 8-39 lists the slots valid for the TSB8 and the corresponding slots for the PD3 and D34S.
Table 8-39 Slots valid for the TSB8 and the corresponding slots for the PD3 and D34S
Slot Valid for the TSB8

Slot Valid for the PD3

Corresponding Slot for


the D34S

Slots 21

Slot 4

Slot 23

Slot 5

Slot 25

Slot 6

Slot 27

Slot 13

Slot 33

Slot 14

Slot 35

Slot 15

Slot 37

Slots 39

Table 8-40 lists the slots valid for the TSB8 and the corresponding slots for the PQ3 and D34S.

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Table 8-40 Slots valid for the TSB8 and the corresponding slots for the PQ3 and D34S
Slot Valid for the TSB8

Slot Valid for the PQ3

Corresponding Slot for


the D34S

Slots 21 and 22

Slots 46

Slots 2328

Slots 39 and 40

Slots 1315

Slots 3338

Table 8-41 lists the slots valid for the TSB8 and the corresponding slots for the SEP1 and EU04.
Table 8-41 Slots valid for the TSB8 and the corresponding slots for the SEP1 and EU04
Slot Valid for the TSB8

Slot Valid for the SEP1

Corresponding Slot for


the EU04

Slots 21

Slot 4

Slot 23

Slot 5

Slot 25

Slot 6

Slot 27

Slot 13

Slot 33

Slot 14

Slot 35

Slot 15

Slot 37

Slots 39

Table 8-42 lists the slots valid for the TSB8 and the corresponding slots for the SEP1 and EU08.
Table 8-42 Slots valid for the TSB8 and the corresponding slots for the SEP1 and EU08
Slot Valid for the TSB8

Slot Valid for the SEP1

Corresponding Slot for


the EU08

Slots 21

Slot 4

Slot 23

Slot 5

Slot 25

Slot 6

Slot 27

Slot 13

Slot 33

Slot 14

Slot 35

Slot 15

Slot 37

Slots 39

Table 8-43 lists the slots valid for the TSB8 and the corresponding slots for the SLH1B and
EU08.

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Table 8-43 Slots valid for the TSB8 and the corresponding slots for the SLH1B and EU08
Slot Valid for the TSB8

Slot Valid for the SLH1B

Corresponding Slot for


the EU08

Slots 21 and 22

Slot 4

Slot 23 and 24

Slot 5

Slot 25 and 26

Slot 6

Slot 27 and 28

Slot 13

Slot 33 and 34

Slot 14

Slot 35 and 36

Slot 15

Slot 37 and 38

Slots 39 and 40

NOTE

The SEP1 is displayed as SEP or SEP1 on the T2000. When the interfaces are available on the front panel
of the SEP1, the SEP1 is displayed as SEP1 on the T2000. When the SEP1 works with the interface board
to realize the TPS protection, the SEP1 is displayed as SEP on the T2000.

Table 8-44 lists the slots valid for the TSB8 and the corresponding slots for the EFS0 and ETS8.
Table 8-44 Slots valid for the TSB8 and the corresponding slots for the EFS0 and ETS8
Slot Valid for the TSB8

Slot Valid for the EFS0

Corresponding Slot for


the ETS8

Slots 21

Slot 4

Slot 23

Slot 5

Slot 25

Slot 6

Slot 27

Slot 13

Slot 33

Slot 14

Slot 35

Slot 15

Slot 37

Slots 39

8.11.6 Technical Specifications


The technical specifications of the TSB8 include the mechanical specifications and power
consumption.

Mechanical Specifications
The mechanical specifications of the TSB8 are as follows:
l

Dimensions (mm): 22 (W) x 110 (D) x 262.05 (H)

Weight (kg): 0.3

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Power Consumption
At room temperature (25C), the maximum power consumption of the TSB8 is 0 W.

8.12 EFF8
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the EFF8 (8x100M Ethernet optical interface board).
8.12.1 Version Description
The EFF8 is available in one functional version, namely, N1.
8.12.2 Functions and Features
The EFF8 receives and transmits 8x100M Ethernet optical signals. The EFF8 must work with
the Ethernet processing board.
8.12.3 Working Principle and Signal Flow
The EFF8 consists of the interface module and power module.
8.12.4 Front Panel
The front panel of the EFF8 has indicators, interfaces, a bar code, and a laser safety class label.
8.12.5 Valid Slots
The EFF8 can be installed in slots 21, 23, 25, 27, 29, 31, 33, 35, 37 and 39 in the subrack and
works as the interface board of the EFT8, EFS0 or EMR0. The EFF8 can be installed in slots
2140 in the subrack and works as the interface board of the EMS4.
8.12.6 Technical Specifications
The technical specifications of the EFF8 include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.

8.12.1 Version Description


The EFF8 is available in one functional version, namely, N1.

8.12.2 Functions and Features


The EFF8 receives and transmits 8x100M Ethernet optical signals. The EFF8 must work with
the Ethernet processing board.

8.12.3 Working Principle and Signal Flow


The EFF8 consists of the interface module and power module.
Figure 8-24 shows the functional block diagram of the EFF8 by describing how to process 1x100
Mbit/s Ethernet signals.

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Figure 8-24 Functional block diagram of the EFF8


Backplane

100 Mbit/s
Ethernet signal

EFT8/EFS0/EMS4/EMR0
Interface
module

100 Mbit/s
Ethernet signal

+3.3 V

EFT8/EFS0/EMS4/EMR0

Power
module

Fuse

+3.3 V backup power

Interface Module
In the receive direction, the interface module performs O/E conversion for the Ethernet signals
and transmits the signals to the EFT8, EFS0, EMS4, or EMR0.
In the transmit direction, the interface module performs E/O conversion for the Ethernet signals
and transmits the signals to the optical interface.

Power Module
The power module provides all the modules of the EFF8 with the required DC voltages.

8.12.4 Front Panel


The front panel of the EFF8 has indicators, interfaces, a bar code, and a laser safety class label.

Diagram of the Front Panel


Figure 8-25 shows the appearance of the front panel of the EFF8.

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Figure 8-25 Front panel of the EFF8

EFF8
1
2
3
4
5
6
7
8
LINK ACT

OUT1 IN1
OUT2 IN2
OUT3 IN3
OUT4 IN4
OUT5 IN5
OUT6 IN6
OUT7 IN7
OUT8 IN8
CLASS 1
LASER
PRODUCT

EFF8

Indicators
The front panel of the board has the following indicators:
l

Eight connection status indicators (LINK) one color (green)

Eight data receiving and transmission indicators (ACT) one color (orange)

For the meanings of the status of the indicators, see A Indicators.

Interfaces
The front panel of the EFF8 has eight optical interfaces.
Table 8-45 describes the types and usage of the interfaces of the EFF8.

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Table 8-45 Interfaces of the EFF8


Interface

Type of
Interface

Usage

IN1IN8

LC

Receives the 1st to the 8th channels of Ethernet


optical signals.

OUT1OUT8

LC

Transmits the 1st to the 8th channels of Ethernet


optical signals.

8.12.5 Valid Slots


The EFF8 can be installed in slots 21, 23, 25, 27, 29, 31, 33, 35, 37 and 39 in the subrack and
works as the interface board of the EFT8, EFS0 or EMR0. The EFF8 can be installed in slots
2140 in the subrack and works as the interface board of the EMS4.
Table 8-46 lists the slots valid for the EFT8/EFS0/EMR0 and the corresponding slots for the
EFF8.
Table 8-46 Slots valid for the EFT8/EFS0/EMR0 and the corresponding slots for the EFF8
Slot Valid for the EFT8/EFS0/EMR0

Corresponding Slot for the EFF8

Slot 3

Slots 21

Slot 4

Slots 23

Slot 5

Slots 25

Slot 6

Slots 27

Slot 7

Slots 29

Slot 12

Slots 31

Slot 13

Slots 33

Slot 14

Slots 35

Slot 15

Slots 37

Slot 16

Slots 39

Table 8-47 lists the slots valid for the EMS4 and the corresponding slots for the EFF8.
Table 8-47 Slots valid for the EMS4 and the corresponding slots for the EFF8

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Slot Valid for the EMS4

Corresponding Slot for the EFF8

Slot 3

Slots 21 and 22

Slot 4

Slots 23 and 24
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Slot Valid for the EMS4

Corresponding Slot for the EFF8

Slot 5

Slots 25 and 26

Slot 6

Slots 27 and 28

Slot 7

Slots 29 and 30

Slot 12

Slots 31 and 32

Slot 13

Slots 33 and 34

Slot 14

Slots 35 and 36

Slot 15

Slots 37 and 38

Slot 16

Slots 39 and 40

8.12.6 Technical Specifications


The technical specifications of the EFF8 include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.

Parameters Specified for Optical Interfaces


Table 8-48 lists the parameters specified for the optical interfaces of the EFF8.
Table 8-48 Parameters specified for the optical interfaces of the EFF8

8-58

Parameter

Value

Nominal bit rate

10 Mbit/s or 100 Mbit/s

Line code pattern

Manchester encoding signal (10M) or MLT-3 encoding signal


(100M)

Type of optical
interface

100BASE-FX

Operating
wavelength range
(nm)

100BASE-FX (15 km): 1261 to 1360

Type of fiber

Single-mode LC

Mean launched
optical power (dBm)

100BASE-FX (15 km): -15 to -8

Receiver sensitivity
(dBm)

100BASE-FX (15 km): -28

Minimum overload
(dBm)

100BASE-FX (15 km): -7

100BASE-FX (2 km): 1270 to 1380

100BASE-FX (2 km): -19 to -14

100BASE-FX (2 km): -30

100BASE-FX (2 km): -14

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Parameter

Value

Minimum extinction
ratio (dB)

10

8 Interface Boards and Switching and Bridging Boards

Laser Safety Class


The safety class of the laser on the board is Class 1. The maximum launched optical power of
the optical interfaces is less than 10 dBm (10 mW).

Mechanical Specifications
The mechanical specifications of the EFF8 are as follows:
l

Dimensions (mm): 22 (W) x 110 (D) x 262.05 (H)

Weight (kg): 0.4

Power Consumption
The maximum power consumption of the EFF8 at room temperature (25C) is 6 W.

8.13 EFF8A
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the EFF8A (8x100M Ethernet optical interface board).
8.13.1 Version Description
The EFF8A is available in one functional version, namely, N1.
8.13.2 Functions and Features
The EFF8A receives and transmits 8x100M Ethernet optical signals. The EFF8A must work
with the N5EFS0.
8.13.3 Working Principle and Signal Flow
The EFF8A consists of the interface module and power module.
8.13.4 Front Panel
The front panel of the EFF8A has indicators, interfaces, a bar code, and a laser safety class label.
8.13.5 Valid Slots
The EFF8A can be installed in slots 2140 in the subrack and works as the interface board of
the N5EFS0.
8.13.6 Technical Specifications
The technical specifications of the EFF8A include the parameters specified for optical interfaces,
mechanical specifications, and power consumption.

8.13.1 Version Description


The EFF8A is available in one functional version, namely, N1.
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8.13.2 Functions and Features


The EFF8A receives and transmits 8x100M Ethernet optical signals. The EFF8A must work
with the N5EFS0.

8.13.3 Working Principle and Signal Flow


The EFF8A consists of the interface module and power module.
Figure 8-26 shows the functional block diagram of the EFF8A by describing how to process
1x100 Mbit/s Ethernet signals.
Figure 8-26 Functional block diagram of the EFF8A
Backplane

100 Mbit/s
Ethernet signal

N5EFS0
Interface
module

100 Mbit/s
Ethernet signal

N5EFS0

+3.3 V

Power
module

Fuse

+3.3 V backup power

Interface Module
In the receive direction, the interface module performs O/E conversion for the Ethernet signals
and transmits the signals to the N5EFS0.
In the transmit direction, the interface module performs E/O conversion for the Ethernet signals
and transmits the signals to the optical interface.

Power Module
The power module provides all the modules of the EFF8A with the required DC voltages.

8.13.4 Front Panel


The front panel of the EFF8A has indicators, interfaces, a bar code, and a laser safety class label.

Diagram of the Front Panel


Figure 8-27 shows the appearance of the front panel of the EFF8A.
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Figure 8-27 Front panel of the EFF8A

EFF8
1
2
3
4
5
6
7
8
LINK ACT

OUT1 IN1
OUT2 IN2
OUT3 IN3
OUT4 IN4
OUT5 IN5
OUT6 IN6
OUT7 IN7
OUT8 IN8
CLASS 1
LASER
PRODUCT

EFF8

Indicators
The front panel of the board has the following indicators:
l

Eight connection status indicators (LINK) one color (green)

Eight data receiving and transmission indicators (ACT) one color (orange)

For the meanings of the status of the indicators, see A Indicators.

Interfaces
The front panel of the EFF8A has eight optical interfaces.
Table 8-49 describes the types and usage of the interfaces of the EFF8A.

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Table 8-49 Interfaces of the EFF8A


Interface

Type of
Interface

Usage

IN1IN8

LC

Receives the 1st to the 8th channels of Ethernet


optical signals.

OUT1OUT8

LC

Transmits the 1st to the 8th channels of Ethernet


optical signals.

8.13.5 Valid Slots


The EFF8A can be installed in slots 2140 in the subrack and works as the interface board of
the N5EFS0.
Table 8-50 lists the slots valid for the N5EFS0 and the corresponding slots for the EFF8A.
Table 8-50 Slots valid for the N5EFS0 and the corresponding slots for the EFF8A
Slot Valid for the N5EFS0

Corresponding Slot for the EFF8A

Slot 3

Slots 21 and 22

Slot 4

Slots 23 and 24

Slot 5

Slots 25 and 26

Slot 6

Slots 29 and 30

Slot 7

Slots 31 and 32

Slot 13

Slots 33 and 34

Slot 14

Slots 35 and 36

Slot 15

Slots 37 and 38

Slot 16

Slots 39 and 40

8.13.6 Technical Specifications


The technical specifications of the EFF8A include the parameters specified for optical interfaces,
mechanical specifications, and power consumption.

Parameters Specified for Optical Interfaces


Table 8-51 lists the parameters specified for the optical interfaces of the EFF8A.

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Table 8-51 Parameters specified for the optical interfaces of the EFF8A
Parameter

Value

Nominal bit rate

10 Mbit/s or 100 Mbit/s

Line code pattern

Manchester encoding signal (10M) or MLT-3 encoding signal


(100M)

Type of optical
interface

100BASE-FX

Operating
wavelength range
(nm)

100BASE-FX (15 km): 1261 to 1360

Type of fiber

Single-mode LC

Mean launched
optical power (dBm)

100BASE-FX (15 km): -15 to -8

Receiver sensitivity
(dBm)

100BASE-FX (15 km): -28

Minimum overload
(dBm)

100BASE-FX (15 km): -7

Minimum extinction
ratio (dB)

10

100BASE-FX (2 km): 1270 to 1380

100BASE-FX (2 km): -19 to -14

100BASE-FX (2 km): -30

100BASE-FX (2 km): -14

Mechanical Specifications
The mechanical specifications of the EFF8A are as follows:
l

Dimensions (mm): 22 (W) x 110 (D) x 262.05 (H)

Weight (kg): 0.4

Power Consumption
The maximum power consumption of the EFF8A at room temperature (25C) is 15 W.

8.14 ETF8
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the ETF8 (8x100M Ethernet twisted pair interface board).
8.14.1 Version Description
The ETF8 is available in one functional version, namely, N1.
8.14.2 Functions and Features
The ETF8 receives and transmits 8x100M Ethernet electrical signals. The ETF8 must work with
the EFT8.
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8.14.3 Working Principle and Signal Flow


The ETF8 consists of the interface module and power module.
8.14.4 Front Panel
The front panel of the ETF8 has interfaces and a bar code.
8.14.5 Valid Slots
The ETF8 can be installed in slots 21, 23, 25, 27, 29, 31, 33, 35, 37, and 39 in the subrack and
works as the interface board of the EFT8, EFS0, or EMR0. The ETF8 can be installed in slots
2140 in the subrack and works as the interface board of the EMS4.
8.14.6 Technical Specifications
The technical specifications of the ETF8 include the parameters specified for electrical
interfaces, mechanical specifications, and power consumption.

8.14.1 Version Description


The ETF8 is available in one functional version, namely, N1.

8.14.2 Functions and Features


The ETF8 receives and transmits 8x100M Ethernet electrical signals. The ETF8 must work with
the EFT8.

8.14.3 Working Principle and Signal Flow


The ETF8 consists of the interface module and power module.
Figure 8-28 shows the functional block diagram of the ETF8 by describing how to process
1x100 Mbit/s Ethernet signals.
Figure 8-28 Functional block diagram of the ETF8
Backplane

100 Mbit/s
Ethernet signal

EFT8/EFS0/EMS4/EMR0
Interface
module

100 Mbit/s
Ethernet signal

+3.3 V

EFT8/EFS0/EMS4/EMR0

Power
module

Fuse

+3.3 V backup power

Interface Module
In the receive direction, the interface module performs O/E conversion for the Ethernet signals
and transmits the signals to the EFT8, EFS0, EMS4, or EMR0.
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In the transmit direction, the interface module performs E/O conversion for the Ethernet signals
and transmits the signals to the optical interface.

Power Module
The power module provides all the modules of the ETF8 with the required DC voltages.

8.14.4 Front Panel


The front panel of the ETF8 has interfaces and a bar code.

Diagram of the Front Panel


Figure 8-29 shows the appearance of the front panel of the ETF8.
Figure 8-29 Front panel of the ETF8

ETF8

FE1
FE2
FE3
FE4
FE5
FE6
FE7
FE8

ETF8

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Interfaces
The front panel of the ETF8 has eight electrical interfaces.
Table 8-52 describes the types and usage of the interfaces of the ETF8.
Table 8-52 Interfaces of the ETF8
Interface

Type of
Interface

Usage

FE1FE8

RJ-45

Receives the 1st to the 8th channels of Ethernet


electrical signals.

Table 8-53 provides the pin assignments of the RJ-45 connector of the ETF8.
Table 8-53 Pin assignments of the RJ-45 connector of the ETF8
Front View

8 7

6 5

3 2

Pin

Description

Transmitting (+)

Transmitting ()

Receiving (+)

Grounding

Grounding

Receiving ()

Grounding

Grounding

8.14.5 Valid Slots


The ETF8 can be installed in slots 21, 23, 25, 27, 29, 31, 33, 35, 37, and 39 in the subrack and
works as the interface board of the EFT8, EFS0, or EMR0. The ETF8 can be installed in slots
2140 in the subrack and works as the interface board of the EMS4.
Table 8-54 lists the slots valid for the EFT8/EFS0/EMR0 and the corresponding slots for the
ETF8.
Table 8-54 Slots valid for the EFT8/EFS0/EMR0 and the corresponding slots for the ETF8

8-66

Slot Valid for the EFT8/EFS0/EMR0

Corresponding Slot for the ETF8

Slot 3

Slots 21

Slot 4

Slots 23
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Slot Valid for the EFT8/EFS0/EMR0

Corresponding Slot for the ETF8

Slot 5

Slots 25

Slot 6

Slots 27

Slot 7

Slots 29

Slot 12

Slots 31

Slot 13

Slots 33

Slot 14

Slots 35

Slot 15

Slots 37

Slot 16

Slots 39

Table 8-55 lists the slots valid for the EMS4 and the corresponding slots for the ETF8.
Table 8-55 Slots valid for the EMS4 and the corresponding slots for the ETF8
Slot Valid for the EMS4

Corresponding Slot for the ETF8

Slot 3

Slots 21 and 22

Slot 4

Slots 23 and 24

Slot 5

Slots 25 and 26

Slot 6

Slots 27 and 28

Slot 7

Slots 29 and 30

Slot 12

Slots 31 and 32

Slot 13

Slots 33 and 34

Slot 14

Slots 35 and 36

Slot 15

Slots 37 and 38

Slot 16

Slots 39 and 40

8.14.6 Technical Specifications


The technical specifications of the ETF8 include the parameters specified for electrical
interfaces, mechanical specifications, and power consumption.

Parameters Specified for Electrical Interfaces


Table 8-56 lists the parameters specified for the electrical interfaces of the ETF8.

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Table 8-56 Parameters specified for the optical interfaces of the ETF8
Parameter

Value

Nominal bit rate

10 Mbit/s or 100 Mbit/s

Line code pattern

Manchester encoding signal (10M) or MLT-3


encoding signal (100M)

Specifications of the
interface

Complies with IEEE 802.3u.

Mechanical Specifications
The mechanical specifications of the ETF8 are as follows:
l

Dimensions (mm): 22 (W) x 110 (D) x 262.05 (H)

Weight (kg): 0.4

Power Consumption
The maximum power consumption of the ETF8 at room temperature (25C) is 2 W.

8.15 ETF8A
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the ETF8A (8x100M Ethernet twisted pair interface board).
8.15.1 Version Description
The ETF8A is available in one functional version, namely, N1.
8.15.2 Functions and Features
The ETF8A receives and transmits 8x100M Ethernet electrical signals. The ETF8A must work
with the N5EFS0.
8.15.3 Working Principle and Signal Flow
The ETF8A consists of the interface module and power module.
8.15.4 Front Panel
The front panel of the ETF8A has interfaces and a bar code.
8.15.5 Valid Slots
The ETF8A can be installed in slots 2140 in the subrack and works as the interface board of
the N5EFS0.
8.15.6 Technical Specifications
The technical specifications of the ETF8A include the parameters specified for electrical
interfaces, mechanical specifications, and power consumption.

8.15.1 Version Description


The ETF8A is available in one functional version, namely, N1.
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8.15.2 Functions and Features


The ETF8A receives and transmits 8x100M Ethernet electrical signals. The ETF8A must work
with the N5EFS0.

8.15.3 Working Principle and Signal Flow


The ETF8A consists of the interface module and power module.
Figure 8-30 shows the functional block diagram of the ETF8A by describing how to process
1x100 Mbit/s Ethernet signals.
Figure 8-30 Functional block diagram of the ETF8A
Backplane

100 Mbit/s
Ethernet signal

N5EFS0
Interface
module

100 Mbit/s
Ethernet signal

+3.3 V

N5EFS0

Power
module

Fuse

+3.3 V backup power

Interface Module
In the receive direction, the interface module performs O/E conversion for the Ethernet signals
and transmits the signals to the N5EFS0.
In the transmit direction, the interface module performs E/O conversion for the Ethernet signals
and transmits the signals to the optical interface.

Power Module
The power module provides all the modules of the ETF8A with the required DC voltages.

8.15.4 Front Panel


The front panel of the ETF8A has interfaces and a bar code.

Diagram of the Front Panel


Figure 8-31 shows the appearance of the front panel of the ETF8A.
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Figure 8-31 Front panel of the ETF8A

ETF8A

FE1
FE2
FE3
FE4
FE5
FE6
FE7
FE8

ETF8A

Interfaces
The front panel of the ETF8A has eight electrical interfaces.
Table 8-57 describes the types and usage of the interfaces of the ETF8A.
Table 8-57 Interfaces of the ETF8A
Interface

Type of
Interface

Usage

FE1FE8

RJ-45

Receives the 1st to the 8th channels of Ethernet


electrical signals.

Table 8-58 provides the pin assignments of the RJ-45 connector of the ETF8A.
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Table 8-58 Pin assignments of the RJ-45 connector of the ETF8A


Front View

8 7

6 5

3 2

Pin

Description

Transmitting (+)

Transmitting ()

Receiving (+)

Grounding

Grounding

Receiving ()

Grounding

Grounding

8.15.5 Valid Slots


The ETF8A can be installed in slots 2140 in the subrack and works as the interface board of
the N5EFS0.
Table 8-59 lists the slots valid for the N5EFS0 and the corresponding slots for the ETF8A.
Table 8-59 Slots valid for the N5EFS0 and the corresponding slots for the ETF8A
Slot Valid for the N5EFS0

Corresponding Slot for the ETF8A

Slot 3

Slots 21 and 22

Slot 4

Slots 23 and 24

Slot 5

Slots 25 and 26

Slot 6

Slots 27 and 28

Slot 7

Slots 29 and 30

Slot 12

Slots 31 and 32

Slot 13

Slots 33 and 34

Slot 14

Slots 35 and 36

Slot 15

Slots 37 and 38

Slot 16

Slots 39 and 40

8.15.6 Technical Specifications


The technical specifications of the ETF8A include the parameters specified for electrical
interfaces, mechanical specifications, and power consumption.
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Parameters Specified for Electrical Interfaces


Table 8-60 lists the parameters specified for the electrical interfaces of the ETF8A.
Table 8-60 Parameters specified for the optical interfaces of the ETF8A
Parameter

Value

Nominal bit rate

10 Mbit/s or 100 Mbit/s

Line code pattern

Manchester encoding signal (10M) or MLT-3


encoding signal (100M)

Specifications of the
interface

Complies with IEEE 802.3u.

Mechanical Specifications
The mechanical specifications of the ETF8A are as follows:
l

Dimensions (mm): 22 (W) x 110 (D) x 262.05 (H)

Weight (kg): 0.4

Power Consumption
The maximum power consumption of the ETF8A at room temperature (25C) is 11 W.

8.16 ETS8
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the ETS8 (8x10/100M Ethernet twisted pair interface switching
board).
8.16.1 Version Description
The ETS8 is available in one functional version, namely, N1.
8.16.2 Functions and Features
The ETS8 is used to provide the TPS protection for 8xFE signals at the electrical interface. The
ETS8 must work with the EFS0 or EFS0A.
8.16.3 Working Principle and Signal Flow
The ETS8 consists of the interface module, switch matrix module, and power module.
8.16.4 Front Panel
The front panel of the ETS8 has interfaces and a bar code.
8.16.5 Valid Slots
The ETS8 can be installed in slots 21, 23, 25, 27, 29, 31, 33, 35, 37, and 39 in the subrack and
works as the interface board of the EFS0. The ETS8 can be installed in slots 21, 23, 24, 25, 27,
29, 31, 33, 35, 37, 38, and 39 in the subrack and works as the interface board of the EFS0A.
8.16.6 Technical Specifications
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The technical specifications of the ETS8 include the parameters specified for electrical
interfaces, mechanical specifications, and power consumption.

8.16.1 Version Description


The ETS8 is available in one functional version, namely, N1.

8.16.2 Functions and Features


The ETS8 is used to provide the TPS protection for 8xFE signals at the electrical interface. The
ETS8 must work with the EFS0 or EFS0A.

8.16.3 Working Principle and Signal Flow


The ETS8 consists of the interface module, switch matrix module, and power module.
Figure 8-32 shows the functional block diagram of the ETS8 by describing how to process
1x100 Mbit/s Ethernet signals.
Figure 8-32 Functional block diagram of the ETS8
Backplane
Cross-connect board
100 Mbit/s
Ethernet signal

Interface
module

100 Mbit/s
Ethernet signal
+3.3 V

Switch
matrix
module

Power
module

Fuse

EFS0
TSB8
TSB8
EFS0

+3.3 V backup power

Interface Module
The interface module receives and transmits the Ethernet optical signals.

Switch Matrix Module


In the receive direction, the switch matrix module receives the signal sent from the interface
module and selects the output direction of the signal according to the TPS protection control
signal sent from the cross-connect board. When the TPS is not performed, the switch matrix
module transmits the signal to the EFS0. When the TPS is performed, the switch matrix module
transmits the signal to the TSB8 for bridging.
In the transmit direction, the switch matrix module performs the reverse process.

Power Module
The power module provides all the modules of the ETS8 with the required DC voltages.
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8.16.4 Front Panel


The front panel of the ETS8 has interfaces and a bar code.

Diagram of the Front Panel


Figure 8-33 shows the appearance of the front panel of the ETS8.
Figure 8-33 Front panel of the ETS8

ETS8

FE1
FE2
FE3
FE4
FE5
FE6
FE7
FE8

ETS8

Interfaces
The front panel of the ETS8 has eight electrical interfaces.
Table 8-61 describes the types and usage of the interfaces of the ETS8.

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Table 8-61 Interfaces of the ETS8


Interface

Type of
Interface

Usage

FE1FE8

RJ-45

Receives the 1st to the 8th channels of Ethernet


electrical signals.

Table 8-62 provides the pin assignments of the RJ-45 connector of the ETS8.
Table 8-62 Pin assignments of the RJ-45 connector of the ETS8
Front View

8 7

6 5

3 2

Pin

Description

Transmitting (+)

Transmitting ()

Receiving (+)

Grounding

Grounding

Receiving ()

Grounding

Grounding

8.16.5 Valid Slots


The ETS8 can be installed in slots 21, 23, 25, 27, 29, 31, 33, 35, 37, and 39 in the subrack and
works as the interface board of the EFS0. The ETS8 can be installed in slots 21, 23, 24, 25, 27,
29, 31, 33, 35, 37, 38, and 39 in the subrack and works as the interface board of the EFS0A.
Table 8-63 lists the slots valid for the EFS0 and the corresponding slots for the ETS8.
Table 8-63 Slots valid for the EFS0 and the corresponding slots for the ETS8

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Slot Valid for the EFS0

Corresponding Slot for the ETS8

Slot 3

Slot 21

Slot 4

Slot 23

Slot 5

Slot 25

Slot 6

Slot 27

Slot 7

Slot 29

Slot 12

Slot 31
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Slot Valid for the EFS0

Corresponding Slot for the ETS8

Slot 13

Slot 33

Slot 14

Slot 35

Slot 15

Slot 37

Slot 16

Slot 39

Table 8-64 lists the slots valid for the EFS0A and the corresponding slots for the ETS8.
Table 8-64 Slots valid for the EFS0A and the corresponding slots for the ETS8
Slot Valid for the EFS0A

Corresponding Slot for the ETS8

Slot 3

Slot 21

Slot 4

Slot 23 and 24

Slot 5

Slot 25

Slot 6

Slot 27

Slot 7

Slot 29

Slot 12

Slot 31

Slot 13

Slot 33

Slot 14

Slot 35

Slot 15

Slot 37 and 38

Slot 16

Slot 39

8.16.6 Technical Specifications


The technical specifications of the ETS8 include the parameters specified for electrical
interfaces, mechanical specifications, and power consumption.

Parameters Specified for Electrical Interfaces


Table 8-65 lists the parameters specified for the electrical interfaces of the ETS8.
Table 8-65 Parameters specified for the optical interfaces of the ETS8

8-76

Parameter

Value

Nominal bit rate

10 Mbit/s or 100 Mbit/s

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Parameter

Value

Line code pattern

Manchester encoding signal (10M) or MLT-3


encoding signal (100M)

Specifications of the
interface

Complies with IEEE 802.3u.

Mechanical Specifications
The mechanical specifications of the ETS8 are as follows:
l

Dimensions (mm): 22 (W) x 110 (D) x 262.05 (H)

Weight (kg): 0.4

Power Consumption
At room temperature (25C), the maximum power consumption of the ETS8 is 0 W.

8.17 DM12
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the DM12 (DDN service interface board).
8.17.1 Version Description
The DM12 is available in one functional version, namely, N1.
8.17.2 Functions and Features
The DM12 receives and transmits four channels of Nx64 kbit/s signals and eight channels of
framed E1 electrical signals. The DM12 must work with the DX1.
8.17.3 Working Principle and Signal Flow
The DM12 consists of the interface module, switch matrix module, and power module.
8.17.4 Front Panel
The front panel of the DM12 has interfaces and a bar code.
8.17.5 Valid Slots
The DM12 can be installed in slots 2140 in the subrack and works as the interface board of the
DX1.
8.17.6 Technical Specifications
The technical specifications of the DM12 include the parameters specified for electrical
interfaces, mechanical specifications, and power consumption.

8.17.1 Version Description


The DM12 is available in one functional version, namely, N1.

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8.17.2 Functions and Features


The DM12 receives and transmits four channels of Nx64 kbit/s signals and eight channels of
framed E1 electrical signals. The DM12 must work with the DX1.

8.17.3 Working Principle and Signal Flow


The DM12 consists of the interface module, switch matrix module, and power module.
Figure 8-34 shows the functional block diagram of the DM12 by describing how to process one
channel of Nx64 kbit/s or framed E1 electrical signals.
Figure 8-34 Functional block diagram of the DM12
Backplane
Cross-connect board
Nx64 kbit/s/
Framed E1
electrical signal

Switch
matrix
module

Interface
module

Nx64 kbit/s/
Framed E1
electrical signal

+3.3 V

Power
module

Fuse

DX1

DX1

+3.3 V backup power

Interface Module
The interface module receives and transmits the Nx64 kbit/s or framed E1 electrical signals.

Switch Matrix Module


In the receive direction, the switch matrix module receives the signal sent from the interface
module and selects the output direction of the signal according to the TPS protection control
signal sent from the cross-connect board. When the TPS is not performed, the switch matrix
module transmits the signal to the DX1. When the TPS is performed, the switch matrix module
transmits the signal to the protection DX1 for bridging.
In the transmit direction, the switch matrix module performs the reverse process.

Power Module
The power module provides all the modules of the DM12 with the required DC voltages.

8.17.4 Front Panel


The front panel of the DM12 has interfaces and a bar code.
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Diagram of the Front Panel


Figure 8-35 shows the appearance of the front panel of the DM12.
Figure 8-35 Front panel of the DM12

DM12

E1(1-8)
DDN1
DDN2
DDN3
DDN4

DM12

Interfaces
The front panel of the DM12 has DB44 and DB28 interfaces. Table 8-66 describes the types
and usage of the interfaces of the DM12.
Table 8-66 Interfaces of the DM12

Issue 02 (2009-07-30)

Interface

Type of
Interface

Usage

E1 (18)

DB44

Accesses eight channels of framed E1 signals.

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Interface

Type of
Interface

Usage

DDN1DDN4

DB28

Accesses the 1st to the 4th channels of Nx64


kbit/s signals.

Table 8-67 provides the pin assignments of the DB44 interface.


Table 8-67 Pin assignments of the DB44 interface
Front View
30

15

Pin

Usage

Pin

Usage

30

Transmits the
1st channel of
signals (T1).

Transmits the 8th


channel of signals
(T8).

Transmits the
2nd channel of
signals (T2).

36

Transmits the
3rd channel of
signals (T3).

35

Transmits the
4th channel of
signals (T4).

34

Transmits the
5th channel of
signals (T5).

33

Transmits the
6th channel of
signals (T6).

32

Transmits the
7th channel of
signals (T7).

31

Receives the 1st


channel of
signals (R1).

4439 and
61

15

44

29
14
28
13
27
31
16

12
26
11
25
10
24
9
38
23
37
22

21

20

19

18

17

16

Receives the 3rd


channel of signals
(R3).
Receives the 4th
channel of signals
(R4).
Receives the 5th
channel of signals
(R5).
Receives the 6th
channel of signals
(R6).
Receives the 7th
channel of signals
(R7).
Receives the 8th
channel of signals
(R8).
Grounding

Receives the
2nd channel of
signals (R2).

Table 8-68 provides the pin assignments of the DB28 interface.

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Table 8-68 Pin assignments of the DB28 interface


Front View
28

Pin

Usage

Pin

Usage

Transmits data
signals.

19

Receives data
signals.

Transmits
clock signals.

21

Grounding

22

Receives the
loopback control
signal.

Detects the
carrier.

23

Permits the
transmission.

Requests for
transmission.

25

Receives the
clock to be
used in the
transmit
direction from
the external
equipment.

27

Receives clock
signals.

2
3
4

11
12
1

13
14
15
16

17
18

20

24

26

28

Receives the DCE


ready signal.
Transmits the DTE
ready signal.

8.17.5 Valid Slots


The DM12 can be installed in slots 2140 in the subrack and works as the interface board of the
DX1.
Table 8-69 lists the slots valid for the DX1 and the corresponding slots for the DM12. The DM12
installed in the slot with a smaller number accesses eight channels of framed E1 signals and four
channels of Nx64 kbit/s signals. The DM12 installed in the slot with a larger number accesses
only four channels of Nx64 kbit/s signals.
Table 8-69 Slots valid for the DX1 and the corresponding slots for the DM12

Issue 02 (2009-07-30)

Slot Valid for the DX1

Corresponding Slot for the DM12

Slot 3

Slots 21 and 22

Slot 4

Slots 23 and 24

Slot 5

Slots 25 and 26

Slot 6

Slots 27 and 28
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Slot Valid for the DX1

Corresponding Slot for the DM12

Slot 7

Slots 29 and 30

Slot 12

Slots 31 and 32

Slot 13

Slots 33 and 34

Slot 14

Slots 35 and 36

Slot 15

Slots 37 and 38

Slot 16

Slots 39 and 40

8.17.6 Technical Specifications


The technical specifications of the DM12 include the parameters specified for electrical
interfaces, mechanical specifications, and power consumption.

Parameters Specified for Electrical Interfaces


Table 8-70 lists the parameters specified for the electrical interfaces of the DM12.
Table 8-70 Parameters specified for the electrical interfaces of the DM12
Interface Type

Description of the Interface

Specification of the Interface

Framed E1
interface (DB44)

Framed E1 signals

The physical and electrical


characteristics of the interface
comply with ITU-T G.703. The
frame structure of the interface
complies with ITU-T G.704.

NX64 kbit/s
interface (DB28)

V.35 interface

Complies with ITU-T V.35.

V.24 interface

Complies with ITU-T V.24.

X.21 interface

Complies with ITU-T X.21.

RS-449 interface

Complies with EIA RS-449


(RS-423A and RS-422A).

RS-530 interface

Complies with EIA RS-530.

RS-530A interface

Complies with EIA RS-530A.

Mechanical Specifications
The mechanical specifications of the DM12 are as follows:

8-82

Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)

Weight (kg): 0.5


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Power Consumption
At room temperature (25C), the maximum power consumption of the DM12 is 0 W.

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Hardware Description

9 Cross-Connect Boards and System Control Boards

Cross-Connect Boards and System Control


Boards

About This Chapter


This topic describes the SCC unit, cross-connect unit, and line unit integrated boards that operate
at different rates.
9.1 CXLLN
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the CXLLN (1xSTM-16/STM-4/STM-1 SCC unit, cross-connect
unit, timing unit, and line unit integrated board).
9.2 CXLQ41
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the CXLQ41 (4xSTM-4/STM-1 SCC unit, cross-connect unit, timing
unit, and line unit integrated board).
9.3 CXS
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the CXS (SCC unit, cross-connect unit, and timing unit integrated
board).

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Hardware Description

9.1 CXLLN
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the CXLLN (1xSTM-16/STM-4/STM-1 SCC unit, cross-connect
unit, timing unit, and line unit integrated board).
9.1.1 Version Description
The CXLLN is available in two functional versions, namely, Q5 and Q6.
9.1.2 Functions and Features
The CXLLN processes SDH signals, controls communication, grooms services, and inputs/
outputs clock signals.
9.1.3 Working Principle and Signal Flow
The CXLLN consists of the synchronous timing module, O/E converting module, MUX/
DEMUX module, SDH overhead processing module, communication and control module, crossconnect module, and DC/DC converter.
9.1.4 Jumpers and DIP Switches
The CXLLN has jumpers, which are used to set the enable state of the battery, and a DIP switch,
which is used to set the running state of the equipment.
9.1.5 Front Panel
The front panel of the CXLLN board has indicators, an optical interface, a bar code, functional
button switches, a laser safety class label.
9.1.6 Valid Slots
The CXLLN can be installed in slot 9 or slot 10 in the subrack.
9.1.7 Feature Code
The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the CXLLN indicates the type of optical interface. The CXLLN supports
optical modules of different configurations. Therefore, no specific feature code is provided.
9.1.8 Parameter Settings
The physical slot that houses the CXLLN is different from the logical slot displayed on the
T2000. You can set the parameters for the CXLLN by using the T2000.
9.1.9 Technical Specifications
The technical specifications of the CXLLN include the parameters specified for optical
interfaces, cross-connect capacity, clock access capability, laser safety class, mechanical
specifications, and power consumption.

9.1.1 Version Description


The CXLLN is available in two functional versions, namely, Q5 and Q6.
Table 9-1 describes the versions of the CXLLN.

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Table 9-1 Versions of the CXLLN


Item

Description

Functional
versions

The CXLLN is available in two functional versions, namely, Q5 and


Q6.

Differences

The Q5CXLLN supports the higher order cross-connection capacity


of 60 Gbit/s.

The Q6CXLLN supports the higher order cross-connection capacity


of 110 Gbit/s.

When the Q5CXLLN boards are used, the access capacity of slot 8
is 5 Gbit/s and the access capacity of the other service slots is 2.5
Gbit/s.

When the Q6CXLLN boards are used, the total access capacity of
slots 7, 8, 11, and 12 is 10 Gbit/s and the total access capacity of the
other service slots is 5 Gbit/s.

None

Substitution

9.1.2 Functions and Features


The CXLLN processes SDH signals, controls communication, grooms services, and inputs/
outputs clock signals.

SDH Processing Unit


Table 9-2 provides the functions and features of the SDH processing unit of the CXLLN.
Table 9-2 Functions and features of the SDH processing unit of the CXLLN

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Function and
Feature

CXLLN

Basic functions

Transmits and receives 1xSTM-1/STM-4/STM-16 optical signals.

Specifications of the
optical interface

The STM-1/STM-4/STM-16 optical module can be used.


l

At the STM-1 level, the standard I-1, S-1.1, L-1.1, L-1.2, and
Ve-1.2 optical interfaces are supported. The optical interfaces of
I-1, S-1.1, L-1.1, and L-1.2 types comply with ITU-T G.957, and
the optical interface of the Ve-1.2 type complies with the standards
defined by Huawei.

At the STM-4 level, the standard I-4, S-4.1, L-4.1, L-4.2, and
Ve-4.2 optical interfaces are supported. The optical interfaces of
the I-4, S-4.1, L-4.1, and L-4.2 types comply with ITU-T G.957,
and the optical interface of the Ve-4.2 type complies with the
standards defined by Huawei.

At the STM-16 level, the standard I-16, S-16.1, L-16.1, and L-16.2
optical interfaces are supported. The optical interfaces of the I-16,
S-16.1, L-16.1, and L-16.2 types comply with ITU-T G.957.

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Function and
Feature

CXLLN

Specifications of the
optical module

Supports the detection and query of the information about the


optical module.

Provides the ALS function. The optical interface supports the


setting of the on/off state of a laser.

Supports the swappable optical modules, thus facilitating the


maintenance and upgrade of the optical modules.

The STM-1 module supports the VC-12/VC-3/VC-4 services.

The STM-4 module supports the VC-12/VC-3/VC-4 and VC-4-4c


concatenation services.

The STM-16 module supports the VC-12/VC-3/VC-4 and


VC-4-4c/VC-4-8c/VC-4-16c concatenation services.

The Q5CXLLN supports the time synchronization feature and


transmission of the time information by using the section overhead
bytes.

Processes the section overheads of the STM-1/STM-4/STM-16


signals.

Supports the transparent transmission and termination of the path


overheads.

Supports the setting and query of the J0, J1, J2 and C2 bytes.

Service processing

Overhead processing

Alarm and
performance event

Reports various alarms and performance events, which facilitates the


management and maintenance of the equipment.

Protection scheme

Supports the two-fiber ring MSP, four-fiber ring MSP, linear MSP,
SNCP, SNCTP, and SNCMP.

Maintenance feature

Supports inloops and outloops at optical interfaces.

Supports warm resets and cold resets. The warm reset does not
affect services.

Supports the query of the manufacturing information of the board.

Supports the in-service loading of the FPGA.

Supports the upgrade of the board software without affecting


services.

SCC Unit
Table 9-3 provides the functions and features of the SCC unit of the CXLLN.

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Table 9-3 Functions and features of the SCC unit of the CXLLN
Function and
Feature

CXLLN

Basic functions

Configures and monitors services, monitors the service performance,


and collects the information about the performance events and
alarms.

Specifications of the
optical interface

Provides one 10M/100M compatible Ethernet NM interface,


which is accessed through the AUX board.

Provides one 10M/100M Ethernet port, which is used for


implementing the inter-board communication.

Provides one 10M Ethernet port, which is used for implementing


the communication between the active and standby SCC boards.

Provides the RS232 OAM interface, which is accessed through the


SEI board and is used for connecting a PC or workstation. Supports
the remote maintenance by using the RS232 DCE modem.

Supports the receiving of the check result of the NE ID and


provides the interface for querying the check result.

Provides one orderwire interface, which is accessed through the


EOW board.

Provides four broadcast data ports (serial14), which are accessed


through the EOW board.

DCC processing
capability

Processes 80 channels of DCC signals.

Fan alarm
management

Manages fan alarms.

PIU management

Supports the in-service check function for the PIU board and supports
the failure check function for the lightning protection module of the
PIU.

Protection scheme

Supports 1+1 hot backup.

Cross-Connect Unit
Table 9-4 provides the functions and features of the cross-connect unit of the CXLLN.

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Table 9-4 Functions and features of the cross-connect unit of the CXLLN
Function and
Feature

CXLLN

Basic functions

The Q5CXLLN realizes 60 Gbit/s higher order cross-connection


at the VC-4 level and 20 Gbit/s lower order cross-connection at
the VC-12 or VC-3 level.

The Q6CXLLN realizes 110 Gbit/s higher order cross-connection


at the VC-4 level and 20 Gbit/s lower order cross-connection at
the VC-12 or VC-3 level.

Fast emergency
channel

Provides two 4 Mbit/s HDLC fast emergency channels, which are


used for the MSP switching, SNCP switching, TPS, or other
functions.

Service processing

Dynamically grooms services.

Adds or deletes services without interrupting other services.

Supports the SNCP protection at the VC-4, VC-3 and VC-12


levels.

Supports a maximum of 1184 SNCP groups.

The STM-4 optical module supports the VC-4-4c concatenation


services.

The STM-16 optical module supports the VC-4-4c, VC-4-8c, and


VC-4-16c concatenation services.

Protection scheme

Supports the 1+1 hot backup (non-revertive, by default).

Clock Unit
Table 9-5 provides the functions and features of the clock unit of the CXLLN.
Table 9-5 Functions and features of the clock unit of the CXLLN
Function and
Feature

CXLLN

Basic functions

Provides the standard system synchronization clock.

Other functions

Supports the extraction, insertion, and management of the SSM


and clock ID.

Supports the transmission of the DCC overhead information at two


external clock interfaces.

Inputs two-channel 2048 kHz or 2048 kbit/s timing signals and


selects the external timing source.

Outputs two-channel 2048 kHz or 2048 kbit/s timing signals.

Input and output

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9.1.3 Working Principle and Signal Flow


The CXLLN consists of the synchronous timing module, O/E converting module, MUX/
DEMUX module, SDH overhead processing module, communication and control module, crossconnect module, and DC/DC converter.
Figure 9-1 shows the functional block diagram of the Q5CXLLN/Q6CXLLN.
Figure 9-1 Functional block diagram of the Q5CXLLN/Q6CXLLN
38 MHz
OSC

Synchronous
timing module
(SETS)
SETG
T0

155 MHz
PLL
STM-1/
STM-4/
STM-16
STM-1/
STM-4/
STM-16

155 Mbit/s/
4x155 Mbit/s/
16x155 Mbit/s
DEMUX
data

O/E
E/O
O/E
converting
module

Laser
shutdown

MUX

Performance
report

155 Mbit/s/
4x155 Mbit/s/
16x155 Mbit/s
data

SDH overhead
processing module
MS
RS
HPT
MST
A
T

Cross-connect
unit

Lower order crossconnect unit

DCC
processing

RAM NVRAM

Service unit
Service unit

High-speed
bus

Another CXL

High-speed
bus

Another crossconnect unit

Cross-connect
unit B

High-speed bus
DCC

Line unit

Communication over ETH


channels
Communication between the active
and standby boards

Power monitor

Flash

Line unit
Tributary unit
AUX/SE1
AUX/SEI

Cross-connect module

Communication and control module

Boot
ROM

Higher order crossconnect unit

High-speed bus

DCC

K1/K2 byte
processing

Laser
control

155 MHz

K1/K2
insertion/
extraction

K1/K2 byte

T1
T2
T3
T4
(clock external output)
Frame header
T0 (reference clock)

Other units
Another CXL

ETH port
OAM interface
F&f interface
Phone interface
S1-S4 interface
+3.3 V

Power Fuse
module

AUX
SEI
EOW
-48 V/-60 V
-48 V/-60 V

Power
module

Synchronous Timing Module


The synchronous timing module provides the system clock (T0) for the service board, the control
unit, and the cross-connect unit in centralized timing distribution mode. This module also selects
one from the reference clock sources as the reference clock for synchronous timing. The
reference clock sources are from the line board (T1), the tributary board (T2), or the external
synchronous clock source (T3). The synchronous system clock source (T0) and 2 Mbit/s external
synchronous source (T4) are generated. The boards adopt the 1+1 hot backup. Hence, both the
active and standby boards trace the same reference source.
The synchronous timing module can extract timing from three types of timing signal:
l

Timing signal (T1) from the STM-N line

Timing signal (T2) from the PDH line

Reference signal (T3) from the external synchronous clock source (2 MHz or 2 Mbit/s)

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The timing module outputs the following timing signals:


l

T0, system clock (38 MHz)

T4, external timing output signal (2 Mbit/s or 2 MHz)

O/E Converting Module


l

Converts the received optical signals into electrical signals, in the receive direction.

Converts the electrical signals into SDH optical signals, and then sends the SDH optical
signals to fibers for transmission, in the transmit direction.

The SPI detects the R_LOS alarm and provides the laser shut down function.

MUX/DEMUX Module
l

In the receive direction, the DEMUX part demultiplexes the high rate electrical signals into
multiple parallel electrical signals, and recovers the clock signal at the same time.

In the transmit direction, the MUX part multiplexes the parallel electrical signals received
from the SDH overhead processing module into high rate electrical signals.

SDH Overhead Processing Module


It includes RST, MST, MSA, and HPT and provides the inloop and outloop functions.
l

9-8

RST

Performs frame alignment detection (A1 and A2), regenerator section trace recovery
(J0), and mismatch detection, BIP-8 errored block count, in the receive direction.

Performs frame alignment insertion, regenerator section path tracer insertion, and BIP-8
calculation and insertion, in the transmit direction.

MST

Performs BIP-24 errored block count, MS_REI recovery, and MS_RDI and MS_AIS
detection, in the receive direction.

Performs BIP-24 calculation and insertion, and MS_REI, MS_RDI, and MS_AIS
insertion, in the transmit direction.

Extracts or inserts the K1 byte and K2 byte.

MSA

Performs pointer interpretation, AU_LOP and AU_AIS detection, and pointer


justification at the AU-4 level, in the receive direction.

Performs AUG assembly, AU-4 pointer regeneration, and AU_AIS generation, in the
transmit direction.

HPT

Terminates the overheads.

Recovers the J1 path trace message.

Recovers the REI information.

Detects the HP_RDI, that is, monitors the path status.

Detects the HP_UNEQ and AIS, that is, monitors the signal label.

Performs VC-4 BIP-8 errored block count.


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Communication and Control Module


l

Traces the clock signal from the active and standby cross-connect units.

Implements the laser controlling function.

Selects the clock signal and frame header signal from the active and standby cross-connect
units.

Controls the indicators on the board.

Provides the CPU control unit, which controls and monitors the other functional modules.
The unit also initializes the other functional modules after it is powered on.

Provides the ETH port, which functions as the 10M/100M Ethernet port for network
management.

Provides the OAM interface, which functions as the serial port for network management.
This port can be used as the MODEM port and thus can be configured as a serial port for
connecting to the MODEM port that is in the running state.

Provides the COM interface, which functions as the commissioning port.

Provides the Ethernet port, namely, a 10 Mbit/s Ethernet port, for inter-board
communication between the active and standby CXL units.

Cross-Connect Module
The cross-connect module consists of two parts:
l

SNCP module, which tests relative alarms and reports the alarms to the software to trigger
the protection switching such as the SNCP switching and MSP switching.

Higher order and lower order cross-connect module, which performs the functions of higher
order and lower order cross-connect units.

Other Functions
l

Responses to and processes the K bytes.

Collects the performance data of the optical module and disables the output of the optical
module.

Collects and processes DCC signal of each board.

Inserts the DCC signal back into each line board after processing.

Monitors the power supply of the board.

Performs the reset of the units.

Mutes alarms.

DC/DC Converter
It converts the 48/60 V power supply into the DC voltages that the modules of the board
require.

9.1.4 Jumpers and DIP Switches


The CXLLN has jumpers, which are used to set the enable state of the battery, and a DIP switch,
which is used to set the running state of the equipment.
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CAUTION
The jumpers and DIP switch are used for test and maintenance. Do not change the setting of the
jumper at random. Otherwise, the board may become faulty.
Figure 9-2 shows the jumpers and DIP switch of the Q5CXLLN.
Figure 9-2 Positions of the jumpers and DIP switch of the Q5CXLLN

Power
module

SW1
123 4

J24
3 21

CPU
CF
card

1
2
3

J10

Figure 9-3 shows the jumpers and DIP switch of the Q6CXLLN.

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Figure 9-3 Positions of the jumpers and DIP switch of the Q6CXLLN

Pow er
module

SW1
12 34

CPU
1
2
3

J10

Table 9-6 lists the jumpers of the Q5CXLLN.


Table 9-6 Jumpers of the Q5CXLLN
Jumper

Function

Description

J10

To enable the
battery

12: If jumper bits (positions) 1 and 2 are capped, the


battery is enabled.
23: If jumper bits (positions) 2 and 3 are capped, the
database and clock are cleared.

J24

To use the
maximum DCC
channels

12: If jumper bits (positions) 1 and 2 are capped,


the maximum of 40 DCC channels are used.

23: If jumper bits (positions) 2 and 3 are capped,


the maximum of 80 DCC channels are used.

Table 9-7 lists the jumper of the Q6CXLLN.

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Table 9-7 Jumper of the Q6CXLLN


Jumper

Function

Description

J10

To enable the
battery

12: If jumper bits (positions) 1 and 2 are capped, the


battery is enabled.
23: If jumper bits (positions) 2 and 3 are capped, the
database and clock are cleared.

Table 9-8 lists the DIP switch of the CXLLN.


Table 9-8 DIP switch of the CXLLN
DIP Switch

Function

Description

SW1

To set the running


state of the board

When a DIP switch bit is at the on position, it


indicates the binary value 1.

The DIP switch is a four-bit DIP switch. The values


of the DIP switch bits are queued in the descending
order of the switch bit numbers. The DIP switch bit
numbered 4 is the most significant bit. For details,
refer to Table 9-9.

Table 9-9 DIP switch SW1


Value

Description

0b0000

Indicates the running state when the watchdog is started. It is the default
state.

0b0011

Indicates the commissioning state when the watchdog is stopped.

0b0100

Indicates the running state when the watchdog is stopped.

0b1011

Erases the database.

0b1100

Erases the NE software, including the patches.

0b1101

Erases the database and NE software, including the patches.

0b1110

Erases the database, NE software, and NE.ini file.

0b1111

Erases the extended BIOS and system parameter area in the file system
and flash memory.

9.1.5 Front Panel


The front panel of the CXLLN board has indicators, an optical interface, a bar code, functional
button switches, a laser safety class label.
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Diagram of the Front Panel


Figure 9-4 shows the appearance of the front panel of the CXLLN.
Figure 9-4 Front panel of the CXLLN

CXLLN
STAT
ACTX
ACTC
PROG
SRVX
SRVL
SYNC
ALMC
CLASS 1
LASER
PRODUCT

OUT1
IN1
RESET

ALM CUT

CXLLN

Indicators
The front panel of the board has the following indicators:
l

Board hardware status indicator (STAT) two colors (red and green)

Active/Standby state indicator of the cross-connect unit (ACTX) one color (green)

Active/Standby state indicator of the SCC unit (ACTC) one color (green)

Board software status indicator (PROG) two colors (red and green)

Service alarm indicator of the cross-connect unit (SRVX) three colors (red, green, and
yellow)

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Service alarm indicator of the line unit (SRVL) three colors (red, green, and yellow)

Synchronization clock status indicator (SYNC) two colors (red and green)

Alarm mute indicator (ALMC) one color (yellow)

For the meanings of the status of the indicators, see A Indicators.

Interfaces
The front panel of the CXLLN has one optical interface and two switches. Table 9-10 describes
the types and usage of the interfaces and switches of the CXLLN.
Table 9-10 Optical interface and switches of the CXLLN
Interface/
Switch

Type of
Interface/
Switch

Usage

IN

LC

Receives optical signals.

OUT

LC

Transmits optical signals.

RESET

Warm reset
switch

Press the switch to perform a warm reset for the SCC


unit.

ALM CUT

Alarm cut
switch

Press the switch to mute the alarm. Press the switch for
five seconds to mute the alarm permanently. Press the
switch again for five seconds to resume the alarm sound.

9.1.6 Valid Slots


The CXLLN can be installed in slot 9 or slot 10 in the subrack.

9.1.7 Feature Code


The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the CXLLN indicates the type of optical interface. The CXLLN supports
optical modules of different configurations. Therefore, no specific feature code is provided.
For the types of optical modules that can be installed on the optical interfaces of the CXLLN,
see B.2 Optical Module Labels.

9.1.8 Parameter Settings


The physical slot that houses the CXLLN is different from the logical slot displayed on the
T2000. You can set the parameters for the CXLLN by using the T2000.

Displayed Slots
The CXLLN occupies one slot in the subrack.
The logical boards for the Q5CXLLN are the Q2SLN, UXCL, and GSCC.
Table 9-11 lists the slots for the logical boards displayed on the T2000.
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Table 9-11 Logical slots displayed on the T2000 for the Q5CXLLN
Board

Logical
Board

Logical Slot

CXLLN

UCXL

Slot 9 or slot 10

GSCC

Slot 17 or slot 18

Q2SLN

Slot 19 or slot 20

The logical boards for the Q6CXLLN are the Q2SLN, SCXL, and GSCC.
Table 9-12 lists the slots for the logical boards displayed on the T2000.
Table 9-12 Logical slots displayed on the T2000 for the Q6CXLLN
Board

Logical
Board

Logical Slot

CXLLN

SCXL

Slot 9 or slot 10

GSCC

Slot 17 or slot 18

Q2SLN

Slot 19 or slot 20

Board Parameters
You can set the following parameters for the CXLLN by using the T2000:
l

J0 byte

J1 byte

J2 byte

C2 byte

Clock parameters

For the description of each parameter, see F Parameter Settings.

9.1.9 Technical Specifications


The technical specifications of the CXLLN include the parameters specified for optical
interfaces, cross-connect capacity, clock access capability, laser safety class, mechanical
specifications, and power consumption.

Parameters Specified for Optical Interfaces


The CXLLN supports the STM-1, STM-4, and STM-16 optical modules.
Table 9-13 lists the parameters specified for the optical interfaces of the CXLLN when the
STM-1 optical module is used.
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Table 9-13 Parameters specified for the optical interfaces of the CXLLN when the STM-1
optical module is used
Parameter

Value

Nominal bit rate

155520 kbit/s

Line code pattern

NRZ

Application code

I-1

S-1.1

L-1.1

L-1.2

Ve-1.2

Transmission
distance (km)

0 to 2

2 to 15

20 to 40

60 to 80

80 to 100

Operating
wavelength range
(nm)

1260 to
1360

1261 to
1360

1263 to
1360

1480 to
1580

1480 to
1580

Type of fiber

Singlemode LC

Singlemode LC

Singlemode LC

Singlemode LC

Singlemode LC

Mean launched
optical power
(dBm)

-15 to -8

-15 to -8

-5 to 0

-5 to 0

-3 to 0

Receiver
sensitivity (dBm)

-23

-28

-34

-34

-34

Minimum
overload (dBm)

-8

-8

-10

-10

-10

Minimum
extinction ratio
(dB)

8.2

8.2

10

10

10

Table 9-14 lists the parameters specified for the optical interfaces of the CXLLN when the
STM-1 optical module is used.
Table 9-14 Parameters specified for the optical interfaces of the CXLLN when the STM-4
optical module is used

9-16

Parameter

Value

Nominal bit rate

622080 kbit/s

Line code pattern

NRZ

Application code

I-4

S-4.1

L-4.1

L-4.2

Ve-4.2

Transmission
distance (km)

0 to 2

2 to 15

20 to 40

50 to 80

80 to 100

Operating
wavelength range
(nm)

1261 to
1360

1274 to
1356

1280 to
1335

1480 to
1580

1480 to
1580

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Parameter

Value

Type of fiber

Singlemode LC

Singlemode LC

Singlemode LC

Singlemode LC

Singlemode LC

Mean launched
optical power
(dBm)

-15 to -8

-15 to -8

-3 to -2

-3 to -2

-3 to -2

Receiver
sensitivity (dBm)

-23

-28

-28

-28

-34

Minimum
overload (dBm)

-8

-8

-8

-8

-13

Minimum
extinction ratio
(dB)

8.2

8.2

10

10

10.5

Table 9-15 lists the parameters specified for the optical interfaces of the CXLLN when the
STM-16 optical module is used.
Table 9-15 Parameters specified for the optical interfaces of the CXLLN when the STM-16
optical module is used

Issue 02 (2009-07-30)

Parameter

Value

Nominal bit rate

2488320 kbit/s

Line code pattern

NRZ

Application code

I-16

S-16.1

L-16.1

L-16.2

Transmission
distance (km)

0 to 2

2 to 15

25 to 40

50 to 80

Operating
wavelength range
(nm)

1266 to
1360

1260 to 1360

1280 to 1335

1500 to 1580

Type of fiber

Singlemode LC

Single-mode LC

Single-mode
LC

Single-mode LC

Mean launched
optical power
(dBm)

-10 to -3

-5 to 0

-2 to +3

-2 to +3

Receiver
sensitivity (dBm)

-18

-18

-27

-28

Minimum
overload (dBm)

-3

-9

-9

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Parameter

Value

Minimum
extinction ratio
(dB)

8.2

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Hardware Description

8.2

8.2

8.2

Cross-Connect Capacity
The cross-connect capacity of the Q5CXLLN is as follows:
l

Higher order cross-connect capacity: 60 Gbit/s

Lower order cross-connect capacity: 20 Gbit/s

Access capacity: 40 Gbit/s

The cross-connect capacity of the Q6CXLLN is as follows:


l

Higher order cross-connect capacity: 110 Gbit/s

Lower order cross-connect capacity: 20 Gbit/s

Access capacity: 90 Gbit/s

Clock Access Capability


The clock access capability of the CXLLN is as follows:
l

External input clock: two channels of 2048 kbit/s or 2048 kHz external clock signals

External output clock: two channels of 2048 kbit/s or 2048 kHz external clock signals

Laser Safety Class


The safety class of the laser on the board is Class 1. The maximum launched optical power of
the optical interfaces is less than 10 dBm (10 mW).

Mechanical Specifications
The mechanical specifications of the CXLLN are as follows:
l

Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)

Weight of the Q5CXLLN (kg): 1.0

Weight of the Q6CXLLN (kg): 1.5

Power Consumption
The maximum power consumption of the Q5CXLLN at room temperature (25C) is 32 W.
The maximum power consumption of the Q6CXLLN at room temperature (25C) is 48 W.

9-18

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9.2 CXLQ41
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the CXLQ41 (4xSTM-4/STM-1 SCC unit, cross-connect unit, timing
unit, and line unit integrated board).
9.2.1 Version Description
The CXLQ41 is available in two functional versions, namely, Q5 and Q6.
9.2.2 Functions and Features
The CXLQ41 processes SDH signals, controls communication, grooms services, and inputs/
outputs clock signals.
9.2.3 Working Principle and Signal Flow
The CXLQ41 consists of the synchronous timing module, O/E converting module, MUX/
DEMUX module, SDH overhead processing module, communication and control module, crossconnect module, and DC/DC converter.
9.2.4 Jumpers and DIP Switches
The CXLQ41 has jumpers, which are used to set the enable state of the battery, and a DIP switch,
which is used to set the running state of the equipment.
9.2.5 Front Panel
The front panel of the CXLQ41 has indicators, interfaces, a bar code, functional button switches,
and a laser safety class label.
9.2.6 Valid Slots
The CXLQ41 can be installed in slot 9 or slot 10 in the subrack.
9.2.7 Feature Code
The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the CXLQ41 indicates the type of optical interface. The CXLQ41 supports
optical modules of different configurations. Therefore, no specific feature code is provided.
9.2.8 Parameter Settings
The physical slot that houses the CXLQ41 is different from the logical slot displayed on the
T2000. You can set the parameters for the CXLQ41 by using the T2000.
9.2.9 Technical Specifications
The technical specifications of the CXLQ41 include the parameters specified for optical
interfaces, cross-connect capacity, clock access capability, laser safety class, mechanical
specifications, and power consumption.

9.2.1 Version Description


The CXLQ41 is available in two functional versions, namely, Q5 and Q6.
Table 9-16 describes the versions of the CXLQ41.

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Hardware Description

Table 9-16 Versions of the CXLQ41


Item

Description

Functional
versions

The CXLQ41 is available in two functional versions, namely, Q5 and


Q6.

Differences

The Q5CXLQ41 supports the higher order cross-connection capacity


of 60 Gbit/s.

The Q6CXLQ41 supports the higher order cross-connection capacity


of 110 Gbit/s.

When the Q5CXLQ41 boards are used, the access capacity of slot 8
is 5 Gbit/s and the access capacity of the other service slots is 2.5
Gbit/s.

When the Q6CXLQ41 boards are used, the total access capacity of
slots 7, 8, 11, and 12 is 10 Gbit/s and the total access capacity of the
other service slots is 5 Gbit/s.

None

Substitution

9.2.2 Functions and Features


The CXLQ41 processes SDH signals, controls communication, grooms services, and inputs/
outputs clock signals.

SDH Processing Unit


Table 9-17 provides the functions and features of the SDH processing unit of the CXLQ41.
Table 9-17 Functions and features of the SDH processing unit of the CXLQ41

9-20

Function and
Feature

CXLQ41

Basic functions

Transmits and receives 4xSTM-1/STM-4 optical signals.

Specifications of the
optical interface

The STM-1/STM-4 optical module can be used.


l

At the STM-1 level, the standard I-1, S-1.1, L-1.1, L-1.2, and
Ve-1.2 optical interfaces are supported. The optical interfaces of
I-1, S-1.1, L-1.1, and L-1.2 types comply with ITU-T G.957, and
the optical interface of the Ve-1.2 type complies with the standards
defined by Huawei.

At the STM-4 level, the standard I-4, S-4.1, L-4.1, L-4.2, and
Ve-4.2 optical interfaces are supported. The optical interfaces of
the I-4, S-4.1, L-4.1, and L-4.2 types comply with ITU-T G.957,
and the optical interface of the Ve-4.2 type complies with the
standards defined by Huawei.

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Function and
Feature

CXLQ41

Specifications of the
optical module

Supports the detection and query of the information about the


optical module.

Provides the ALS function. The optical interface supports the


setting of the on/off state of a laser.

Supports the swappable optical modules, thus facilitating the


maintenance and upgrade of the optical modules.

Supports the installation of four optical modules with different


port rates.

The STM-1 module supports the VC-12/VC-3/VC-4 services.

The STM-4 module supports the VC-12/VC-3/VC-4 and VC-4-4c


concatenation services.

Processes the section overheads of the STM-1/STM-4 signals.

Supports the transparent transmission and termination of the path


overheads.

Supports the setting and query of the J0, J1, J2, and C2 bytes.

The Q5CXLQ41 supports the time synchronization feature and


transmission of the time information by using the section overhead
bytes.

Service processing

Overhead processing

Alarm and
performance event

Reports various alarms and performance events, which facilitates the


management and maintenance of the equipment.

Protection scheme

Supports the two-fiber ring MSP, four-fiber ring MSP, linear MSP,
SNCP, SNCTP, and SNCMP.

Maintenance feature

Supports inloops and outloops at optical interfaces.

Supports warm resets and cold resets. The warm reset does not
affect services.

Supports the query of the manufacturing information of the board.

Supports the in-service loading of the FPGA.

Supports the upgrade of the board software without affecting


services.

SCC Unit
Table 9-18 provides the functions and features of the SCC unit of the CXLQ41.

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Hardware Description

Table 9-18 Functions and features of the SCC unit of the CXLQ41
Function and
Feature

CXLQ41

Basic functions

Configures and monitors services, monitors the service performance,


and collects the information about the performance events and
alarms.

Specifications of the
optical interface

Provides one 10M/100M compatible Ethernet NM interface,


which is accessed through the AUX board.

Provides one 10M/100M Ethernet port, which is used for


implementing the inter-board communication.

Provides one 10M Ethernet port, which is used for implementing


the communication between the active and standby SCC boards.

Provides the RS232 OAM interface, which is accessed through the


SEI board and is used for connecting a PC or workstation. Supports
the remote maintenance by using the RS232 DCE modem.

Supports the receiving of the check result of the NE ID and


provides the interface for querying the check result.

Provides one orderwire interface, which is accessed through the


EOW board.

Provides four broadcast data ports (serial14), which are accessed


through the EOW board.

DCC processing
capability

Processes 80 channels of DCC signals.

Fan alarm
management

Manages fan alarms.

PIU management

Supports the in-service check function for the PIU board and supports
the failure check function for the lightning protection module of the
PIU.

Protection scheme

Supports 1+1 hot backup.

Cross-Connect Unit
Table 9-19 provides the functions and features of the cross-connect unit of the CXLQ41.

9-22

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Table 9-19 Functions and features of the cross-connect unit of the CXLQ41
Function and
Feature

CXLQ41

Basic functions

The Q5CXLQ41 realizes 60 Gbit/s higher order cross-connection


at the VC-4 level, and 20 Gbit/s lower order cross-connection at
the VC-12 or VC-3 level.

The Q6CXLQ41 realizes 110 Gbit/s higher order cross-connection


at the VC-4 level and 20 Gbit/s lower order cross-connection at
the VC-12 or VC-3 level.

Fast emergency
channel

Provides two 4 Mbit/s HDLC fast emergency channels, which are


used for the MSP switching, SNCP switching, TPS, or other
functions.

Service processing

Dynamically grooms services.

Adds or deletes services without interrupting other services.

Supports the SNCP protection at the VC-4, VC-3 and VC-12


levels.

Supports a maximum of 1184 SNCP groups.

The STM-4 optical module supports the VC-4-4c concatenation


services.

Protection scheme

Supports the 1+1 hot backup (non-revertive, by default).

Clock Unit
Table 9-20 provides the functions and features of the clock unit of the CXLQ41.
Table 9-20 Functions and features of the clock unit of the CXLQ41
Function and
Feature

CXLQ41

Basic functions

Provides the standard system synchronization clock.

Other functions

Supports the extraction, insertion, and management of the SSM


and clock ID.

Supports the transmission of the DCC overhead information at two


external clock interfaces.

Inputs two-channel 2048 kHz or 2048 kbit/s timing signals, and


selects the external timing source.

Outputs two-channel 2048 kHz or 2048 kbit/s timing signals.

Input and output

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9.2.3 Working Principle and Signal Flow


The CXLQ41 consists of the synchronous timing module, O/E converting module, MUX/
DEMUX module, SDH overhead processing module, communication and control module, crossconnect module, and DC/DC converter.
Figure 9-5 shows the functional block diagram of the Q5CXLQ41/Q6CXLQ41.
Figure 9-5 Functional block diagram of the Q5CXLQ41/Q6CXLQ41
Synchronous
timing module
(SETS)

38 MHz
OSC

SETG
T0

155 MHz
PLL

STM-1/
STM-4

O/E

STM-1/
STM-4

E/O

155 Mbit/s/
4x155 Mbit/s
data
DEMUX

O/E
converting
module

Laser
shutdown

MUX

Performance
report

155 Mbit/s/
4x155 Mbit/s
data

SDH overhead
processing module
MS
RS
HPT
MST
A
T

K1/K2 byte
processing

Laser
control

155 MHz
Cross-connect
unit

High-speed
bus

Another CXL
Another crossconnect unit

Cross-connect module
High-speed bus

DCC
DCC
processing

RAM NVRAM

Cross-connect
unit B
DCC

Line unit

Communication over ETH


channels
Communication between the active
and standby boards

Power monitor

Flash

High-speed
bus

Service unit
Service unit

Lower order crossconnect unit

Communication and control module

Boot
ROM

Higher order crossconnect unit

Line unit
Tributary unit
AUX/SEI
AUX/SEI

High-speed bus

K1/K2
insertion/
extraction

K1/K2 byte

T1
T2
T3
T4
(clock external output)
Frame header
T0 (reference clock)

ETH port
OAM interface
F&f interface
Phone interface
S1-S4 interface
+3.3 V

Power Fuse
module

Other units
Another CXL
AUX
SEI
EOW

-48 V/-60 V
-48 V/-60 V

Power
module

Synchronous Timing Module


The synchronous timing module provides the system clock (T0) for the service board, the control
unit, and the cross-connect unit in centralized timing distribution mode. This module also selects
one from the reference clock sources as the reference clock for synchronous timing. The
reference clock sources are from the line board (T1), the tributary board (T2), or the external
synchronous clock source (T3). The synchronous system clock source (T0) and 2 Mbit/s external
synchronous source (T4) are generated. The boards adopt the 1+1 hot backup. Hence, both the
active and standby boards trace the same reference source.
The synchronous timing module can extract timing from three types of timing signal:

9-24

Timing signal (T1) from the STM-N line

Timing signal (T2) from the PDH line


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l

9 Cross-Connect Boards and System Control Boards

Reference signal (T3) from the external synchronous clock source (2 MHz or 2 Mbit/s)

The timing module outputs the following timing signals:


l

T0, system clock (38 MHz)

T4, external timing output signal (2 Mbit/s or 2 MHz)

O/E Converting Module


l

Converts the received optical signals into electrical signals, in the receive direction.

Converts the electrical signals into SDH optical signals, and then sends the SDH optical
signals to fibers for transmission, in the transmit direction.

The SPI detects the R_LOS alarm and provides the laser shut down function.

MUX/DEMUX Module
l

In the receive direction, the DEMUX part demultiplexes the high rate electrical signals into
multiple parallel electrical signals, and recovers the clock signal at the same time.

In the transmit direction, the MUX part multiplexes the parallel electrical signals received
from the SDH overhead processing module into high rate electrical signals.

SDH Overhead Processing Module


It includes RST, MST, MSA, and HPT and provides the inloop and outloop functions.
l

Issue 02 (2009-07-30)

RST

Performs frame alignment detection (A1 and A2), regenerator section trace recovery
(J0), and mismatch detection, BIP-8 errored block count, in the receive direction.

Performs frame alignment insertion, regenerator section path tracer insertion, and BIP-8
calculation and insertion, in the transmit direction.

MST

Performs BIP-24 errored block count, MS_REI recovery, and MS_RDI and MS_AIS
detection, in the receive direction.

Performs BIP-24 calculation and insertion, and MS_REI, MS_RDI, and MS_AIS
insertion, in the transmit direction.

Extracts or inserts the K1 byte and K2 byte.

MSA

Performs pointer interpretation, AU_LOP and AU_AIS detection, and pointer


justification at the AU-4 level, in the receive direction.

Performs AUG assembly, AU-4 pointer regeneration, and AU_AIS generation, in the
transmit direction.

HPT

Terminates the overheads.

Recovers the J1 path trace message.

Recovers the REI information.

Detects the HP_RDI, that is, monitors the path status.

Detects the HP_UNEQ and AIS, that is, monitors the signal label.
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Performs VC-4 BIP-8 errored block count.

Communication and Control Module


l

Traces the clock signal from the active and standby cross-connect units.

Implements the laser controlling function.

Selects the clock signal and frame header signal from the active and standby cross-connect
units.

Controls the indicators on the board.

Provides the CPU control unit, which controls and monitors the other functional modules.
The unit also initializes the other functional modules after it is powered on.

Provides the ETH port, which functions as the 10M/100M Ethernet port for network
management.

Provides the OAM interface, which functions as the serial port for network management.
This port can be used as the MODEM port and thus can be configured as a serial port for
connecting to the MODEM port that is in the running state.

Provides the COM interface, which functions as the commissioning port.

Provides the Ethernet port, namely, a 10 Mbit/s Ethernet port, for inter-board
communication between the active and standby CXL units.

Cross-Connect Module
The cross-connect module consists of two parts:
l

SNCP module, which tests relative alarms and reports the alarms to the software to trigger
the protection switching such as the SNCP switching and MSP switching.

Higher order and lower order cross-connect module, which performs the functions of higher
order and lower order cross-connect units.

Other Functions
l

Responses to and processes the K bytes.

Collects the performance data of the optical module and disables the output of the optical
module.

Collects and processes DCC signal of each board.

Inserts the DCC signal back into each line board after processing.

Monitors the power supply of the board.

Performs the reset of the units.

Mutes alarms.

DC/DC Converter
It converts the 48/60 V power supply into the DC voltages that the modules of the board
require.

9.2.4 Jumpers and DIP Switches


The CXLQ41 has jumpers, which are used to set the enable state of the battery, and a DIP switch,
which is used to set the running state of the equipment.
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CAUTION
The jumpers and DIP switch are used for test and maintenance. Do not change the setting of the
jumper at random. Otherwise, the board may become faulty.
Figure 9-6 shows the jumpers and DIP switch of the Q5CXLQ41.
Figure 9-6 Positions of the jumpers and DIP switch of the Q5CXLQ41

Power
module

SW1
123 4

J24
3 21

CPU
CF
card

1
2
3

J10

Figure 9-7 shows the jumper and DIP switch of the Q6CXLQ41.

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Figure 9-7 Positions of the jumper and DIP switch of the Q6CXLQ41

Pow er
module

SW1
12 34

CPU
1
2
3

J10

Table 9-21 lists the jumpers of the Q5CXLQ41.


Table 9-21 Jumpers of the Q5CXLQ41
Jumper

Function

Description

J10

To enable the
battery

12: If jumper bits (positions) 1 and 2 are capped, the


battery is enabled.
23: If jumper bits (positions) 2 and 3 are capped, the
database and clock are cleared.

J24

To use the
maximum DCC
channels

12: If jumper bits (positions) 1 and 2 are capped,


the maximum of 40 DCC channels are used.

23: If jumper bits (positions) 2 and 3 are capped,


the maximum of 160 DCC channels are used.

Table 9-22 lists the jumper of the Q6CXLQ41.

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Table 9-22 Jumper of the Q6CXLQ41


Jumper

Function

Description

J10

To enable the
battery

12: If jumper bits (positions) 1 and 2 are capped, the


battery is enabled.
23: If jumper bits (positions) 2 and 3 are capped, the
database and clock are cleared.

Table 9-23 lists the DIP switch of the CXLQ41.


Table 9-23 DIP switch of the CXLQ41
Jumper

Function

Description

SW1

To set the running


state of the board

When a DIP switch bit is at the on position, it


indicates the binary value 1.

The DIP switch is a four-bit DIP switch. The values


of the DIP switch bits are queued in the descending
order of the switch bit numbers. The DIP switch bit
numbered 4 is the most significant bit. For details,
refer to Table 9-24.

Table 9-24 DIP switch SW1


Value

Description

0b0000

Indicates the running state when the watchdog is started. It is the default
state.

0b0011

Indicates the commissioning state when the watchdog is stopped.

0b0100

Indicates the running state when the watchdog is stopped.

0b1011

Erases the database.

0b1100

Erases the NE software, including the patches.

0b1101

Erases the database and NE software, including the patches.

0b1110

Erases the database, NE software, and NE.ini file.

0b1111

Erases the extended BIOS and system parameter area in the file system
and flash memory.

9.2.5 Front Panel


The front panel of the CXLQ41 has indicators, interfaces, a bar code, functional button switches,
and a laser safety class label.
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Diagram of the Front Panel


Figure 9-8 shows the appearance of the front panel of the CXLQ41.
Figure 9-8 Front panel of the CXLQ41

CXLQ41
STAT
ACTX
ACTC
PROG
SRVX
SRVL
SYNC
ALMC
CLASS 1
LASER
PRODUCT

OUT1
IN1
OUT2
IN2
OUT3
IN3
OUT4
IN4
RESET

ALM CUT

CXLQ41

Indicators
The front panel of the board has the following indicators:

9-30

Board hardware status indicator (STAT) two colors (red and green)

Active/Standby state indicator of the cross-connect unit (ACTX) one color (green)

Active/Standby state indicator of the SCC unit (ACTC) one color (green)

Board software status indicator (PROG) two colors (red and green)

Service alarm indicator of the cross-connect unit (SRVX) three colors (red, green, and
yellow)
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Service alarm indicator of the line unit (SRVL) three colors (red, green, and yellow)

Synchronization clock status indicator (SYNC) two colors (red and green)

Alarm mute indicator (ALMC) one color (yellow)

For the meanings of the status of the indicators, see A Indicators.

Interfaces
The front panel of the CXLQ41 has four optical interfaces and two switches. Table 9-25
describes the types and usage of the interfaces and switches of the CXLQ41.
Table 9-25 Optical interfaces and switches of the CXLQ41
Interface/
Switch

Type of
Interface/
Switch

Usage

IN1/OUT1

LC

Transmits and receives the first channel of optical signal.

IN2/OUT2

LC

Transmits and receives the second channel of optical


signal.

IN3/OUT3

LC

Transmits and receives the third channel of optical


signal.

IN4/OUT4

LC

Transmits and receives the fourth channel of optical


signal.

RESET

Warm reset
switch

Press the switch to perform a warm reset for the SCC


unit.

ALM CUT

Alarm cut
switch

Press the switch to mute the alarm. Press the switch for
five seconds to mute the alarm permanently. Press the
switch again for five seconds to resume the alarm sound.

9.2.6 Valid Slots


The CXLQ41 can be installed in slot 9 or slot 10 in the subrack.

9.2.7 Feature Code


The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the CXLQ41 indicates the type of optical interface. The CXLQ41 supports
optical modules of different configurations. Therefore, no specific feature code is provided.
For the types of optical modules that can be installed on the optical interfaces of the CXLQ41,
see B.2 Optical Module Labels

9.2.8 Parameter Settings


The physical slot that houses the CXLQ41 is different from the logical slot displayed on the
T2000. You can set the parameters for the CXLQ41 by using the T2000.
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Displayed Slots
The CXLQ41 occupies one slot in the subrack.
Table 9-26 lists the slots for the logical boards displayed on the T2000.
Table 9-26 Logical slots displayed on the T2000 for the Q5CXLQ41
Board

Logical
Board

Logical Slot

CXLQ41

UCXL

Slot 9 or slot 10

GSCC

Slot 17 or slot 18

Q2SLQ41

Slot 19 or slot 20

The logical boards for the Q6CXLQ41 are the Q2SLQ41, SCXL, and GSCC.
Table 9-27 lists the slots for the logical boards displayed on the T2000.
Table 9-27 Logical slots displayed on the T2000 for the Q6CXLQ41
Board

Logical
Board

Logical Slot

CXLQ41

SCXL

Slot 9 or slot 10

GSCC

Slot 17 or slot 18

Q2SLQ41

Slot 19 or slot 20

Board Parameters
You can set the following parameters for the CXLQ41 by using the T2000:
l

J0 byte

J1 byte

J2 byte

C2 byte

Clock parameters

For the description of each parameter, see F Parameter Settings.

9.2.9 Technical Specifications


The technical specifications of the CXLQ41 include the parameters specified for optical
interfaces, cross-connect capacity, clock access capability, laser safety class, mechanical
specifications, and power consumption.
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Parameters Specified for Optical Interfaces


The CXLQ41 supports the STM-1 and STM-4 optical modules.
Table 9-28 lists the parameters specified for the optical interfaces of the CXLQ41 when the
STM-1 optical module is used.
Table 9-28 Parameters specified for the optical interfaces of the CXLQ41 when the STM-1
optical module is used
Parameter

Value

Nominal bit rate

155520 kbit/s

Line code pattern

NRZ

Application code

I-1

S-1.1

L-1.1

L-1.2

Ve-1.2

Transmission
distance (km)

0 to 2

2 to 15

20 to 40

60 to 80

80 to 100

Operating
wavelength range
(nm)

1260 to
1360

1261 to
1360

1263 to
1360

1480 to
1580

1480 to
1580

Type of fiber

Singlemode LC

Singlemode LC

Singlemode LC

Singlemode LC

Singlemode LC

Mean launched
optical power
(dBm)

-15 to -8

-15 to -8

-5 to 0

-5 to 0

-3 to 0

Receiver
sensitivity (dBm)

-23

-28

-34

-34

-34

Minimum
overload (dBm)

-8

-8

-10

-10

-10

Minimum
extinction ratio
(dB)

8.2

8.2

10

10

10

Table 9-29 lists the parameters specified for the optical interfaces of the CXLQ41 when the
STM-4 optical module is used.
Table 9-29 Parameters specified for the optical interfaces of the CXLQ41 when the STM-4
optical module is used

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Parameter

Value

Nominal bit rate

622080 kbit/s

Line code pattern

NRZ

Application code

I-4

S-4.1

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Parameter

Value

Transmission
distance (km)

0 to 2

2 to 15

20 to 40

50 to 80

80 to 100

Operating
wavelength range
(nm)

1261 to
1360

1274 to
1356

1280 to
1335

1480 to
1580

1480 to
1580

Type of fiber

Singlemode LC

Singlemode LC

Singlemode LC

Singlemode LC

Singlemode LC

Mean launched
optical power
(dBm)

-15 to -8

-15 to -8

-3 to -2

-3 to -2

-3 to -2

Receiver
sensitivity (dBm)

-23

-28

-28

-28

-34

Minimum
overload (dBm)

-8

-8

-8

-8

-13

Minimum
extinction ratio
(dB)

8.2

8.2

10

10

10.5

Cross-Connect Capacity
The cross-connect capacity of the Q5CXLQ41 is as follows:
l

Higher order cross-connect capacity: 60 Gbit/s

Lower order cross-connect capacity: 20 Gbit/s

Access capacity: 40 Gbit/s

The cross-connect capacity of the Q6CXLQ41 is as follows:


l

Higher order cross-connect capacity: 110 Gbit/s

Lower order cross-connect capacity: 20 Gbit/s

Access capacity: 90 Gbit/s

Clock Access Capability


The clock access capability of the CXLQ41 is described as follows:
l

External input clock: two channels of 2048 kbit/s or 2048 kHz external clock signals

External output clock: two channels of 2048 kbit/s or 2048 kHz external clock signals

Laser Safety Class


The safety class of the laser on the board is Class 1. The maximum launched optical power of
the optical interfaces is less than 10 dBm (10 mW).
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Mechanical Specifications
The mechanical specifications of the CXLQ41 are as follows:
l

Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)

Weight of the Q5CXLQ41 (kg): 1.0

Weight of the Q6CXLQ41 (kg): 1.5

Power Consumption
The maximum power consumption of the Q5CXLQ41 at room temperature (25C) is 32 W.
The maximum power consumption of the Q6CXLQ41 at room temperature (25C) is 48 W.

9.3 CXS
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the CXS (SCC unit, cross-connect unit, and timing unit integrated
board).
9.3.1 Version Description
The CXS is available in one functional versions, namely, Q5.
9.3.2 Functions and Features
The CXS controls communication, grooms services, and inputs/outputs clock signals.
9.3.3 Working Principle and Signal Flow
The CXS consists of the synchronous timing module, communication and control module, crossconnect module, DC/DC converter.
9.3.4 Jumpers and DIP Switches
The CXS has jumpers, which are used to set the enable state of the battery and the number of
ECCs, and a DIP switch, which is used to set the running state of the equipment.
9.3.5 Front Panel
The front panel of the CXS has indicators, interfaces, a bar code, functional button switches,
and a laser safety class label.
9.3.6 Valid Slots
The CXS can be installed in slot 9 or slot 10 in the subrack.
9.3.7 Parameter Settings
The physical slot that houses the CXS is different from the logical slot displayed on the T2000.
You can set the parameters for the CXS by using the T2000.
9.3.8 Technical Specifications
The technical specifications of the CXS include cross-connect capacity, clock access capability,
laser safety class, mechanical specifications, and power consumption.

9.3.1 Version Description


The CXS is available in one functional versions, namely, Q5.

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9.3.2 Functions and Features


The CXS controls communication, grooms services, and inputs/outputs clock signals.

SCC Unit
Table 9-30 provides the functions and features of the SCC unit of the CXS.
Table 9-30 Functions and features of the SCC unit of the CXS
Function and
Feature

CXS

Basic functions

Configures and monitors services, monitors the service performance,


and collects the information about the performance events and
alarms.

Specifications of the
optical interface

Provides one 10M/100M compatible Ethernet NM interface,


which is accessed through the AUX.

Provides one 10M/100M Ethernet port, which is used for


implementing the inter-board communication.

Provides one 10M Ethernet port, which is used for implementing


the communication between the active and standby SCC boards.

Provides the RS232 OAM interface, which is accessed through the


SEI and is used for connecting a PC or workstation. Supports the
remote maintenance by using the RS232 DCE modem.

Supports the receiving of the check result of the NE ID and


provides the interface for querying the check result.

Provides one orderwire interface, which is accessed through the


EOW board.

Provides four broadcast data ports (serial14), which are accessed


through the EOW board.

DCC processing
capability

Processes 80 channels of DCC signals.

Fan alarm
management

Manages fan alarms.

PIU management

Supports the in-service check function for the PIU board and supports
the failure check function for the lightning protection module of the
PIU.

Protection scheme

Supports 1+1 hot backup.

Cross-Connect Unit
Table 9-31 provides the functions and features of the cross-connect unit of the CXS.

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Table 9-31 Functions and features of the cross-connect unit of the CXS
Function and
Feature

CXS

Basic functions

Realizes 60 Gbit/s higher order cross-connection at the VC-4 level


and 20 Gbit/s lower order cross-connection at the VC-12 or VC-3
level when the board is installed on the new backplane, and realizes
20 Gbit/s higher order cross-connection at the VC-4 level and 20
Gbit/s lower order cross-connection at the VC-12 or VC-3 level when
the board is installed on the old backplane.

Fast emergency
channel

Provides two 4 Mbit/s HDLC fast emergency channels, which are


used for the MSP switching, SNCP switching, or other functions.

Service processing

Dynamically grooms services.

Adds or deletes services without interrupting other services.

Supports the SNCP protection at the VC-3 and VC-12 levels.

Supports a maximum of 1024 SNCP groups.

The STM-4 optical module supports the VC-4-4c concatenation


services.

Protection scheme

Supports the 1+1 hot backup (non-revertive, by default).

Clock Unit
Table 9-32 provides the functions and features of the clock unit of the CXS.
Table 9-32 Functions and features of the clock unit of the CXS
Function and
Feature

CXS

Basic functions

Provides the standard system synchronization clock.

Other functions

Supports the extraction, insertion, and management of the SSM


and clock ID.

Supports the transmission of the DCC overhead information at two


external clock interfaces.

Inputs two-channel 2048 kHz or 2048 kbit/s timing signals, and


selects the external timing source.

Outputs two-channel 2048 kHz or 2048 kbit/s timing signals.

Input and output

9.3.3 Working Principle and Signal Flow


The CXS consists of the synchronous timing module, communication and control module, crossconnect module, DC/DC converter.
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Figure 9-9 shows the functional block diagram of the CXS by describing how to process
1xSTM-1/STM-4 signals.
Figure 9-9 Functional block diagram of the CXS
Time &
synchronization
(SETS)

38MHz
OSC

T1
T2

SETG

T3
T4 (clock external output)

T0

Frame header
T0 (reference clock)

155MHz PLL

High-speed
bus

Line units
Tributary units
PIU
AUX
Service units
Service units

Another
CXS

XC
Cross-connection
(HPC)
High-speed
bus
SCC unit

Another crossconnect unit

XC
Cross-connection
(LPC)
ETH channel communication
Master and slaver board
communication

Communication and
control module

ETH interface
OAM interface

Boot
ROM

FLASH

RAM

NVRAM

Power monitor

F&f interface
Phone interface
S1-S4 interface

+3.3 V

DC/DC
converter

Fuse

Other units
Another CXS
AUX
AUX
EOW

-48 V/-60V
-48 V/-60V

DC/DC
converter

Synchronous Timing Module


The synchronous timing module provides the system clock (T0) for the service board, the control
unit, and the cross-connect unit in centralized timing distribution mode. This unit also selects
one from the 17 reference clock sources as the reference clock for synchronous timing. The
17 reference clock sources are from the line board (T1), the tributary board (T2), or the external
synchronous clock source (T3). The synchronous system clock source (T0) and 2 Mbit/s external
synchronous source (T4) are generated. The boards adopt the 1+1 hot backup. Hence, both the
active and standby boards trace the same reference source.
The synchronous timing module can extract timing from three types of timing signal:

9-38

Timing signal (T1) from the STM-N line

Timing signal (T2) from the PDH line


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l

9 Cross-Connect Boards and System Control Boards

Reference signal (T3) from the external synchronous clock source (2 MHz or 2 Mbit/s)

The timing module outputs the following timing signals:


l

T0, system clock (38 MHz)

T4, external timing (2 Mbit/s or 2 MHz) from the line

Communication and Control Module


l

Traces the clock signal from the active and standby cross-connect units.

Implements the laser controlling function.

Selects the clock signal and frame header signal from the active and standby cross-connect
units.

Controls the indicators on the board.

Provides the CPU control unit, which controls and monitors the other functional modules.
The unit also initializes the other functional modules after it is powered on.

Provides the ETH port, which functions as the 10M/100M Ethernet port for network
management.

Provides the OAM interface, which functions as the serial port for network management.
This port can be used as the MODEM port and thus can be configured as a serial port for
connecting to the MODEM port that is in the running state.

Provides the COM interface, which functions as the commissioning port.

Provides the Ethernet port, namely, a 10 Mbit/s Ethernet port, for inter-board
communication between the active and standby CXL units.

Cross-Connect Module
The cross-connect module consists of two parts:
l

SNCP module, which tests relative alarms and reports the alarms to the software, to trigger
the SNCP switching.

Higher order and lower order cross-connect module, which performs the functions of higher
order and lower order cross-connect units.

Other Functions
l

Monitors the power supply of the board.

Performs the reset of the units.

Mutes alarms.

DC/DC Converter
It converts the 48/60 V power supply into the DC voltages that the modules of the board
require.

9.3.4 Jumpers and DIP Switches


The CXS has jumpers, which are used to set the enable state of the battery and the number of
ECCs, and a DIP switch, which is used to set the running state of the equipment.
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CAUTION
The jumpers and DIP switch are used for test and maintenance. Do not change the setting of the
jumper at random. Otherwise, the board may become faulty.
Figure 9-10 shows the jumpers and DIP switch of the CXS.
Figure 9-10 Positions of the jumpers and DIP switch of the CXS

Power
module

SW1
123 4

J24
3 21

CPU
CF
card

1
2
3

J10

Table 9-33 lists the jumpers of the CXS.


Table 9-33 Jumpers of the CXS
Jumper

Function

Description

J10

To enable the
battery

12: If jumper bits (positions) 1 and 2 are capped,


the battery is enabled.

23: If jumper bits (positions) 2 and 3 are capped,


the database and clock are cleared.

12: If jumper bits (positions) 1 and 2 are capped,


the maximum of 40 DCC channels are used.

23: If jumper bits (positions) 2 and 3 are capped,


the maximum of 80 DCC channels are used.

J24

To use the
maximum ECC
channels

Table 9-34 lists the DIP switch of the CXS.


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Table 9-34 DIP switch of the CXS


DIP Switch

Function

Description

SW1

To set the running


state of the board

When a DIP switch bit is at the on position, it


indicates the binary value 1.

The DIP switch is a four-bit DIP switch. The values


of the DIP switch bits are queued in the descending
order of the switch bit numbers. The DIP switch bit
numbered 4 is the most significant bit. For details,
refer to Table 9-35.

Table 9-35 DIP switch SW1


Value

Description

0b0000

Indicates the running state when the watchdog is started. It is the default
state.

0b0011

Indicates the commissioning state when the watchdog is stopped.

0b0100

Indicates the running state when the watchdog is stopped.

0b1011

Erases the database.

0b1100

Erases the NE software, including the patches.

0b1101

Erases the database and NE software, including the patches.

0b1110

Erases the database, NE software, and NE.ini file.

0b1111

Erases the extended BIOS and system parameter area in the file system
and flash memory.

9.3.5 Front Panel


The front panel of the CXS has indicators, interfaces, a bar code, functional button switches,
and a laser safety class label.

Diagram of the Front Panel


Figure 9-11 shows the appearance of the front panel of the CXS.

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Figure 9-11 Front panel of the CXS

CXS
STAT
ACTX
ACTC
PROG
SRVX
SYNC
ALMC

CF R/W

RESET

ALM CUT

CXS

Indicators
The front panel of the board has the following indicators:
l

Board hardware status indicator (STAT) two colors (red and green)

Active/Standby state indicator of the cross-connect unit (ACTX) one color (green)

Active/Standby state indicator of the SCC unit (ACTC) one color (green)

Board software status indicator (PROG) two colors (red and green)

Service alarm indicator of the cross-connect unit (SRVX) three colors (red, green, and
yellow)

Synchronization clock status indicator (SYNC) two colors (red and green)

Alarm mute indicator (ALMC) one color (yellow)

For the meanings of the status of the indicators, see A Indicators.


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Interfaces
The front panel of the CXS has two switches. Table 9-36 describes the types and usage of the
switches of the CXS.
Table 9-36 Switches of the CXS
Switch

Type of
Switch

Usage

RESET

Warm reset
switch

Press the switch to perform a warm reset for the SCC unit.

ALM CUT

Alarm cut
switch

Press the switch to mute the alarm. Press the switch for five
seconds to mute the alarm permanently. Press the switch
again for five seconds to resume the alarm sound.

9.3.6 Valid Slots


The CXS can be installed in slot 9 or slot 10 in the subrack.

9.3.7 Parameter Settings


The physical slot that houses the CXS is different from the logical slot displayed on the T2000.
You can set the parameters for the CXS by using the T2000.

Displayed Slots
The CXS occupies one slot in the subrack.
The logical boards for the CXS are the UCXL and GSCC.
Table 9-37 lists the slots for the logical boards displayed on the T2000.
Table 9-37 Logical slots displayed on the T2000 for the CXS
Board

Logical Board

Logical Slot

CXS

UCXL

Slot 9 or slot 10

GSCC

Slot 17 or slot 18

Board Parameters
You can set the following parameters for the CXS by using the T2000:
l

C2 byte

Clock parameters

For the description of each parameter, see F Parameter Settings.


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9.3.8 Technical Specifications


The technical specifications of the CXS include cross-connect capacity, clock access capability,
laser safety class, mechanical specifications, and power consumption.

Cross-Connect Capacity
The cross-connect capacity of the CXS is as follows:
l

Higher order cross-connect capacity: 60 Gbit/s

Lower order cross-connect capacity: 20 Gbit/s

Access capacity: 40 Gbit/s

Clock Access Capability


The clock access capability of the CXS is as follows:
l

External input clock: two channels of 2048 kbit/s or 2048 kHz external clock signals

External output clock: two channels of 2048 kbit/s or 2048 kHz external clock signals

Mechanical Specifications
The mechanical specifications of the CXS are as follows:
l

Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)

Weight (kg): 0.8

Power Consumption
The maximum power consumption of the CXS at room temperature (25C) is 28 W.

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10

10 Auxiliary Boards

Auxiliary Boards

About This Chapter


This topic describes the auxiliary boards including the AUX, EOW, SEI, FAN, FANA, and
FANB.
10.1 EOW
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the EOW (orderwire processing board).
10.2 AUX
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the AUX (system auxiliary interface board).
10.3 SEI
This topic describes the version, functions, working principle, front panel, valid slots and
technical specifications of the SEI (signal extended interface board).
10.4 FAN/FANB
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the FAN/FANB (fan board).
10.5 FANA
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the FANA (fan board).

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10 Auxiliary Boards

10.1 EOW
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the EOW (orderwire processing board).
10.1.1 Version Description
The EOW is available in one functional versions, namely, R1.
10.1.2 Functions and Features
The EOW extracts, inserts, and processes the overhead bytes E1 and E2, and other data bytes.
10.1.3 Working Principle and Signal Flow
The EOW consists of the clock module, overhead processing module, and power module.
10.1.4 Front Panel
The front panel of the EOW has indicators and interfaces.
10.1.5 Valid Slots
The EOW can be installed in slot 43 in the subrack.
10.1.6 Technical Specifications
The technical specifications of the EOW include the mechanical specifications and power
consumption.

10.1.1 Version Description


The EOW is available in one functional versions, namely, R1.

10.1.2 Functions and Features


The EOW extracts, inserts, and processes the overhead bytes E1 and E2, and other data bytes.
Table 10-1 provides the functions and features of the EOW.
Table 10-1 Functions and features of the EOW

10-2

Function and
Feature

EOW

Auxiliary interface

Provides the serial interfaces Serial 1Serial 4, which can function


as four broadcast data interfaces or two pairs of time interfaces. The
two functions of the interfaces are mutually exclusive.

The two pairs of time interfaces work in full-duplex mode and


support synchronous time input and output of two channels.

The time interface supports the RS-422 level only. The broadcast
data interface supports the RS-422 level and RS-232 level.

Orderwire interface

Provides one orderwire interface.

Overhead
processing

Processes the E1, E2, and Serial 1Serial 4 bytes.

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10 Auxiliary Boards

Function and
Feature

EOW

Power supply
checking

Monitors all the power supplies of the board (except the 48 V power),
supports the power supply switching when the primary power supply
enters the undervoltage state, and supports the power overvoltage
alarm and power undervoltage alarm. The undervoltage threshold is
3.45 V and the overvoltage threshold is 3.82 V.

High-precision
time

Supports the time synchronization feature, and complies with the IEEE
1588 V2 protocol.

10.1.3 Working Principle and Signal Flow


The EOW consists of the clock module, overhead processing module, and power module.
Figure 10-1 shows the functional block diagram of the EOW.
Figure 10-1 Functional block diagram of the EOW
Refercen clock

Clock
module
Serial 1Serial4
E1/E2

Overhead
processing
module

CXL unit

CXL unit

Power
module

-48 V

Clock Module
The clock module extracts and processes the reference clock signal from the CXL.

Overhead Processing Module


This module processes E1, E2, F1, and Serial 1Serial 4 bytes. Figure 10-2 shows the positions
of the orderwire bytes in the SDH frame.

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Figure 10-2 Positions of the orderwire bytes in the SDH frame


A1

A1

A1

A2

A2

A2

J0

B1

E1

F1

D1

D2

D3

Serial 1 Serial2

AU_PTR
B2

B2

D4

Serial 4

B2

K1

K2

D5

D6

D7

D8

D9

D10

D11

D12

S1

M1

Serial3

E2

Power Module
The power module provides the working power supply for the EOW, combines two channels of
48 V power supplies, converts the 48 V power supply into the +3.6 V power supply, switches
the active and standby +3.3 V power supplies, and generates the +1.8 V power supply.
NOTE

The EOW supports the power input in both DC-C mode and DC-I mode. The 48 V ground (BGND) cannot
be connected to the +3.3 V ground (GND) in DC-I mode.

10.1.4 Front Panel


The front panel of the EOW has indicators and interfaces.

Diagram of the Front Panel


Figure 10-3 shows the appearance of the front panel of the EOW.

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Figure 10-3 Front panel of the EOW

EOW
STAT
PROG

PHONE
S1
S2
S3
S4

EOW

Indicators
The front panel of the board has the following indicators:
l

Board hardware status indicator (STAT) two colors (red and green)

Board software status indicator (PROG) two colors (red and green)

For the meanings of the status of the indicators, see A Indicators.

Interfaces
The front panel of the EOW has five indicators. Table 10-2 describes the types and usage of the
interfaces of the EOW.
Table 10-2 Interfaces of the EOW
Interface

Type of
Interface

Usage

PHONE

RJ-45

Orderwire phone interface

S1

RJ-45

Broadcast data interface S1

S2

RJ-45

Broadcast data interface S2

S3

RJ-45

Broadcast data interface S3

S4

RJ-45

Broadcast data interface S4

Note: S1/S3 and S2/S4 form a pair of time input and output interfaces.

Table 10-3 describes the pins of the PHONE interface.


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Table 10-3 Pins of the PHONE interface


Front View

Pin

Usage

Transmits signal 1.

Transmits signal 2.

1, 2, 3, 6, 7, 8

Unspecified

Table 10-4 describes the pins of the S1, S2, S3, and S4 interfaces.
Table 10-4 Pins of the S1, S2, S3, and S4 interfaces
Front View

Pin

Usage

RS-422 data transmitting (+)

RS-422 data transmitting ()

RS-422 data receiving (+)

Receive end for RS-232 data

Grounding

RS-422 data receiving ()

Unspecified

Transmit end for RS-232 data

10.1.5 Valid Slots


The EOW can be installed in slot 43 in the subrack.

10.1.6 Technical Specifications


The technical specifications of the EOW include the mechanical specifications and power
consumption.

Mechanical Specifications
The mechanical specifications of the EOW are as follows:
l

10-6

Dimensions (mm): 25.4 (W) x 220 x (D) x 111.8 (H)


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l

10 Auxiliary Boards

Weight: 0.4 kg

Power Consumption
At room temperature (25C), the maximum power consumption of the EOW is 10 W.

10.2 AUX
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the AUX (system auxiliary interface board).
10.2.1 Version Description
The AUX is available in one functional version, namely, Q1.
10.2.2 Functions and Features
The AUX provides various management and auxiliary interfaces for the system, and provides
the centralized backup for the +3.3 V power supply of the boards in the subrack.
10.2.3 Working Principle and Signal Flow
The AUX consists of the communication module, interface module, and power module.
10.2.4 Jumpers
The AUX has jumpers J1 and J6 that are used to set the input voltage as 48 V or 60 V.
10.2.5 Front Panel
The front panel of the AUX has interfaces of various types.The front panel of the AUX has
indicators and interfaces of various types.
10.2.6 Valid Slots
The AUX can be installed in slot 42 in the subrack.
10.2.7 Technical Specifications
The technical specifications of the AUX include the mechanical specifications and power
consumption.

10.2.1 Version Description


The AUX is available in one functional version, namely, Q1.

10.2.2 Functions and Features


The AUX provides various management and auxiliary interfaces for the system, and provides
the centralized backup for the +3.3 V power supply of the boards in the subrack.
Table 10-5 provides the functions and features of the AUX.

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Table 10-5 Functions and features of the AUX


Item

AUX

Management
interface

Provides the OAM interface, which supports the X.25 protocol.


The interface is available on the SEI.

Provides the management serial interface F&f. The interface is


available on the SEI.

Provides the 10M/100M NM interface.

Provides the 10M/100M Ethernet EXT interface to manage the


extended subrack.

Provides one F1 interface for the 64 kbit/s codirectional data


channel.

Auxiliary interface

Provides one F1 interface for the 64 kbit/s codirectional data channel.


The interfaces are available on the SEI.
Clock interface

Provides two BITS clock input interfaces and two BITS clock
output interfaces (impedance: 120 ohms).

Provides two BITS clock input interfaces and two BITS clock
output interfaces (impedance: 75 ohms).

The interfaces are available on the SEI.

Provides 16-input and 4-output alarm interfaces.

Provides 4-output alarm cascading interfaces.

Cabinet alarm
indicator

Provides four cabinet alarm indicator output interfaces.

Provides four cabinet alarm indicator input cascading interfaces.

Commissioning
interface

Provides one commissioning interface COM.

Internal
communication

Realizes communication between boards in the subrack.

Power supply backup


and checking

Monitors the two independent 48 V power supplies, detects the


overvoltage (72 V) and undervoltage (38.4 V) conditions, and
reports alarms to the SCC unit in the case of overvoltage or
undervoltage occurs.

Provides the centralized backup for the +3.3 V power supply of


the boards in the subrack, which realizes the 1:N protection for
the secondary power supply of each board.

Detects the overvoltage (+3.8 V) and undervoltage (+3.1 V)


conditions for the +3.3 V backup power supply.

Alarm interface

10-8

Audible alarm

Supports the audible alarm and the clearing of the audible alarm.

Ethernet port
connection status
checking

Supports the checking of the Ethernet port connection status.

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10 Auxiliary Boards

AUX

Note: The COM interface is used for internal commissioning only. That is, the COM interface
cannot be used for equipment monitoring. Otherwise, the Ethernet communication between
boards may become abnormal.

10.2.3 Working Principle and Signal Flow


The AUX consists of the communication module, interface module, and power module.
Figure 10-4 shows the functional block diagram of the AUX.
Figure 10-4 Functional block diagram of the AUX

SCC A
2-input and 2-output clock
interface
Cabinet alarm indicator interface

Interface
module

SCC B

Cabinet alarm indicator


cascading interface

Crossconnect
unit

ETH interface 100/10 Mbit/s


(VLAN A)
COM interface 100/10 Mbit/s
(VLAN B)

16x100/10 Mbit/s
Ethernet bus

Communication module

100/10 Mbit/s
100/10 Mbit/s

Power
module

Other
units

(VLAN B)

SCC A (VLAN A)
SCC B (VLAN A)

-48V

+3.3 V backup power supply


(SEI)

Le ve l
conve rting

+5 V
SEI

Communication Module
This module provides the network management interface for the active and standby GSCC
boards, OAM interface for remote maintenance, and interface for communication between
boards.

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Interface Module
Provides various auxiliary interfaces, including the ETH, OAM, cabinet alarm indicator
interface, and clock input/output interface.

Power Module
This module provides the working power supply for the board and centralized +3.3 V backup
power supply for the other boards.

10.2.4 Jumpers
The AUX has jumpers J1 and J6 that are used to set the input voltage as 48 V or 60 V.
Figure 10-5 shows the positions of the jumpers J1 and J6 on the AUX.

J1

Module

Power

Figure 10-5 Positions of the J1 and J6 on the AUX

J6

Table 10-6 describes the jumpers on the AUX.


Table 10-6 Jumpers on the AUX
Jumper

Function

Indication

J1, J6

To select the 48 V or
60 V input voltage

If the jumpers are not capped, the equipment uses


the power supply whose input voltage is 60 V.
If the jumpers are capped, the equipment uses the
power supply that whose input voltage is 48 V.

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10.2.5 Front Panel


The front panel of the AUX has interfaces of various types.The front panel of the AUX has
indicators and interfaces of various types.

Diagram of the Front Panel


Figure 10-6 shows the appearance of the front panel of the AUX.
Figure 10-6 Front panel of the AUX

AUX

ETH
COM
CLK
LAMP1
LAMP2

AUX

Interfaces
The front panel of the AUX has five interfaces. Table 10-7 describes the types and usage of the
interfaces of the AUX.
Table 10-7 Interfaces of the AUX
Interface

Type of
Interface

Usage

ETH

RJ-45

NM interface

COM

RJ-45

Commissioning interface

CLK

RJ-45

120-ohm external clock input/output interface

LAMP1

RJ-45

Cabinet alarm indicator output interface

LAMP2

RJ-45

Cabinet alarm indicator input cascading interface

Table 10-8 describes the pins of the CLK interface.


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Table 10-8 Pins of the CLK interface


Front View

Pin

Usage

120-ohm clock 1 receiving ()

120-ohm clock 1 receiving (+)

120-ohm clock 2 receiving ()

120-ohm clock 1 transmitting ()

120-ohm clock 1 transmitting (+)

120-ohm clock 2 receiving (+)

120-ohm clock 2 transmitting ()

120-ohm clock 2 transmitting (+)

Table 10-9 describes the pins of the ETH and COM interfaces.
Table 10-9 Pins of the ETH and COM interfaces
Front View

Pin

Usage

Transmitting (+)

Transmitting ()

Receiving (+)

Unspecified

Unspecified

Receiving ()

7, 8

Unspecified

Table 10-10 describes the pins of the LAMP1 and LAMP2 interfaces.
Table 10-10 Pins of the LAMP1 and LAMP2 interfaces
Front View

10-12

Pin

Usage

Critical alarm signal (+)

Critical alarm signal ()

Major alarm signal (+)

Power indicator driving signal


(+)

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10 Auxiliary Boards

Pin

Usage

Power indicator driving signal


()

Major alarm signal ()

Minor alarm signal (+)

Minor alarm signal ()

Connections for Alarm Cascading


l

Connections for alarm signal cascading

Figure 10-7 shows the connections when one or multiple cabinets input or output alarm signals.
Connect the alarm output interface to the alarm cascading interface of a lower level. Make the
connections one by one until the alarm output is connected to the centralized alarm system.
Figure 10-7 Connections for alarm input, alarm cascading, and alarm output
Cabinet1

Cabinet2

Subrack1

Centralized
alarm system

Subrack3

ALMO1

ALMO1

ALMO2

ALMO2

ALMI1

ALMI1

Subrack2

Subrack4

ALMO1

ALMO1

ALMO2

ALMO2

ALMI1

ALMI1

Connections of cabinet alarm indicators

Figure 10-8 shows the connections of the 4-channel cabinet alarm indicators. Connect LAMP1
of subrack 2 to LAMP2 of subrack 1. Finally, connect LAMP1 of subrack 1 to the indicator
interface at the top of the cabinet.

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Figure 10-8 Connections of cabinet alarm indicators


4 cabinet
alarm indicators

Cabinet indicator
subrack 1

LAMP1
LAMP2

subrack 2
LAMP1
LAMP2

10.2.6 Valid Slots


The AUX can be installed in slot 42 in the subrack.

10.2.7 Technical Specifications


The technical specifications of the AUX include the mechanical specifications and power
consumption.

Mechanical Specifications
The mechanical specifications of the AUX are as follows:
l

Dimensions (mm): 25.4 (W) x 220 x (D) x 111.8 (H)

Weight: 0.5 kg

Dimensions (mm): 25.4 (W) x 220 x (D) x 111.8 (H)

Weight: 1.0 kg

Power Consumption
At room temperature (25C), the maximum power consumption of the AUX is 12 W.

10.3 SEI
This topic describes the version, functions, working principle, front panel, valid slots and
technical specifications of the SEI (signal extended interface board).
10.3.1 Version Description
The SEI is available in one functional version, namely, N1.
10.3.2 Functions and Features
The SEI provides various auxiliary and management interfaces for the equipment.
10.3.3 Working Principle and Signal Flow
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The SEI consists of the cabinet alarm indicator and alarm cascading circuit, and the interface
protection and filter circuit.
10.3.4 Front Panel
The front panel of the SEI has interfaces of various types.
10.3.5 Valid Slots
The SEI can be installed in slot 32 in the subrack. This slot can also house the interface board.
10.3.6 Technical Specifications
The technical specifications of the SEI include the mechanical specifications and power
consumption.

10.3.1 Version Description


The SEI is available in one functional version, namely, N1.

10.3.2 Functions and Features


The SEI provides various auxiliary and management interfaces for the equipment.
Table 10-11 provides the functions and features of the SEI.
Table 10-11 Functions and features of the SEI
Item

SEI

Management
interface

Provides the OAM interface, which supports the X.25 protocol.

Provides the management serial interface F&f.

Auxiliary interface

Provides one F1 interface for the 64 kbit/s codirectional data channel.

Clock interface

Provides the 2M external clock interface whose impedance is 75


ohms.

Alarm interface

Provides 16-input and 4-output alarm interfaces.

Provides 4-output alarm cascading interfaces.

10.3.3 Working Principle and Signal Flow


The SEI consists of the cabinet alarm indicator and alarm cascading circuit, and the interface
protection and filter circuit.
The SEI accesses various control and management signals, performs protection and filter
functions for these signals, and transmits the signals to the for processing through the backplane.
Figure 10-9 shows the functional block diagram of the SEI.

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Figure 10-9 Functional block diagram of the SEI


Ouput of four cabinet indicators
Alarm cascading interface
F&f interface
Phone (one orderwire interface)

Cabinet alarm
indicator and
alarm cascading
circuit

Cabinet indicator
output
Alarm cascading

V1/V2 (NNI phone interface)


S1-S4 interface
F1 interface
8-input/4-output alarm interface

protection and
filter Interface
circuit

OAM interface

F&f
Phone
NNI phone
S1-S4
F1
Alarm input/output
OAM

2-in and 2-out clock interface

Clock input and


output

SAP

CXL unit

Interface Protection and Filter Circuit


This module performs protection and filter functions for the following interfaces:
l

8-input and 4-output alarm interface

Alarm cascading interface

F1 codirectional data interface

S1-S4 broadcast data interface

Orderwire and NNI audio interface

F&f interface

OAM serial interface for network management

2-input and 2-output BITS clock interface

This module also provides physical interfaces for all the previously listed interfaces.

Cabinet Alarm Indicator and Alarm Cascading Circuit


This module provides four alarm indicators at the top of the cabinet and alarm cascading
interfaces.

10.3.4 Front Panel


The front panel of the SEI has interfaces of various types.

Diagram of the Front Panel


Figure 10-10 shows the appearance of the front panel of the SEI.

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Figure 10-10 Front panel of the SEI

SEI
CLKO2
CLKI2
CLKO1
CLKI1
F1
OAM
F&f
ALMO1
ALMO2
ALMI1
ALMI2
ALMI3
ALMI4

SEI

Interfaces
The front panel of the SEI has five interfaces. Table 10-12 describes the types and usage of the
interfaces of the SEI.
Table 10-12 Interfaces of the SEI

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Interfac
e

Type of
Interface

Usage

Interfa
ce

Type of
Interfa
ce

Usage

ALMO1

RJ-45

Interface for 4channel alarm outputs

F1

RJ-45

F1 interface

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Interfac
e

Type of
Interface

Usage

Interfa
ce

Type of
Interfa
ce

Usage

ALMO2

RJ-45

Cascading interface
for 4-channel alarm
inputs

F&f

RJ-45

F&f interface

ALMI1

RJ-45

Interface for the 1st to


the 4th channels of
alarm inputs

CLKO1

SMB

75-ohm clock
output 1

ALMI2

RJ-45

Interface for the 5th to


the 8th channels of
alarm inputs

CLKI1

SMB

75-ohm clock input


1

ALMI3

RJ-45

Interface for the 9th to


the 12th channels of
alarm inputs

CLKO2

SMB

75-ohm clock
output 2

ALMI4

RJ-45

Interface for the 13th


to the 16th channels of
alarm inputs

CLKI2

SMB

75-ohm clock input


2

OAM

RJ-45

OAM interface

Table 10-13 Pins of the CLK1 and CLK2 interfaces


Front View

Pin

Usage

Receiving ()

Receiving (+)

Grounding

Transmitting ()

Transmitting (+)

Grounding

7, 8

Unspecified

Table 10-14 describes the pins of the F1 interface.

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Table 10-14 Pins of the F1 interface


Front View

Pin

Usage

Transmitting (+)

Transmitting ()

Receiving (+)

Unspecified

Unspecified

Receiving ()

7, 8

Unspecified

Table 10-15 describes the pins of the F&f interface.


Table 10-15 Pins of the F&f interface
Front View

Pin

Usage

Receive end for RS-232 data

Grounding

Transmit end for RS-232 data

1, 2, 3, 6, 7

Unspecified

Table 10-16 describes the pins of the PHONE, V1, and V2 interfaces.
Table 10-16 Pins of the PHONE, V1, and V2 interfaces
Front View

Pin

Usage

Signal 1

Signal 2

1, 2, 3, 6, 7, 8

Unspecified

Table 10-17 describes the pins of the LAMP1 and LAMP2 interfaces.
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Table 10-17 Pins of the LAMP1 and LAMP2 interfaces


Front View

Pin

Usage

Critical alarm signal (+)

Critical alarm signal ()

Major alarm signal (+)

Power indicator driving signal


(+)

Power indicator driving signal


()

Major alarm signal ()

Minor alarm signal (+)

Minor alarm signal ()

Table 10-18 describes the pins of the ALM01 and ALM02 interfaces.
Table 10-18 Pins of the ALM01 and ALM02 interfaces
Front View

Pin

Usage

Critical and major alarm signal output


(+)

Critical and major alarm signal output


()

Minor and warning alarm signal output


(+)

Alarm signal output 1 (+)

Alarm signal output 1 ()

Minor and warning alarm signal output


()

Alarm signal output 2 (+)

Alarm signal output 2 ()

Table 10-19 describes the pins of the OAM interface.

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Table 10-19 Pins of the OAM interface


Front View

Pin

Usage

Requests for transmission.

Transmits the DTE ready signal.

Transmits data.

Grounding

Grounding

Receives data.

Transmits the DCE ready signal.

Ready for receiving signals.

Table 10-20 describes the pins of the S1, S2, S3, and S4 interfaces.
Table 10-20 Pins of the S1, S2, S3, and S4 interfaces
Front View

Pin

Usage

RS-422 data transmitting (+)

RS-422 data transmitting ()

RS-422 data receiving (+)

Receive end for RS-232 data

Grounding

Receive end for RS-422 data

Unspecified

Transmit end for RS-232 data

Table 10-21 describes the pins of the ALMI1 interface.

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Table 10-21 Pins of the ALMI1 interface


Front View

Pin

Usage

Alarm input 1

Ground for alarm input 1

Alarm input 2

Alarm input 3

Ground for alarm input 3

Ground for alarm input 2

Alarm input 4

Ground for alarm input 4

Table 10-22 describes the pins of the ALMI2 interface.


Table 10-22 Pins of the ALMI2 interface
Front View

Pin

Usage

Alarm input 5

Ground for alarm input 5

Alarm input 6

Alarm input 7

Ground for alarm input 7

Ground for alarm input 6

Alarm input 8

Ground for alarm input 8

Connections for Alarm Cascading


Figure 10-11 shows the connections when one or multiple cabinets input or output alarm signals.
Connect the alarm output interface to the alarm cascading interface of a lower level. Make the
connections one by one until the alarm output is connected to the centralized alarm system.

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Figure 10-11 Connections for alarm input, alarm cascading, and alarm output
To the
centralized
alarm system
ALMO1 ALMO2

ALMO1 ALMO2

Subrack 1

Subrack 3

ALMO1 ALMO2

ALMO1 ALMO2

Subrack 2

Subrack 4

Cabinet 1

Cabinet 2

10.3.5 Valid Slots


The SEI can be installed in slot 32 in the subrack. This slot can also house the interface board.

10.3.6 Technical Specifications


The technical specifications of the SEI include the mechanical specifications and power
consumption.

Mechanical Specifications
The mechanical specifications of the SEI are as follows:
l

Dimensions (mm): 25.4 (W) x 100 (D) x 245.10 (H)

Weight: 0.9 kg

Power Consumption
At room temperature (25C), the maximum power consumption of the SEI is 1 W.

10.4 FAN/FANB
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the FAN/FANB (fan board).
10.4.1 Version Description
The FAN/FANB is available in one functional version, namely, N1.
10.4.2 Functions and Features
The FAN/FANBadjusts the fan speed, checks the fan status, reports the fault of the fan control
board, and reports the off-position alarm of the fan.
10.4.3 Working Principle and Signal Flow
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The FAN consists of the fan control unit and fan power supply unit.
10.4.4 Front Panel
The front panel of the FAN has indicators.
10.4.5 Valid Slots
The FAN/FANB can be installed in slots 4446 in the subrack.
10.4.6 Technical Specifications
The technical specifications of the FAN include the mechanical specifications, power
consumption, and working voltages.

10.4.1 Version Description


The FAN/FANB is available in one functional version, namely, N1.
The logical board of fan tray assembly XE1FAN is displayed as N1FAN on the T2000. The
XE1FAN is of the two-layer structure. The one-layer fan is no longer manufactured.
The logical board of fan tray assembly XE3FAN is displayed as N1FANB on the T2000. The
XE3FAN is of the two-layer structure. The one-layer fan is no longer manufactured.

10.4.2 Functions and Features


The FAN/FANBadjusts the fan speed, checks the fan status, reports the fault of the fan control
board, and reports the off-position alarm of the fan.
Table 10-23 provides the functions and features of the FAN/FANB.
Table 10-23 Functions and features of the FAN/FANB
Function and
Feature

FAN

Function of
intelligent speed
adjustment

In normal situations, all the fan tray assemblies operate normally.


When one fan tray assembly reports an alarm, the other fan tray
assemblies adjust the fan speed to operate at full speed.

Hot swapping
function

Provides the hot swapping function for the fan tray assembly.

Backup function

Provides the mutual backup function for the power supplies of the
fans in the fan tray assemblies.

Status checking

Supports the checking of the fan status.

Alarm function

Reports the fan alarm and in-service information.

NOTE

When one fan tray assembly of the three fan three assemblies fails, the system can work normally for
96 hours at the ambient temperature ranging from 0C to 45C.

The fan tray assembly must be replaced when one or more fans in each fan tray assembly of the three
fan tray assemblies are faulty.

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10.4.3 Working Principle and Signal Flow


The FAN consists of the fan control unit and fan power supply unit.
Figure 10-12 shows the functional block diagram of the XE1FAN. Figure 10-13 shows the
functional block diagram of the XE3FAN.
Figure 10-12 Functional block diagram of the XE1FAN
Status signal
Speed adjusting signal
Status signal

Fan control
unit
Fan

Alarm signal
Power
Fan power
supply
unit

External power supply 1


External power supply 2

Figure 10-13 shows the functional block diagram of the XE3FAN.


Figure 10-13 Functional block diagram of the XE3FAN
Status signal
Speed adjusting signal

Fan control
unit

Alarm signal

Fan

Power
Fan power
supply
unit

External power supply 1


External power supply 2

Fan Power Supply Unit


This unit provides the driving voltage for the fan to operate.

Fan Control Unit


The fan control units of the XE3FAN and XE1FAN perform different functions:
l

XE1FAN

The fan control unit controls the operation speed of the fan through the speed adjusting signal.
The fan control unit also detects its faults, faults in the fans, and faults in the fan power supply
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10 Auxiliary Boards

unit. When detecting any fault, the fan control unit reports alarm information and the SCC then
issues commands to enable other fans to operate at full speed. The fan control unit also receives
commands from the SCC when the temperature is very low, and stops the fans. The fan control
unit detects the fault in the fan power supply unit, speed adjusting signal, fan state, and in-position
state of the FAN.
l

XE3FAN

The fan control unit controls the operation speed of the fan through the speed adjusting signal.
The fan control unit also detects faults in the fans and itself. When detecting any fault, the fan
control unit reports alarm information and the SCC then issues commands to enable other fans
to operate at full speed. The fan control unit also receives commands from the SCC when the
temperature is very low, and stops the fans. The fan control unit detects the fault in the speed
adjusting signal, fan state, and in-position state of the FAN.

10.4.4 Front Panel


The front panel of the FAN has indicators.

Diagram of the Front Panel


The OptiX OSN equipment series use a modular fan platform.
One subrack uses three fan tray assemblies, as shown in Figure 10-14.
Figure 10-14 Modular fan tray assembly

10.4.5 Valid Slots


The FAN/FANB can be installed in slots 4446 in the subrack.

10.4.6 Technical Specifications


The technical specifications of the FAN include the mechanical specifications, power
consumption, and working voltages.
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Mechanical Specifications
The mechanical specifications of the FAN are as follows:
l

Dimensions (mm): 120 (W) x 120 (D) x 50.8 (H)

Weight of the XE1FAN: 1.5 kg

Weight of the XE3FAN:1.2 kg

Power Consumption
At room temperature (25C), the maximum power consumption of each fan assembly of the
XE1FAN is 16 W when the input voltage is -48 V.
At room temperature (25C), the maximum power consumption of each fan assembly of the
XE3FAN is 16 W when the input voltage is -48 V.

Working Voltages
The working voltages of the FAN can be -48 V20% DC or -60 V20% DC.

10.5 FANA
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the FANA (fan board).
10.5.1 Version Description
The FANA is available in one functional version, namely, N1.
10.5.2 Function and Feature
The FANA adjusts the fan speed, checks the fan status, reports the fault of the fan control board,
and reports the off-service alarm of the fan.
10.5.3 Working Principle and Signal Flow
The fan unit of the TE2FANA consists of the fan control unit and fans.
10.5.4 Front Panel
The front panel of the FANA has indicators.
10.5.5 Valid Slots
The FANA can be installed in slots 4446 in the subrack.
10.5.6 Technical Specifications
The technical specifications of the FANA include the mechanical specifications, power
consumption, and working voltages.

10.5.1 Version Description


The FANA is available in one functional version, namely, N1.
The logical boards of fan tray assemblies assembly TE2FANA is displayed as N1FANA on the
T2000. The TE2FANA is of the two-layer structure.
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10.5.2 Function and Feature


The FANA adjusts the fan speed, checks the fan status, reports the fault of the fan control board,
and reports the off-service alarm of the fan.
Table 10-24 provides the functions and features of the FANA.
Table 10-24 Functions and features of the FANA
Function and
Feature

FANA

Function of
intelligent speed
adjustment

Provides the following functions of intelligent speed adjustment:

Hot swapping
function

Provides the hot swapping function for the fan tray assembly.

Backup function

The TE2FANA does not support the mutual backup function for the
power supplies of the fans in the fan tray assemblies. The power
modules inside the fan tray assemblies function as a backup for each
other.

Status checking

Supports the checking of the fan status.

Alarm function

Reports the fan alarm and in-service information.

Automatically adjusts the fan speed.

Ensures that the fan operates at full speed, when the speed
adjustment signal is abnormal.

NOTE

When one fan tray assembly of the three fan three assemblies fails, the system can work normally for
96 hours at the ambient temperature ranging from 0C to 45C.

The fan tray assembly must be replaced when one or more fans in each fan tray assembly of the three
fan tray assemblies are faulty.

10.5.3 Working Principle and Signal Flow


The fan unit of the TE2FANA consists of the fan control unit and fans.
Figure 10-15 shows the functional block diagram of the TE2FANA.

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Figure 10-15 Functional block diagram of the TE2FANA


Status signal
Speed adjusting signal

Fan control
unit
Fan

Alarm signal

External power
supply 2

External power
supply 1

Fan Control Unit


The fan control unit controls the operation speed of the fan through the speed adjusting signal.
The fan control unit also detects faults in the fans and itself. When detecting any fault, the fan
control unit reports alarm information and the SCC then issues commands to enable the other
two fans to operate at full speed. The fan control unit also receives commands from the SCC
when the temperature is very low, and stops the fans. The fan control unit detects the fault in
the speed adjusting signal, fan state, and in-position state of the FAN.

10.5.4 Front Panel


The front panel of the FANA has indicators.

Diagram of the Front Panel


The OptiX OSN equipment series use a modular fan platform, as shown in Figure 10-16. One
subrack uses three fan tray assemblies.
Figure 10-16 Modular fan tray assembly

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Indicators
The indicator (STATE) on the front panel of the board indicates the running state of the hardware.
This indicator is red, green, or yellow when it is on.
For the meanings of the status of the indicator, see A Indicators.

10.5.5 Valid Slots


The FANA can be installed in slots 4446 in the subrack.

10.5.6 Technical Specifications


The technical specifications of the FANA include the mechanical specifications, power
consumption, and working voltages.

Mechanical Specifications
The mechanical specifications of the FANA are as follows:
l

Dimensions (mm): 120 (W) x 120 (D) x 50.8 (H)

Weight (kg): 1.2

Power Consumption
The maximum power consumption of the FANA at room temperature (25C) is 19 W when the
input voltage is -48 V.

Working Voltages
The working voltages of the FANA can be -48 V/-60 V20% DC.

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11 WDM Boards

11

WDM Boards

About This Chapter


The WDM boards include the CMR2, CMR4, MR2, MR2A, MR2C, MR4, LWX, and FIB.
11.1 CMR2
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the TN11CMR2 (2-channel optical add/drop multiplexing board).
11.2 CMR4
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the TN11CMR4 (4-channel optical add/drop multiplexing board).
11.3 MR2
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the TN11MR2 (2-channel optical add/drop multiplexing board).
11.4 MR2A
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the MR2A (2-channel optical add/drop multiplexing board).
11.5 MR2C
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the MR2C (2-channel optical add/drop multiplexing board).
11.6 MR4
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the TN11MR4 (4-channel optical add/drop multiplexing board).
11.7 LWX
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the LWX (arbitrary bit rate wavelength conversion board).
11.8 FIB
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the FIB (filter isolating board).

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11.1 CMR2
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the TN11CMR2 (2-channel optical add/drop multiplexing board).
11.1.1 Version Description
The CMR2 is available in one functional version, namely, TN11.
11.1.2 Functions and Features
The CMR2 is applied to the coarse wavelength division multiplexing (CWDM) system. The
channel spacing is 20 nm. The CMR2 supports the add/drop multiplexing function and channel
expansion function.
11.1.3 Working Principle and Signal Flow
The CMR2 consists of the OADM module, communication and control module, and power
module.
11.1.4 Front Panel
The front panel of the CMR2 has indicators, interfaces, and a laser safety class label.
11.1.5 Valid Slots
The CMR2 can be installed in slots 28 and 1116 in the subrack.
11.1.6 Feature Code
The feature code of the CMR2 contains eight characters, which indicate the wavelengths of the
two channels of optical signals processed by the CMR2.
11.1.7 Technical Specifications
The technical specifications of the CMR2 include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.

11.1.1 Version Description


The CMR2 is available in one functional version, namely, TN11.

11.1.2 Functions and Features


The CMR2 is applied to the coarse wavelength division multiplexing (CWDM) system. The
channel spacing is 20 nm. The CMR2 supports the add/drop multiplexing function and channel
expansion function.
Table 11-1 provides the functions and features of the CMR2.
Table 11-1 Functions and features of the CMR2

11-2

Function and
Feature

CMR2

Basic functions

Adds/Drops and multiplexes two signals to/from the multiplexed


signals.

Channel expansion

Provides the interface to cascade another optical add/drop


multiplexing board to realize the expansion of the add/drop channel.

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11.1.3 Working Principle and Signal Flow


The CMR2 consists of the OADM module, communication and control module, and power
module.
Figure 11-1 shows the functional block diagram of the CMR2.
Figure 11-1 Functional block diagram of the CMR2
D1

IN

D2

MO

MI

Drop optical
module

A1

A2

Add optical
module

OUT

OADM optical
module
Control
Memory

CPU

Communication

Control and communication module


Power supply
module
Fuse

Required
voltage

DC power supply
from a backplane

Backplane
(controlled by SCC)
SCC

The CMR2 contains the OADM module that adds, drops, and multiplexes two channels of
signals. In addition, the CMR2 provides the interface to cascade another optical add/drop
multiplexing board to increase the add/drop capability. The CMR2 is a passive board and does
not have an interface with the backplane.

OADM Module
The board receives one multiplexed optical signal that is sent by the upstream station on the IN
interface. Then, the drop optical module drops two wavelengths from the signal through optical
interfaces D01 and D02. The two dropped wavelengths are transmitted through the MO optical
interface.
The board receives one multiplexed signal that travels over the main optical path on the MI
optical interface. Then, the add optical module adds two wavelengths through optical interfaces
A01 and A02 and multiplexes them with the signal on the main optical path into one signal. This
multiplexed signal is transmitted through the OUT interface.
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Communication and Control Module


l

Controls the operations of the entire board.

Collects the following information of each functional module of the board: alarms,
performance events, working status, and voltage detection.

Communicates data with the SCC.

DC/DC Converter
It converts 48 V DC or 60 V DC into a voltage required by each module of the board.

11.1.4 Front Panel


The front panel of the CMR2 has indicators, interfaces, and a laser safety class label.

Diagram of the Front Panel


Figure 11-2 shows the appearance of the front panel of the CMR2.
Figure 11-2 Front panel of the CMR2

CMR2
STAT
LASER
RADIATION
DO NOT VIEW DIRECTLY
WITH OPTICAL
INSTRUMENTS

CLASS 1M LASER
PRODUCT

OUT
IN
MO
MI
D1
A1
D2
A2

CMR2

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Indicator
The front panel of the CMR2 has one indicator as follows: board hardware status indicator
(STAT) two colors (red and green)
For the meanings of the status of the indicator, see A Indicators.

Interfaces
The front panel of the CMR2 has eight optical interfaces. Table 11-2 describes the types and
usage of the optical interfaces of the CMR2.
Table 11-2 Optical interfaces of the CMR2
Interface

Type of
Interface

Usage

A1A2

LC

Receives the signals sent from the optical wavelength


converting board or centralized client-side equipment.

D1D2

LC

Transmits signals to the optical wavelength converting board


or centralized client-side equipment.

IN

LC

Receives the multiplexed signals.

OUT

LC

Transmits the multiplexed signals.

MO

LC

Works as a cascading output optical interface and is connected


to the input optical interface of an OADM board.

MI

LC

Works as a cascading input optical interface and is connected


to the output optical interface of an OADM board.

11.1.5 Valid Slots


The CMR2 can be installed in slots 28 and 1116 in the subrack.

11.1.6 Feature Code


The feature code of the CMR2 contains eight characters, which indicate the wavelengths of the
two channels of optical signals processed by the CMR2.
Table 11-3 describes the feature code of the CMR2.

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Table 11-3 Feature code of the CMR2


Feature Code

Indication

Description

First four characters

Wavelength of optical
signals

Indicates the wavelength of


the first channel of optical
signals processed by the
CMR2.

Last four characters

Wavelength of optical
signals

Indicates the wavelength of


the second channel of optical
signals processed by the
CMR2.

Consider the TN11CMR2 whose feature code is "14711571" as an example. The meaning of
the feature code of the TN11CMR2 is as follows:
l

"1471" indicates that the wavelength of the first channel of optical signals is 1471 nm.

"1571" indicates that the wavelength of the second channel of optical signals is 1571 nm.

11.1.7 Technical Specifications


The technical specifications of the CMR2 include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.

Parameters Specified for Optical Interfaces


Table 11-4 lists the parameters specified for the optical interfaces of the CMR2.
Table 11-4 Parameters specified for the optical interfaces of the CMR2
Optical
Interface

Parameter

Value

Operating wavelength range


(nm)

1271 to 1611

Channel spacing (nm)

20

IN-D1
IN-D2

0.5 dB passband bandwidth


(nm)

6.5

Insertion loss (dB) on the


drop channel

1.5

Adjacent channel isolation


(dB)

> 25

Non-adjacent channel
isolation (dB)

> 35

0.5 dB passband bandwidth


(nm)

6.5

A1-OUT
A2-OUT
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Optical
Interface

11 WDM Boards

Parameter

Value

Insertion loss (dB) on the add


channel

1.5

IN-MO
MI-OUT

Insertion loss (dB)

1.0

Isolation (dB)

> 13

Return loss (dB)

> 40

Laser Safety Class


The safety class of the laser on the board is Class 1M. The maximum launched optical power of
the optical interfaces is within the range from 10 dBm (10 mW) to 22.15 dBm (164 mW).

Mechanical Specifications
The mechanical specifications of the CMR2 are as follows:
l

Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)

Weight (kg): 0.8

Power Consumption
The power consumption of the CMR2 at room temperature (25C) is 0 W.

11.2 CMR4
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the TN11CMR4 (4-channel optical add/drop multiplexing board).
11.2.1 Version Description
The CMR4 is available in one functional version, namely, TN11.
11.2.2 Functions and Features
The CMR4 is applied to the CWDM system. The channel spacing is 20 nm. The CMR4 supports
the add/drop multiplexing function and channel expansion function.
11.2.3 Working Principle and Signal Flow
The CMR4 consists of the OADM module, communication and control module, and power
module.
11.2.4 Front Panel
The front panel of the CMR4 has indicators, interfaces, and a laser safety class label.
11.2.5 Valid Slots
The CMR4 can be installed in slots 28 and 1116 in the subrack.
11.2.6 Feature Code
The feature code of the CMR4 contains eight characters, which indicate the wavelengths of the
four channels of optical signals processed by the CMR4.
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11.2.7 Technical Specifications


The technical specifications of the CMR4 include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.

11.2.1 Version Description


The CMR4 is available in one functional version, namely, TN11.

11.2.2 Functions and Features


The CMR4 is applied to the CWDM system. The channel spacing is 20 nm. The CMR4 supports
the add/drop multiplexing function and channel expansion function.
Table 11-5 provides the functions and features of the CMR4.
Table 11-5 Functions and features of the CMR4
Function and
Feature

CMR4

Basic functions

Adds/Drops and multiplexes four signals to/from the multiplexed


signals.

Channel expansion

Provides the interface to cascade another optical add/drop


multiplexing board to realize the expansion of the add/drop channel.

11.2.3 Working Principle and Signal Flow


The CMR4 consists of the OADM module, communication and control module, and power
module.
Figure 11-3 shows the functional block diagram of the CMR4.

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Figure 11-3 Functional block diagram of the CMR4


D01 D02 D03 D04

MO

MI

A01 A02 A03 A04

Drop

IN

Add

OUT

OADM module

Communication and control module

Pow er module
DC/DC
converter
Delayed
startup
Fuse
SCC

Backplane

-48 V/-60 V

-48 V/-60 V

SCC

OADM Module
The board receives one multiplexed optical signal that is sent by the upstream station on the IN
interface. Then, the drop optical module drops four wavelengths from the signal through optical
interfaces D01D04. The four dropped wavelengths are transmitted through the MO optical
interface.
The board receives one multiplexed signal that travels over the main optical path on the MI
optical interface. Then, the add optical module adds four wavelengths through optical interfaces
A01A04 and multiplexes them with the signal on the main optical path into one signal. This
multiplexed signal is transmitted through the OUT interface.

Communication and Control Module


l

Controls the operations of the entire board.

Collects the following information of each functional module of the board: alarms,
performance events, working status, and voltage detection.

Communicates data with the SCC.

DC/DC Converter
It converts 48 V DC or 60 V DC into a voltage required by each module of the board.
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11.2.4 Front Panel


The front panel of the CMR4 has indicators, interfaces, and a laser safety class label.

Diagram of the Front Panel


Figure 11-4 shows the appearance of the front panel of the CMR4.
Figure 11-4 Front panel of the CMR4

CMR4
STAT
LASER
RADIATION
DO NOT VIEW DIRECTLY
WITH OPTICAL
INSTRUMENTS

CLASS 1M LASER
PRODUCT

OUT
IN
MO
MI
D1
A1
D2
A2
D3
A3
D4
A4

CMR4

Indicators
The front panel of the CMR4 has one indicator as follows: board hardware status indicator
(STAT) two colors (red and green)
For the meanings of the status of the indicator, see A Indicators.
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Interfaces
The front panel of the CMR4 has 12 optical interfaces. Table 11-6 describes the types and usage
of the optical interfaces of the CMR4.
Table 11-6 Optical interfaces of the CMR4
Interface

Type of
Interface

Usage

A1A4

LC

Receives the signals sent from the optical wavelength


converting board or centralized client-side equipment.

D1D4

LC

Transmits signals to the optical wavelength converting


board or centralized client-side equipment.

IN

LC

Receives the multiplexed signals.

OUT

LC

Transmits the multiplexed signals.

MO

LC

Works as a cascading output optical interface and is


connected to the input optical interface of an OADM
board.

MI

LC

Works as a cascading input optical interface and is


connected to the output optical interface of an OADM
board.

11.2.5 Valid Slots


The CMR4 can be installed in slots 28 and 1116 in the subrack.

11.2.6 Feature Code


The feature code of the CMR4 contains eight characters, which indicate the wavelengths of the
four channels of optical signals processed by the CMR4.
Table 11-7 describes the feature code of the CMR4.
Table 11-7 Feature code of the CMR4

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Feature Code

Indication

Description

1st and 2nd characters

Wavelength of optical
signals

The two characters are the


two middle characters of the
figure that indicates the
wavelength of the first
channel of optical signals
processed by the CMR4.

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Feature Code

Indication

Description

3rd and 4th characters

Wavelength of optical
signals

The two characters are the


two middle characters of the
figure that indicates the
wavelength of the second
channel of optical signals
processed by the CMR4.

5th and 6th characters

Wavelength of optical
signals

The two characters are the


two middle characters of the
figure that indicates the
wavelength of the third
channel of optical signals
processed by the CMR4.

7th and 8th characters

Wavelength of optical
signals

The two characters are the


two middle characters of the
figure that indicates the
wavelength of the fourth
channel of optical signals
processed by the CMR4.

Consider the TN11CMR4 whose feature code is "47495961" as an example. The meaning of
the feature code of the TN11CMR4 is as follows:
l

"47" indicates that the wavelength of the first channel of optical signals is 1471 nm.

"49" indicates that the wavelength of the second channel of optical signals is 1491 nm.

"59" indicates that the wavelength of the third channel of optical signals is 1591 nm.

"61" indicates that the wavelength of the fourth channel of optical signals is 1611 nm.

11.2.7 Technical Specifications


The technical specifications of the CMR4 include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.

Parameters Specified for Optical Interfaces


Table 11-8 lists the parameters specified for the optical interfaces of the CMR4.
Table 11-8 Parameters specified for the optical interfaces of the CMR4

11-12

Optical
Interface

Parameter

Value

Operating wavelength range


(nm)

1291 to 1611 (1371 nm excluded)

Channel spacing (nm)

20

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Optical
Interface

Parameter

Value

IN-D1
IN-D2
IN-D3
IN-D4

0.5 dB passband bandwidth


(nm)

6.5

Insertion loss (dB) on the


drop channel

Adjacent channel isolation


(dB)

> 25

Non-adjacent channel
isolation (dB)

> 35

A1-OUT
A2-OUT
A3-OUT
A4-OUT

0.5 dB passband bandwidth


(nm)

6.5

Insertion loss (dB) on the add


channel

IN-MO
MI-OUT

Insertion loss (dB)

1.5

Isolation (dB)

> 13

Return loss (dB)

> 40

Laser Safety Class


The safety class of the laser on the board is Class 1M. The maximum launched optical power of
the optical interfaces is within the range from 10 dBm (10 mW) to 22.15 dBm (164 mW).

Mechanical Specifications
The mechanical specifications of the CMR4 are as follows:
l

Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)

Weight (kg): 0.9

Power Consumption
The power consumption of the CMR4 at room temperature (25C) is 0 W.

11.3 MR2
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the TN11MR2 (2-channel optical add/drop multiplexing board).
11.3.1 Version Description
The MR2 is available in one functional version, namely, TN11.
11.3.2 Functions and Features
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The MR2 is applied to the dense wavelength division multiplexing (DWDM) system. The
channel spacing is 0.8 nm. The MR2 supports the add/drop multiplexing function and channel
expansion function.
11.3.3 Working Principle and Signal Flow
The MR2 consists of the OADM module, communication and control module, and power
module.
11.3.4 Front Panel
The front panel of the MR2 has indicators, interfaces, and a laser safety class label.
11.3.5 Valid Slots
The MR2 can be installed in slots 28 and 1116 in the subrack.
11.3.6 Feature Code
The feature code of the MR2 contains eight characters, which indicate the frequencies of the
two channels of optical signals processed by the MR2.
11.3.7 Technical Specifications
The technical specifications of the MR2 include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.

11.3.1 Version Description


The MR2 is available in one functional version, namely, TN11.

11.3.2 Functions and Features


The MR2 is applied to the dense wavelength division multiplexing (DWDM) system. The
channel spacing is 0.8 nm. The MR2 supports the add/drop multiplexing function and channel
expansion function.
Table 11-9 provides the functions and features of the MR2.
Table 11-9 Functions and features of the MR2
Function and
Feature

MR2

Basic functions

Adds/Drops and multiplexes two signals to/from the multiplexed


signals.

Channel expansion

Provides the interface to cascade another optical add/drop


multiplexing board to realize the expansion of the add/drop channel.

11.3.3 Working Principle and Signal Flow


The MR2 consists of the OADM module, communication and control module, and power
module.
Figure 11-5 shows the functional block diagram of the MR2.

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Figure 11-5 Functional block diagram of the MR2


D1

IN

D2

MO

MI

Drop optical
module

A1

A2

Add optical
module

OUT

OADM optical
module
Control
Memory

CPU

Communication

Control and communication module


Power supply
module
Fuse

Required
voltage

DC power supply
from a backplane

Backplane
(controlled by SCC)
SCC

OADM Module
The board receives one multiplexed optical signal that is sent by the upstream station on the IN
interface. Then, the drop optical module drops two wavelengths from the signal through optical
interfaces D01 and D02. The two dropped wavelengths are transmitted through the MO optical
interface.
The board receives one multiplexed signal that travels over the main optical path on the MI
optical interface. Then, the add optical module adds two wavelengths through optical interfaces
A01 and A02 and multiplexes them with the signal on the main optical path into one signal. This
multiplexed signal is transmitted through the OUT interface.

Communication and Control Module


l

Controls the operations of the entire board.

Collects the following information of each functional module of the board: alarms,
performance events, working status, and voltage detection.

Communicates data with the SCC.

DC/DC Converter
It converts 48 V DC or 60 V DC into a voltage required by each module of the board.
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11.3.4 Front Panel


The front panel of the MR2 has indicators, interfaces, and a laser safety class label.

Diagram of the Front Panel


Figure 11-6 shows the appearance of the front panel of the MR2.
Figure 11-6 Front panel of the MR2

MR2
STAT

LASER
RADIATION
DO NOT VIEW DIRECTLY
WITH OPTICAL
INSTRUMENTS

CLASS 1M LASER
PRODUCT

OUT
IN
MO
MI
D1
A1
D2
A2

MR2

Indicators
The front panel of the MR2 has one indicator as follows: board hardware status indicator (STAT)
two colors (red and green)
For the meanings of the status of the indicator, see A Indicators.
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Interfaces
The front panel of the MR2 has eight optical interfaces. Table 11-10 describes the types and
usage of the optical interfaces of the MR2.
Table 11-10 Optical interfaces of the MR2
Interface

Type of
Interface

Usage

A1A2

LC

Receives the signals sent from the optical wavelength


converting board or centralized client-side equipment.

D1D2

LC

Transmits signals to the optical wavelength converting


board or centralized client-side equipment.

IN

LC

Receives the multiplexed signals.

OUT

LC

Transmits the multiplexed signals.

MO

LC

Works as a cascading output optical interface and is


connected to the input optical interface of an OADM
board.

MI

LC

Works as a cascading input optical interface and is


connected to the output optical interface of an OADM
board.

11.3.5 Valid Slots


The MR2 can be installed in slots 28 and 1116 in the subrack.

11.3.6 Feature Code


The feature code of the MR2 contains eight characters, which indicate the frequencies of the
two channels of optical signals processed by the MR2.
Table 11-11 describes the feature code of the MR2.
Table 11-11 Feature code of the MR2

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Feature Code

Indication

Description

First four (14) characters

Frequency of optical signals

The four characters are the


last four characters of the
figure that indicates the
frequency of the first channel
of optical signals processed
by the MR2.

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Feature Code

Indication

Description

Last four (58) characters

Frequency of optical signals

The four characters are the


last four characters of the
figure that indicates the
frequency of the second
channel of optical signals
processed by the MR2.

Consider the TN11MR2 whose feature code is "93609370" as an example. The meaning of the
feature code of the TN11MR2 is as follows:
l

"9360" indicates that the frequency of the first channel of optical signals is 193.60 THz.

"9370" indicates that the frequency of the second channel of optical signals is 193.70 THz.

11.3.7 Technical Specifications


The technical specifications of the MR2 include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.

Parameters Specified for Optical Interfaces


Table 11-12 lists the parameters specified for the optical interfaces of the MR2.
Table 11-12 Parameters specified for the optical interfaces of the MR2
Optical
Interface

Parameter

Value

Operating wavelength range


(nm)

1529 to 1561

Channel spacing (GHz)

100

IN-D1
IN-D2

0.5 dB passband bandwidth


(nm)

0.11

Insertion loss (dB) on the


drop channel

1.5

Adjacent channel isolation


(dB)

> 25

Non-adjacent channel
isolation (dB)

> 35

0.5 dB passband bandwidth


(nm)

0.11

Insertion loss (dB) on the add


channel

1.5

Insertion loss (dB)

1.0

A1-OUT
A2-OUT

IN-MO
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Optical
Interface

Parameter

Value

MI-OUT

Isolation (dB)

> 13

Return loss (dB)

> 40

Laser Safety Class


The safety class of the laser on the board is Class 1M. The maximum launched optical power of
the optical interfaces is within the range from 10 dBm (10 mW) to 22.15 dBm (164 mW).

Mechanical Specifications
The mechanical specifications of the MR2 are as follows:
l

Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)

Weight (kg): 0.9

Power Consumption
The power consumption of the MR2 at room temperature (25C) is 0 W.

11.4 MR2A
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the MR2A (2-channel optical add/drop multiplexing board).
11.4.1 Version Description
The MR2A is available in one functional version, namely, N1.
11.4.2 Functions and Features
The MR2A is applied to the DWDM system. The channel spacing is 0.8 nm. The MR2A supports
the add/drop multiplexing function between any two adjacent wavelengths.
11.4.3 Working Principle and Signal Flow
The MR2A consists of the OADM module.
11.4.4 Front Panel
The front panel of the MR2A has interfaces and a laser safety class label.
11.4.5 Valid Slots
The MR2A can be installed in slots 28 and 1116 in the subrack.
11.4.6 Technical Specifications
The technical specifications of the MR2A include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.

11.4.1 Version Description


The MR2A is available in one functional version, namely, N1.
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11.4.2 Functions and Features


The MR2A is applied to the DWDM system. The channel spacing is 0.8 nm. The MR2A supports
the add/drop multiplexing function between any two adjacent wavelengths.
Table 11-13 provides the functions and features of the MR2A.
Table 11-13 Functions and features of the MR2A
Function and
Feature

MR2A

Basic functions

Adds/Drops any two adjacent standard wavelengths defined in ITUT G.692 (DWDM). The signals are transparently transmitted and the
operating wavelength ranges from 1535.82 nm to 1560.61 nm.

OTM function

One MR2A board can work as a two-channel add/drop OTM station,


as shown in Figure 11-7. Two MR2A boards can be cascaded to
work as a four-channel add/drop OTM station, as shown in Figure
11-8.

OADM function

Works as a two-channel add/drop OADM station when working with


the LWX. For details, see Figure 11-9.

Central wavelength

Supports the standard wavelengths defined in ITU-T


Recommendations. The channel spacing is 100 GHz.

Figure 11-7 One MR2A board working as a two-channel add/drop OTM station
D2

D1

IN

MO

Drop

OUT

MI

Add
MR2A
A1

A2

Figure 11-8 Two MR2A boards being cascaded to work as a four-channel add/drop OTM station
D2

D1

IN

Drop

OUT

MO IN

MR2A

D2

Drop

MI OUT

Add

MO

MI

Add
MR2A

A1

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D1

A2

A1

A2

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Figure 11-9 MR2A and LWX working as a two-channel add/drop OADM station

LWX
A2

D2
MO

Out

MI

MR2A

In
D1

A1
LWX

11.4.3 Working Principle and Signal Flow


The MR2A consists of the OADM module.
Figure 11-10 shows the functional block diagram of the MR2A.
Figure 11-10 Functional block diagram of the MR2A
D01

IN

D02

MO

MI

Drop

A01

A02

Add

OUT

OADM
module

The MR2A contains the OADM module that adds, drops, and multiplexes two channels of
signals. In addition, the MR2A provides the interface to cascade another optical add/drop
multiplexing board to increase the add/drop capability. The MR2A is a passive board and does
not have an interface with the backplane.

OADM Module
The board receives one multiplexed optical signal that is sent by the upstream station on the IN
interface. Then, the drop optical module drops two wavelengths from the signal through optical
interfaces D01 and D02. The two dropped wavelengths are transmitted through the MO optical
interface.
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The board receives one multiplexed signal that travels over the main optical path on the MI
optical interface. Then, the add optical module adds two wavelengths through optical interfaces
A01 and A02 and multiplexes them with the signal on the main optical path into one signal. This
multiplexed signal is transmitted through the OUT interface.

11.4.4 Front Panel


The front panel of the MR2A has interfaces and a laser safety class label.

Diagram of the Front Panel


Figure 11-11 shows the appearance of the front panel of the MR2A.
Figure 11-11 Front panel of the MR2A

MR2A

CLASS 1
LASER
PRODUCT

OUT
IN
MO
MI
D1
A1
D2 A2

MR2A

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Interfaces
The front panel of the MR2A has four LC optical interfaces. Table 11-14 describes the types
and usage of the optical interfaces of the MR2A.
Table 11-14 Optical interfaces of the MR2A
Interface

Type of
Interface

Usage

A01A02

LC

Adds two wavelengths of signals from the local equipment.

D01D02

LC

Drops two wavelengths of signals to the local equipment.

IN

LC

Receives the multiplexed signals of two wavelengths.

OUT

LC

Transmits the multiplexed signals of two wavelengths.

MO/MI

LC

Works as a cascading interface and cascades several MR2A


boards.

11.4.5 Valid Slots


The MR2A can be installed in slots 28 and 1116 in the subrack.

11.4.6 Technical Specifications


The technical specifications of the MR2A include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.

Parameters Specified for Optical Interfaces


Table 11-15 lists the parameters specified for the optical interfaces of the MR2A.
Table 11-15 Parameters specified for the optical interfaces of the MR2A

Issue 02 (2009-07-30)

Parameter

Value

Operating wavelength
range (nm)

The operating wavelength range is from 1535.82 nm to 1560.61


nm. The working wavelengths can be any two adjacent standard
wavelengths defined in ITU-T G.692 (DWDM).

Line code pattern

NRZ

Channel spacing (GHz)

100

Insertion loss on the add


channel or drop channel
(dB)

<2

Adjacent channel isolation


(dB)

> 25

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Parameter

Value

Non-adjacent channel
isolation (dB)

> 35

-0.5 dB channel bandwidth


(nm)

< 0.11

Laser Safety Class


The safety class of the laser on the board is Class 1. The maximum launched optical power of
the optical interfaces is less than 10 dBm (10 mW).

Mechanical Specifications
The mechanical specifications of the MR2A are as follows:
l

Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)

Weight (kg): 1.0

Power Consumption
The maximum power consumption of the MR2A at room temperature (25C) is 0 W.

11.5 MR2C
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the MR2C (2-channel optical add/drop multiplexing board).
11.5.1 Version Description
The MR2C is available in one functional version, namely, N1.
11.5.2 Functions and Features
The MR2C is applied to the DWDM system. The channel spacing is 0.8 nm. The MR2C supports
the add/drop multiplexing function between any two adjacent wavelengths.
11.5.3 Working Principle and Signal Flow
The MR2C consists of the OADM module.
11.5.4 Front Panel
The front panel of the MR2C has interfaces and a laser safety class label.
11.5.5 Valid Slots
The MR2C can be installed in slots 2140 in the subrack.
11.5.6 Technical Specifications
The technical specifications of the MR2C include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.

11.5.1 Version Description


The MR2C is available in one functional version, namely, N1.
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11.5.2 Functions and Features


The MR2C is applied to the DWDM system. The channel spacing is 0.8 nm. The MR2C supports
the add/drop multiplexing function between any two adjacent wavelengths.
Table 11-16 provides the functions and features of the MR2C.
Table 11-16 Functions and features of the MR2C
Function and
Feature

MR2C

Basic functions

Adds/Drops any two adjacent standard wavelengths defined in


ITU-T G.692 (DWDM). The signals are transparently
transmitted and the operating wavelength ranges from 1535.82
nm to 1560.61 nm.

OTM function

One MR2C board can work as a two-channel add/drop OTM


station, as shown in Figure 11-12. Two MR2C boards can be
cascaded to work as a four-channel add/drop OTM station, as
shown in Figure 11-13.

OADM function

Works as a two-channel add/drop OADM station when working


with the LWX. For details, see Figure 11-14.

Central wavelength

Supports the standard wavelengths defined in ITU-T


Recommendations. The channel spacing is 100 GHz.

Figure 11-12 One MR2C board working as a two-channel add/drop OTM station
D2

D1

IN

Drop

OUT

MO

MI

Add
MR2C
A1

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Figure 11-13 Two MR2C boards being cascaded to work as a four-channel add/drop OTM
station
D2

D1

IN

D1

MO IN

Drop

OUT
MR2C

MO

Drop

MI OUT

Add

D2

MI

Add

MR2C
A1

A2

A1

A2

Figure 11-14 MR2C and LWX working as a two-channel add/drop OADM station

LWX
A2

D2
MO

Out
MR2C

In
D1

MI
A1

LWX

11.5.3 Working Principle and Signal Flow


The MR2C consists of the OADM module.
Figure 11-15 shows the functional block diagram of the MR2C.
Figure 11-15 Functional block diagram of the MR2C
D01

IN

D02

MO

MI

Drop

A01

A02

Add

OUT

OADM
module

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The MR2C contains the OADM module that adds, drops, and multiplexes two channels of
signals. In addition, the MR2C provides the interface to cascade another optical add/drop
multiplexing board to increase the add/drop capability. The MR2C is a passive board and does
not have an interface with the backplane.

OADM Module
The board receives one multiplexed optical signal that is sent by the upstream station on the IN
interface. Then, the drop optical module drops two wavelengths from the signal through optical
interfaces D01 and D02. The two dropped wavelengths are transmitted through the MO optical
interface.
The board receives one multiplexed signal that travels over the main optical path on the MI
optical interface. Then, the add optical module adds two wavelengths through optical interfaces
A01 and A02 and multiplexes them with the signal on the main optical path into one signal. This
multiplexed signal is transmitted through the OUT interface.

11.5.4 Front Panel


The front panel of the MR2C has interfaces and a laser safety class label.

Diagram of the Front Panel


Figure 11-16 shows the appearance of the front panel of the MR2C.

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Figure 11-16 Front panel of the MR2C

MR2C

OUT AO1
AO2
MI
MO
DO2
DO1
IN
CLASS 1
LASER
PRODUCT

MR2C

Interfaces
The front panel of the MR2C has four pairs of LC optical interfaces. Table 11-17 describes the
types and usage of the optical interfaces of the MR2C.
Table 11-17 Optical interfaces of the MR2C

11-28

Interface

Type of
Interface

Usage

A01A02

LC

Adds two wavelengths of signals from the local equipment.

D01D02

LC

Drops two wavelengths of signals to the local equipment.

IN

LC

Receives the multiplexed signals of two wavelengths.

OUT

LC

Transmits the multiplexed signals of two wavelengths.

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Interface

Type of
Interface

Usage

MO/MI

LC

Works as a cascading interface and cascades several MR2C


boards.

11.5.5 Valid Slots


The MR2C can be installed in slots 2140 in the subrack.

11.5.6 Technical Specifications


The technical specifications of the MR2C include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.

Parameters Specified for Optical Interfaces


Table 11-18 lists the parameters specified for the optical interfaces of the MR2C.
Table 11-18 Parameters specified for the optical interfaces of the MR2C
Parameter

Value

Operating wavelength
range (nm)

The operating wavelength range is from 1535.82 nm to 1560.61


nm. The working wavelengths can be any two adjacent standard
wavelengths defined in ITU-T G.692 (DWDM).

Line code pattern

NRZ

Channel spacing (GHz)

100

Insertion loss on the add


channel or drop channel
(dB)

<2

Adjacent channel isolation


(dB)

> 25

Non-adjacent channel
isolation (dB)

> 35

-0.5 dB channel bandwidth


(nm)

< 0.11

Laser Safety Class


The safety class of the laser on the board is Class 1. The maximum launched optical power of
the optical interfaces is less than 10 dBm (10 mW).

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Mechanical Specifications
The mechanical specifications of the MR2C are as follows:
l

Dimensions (mm): 22 (W) x 110 (D) x 262.05 (H)

Weight (kg): 1.0

Power Consumption
The maximum power consumption of the MR2C at room temperature (25C) is 0 W.

11.6 MR4
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the TN11MR4 (4-channel optical add/drop multiplexing board).
11.6.1 Version Description
The MR4 is available in one functional version, namely, TN11.
11.6.2 Functions and Features
The MR4 is applied to the DWDM system. The channel spacing is 0.8 nm. The MR4 supports
the add/drop multiplexing function and channel expansion function.
11.6.3 Working Principle and Signal Flow
The MR4 consists of the OADM module, communication and control module, and power
module.
11.6.4 Front Panel
The front panel of the MR4 has indicators, interfaces, and a laser safety class label.
11.6.5 Valid Slots
The MR4 can be installed in slots 28 and 1116 in the subrack.
11.6.6 Feature Code
The feature code of the MR4 contains eight characters, which indicate the frequencies of the
first channel and fourth channel of optical signals processed by the MR4.
11.6.7 Technical Specifications
The technical specifications of the MR4 include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.

11.6.1 Version Description


The MR4 is available in one functional version, namely, TN11.

11.6.2 Functions and Features


The MR4 is applied to the DWDM system. The channel spacing is 0.8 nm. The MR4 supports
the add/drop multiplexing function and channel expansion function.
Table 11-19 provides the functions and features of the MR4.

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Table 11-19 Functions and features of the MR4


Function and
Feature

MR4

Basic functions

Adds/Drops and multiplexes four signals to/from the multiplexed


signals.

Channel expansion

Provides the interface to cascade another optical add/drop


multiplexing board to realize the expansion of the add/drop channel.

11.6.3 Working Principle and Signal Flow


The MR4 consists of the OADM module, communication and control module, and power
module.
Figure 11-17 shows the functional block diagram of the MR4.
Figure 11-17 Functional block diagram of the MR4
D01 D02 D03 D04

MO

MI

A01 A02 A03 A04

Drop

IN

Add

OUT

OADM module

Communication and control module

Pow er module
DC/DC
converter
Delayed
startup
Fuse
SCC

Backplane

-48 V/-60 V

-48 V/-60 V

SCC

OADM Module
The board receives one multiplexed optical signal that is sent by the upstream station on the IN
interface. Then, the drop optical module drops four wavelengths from the signal through optical
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interfaces D01D04. The four dropped wavelengths are transmitted through the MO optical
interface.
The board receives one multiplexed signal that travels over the main optical path on the MI
optical interface. Then, the add optical module adds four wavelengths through optical interfaces
A01A04 and multiplexes them with the signal on the main optical path into one signal. This
multiplexed signal is transmitted through the OUT interface.

Communication and Control Module


l

Controls the operations of the entire board.

Collects the following information of each functional module of the board: alarms,
performance events, working status, and voltage detection.

Communicates data with the SCC.

DC/DC Converter
It converts 48 V DC or 60 V DC into a voltage required by each module of the board.

11.6.4 Front Panel


The front panel of the MR4 has indicators, interfaces, and a laser safety class label.

Diagram of the Front Panel


Figure 11-18 shows the appearance of the front panel of the MR4.

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Figure 11-18 Front panel of the MR4

MR4
STAT

OUT
IN
MO
IN
D1
A1
D2
A2
D3
A3
D4
A4
LASER
RADIATION
DO NOT VIEW DIRECTLY
WITH OPTICAL
INSTRUMENTS

CLASS 1M LASER
PRODUCT

MR4

Indicators
The front panel of the MR4 has one indicator as follows: board hardware status indicator (STAT)
two colors (red and green)
For the meanings of the status of the indicator, see A Indicators.

Interfaces
The front panel of the MR4 has 12 optical interfaces. Table 11-20 describes the types and usage
of the optical interfaces of the MR4.

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Table 11-20 Optical interfaces of the MR4


Interface

Type of
Interface

Usage

A1A4

LC

Receives the signals sent from the optical wavelength


converting board or centralized client-side equipment.

D1D4

LC

Transmits signals to the optical wavelength converting


board or centralized client-side equipment.

IN

LC

Receives the multiplexed signals.

OUT

LC

Transmits the multiplexed signals.

MO

LC

Works as a cascading output optical interface and is


connected to the input optical interface of an OADM
board.

MI

LC

Works as a cascading input optical interface and is


connected to the output optical interface of an OADM
board.

11.6.5 Valid Slots


The MR4 can be installed in slots 28 and 1116 in the subrack.

11.6.6 Feature Code


The feature code of the MR4 contains eight characters, which indicate the frequencies of the
first channel and fourth channel of optical signals processed by the MR4.
Table 11-21 describes the feature code of the MR4.
Table 11-21 Feature code of the MR4

11-34

Feature Code

Indication

Description

First four (14) characters

Frequency of optical signals

The four characters are the


last four characters of the
figure that indicates the
frequency of the first channel
of optical signals processed
by the MR4.

Last four (58) characters

Frequency of optical signals

The four characters are the


last four characters of the
figure that indicates the
frequency of the fourth
channel of optical signals
processed by the MR4.

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Consider the TN11MR4 whose feature code is "92109240" as an example. The meaning of the
feature code of the TN11MR4 is as follows:
l

"9210" indicates that the frequency of the first channel of optical signals is 192.10 THz.

"9240" indicates that the frequency of the fourth channel of optical signals is 192.40 THz.

The four channels of optical signals processed by the MR4 are successive. Hence, we can infer
the following:
l

The frequency of the second channel of optical signals is 192.20 THz.

The frequency of the third channel of optical signals is 192.30 THz.

11.6.7 Technical Specifications


The technical specifications of the MR4 include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.

Parameters Specified for Optical Interfaces


Table 11-22 lists the parameters specified for the optical interfaces of the MR4.
Table 11-22 Parameters specified for the optical interfaces of the MR4
Optical Interface

Parameter

Value

Operating wavelength range (nm)

1529 to 1561

Channel spacing (GHz)

100

IN-D1
IN-D2
IN-D3
IN-D4

0.5 dB passband bandwidth (nm)

0.11

Insertion loss on the drop channel (dB)

2.2

Adjacent channel isolation (dB)

> 25

Non-adjacent channel isolation (dB)

> 35

A1-OUT
A2-OUT
A3-OUT
A4-OUT

0.5 dB passband bandwidth (nm)

0.11

Insertion loss on the add channel (dB)

2.2

IN-MO
MI-OUT

Insertion loss (dB)

1.5

Isolation (dB)

> 13

Return loss (dB)

> 40

Laser Safety Class


The safety class of the laser on the board is Class 1M. The maximum launched optical power of
the optical interfaces is within the range from 10 dBm (10 mW) to 22.15 dBm (164 mW).
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Mechanical Specifications
The mechanical specifications of the MR4 are as follows:
l

Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)

Weight (kg): 0.9

Power Consumption
The power consumption of the MR4 at room temperature (25C) is 0 W.

11.7 LWX
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the LWX (arbitrary bit rate wavelength conversion board).
11.7.1 Version Description
The LWX is available in one functional version, namely, N1.
11.7.2 Functions and Features
The LWX converts a wavelength at an arbitrary rate (10 Mbit/s to 2.7 Gbit/s, NRZ code) on the
client side into a standard wavelength defined in ITU-T G.692, and performs the reverse process.
11.7.3 Working Principle and Signal Flow
The LWX consists of the O/E converting module, cross-connect module, CDR module, logic
and control module, DC/DC converter, and other modules.
11.7.4 Front Panel
The front panel of the LWX has indicators, interfaces, and a laser safety class label.
11.7.5 Valid Slots
The LWX can be installed in slots 28 and 1116 in the subrack.
11.7.6 Feature Code
The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the LWX indicates the scheme that the optical interfaces use to receive and
transmit signals.
11.7.7 Parameter Settings
You can set the parameters for the LWX by using the T2000.
11.7.8 Technical Specifications
The technical specifications of the LWX include the parameters specified for optical interfaces,
the safety class of the laser, mechanical specifications and power consumption.

11.7.1 Version Description


The LWX is available in one functional version, namely, N1.

11.7.2 Functions and Features


The LWX converts a wavelength at an arbitrary rate (10 Mbit/s to 2.7 Gbit/s, NRZ code) on the
client side into a standard wavelength defined in ITU-T G.692, and performs the reverse process.
The LWX supports the optical wavelength conversion, 3R function, protection, and loopback
function.
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Table 11-23 provides the functions and features of the LWX.


Table 11-23 Functions and features of the LWX
Function
and Feature

LWX

Basic
functions

Converts a wavelength on the client side into a standard wavelength defined


in ITU-T G.692 (DWDM), and performs the reverse process.
Transparently transmits signals.

3R function

Provides the 3R function for the signals at a rate ranging from 10 Mbit/s to
2.7 Gbit/s on the client side, restores the clock, and monitors the rate.

Protection
schemes

Single fed and single


receiving

Supports the inter-board protection and 1+1 interboard hot standby protection. The protection
switching time is less than 50 ms.

Dual fed and


selective receiving

Supports the intra-board protection. One board can


realize the optical channel protection. The protection
switching time is less than 50 ms.

ALS function

Supports the ALS function. When the LWX does not receive light, the LWX
automatically turns off the corresponding optical transmit module.

Loopback
function

Supports inloops and outloops at optical interfaces so that faults can be


located quickly.

Performance
and alarm
monitoring

Reports various alarms and performance events, which facilitates the


maintenance of the equipment.

Central
wavelength

Supports the standard wavelengths defined in ITU-T Recommendations. The


channel spacing is 100 GHz.

11.7.3 Working Principle and Signal Flow


The LWX consists of the O/E converting module, cross-connect module, CDR module, logic
and control module, DC/DC converter, and other modules.
Figure 11-19 shows the functional block diagram of the LWX.

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Figure 11-19 Functional block diagram of the LWX


Loopback control

Reference clock

10 Mbit/s to 2.7
Gbit/s
Optical module on
the client side
10 Mbit/s to 2.7
Gbit/s

O/E

E/O

2x2 crossconnection

WDM side
loopback

Data
LOS
Laser
Communication
shutdown
and control
module
LOS

10 Mbit/s to 2.7
Gbit/s
Optical module 2
on the WDM side

Multi-rate
CDR

Client side
loopback
O/E
2x2 crossconnection

Multi-rate
CDR

Loopback control
10 Mbit/s to 2.7
Gbit/s
Optical module 1
on the WDM side

O/E
Clock

10 Mbit/s to 2.7
Gbit/s
Optical
splitter

Reference
clock

E/O

Data

LOS

Communication
and control
module
Communication

Laser shutdown

+3.3
V
DC/DC
converter

DC/DC
converter

Fuse

SCC unit

-48 V/ -60 V
-48 V/ -60 V

Fuse

+3.3 V backup
power

O/E Converting Module

11-38

The optical module on the client side applies SFP encapsulation and can be configured as
different types of optical modules. This module can access the optical signals at a rate
ranging from 10 Mbit/s to 2.7 Gbit/s.

The optical module on the WDM side can be configured as an optical transceiver module,
or both an optical transceiver module and an optical receiver module. When two modules
are configured on the WDM side, an optical splitter is used to perform dual feeding.
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In the receive direction, the module converts the received optical signals into electrical
signals.

In the transmit direction, the module converts the electrical signals into SDH optical signals
and sends the SDH optical signals to fibers for transmission.

Detects the R_LOS alarm and provides the function of shutting down the laser.

Cross-Connect Module
l

Supports the data selection from the client side to the WDM side and the data selection
from the WDM side to the client side.

Supports the selection of WDM-side optical modules.

Supports the loopback of client-side signals.

Supports the loopback of WDM-side signals.

Restores the data and clock signals from the signals that are at a rate ranging from 10 Mbit/
s to 2.7 Gbit/s.

Reads the rates of the accessed services.

CDR Module

Logic and Control Module


l

Supports Ethernet communication.

Supports the reference clock of the CDR module.

Selects and configures the services of the other modules.

Controls the laser.

Selects the clock signal from the active and standby cross-connect boards.

Controls the indicators on the board.

DC/DC Converter
It converts the 48/60 V power supply into the DC voltages that the modules of the board
require.

11.7.4 Front Panel


The front panel of the LWX has indicators, interfaces, and a laser safety class label.

Diagram of the Front Panel


Figure 11-20 shows the appearance of the front panel of the LWX.

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Figure 11-20 Front panel of the LWX

LWX
STAT
ACT
PROG
SRV

CLASS 1
LASER
PRODUCT

TX
RX
OUT1 IN1
OUT2 IN2

LWX

Indicators
The front panel of the board has the following indicators:
l

Board hardware status indicator (STAT) two colors (red and green)

Service activation status indicator (ACT) one color (green)

Board software status indicator (PROG) two colors (red and green)

Service alarm indicator (SRV) three colors (red, green, and yellow)

For the meanings of the status of the indicators, see A Indicators.

Interfaces
The front panel of the LWX has six optical interfaces. Table 11-24 describes the types and usage
of the optical interfaces of the LWX.
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Table 11-24 Optical interfaces of the LWX


Interface

Type of
Interface

Usage

IN1IN2

LC

Receives the signals sent from the MR2A.

OUT1OUT2

LC

Transmits signals to the MR2A.

TX

LC

Transmits signals to the client-side equipment.

RX

LC

Receives the signals sent from the client-side


equipment.

11.7.5 Valid Slots


The LWX can be installed in slots 28 and 1116 in the subrack.

11.7.6 Feature Code


The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the LWX indicates the scheme that the optical interfaces use to receive and
transmit signals.
Table 11-25 provides the relationship between the feature code of the LWX and the signal
receive/transmit scheme.
Table 11-25 Relationship between the feature code of the LWX and the signal receive/transmit
scheme
Board

Feature Code

Signal Receive/Transmit Scheme

SSN1LWX01

01

Single fed and single receiving

SSN1LWX02

02

Dual fed and selective receiving

11.7.7 Parameter Settings


You can set the parameters for the LWX by using the T2000.
You can set the following parameters for the LWX by using the T2000:
l

Path use status

Optical interface loopback

Service type

Client service bearer rate (M)

Laser status

Automatic laser shutdown

Current bearer rate (M)

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l

Actual wavelength No./wavelength (nm)/frequency (THz)

Actual band type

Configure wavelength No./wavelength (nm)/frequency (THz)

Configure band type

SD trigger condition

11.7.8 Technical Specifications


The technical specifications of the LWX include the parameters specified for optical interfaces,
the safety class of the laser, mechanical specifications and power consumption.

Parameters Specified for Optical Interfaces


Table 11-26 and Table 11-27 list the parameters specified for the client-side and WDM-side
optical interfaces of the LWX.
Table 11-26 Parameters specified for the client-side optical interfaces of the LWX
Parameter

Value

Nominal bit rate

10 Mbit/s to 2.7 Gbit/s

Line code pattern

NRZ

Type of fiber

Single-mode LC

Single-mode LC

Single-mode LC

Transmission
distance (km)

15

40

80

Characteristics of the transmitter at point S


Operating
wavelength range
(nm)

1260 to 1360

1260 to 1360

1500 to 1580

Maximum mean
launched power
(dBm)

+3

+3

Minimum mean
launched power
(dBm)

-5

-2

-2

Minimum extinction
ratio (dB)

+8.2

+8.2

+8.2

Minimum side mode


suppression ratio
(dB)

30

30

30

Eye pattern mask

Complies with the


mask defined in ITUT G.957.

Complies with the


mask defined in ITUT G.957.

Complies with the


mask defined in ITUT G.957.

Characteristics of the receiver at point S


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Parameter

Value

Receiver type

PIN

APD

APD

Receiver wavelength
range (nm)

1200 to 1600

1200 to 1600

1200 to 1600

Receiver sensitivity
(dBm)

-18

-27

-28

Minimum overload
(dBm)

-9

-9

Maximum
reflectance (dB)

-27

-27

-27

Table 11-27 Parameters specified for the WDM-side optical interfaces of the LWX
Parameter

Value

Channel
spacing (GHz)

100

Line code
pattern

NRZ

Characteristics of the transmitter at point Sn

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Transmission
distance (km)

640

170 (2 mW)

170 (10 mW)

360

Maximum mean
launched power
(dBm)

+3

+3

+7

+3

Minimum mean
launched power
(dBm)

-2

-2

+5

-2

Minimum
extinction ratio
(dB)

+10

+10

+10

+10

Nominal central
frequency
(THz)

192.10 to
196.00

192.10 to
196.00

192.10 to
196.00

192.10 to
196.00

Central
frequency
deviation (GHz)

12.5

12.5

12.5

12.5

Maximum -20
dB spectral
width (nm)

0.2

0.4

0.4

0.4

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Parameter

Value

Minimum side
mode
suppression
ratio (dB)

35

35

35

35

Dispersion
compensation
(ps/nm)

12800

3400

3400

7200

Eye pattern
mask

Complies with
the mask
defined in ITUT G.957.

Complies with
the mask
defined in ITUT G.957.

Complies with
the mask
defined in ITUT G.957.

Complies with
the mask
defined in ITUT G.957.

Characteristics of the receiver at point Rn


Receiver type

APD

PIN

Receiver
wavelength
range (nm)

1200 to 1600

1200 to 1600

Receiver
sensitivity
(dBm)

-28

-18

Minimum
overload (dBm)

-9

Maximum
reflectance (dB)

-27

-27

Laser Safety Class


The safety class of the laser on the board is Class 1. The maximum launched optical power of
the optical interfaces is less than 10 dBm (10 mW).

Mechanical Specifications
The mechanical specifications of the LWX are as follows:
l

Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)

Weight (kg): 1.1

Power Consumption
The maximum power consumption of the LWX at room temperature (25C) is 30 W.

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11.8 FIB
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the FIB (filter isolating board).
11.8.1 Version Description
The FIB is available in one functional version, namely, N1.
11.8.2 Functions and Features
The FIB filters and isolates 1xSTM-16 optical signals.
11.8.3 Working Principle and Signal Flow
The FIB consists of an isolator and a filter.
11.8.4 Front Panel
The front panel of the FIB has one optical interface.
11.8.5 Valid Slots
The FIB can be installed in slots 28 and 1116 in the subrack.
11.8.6 Technical Specifications
The technical specifications of the FIB include the parameters specified for optical interfaces,
mechanical specifications, and power consumption.

11.8.1 Version Description


The FIB is available in one functional version, namely, N1.

11.8.2 Functions and Features


The FIB filters and isolates 1xSTM-16 optical signals.
The FIB is used in the remote optical pumping amplifier (ROPA) system. The FIB can realize
long-distance optical regeneration transmission when it works with the single-wavelength longdistance board ROP. Figure 11-21 shows the position of the FIB in an optical transmission
system.
Figure 11-21 Position of the FIB in an optical transmission system
C (single span)
a (54 dB)
Optical
transmitter

BA17

G.652 fiber

FIB

b (18 dB)

Erbium
ROP
doped fiber G.652 fiber

->

ISO

Filter
1550.12

Optical
receiver

Table 11-28 provides the functions and features of the FIB.

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Table 11-28 Functions and features of the FIB


Function and
Feature

FIB

Optical isolator

The isolator allows optical signals to pass in a single direction. The


operating wavelength ranges from 1529 nm to 1561 nm.

Optical filter

The filter filters out the wavelengths other than the 1550.12 nm
wavelength.

11.8.3 Working Principle and Signal Flow


The FIB consists of an isolator and a filter.
Figure 11-22 shows the functional block diagram of the FIB.
Figure 11-22 Functional block diagram of the FIB
Isolator

Filter

Optical signals are heavily attenuated and degraded after they travel for a long distance in fibers.
The degraded signals cannot be normally received by an optical receiver. Hence, an ROP needs
to be used to amplify the gain of the optical signals. To prevent other factors from affecting the
ROP because the ROP has high optical power, the FIB needs to be used to filter wavelengths.
The isolator of the FIB allows the optical signals to pass in a single direction. The filter of the
FIB filters out the wavelengths other than the 1550.12 nm wavelength. As a result, the optical
receiver receives the optical signals normally.

11.8.4 Front Panel


The front panel of the FIB has one optical interface.

Diagram of the Front Panel


Figure 11-23 shows the appearance of the front panel of the FIB.

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Figure 11-23 Front panel of the FIB

FIB

CLASS 1
LASER
PRODUCT

OUT
IN

FIB

Interfaces
The front panel of the FIB has one optical interface. The optical interface is used to receive and
transmit one channel of 2.5 Gbit/s optical signals. Table 11-29 describes the types and usage of
the optical interfaces of the FIB.
Table 11-29 Optical interfaces of the FIB

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Interface

Type of
Interface

Usage

IN

LSH

Receives one channel of 2.5 Gbit/s optical signals.

OUT

LC

Transmits one channel of 2.5 Gbit/s optical


signals.

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11.8.5 Valid Slots


The FIB can be installed in slots 28 and 1116 in the subrack.

11.8.6 Technical Specifications


The technical specifications of the FIB include the parameters specified for optical interfaces,
mechanical specifications, and power consumption.

Parameters Specified for Optical Interfaces


Table 11-30 lists the parameters specified for the optical interfaces of the FIB.
Table 11-30 Parameters specified for the optical interfaces of the FIB
Parameter

Value

Nominal bit rate

2488320 kbit/s

Line code pattern

NRZ

Central wavelength
(nm)

1550.120.05

-0.5 dB bandwidth
(nm)

> 0.4

Laser Safety Class


The safety class of the laser on the board is Class 1. The maximum launched optical power of
the optical interfaces is less than 10 dBm (10 mW).

Mechanical Specifications
The mechanical specifications of the FIB are as follows:
l

Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)

Weight (kg): 0.4

Power Consumption
The maximum power consumption of the FIB at room temperature (25C) is 0 W.

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12 Microwave Boards

Microwave Boards

About This Chapter


The microwave boards include the microwave intermediate frequency (IF) board IFSD1 and
microwave power board RPWR. The microwave boards need to work with the outdoor unit
(ODU). The equipment supports the standard-power (SP) ODU and high-power (HP) ODU.
NOTE

This topic describes only the microwave boards. For the description of the ODU, see the ODU Hardware
Description.

12.1 IFSD1
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the IFSD1 (dual-port IF board).
12.2 RPWR
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the RPWR (6-channel ODU power board).

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12.1 IFSD1
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the IFSD1 (dual-port IF board).
12.1.1 Version Description
The IFSD1 is available in one functional version, namely, N1.
12.1.2 Functions and Features
The IFSD1 transmits and receives two IF signals, provides the management channel to the ODU,
and supplies the 48 V power to the ODU.
12.1.3 Working Principle and Signal Flow
The IFSD1 consists of the combiner interface module, IF processing module, MODEM module,
FPGA module, rate converting module, and communication and control module.
12.1.4 Front Panel
The front panel of the IFSD1 has indicators, interfaces, power switches, and labels.
12.1.5 Valid Slots
The IFSD1 can be installed in slots 28 and 1116 in the subrack.
12.1.6 Parameter Settings
You can set the parameters for the IFSD1 by using the T2000 LCT and T2000.
12.1.7 Technical Specifications
The technical specifications of the IFSD1 include the IF performance, baseband signal
processing performance, board mechanical specifications, and power consumption.

12.1.1 Version Description


The IFSD1 is available in one functional version, namely, N1.

12.1.2 Functions and Features


The IFSD1 transmits and receives two IF signals, provides the management channel to the ODU,
and supplies the 48 V power to the ODU.
Table 12-1 provides the functions and features of the IFSD1.
Table 12-1 Functions and features of the IFSD1

12-2

Function and
Feature

IFSD1

Basic functions

Supports 2xSTM-1 SDH or PDH IF signals and management control


signals between the IDU and ODU, and supplies power to the ODU.

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Function and
Feature

IFSD1

IF processing

Maps PDH signals and SDH signals into IF signals.

Codes and decodes IF signals.

Modulates and demodulates IF signals.

Modulates and demodulates ODU control signals.

Combines and splits service signals, ODU control signals, and 48


V power supplies.

Supports the software programmable radio (SPR) function. That


is, you can set the microwave capacity and modulation scheme by
using the software.

Supports the microwave frame that is based on the tributary and


STM-1, and hence supports the interconnection with the OptiX
OSN products or the OptiX RTN 600 products that support this
type of microwave frame through the air interface.

Supports the automatic transmit power control (ATPC) function.

Microwave features

Service processing

Supports the configuration of VC-12, VC-3, and VC-4 services.

Overhead processing

Processes the section overheads of the STM-1 IF signals.

Supports the transparent transmission and termination of the path


overheads of the STM-1 IF signals.

Supports the setting and query of the J1 and C2 bytes.

Processes AU pointers of SDH IF signals.

Processes TU pointers of PDH IF signals.

Pointer processing

Alarms and
performance events

Reports various alarms and performance events, which facilitates the


management and maintenance of the equipment.

Protection schemes

Supports 1+1 HSB/FD/SD protection and N+1 protection.

Supports the lower order SNCP.

Supports loopbacks on VC-4 paths.

Supports loopbacks on IF ports.

Supports the detection of the board temperature.

Supports warm resets and cold resets. The warm reset does not
affect the services.

Supports the query of the manufacturing information of the board.

Supports the in-service loading of the FPGA.

Supports the detection of the hardware fault.

Supports the PRBS function.

Maintenance
features

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12.1.3 Working Principle and Signal Flow


The IFSD1 consists of the combiner interface module, IF processing module, MODEM module,
FPGA module, rate converting module, and communication and control module.
This topic considers the processing of one IF signal that is sent from the ODU as an example to
describe the working principle and signal flow of the IFSD1.
Figure 12-1 shows the functional block diagram of the IFSD1.
Figure 12-1 Functional block diagram of the IFSD1
Backplane

ODU

IF Combiner
interface
module

IF
processing
module

MODEM
module

SMOD
EM

M
U
X/
D
E
M
U
X

Rate
converting

FPGA module

Overhead
processing

Overhead
s related
to HSM

Cross-connect
unit

Board in the paired slot


SCC

-48 V
Clock
module
Power
module
Service bus
Overhead bus

Communication and
control module

IF signal
Control bus

SCC
SCC

ODU control signal


Communication bus

-48 V power supply

Signal Processing Flow in the Transmit Direction


After the service signals are processed by the rate converting module, the signals from the crossconnect unit are sent to the MUX/DEMUX module of the FPGA module where the signals are
scrambled and the overhead byte and pointer are set. Then, the signals are sent to the MODEM
module for FEC coding and digital modulation and to the IF processing module for D/A
converting and analog modulation. The ODU control signals sent from the logic and control
module are sent to the combiner interface module after being modulated by the SMODEM
module. Finally, the IF signals, ODU control signals, and 48 V power supplies are combined
at the combiner interface module and then sent to the ODU over IF cables.

Signal Processing Flow in the Receive Direction


The combiner interface module divides the ODU control signals and IF signals from the received
IF signals. The ODU control signals are sent to the SMODEM module for demodulation and
then to the logic and control module. The IF signals are sent to the IF processing module for
filtering and A/D converting and then to the FPGA module for demultiplexing and overhead
processing. Then, the signals are sent to the rate converting module. Finally, the signals are sent
to the cross-connect unit.

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Auxiliary Modules
The auxiliary modules include the logic and control module, clock module, and power module.
The functions of these modules are as follows:
l

Logic and control module

This module realizes the alarm display, performance monitoring, and communication with the
system control and communication board and the other boards through the Ethernet interface.
In addition, this module provides two pairs of RS485 data buses and can provide quick response
in real time. This module supports the in-service loading of programs.
l

Clock module

Extracts the clock from the received signal and sends the 8 KHz clock to the clock unit.

Supports the 38 MHz system clock in the transmit direction.

Power module

Provides two 48 V power input interfaces and supports the DC power supply whose
input voltage ranges from 38.4 V to 72 V.

Provides DC power supplies for all the modules on the IFSD1.

Monitors all the power supplies for the IFSD1 and reports alarms in the case of a board
voltage abnormality.

Provides one 48 V DC power supply for the ODU.

12.1.4 Front Panel


The front panel of the IFSD1 has indicators, interfaces, power switches, and labels.

Diagram of the Front Panel


Figure 12-2 shows the appearance of the front panel of the IFSD1.

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Figure 12-2 Front panel of the IFSD1


IFSD1
STAT
PROG
SRV
LINK1
ODU1
ACT1
LINK2
ODU2
ACT2

!
WARNING

-48V OUTPUT
TURNOFFPOWERBEFORE
DISCONNECTING IF CABLE

IF1

ODU-PWR1
I
O
PWR1

PWR2

ODU-PWR2
I
O
IF2

IFSD1

Indicators
The front panel of the board has the following indicators:
l

Board hardware status indicator (STAT) two colors (red and green)

Board software status indicator (PROG) two colors (red and green)

Active/Standby state indicator (ACT1) one color (green)

Active/Standby state indicator (ACT2) one color (green)

Service alarm indicator (SRV) three colors (red, green, and yellow)

Connection status indicator 1 (LINK1) two colors (red and green)

Connection status indicator 2 (LINK2) two colors (red and green)

Working indicator of ODU 1 (ODU1) two colors (red and green)

Working indicator of ODU 2 (ODU2) two colors (red and green)

For the meanings of the status of the indicators, see A Indicators.

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Interfaces
Table 12-2 Interfaces of the IFSD1
Interface

Description

Usage

IF1

IF port 1

IF port 1 refers to the IF interface between the


IDU and the ODU. This port transmits the
signal that combines the IF service signal,
ODU control signal, and 48 V power supply
required by the ODU. A single type-N IF
cable is used for connection.

IF2

IF port 2

IF port 2 refers to the IF interface between the


IDU and the ODU. This port transmits the
signal that combines the IF service signal,
ODU control signal, and 48 V power supply
required by the ODU. A single N-Type IF
cable is used for connection.

PWR1

Power interface 1

The power supply provided by the RPWR is


transferred by the combiner unit of the IF
board to supply power to the ODU. The IF
board can provide a maximum throughcurrent of 1.76 A for the ODU. The PWR1
interface must be connected to the dedicated
power cable that is delivered with the
equipment.

PWR2

Power interface 2

The power supply provided by the RPWR is


transferred by the combiner unit of the IF
board to supply power to the ODU. The IF
board can provide a maximum throughcurrent of 1.76 A for the ODU. The PWR2
interface must be connected to the dedicated
power cable that is delivered with the
equipment.

ODU-PWR1a

ODU power switch 1

Turns on or turns off the 48 V DC power


supply for the ODU.

ODU-PWR2a

ODU power switch 2

Turns on or turns off the 48 V DC power


supply for the ODU.

CAUTION
a: The ODU-PWR1 and ODU-PWR2 switches are equipped with lockup devices. To move the
switch, you need to pull the switch lever partially. When the switch is set to "O", it indicates that
the circuit is open. When the switch is set to "I", it indicates that the circuit is closed.

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Labels
The front label has a high temperature warning label and an operation warning label.
The high temperature warning label indicates that the board surface temperature may exceed
70C when the ambient temperature is higher than 55C. In this case, you need to wear protective
gloves before touching the board.
The operation warning label indicates that the ODU power switch must be turned off before the
IF cable is removed.

12.1.5 Valid Slots


The IFSD1 can be installed in slots 28 and 1116 in the subrack.

12.1.6 Parameter Settings


You can set the parameters for the IFSD1 by using the T2000 LCT and T2000.
You can set the following parameters for the IFSD1 by using the network management system:
l

Radio work mode

Radio link ID

ATPC attributes

J1 byte

The J1 byte apply to SDH microwave only. The other parameters apply to both PDH and SDH
microwaves.

Radio Work Mode


Table 12-3 Radio work modes

12-8

Service Capacity

Modulation Scheme

Channel Spacing (MHz)

4xE1

QPSK

4xE1

16QAM

3.5

8xE1

QPSK

14 (13.75)

8xE1

16QAM

16xE1

QPSK

28 (27.5)

16xE1

16QAM

14 (13.75)

22xE1

32QAM

14 (13.75)

26xE1

64QAM

14 (13.75)

35xE1

16QAM

28 (27.5)

44xE1

32QAM

28 (27.5)

53xE1

64QAM

28 (27.5)

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Service Capacity

Modulation Scheme

Channel Spacing (MHz)

STM-1

128QAM

28 (27.5)

NOTE

The channel spacings 13.75 MHz and 27.5 MHz are applied to the 18 GHz frequency band.

The channel spacings provided in the table are the minimum channel spacings supported by the OptiX OSN
equipment series. The channel spacings equal to or larger than the values are also supported.

Radio Link ID
The radio link ID is an identification of the radio link. The transmit end sends the radio link ID
byte continuously so that the receive end can learn that the transmit end is in a constant
connection state. If the receive end detects a mismatch of the radio link ID, the MW_LIM alarm
is reported on the corresponding IF port.

ATPC Attributes
The ATPC is a technology that automatically adjusts the transmit power of the transmitter
according to the attenuation of the received signal level (RSL) at the receive end. The ATPC
attributes include the following parameters:
l

ATPC enable status


This parameter specifies whether the NE enables the ATPC function to control the transmit
power of the transmitter. By default, the ATPC function is disabled.

ATPC upper threshold


When the RSL at the receive end is higher than the set value of this parameter, the receive
end notifies the transmit end to reduce the transmit power by using the ATPC overhead in
the microwave frame. The decrement depends on the value of the ATPC adjustment
parameter.

ATPC lower threshold


When the RSL at the receive end is lower than the set value of this parameter, the receive
end notifies the transmit end to increase the transmit power by using the ATPC overhead
in the microwave frame. The increment depends on the value of the ATPC adjustment
parameter.

ATPC adjustment
This parameter specifies the decrement/increment of an ATPC adjustment.
NOTE

The ATPC adjustment cannot exceed the range of the ODU transmit power.

J1 Byte
The IFSD1 board supports four byte modes, which are as follows:
l

Single-byte mode

16-byte mode with CRC

16-byte mode without CRC

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l

64-byte mode

By default, the IFSD1 board does not monitor the received J1 byte. That is, the J1 byte to be
received is set to the disabled mode. The J1 byte to be sent is a 16-byte string with CRC. The
first byte is created automatically and the following 15 bytes are the ASCII codes "HuaWei SBS
". The last five characters of the string are blank spaces.

12.1.7 Technical Specifications


The technical specifications of the IFSD1 include the IF performance, baseband signal
processing performance, board mechanical specifications, and power consumption.

Microwave Capacity
One IFSD1 board can access microwave signals in two directions. The capacity of microwave
signals in each direction depends on the radio work mode of these microwave signals. For details
about the radio work modes, see 12.1.6 Parameter Settings.

IF Performance
Table 12-4 IF performance
Item

Performance

IF signal
Transmit frequency of the IF
board (MHz)

350

Receive frequency of the IF


board (MHz)

140

Impedance (ohm)

50

ODU O&M signal

12-10

Modulation scheme

ASK

Transmit frequency of the IF


board (MHz)

5.5

Receive frequency of the IF


board (MHz)

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Baseband Signal Processing Performance of the Modem


Table 12-5 Baseband signal processing performance of the modem
Item

Performance

Coding mode

Uses Reed-Solomon (RS) coding for PDH signals.

Uses Trellis-Coded Modulation (TCM) and RS two-level coding


for SDH signals.

Adaptive timedomain equalizer for


baseband signals

Consists of the feed forward equalizer filter and decision feedback


equalizer.

Mechanical Specification
The mechanical specifications of the IFSD1 are as follows:
l

Dimensions (mm): 25.4 (W) x 220 (D) x 245.1 (H)

Weight (kg): 1.1

Power Consumption
The maximum power consumption of the IFSD1 at room temperature (25C) is 24 W.

12.2 RPWR
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the RPWR (6-channel ODU power board).
12.2.1 Version Description
The RPWR is available in one functional version, namely, N1.
12.2.2 Functions and Features
The RPWR accesses two 48 V/60 V DC power supplies and supplies the 48 V power to six
ODUs.
12.2.3 Working Principle and Signal Flow
The RPWR consists of the combiner module, protection module, filtering module, DC/DC power
module (that is, power module), and status detection module.
12.2.4 Front Panel
The front panel of the RPWR has indicators, power input interfaces, and power output interfaces.
12.2.5 Valid Slots
The RPWR can be installed in slots 28 and 1116.
12.2.6 Technical Specifications
The technical specifications of the RPWR include the mechanical specifications, power
consumption, input voltage, and specifications of the fuse.
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12.2.1 Version Description


The RPWR is available in one functional version, namely, N1.

12.2.2 Functions and Features


The RPWR accesses two 48 V/60 V DC power supplies and supplies the 48 V power to six
ODUs.
Table 12-6 provides the functions and features of the RPWR.
Table 12-6 Functions and features of the RPWR
Function and
Feature

RPWR

Input power

Provides the 48 V power supply after converting the 48 V DC


power supply, which is realized through the internal power module.

Accesses the 48 V/60 V DC power system. The voltage of the


two input DC power supplies ranges from 38.4 V to 72 V.

Combiner function

Combines the power supplies.

Protection against
lightning surge,
and short-circuit

Provides protection against lightning, surge, and short-circuit.

Protection
function

In the case of the DC power interface, the differential-mode voltage


must be more than 2 kV and the common-mode voltage must be more
than 4 kV.

Filtering function

Provides the filtering for the power interface and has the structural
shielding that improves the electromagnetic compatibility.

Power output

Provides six 48 V power supplies for the ODU. The maximum power
consumption of each power supply is 60 W.

Alarm and
indication

Provides one board operation indicator.

Power supply
backup

When the indicator turns red, it indicates that one or more power
modules are faulty.

When the indicator is on and green, it indicates that the board works
normally and no alarms are reported.

The input of the power board supports the 1+1 hot backup. The output
of the power module has no backup.

12.2.3 Working Principle and Signal Flow


The RPWR consists of the combiner module, protection module, filtering module, DC/DC power
module (that is, power module), and status detection module.
Figure 12-3 shows the functional block diagram of the RPWR.
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Figure 12-3 Functional block diagram of the RPWR

Fuse 1

Power
module 1

IF port 1

Fuse 2

Power
module 2

IF port 2

Fuse 3

Power
module 3

IF port 3

Fuse 4

Power
module 4

IF port 4

Fuse 5

Power
module 5

IF port 5

Fuse 6

Power
module 6

IF port 6

-48V_1
-48V_2

Combiner
module

Protection
module

Filtering
module

Soft start
module

Board operation
indicator

Status
detection
module

Optical
coupling
isolation

Six channels

Signal Flow
The two 48 V power supplies pass through the combiner, protection, filtering, soft start, and
power modules after they are accessed to the power board. The voltage converting operation is
performed on the two 48 V power supplies at the power module (using the DC_I and DC_C
grounding mode). Then, six isolated ODU power supplies are sent to the IF board for processing
and finally are used to supply power to ODUs.

Status Detection Module


The status detection module checks whether the output power supply exists and reports the real
condition so that the STAT indicator indicates the condition. When the STAT indicator turns
red, it indicates that one ore more power modules are faulty. When the STAT indicator is on and
green, it indicates that the power supply works normally.

Power Module
The two 48 V power supplies enter the DC/DC power converting module after they traverse
the protection, filtering, and soft start modules. The power supplies are isolated by the internal
transformer of the power module so that six independent stable power supplies can be sent to
the status detection module and finally to the IF board.

12.2.4 Front Panel


The front panel of the RPWR has indicators, power input interfaces, and power output interfaces.

Diagram of the Front Panel


Figure 12-4 shows the appearance of the front panel of the RPWR.
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Figure 12-4 Front panel of the RPWR

RPWR
STAT

NEG(-)
RTN(+)
NEG(-)
RTN(+)
POWER1
POWER2
POWER3
POWER4
POWER4
POWER4

RPWR

Indicators
The front panel of the board has one indicator as follows: board hardware status indicator (STAT)
two colors (red and green)
For the meanings of the status of the indicator, see A Indicators.

Interfaces
The front panel of the RPWR has two power input interfaces and six power output interfaces.
Table 12-7 describes the types and usage of the interfaces of the RPWR.

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Table 12-7 Interfaces of the RPWR


Interface

Type of Interface

Usage

PWR1

48 V power input
interface

Accesses the 48 V power supply.

PWR2

48 V power input
interface

Accesses the 48 V power supply.

POWER1
POWER6

48 V power output
interface

Supplies the 48 V power to the IF board for


processing. Then, the IF board supplies the
power to the ODU.

12.2.5 Valid Slots


The RPWR can be installed in slots 28 and 1116.

12.2.6 Technical Specifications


The technical specifications of the RPWR include the mechanical specifications, power
consumption, input voltage, and specifications of the fuse.

Mechanical Specifications
The mechanical specifications of the RPWR are as follows:
l

Dimensions (mm): 25.4 (W) x 220 (D) x 245.1 (H)

Weight (kg): 1.4

Power Consumption
The maximum power consumption of the RPWR at room temperature (25C) is 60 W.

Input Voltage
The input voltage range of the RPWR is as follows:
l

If the standard voltage of the accessed power supply is -48 V, the voltage of the power
supply ranges from -38.4 V to -57.6 V.

If the standard voltage of the accessed power supply is -60 V, the voltage of the power
supply ranges from -48 V to -72 V.

Specifications of the Fuses


Two types of fuses are available for the main circuit and power modules of the RPWR.
l

Issue 02 (2009-07-30)

Specifications of the fuse for the main circuit are as follows: fast blow fuse, 250 V, 20 A,
UL certificated, 0.00355 ohms, 631 A x A x second, UL/CSA/METI
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Hardware Description

Specifications of the fuse for the power modules of the RPWR are as follows: slow blow
fuse, surface-mounted fuse, 125 V, 4 A, UL certificated, 0.023 ohms, 23 A x A x second,
UL.

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OptiX OSN 3500 II Intelligent Optical Transmission System 13 Optical Amplifier Boards and Dispersion Compensation
Hardware Description
Boards

13

Optical Amplifier Boards and

Dispersion Compensation Boards

About This Chapter


This topic describes the optical amplifier boards such as the BA2, BPA, COA, OBU1, RPC01,
and RPC02, and the dispersion compensation boards such as the DCU.
13.1 BA2
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the BA2 (optical booster amplifier board).
13.2 BPA
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the BPA (optical booster and pre-amplifier board).
13.3 COA
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the COA (case-shaped optical amplifier).
13.4 RPC01
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the RPC01 (forward Raman driving board).
13.5 RPC02
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the RPC02 (backward Raman driving board).
13.6 OBU1
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the TN11OBU1 (optical booster amplifier board).
13.7 DCU
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the DCU (dispersion compensation board).

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Boards
Hardware Description

13.1 BA2
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the BA2 (optical booster amplifier board).
13.1.1 Version Description
The BA2 is available in one functional version, namely, N1.
13.1.2 Functions and Features
During the long-haul transmission of optical signals, the attenuation of the signals is high. Hence,
the BA is required to ensure that the optical receiver can receive normal optical signals.
13.1.3 Working Principle and Signal Flow
The BA2 consists of the EDFA module, control module, communication module, and DC/DC
converter module.
13.1.4 Front Panel
The front panel of the BA2 has indicators and interfaces.
13.1.5 Valid Slots
The BA2 can be installed in slots 28 and 1116 in the subrack.
13.1.6 Feature Code
The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the BA2 indicates the output optical power of the optical interfaces.
13.1.7 Technical Specifications
The technical specifications of the BA2 include the parameters specified for optical interfaces,
mechanical specifications, and power consumption.

13.1.1 Version Description


The BA2 is available in one functional version, namely, N1.

13.1.2 Functions and Features


During the long-haul transmission of optical signals, the attenuation of the signals is high. Hence,
the BA is required to ensure that the optical receiver can receive normal optical signals.
Figure 13-1 shows the position of the BA in the optical transmission system.
Figure 13-1 Position of the BA in the optical transmission system
Transmit

BA

Receive

The BA2 amplifies the power of two-channel optical signals. Table 13-1 provides the functions
and features of the BA2.
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Hardware Description
Boards

Table 13-1 Functions and features of the BA2


Function and
Feature

BA2

Basic functions

Increases the launched optical power of the line board to


1315 dBm or 1518 dBm. As a result, when the G.652
optical fiber with a loss of 0.275 dB/km is used, the
transmission distance can be 120 km, 130 km, or above.

Supporting the
EDFA

Supports the automatic control of the laser temperature and


optical power of the EDFA module.
Supports the automatic monitoring of the input and output
optical power of the EDFA module and query of the optical
power of the EDFA module.
Supports the protection function of the EDFA module.
When no optical signals are received, the laser is
automatically turned off. When optical signals are received,
the laser is automatically turned on.

Performance
events and alarms
monitoring

Supports the reporting of the performance parameters of the


laser. Reports various alarms and performance events,
which facilitates the management and maintenance of the
equipment.

Software upgrade

Supports the software upgrade and expansion without


interrupting services.

CAUTION
The wavelength of the optical signal transmitted to the BA2 must be within the range from 1530
nm to 1560 nm. Otherwise, the input optical signal cannot be amplified correctly. Hence, make
sure that the output wavelength of the line board that is interconnected with the BA2 is within
the required range.
NOTE

The BA2 provides the intelligent power adjustment (IPA) function. When the IPA function is enabled and
no input signals are detected on the receive side of a line board, the pumping laser is turned off to prevent
high laser power from damaging the eyes.

13.1.3 Working Principle and Signal Flow


The BA2 consists of the EDFA module, control module, communication module, and DC/DC
converter module.
Figure 13-2 shows the functional block diagram of the BA2.

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Boards
Hardware Description

Figure 13-2 Functional block diagram of the BA2


Optical
input

Fiber
distributor

EDFA module
Doped
erbium
fiber
WDM
Input
Output
isolate
isolate
coupler

Input
power
monitor
(Pin1)
Input
power

Optical
splitter

Filter

Optical
output

Output
power
monitor
(Pin2)

Laser pump

Pump Pump Temperat


current
ure
current detect
Laser
shutdown
Manual
LOS in
control
AD/DA

Output
power
Pump
temperature
control

Control&Generation alarms
Control module

Communication
module
+3.3 V
DC/DC
converter
module

DC/DC
converter
module

Communication
SCC unit

Fuse

-48 V/ -60 V
-48 V/ -60 V

Fuse

+3.3 V
backup
power

EDFA Module
The optical amplifier unit consists of two EDFA modules. One module is the BA and the other
module is the PA. When the board is used as a PA, an optical filter with 1550.12 nm as the
central wavelength is added to the optical output end of the module. A BA does not have the
filter. A semi-conductor laser bump with 980 nm as the central wavelength is in the erbium fiber
inside the EDFA module. Bump light and input signal light are coupled into the erbium fiber
through an optical coupler. The input and output optical signals of the module are led out by two
fiber splitters according to a specific coupling ratio. Then, the optical signals are converted into
optical current by two PIN photoelectrical diodes. The input and output power of the EDFA
module is determined according to the optical signals. The module also applies optical isolating
measures at the input and output ends to improve the performance of the module.

Control Module
The control module performs the following functions:

13-4

Detects and drives bump electricity.

Controls the temperature of the bump laser.


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Hardware Description
Boards
l

Detects the input and output power.

Reports alarms.

The control module consists of the A/D converting unit, D/A converting unit, and CPU. The A/
D converting unit converts the temperature value of the cooling electricity and the input/output
optical power from analog values into digital values. The converted values are sent to the CPU,
which generates performance reporting events or alarms. The A/D converting unit also converts
bump electricity from analog values into digital values. The converted values are also sent to
the CPU. After the CPU processes the converted values, the D/A converting unit precisely
controls the driving analog circuit of the bump laser of the EDFA optical module. The internal
temperature of the bump laser module remains at 25. The temperature sensor inside the bump
laser outputs temperature change to drive the cooler to keep the internal temperature of the bump
laser module at 25.

Communication Module
The communication module supports Ethernet communication.

DC/DC Converter Module


It converts the 48/60 V power supply into the DC voltages that the modules of the board
require.

13.1.4 Front Panel


The front panel of the BA2 has indicators and interfaces.

Diagram of the Front Panel


The BA2 is available in two types, namely, one-interface BA2 and two-interface BA2.
Figure 13-3 shows the appearance of the front panel of the one-interface BA2.

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Hardware Description

Figure 13-3 Front panel of the one-interface BA2

BA2
STAT
ACT
PROG
SRV

LASER
RADIATION
DO NOT VIEW DIRECTLY
WITH OPTICAL
INSTRUMENTS

CLASS 1M LASER
PRODUCT

OUT1
IN1

BA2

Figure 13-4 shows the appearance of the front panel of the two-interface BA2.

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Boards

Figure 13-4 Front panel of the two-interface BA2

BA2
STAT
ACT
PROG
SRV

LASER
RADIATION
DO NOT VIEW DIRECTLY
WITH OPTICAL
INSTRUMENTS

CLASS 1M LASER
PRODUCT

OUT1
IN1
OUT2 IN2

BA2

Indicators
The front panel of the board has the following indicators:
l

Board hardware status indicator (STAT) two colors (red and green)

Service activation status indicator (ACT) one color (green)

Board software status indicator (PROG) two colors (red and green)

Service alarm indicator (SRV) three colors (red, green, and yellow)

For the meanings of the status of the indicators, see A Indicators.

Interfaces
The front panel of the one-interface BA2 has one optical interface. The optical interface transmits
and receives one channel of optical signals. The one-interface BA2 uses the swappable optical
module, which facilitates the maintenance and upgrading of the optical module.
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Hardware Description

The front panel of the two-interface BA2 has two optical interfaces. The optical interfaces
transmit and receive two channels of optical signals. The two-interface BA2 uses the swappable
optical module, which facilitates the maintenance and upgrading of the optical module.

WARNING
If the front panel of the one-interface BA2 has two LC optical interfaces, only the upper optical
interface (IN1/OUT1) is valid. In the case of the BA2 whose front panel has two LC optical
interfaces, determine whether the BA2 is a one-interface BA2 or a two-interface BA2 according
to 13.1.6 Feature Code.
Table 13-2 describes the type and usage of the optical interface of the one-interface BA2.
Table 13-2 Optical interface of the one-interface BA2
Interface

Type of
Interface

Usage

IN

LC

Receives one channel of optical signals.

OUT

LC

Transmits one channel of optical signals.

Table 13-3 describes the types and usage of the optical interfaces of the two-interface BA2.
Table 13-3 Optical interfaces of the two-interface BA2
Interface

Type of Interface

Usage

IN1

LC

Receives the first channel of optical signals.

OUT1

LC

Transmits the first channel of optical signals.

IN2

LC

Receives the second channel of optical signals.

OUT2

LC

Transmits the second channel of optical signals.

13.1.5 Valid Slots


The BA2 can be installed in slots 28 and 1116 in the subrack.

13.1.6 Feature Code


The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the BA2 indicates the output optical power of the optical interfaces.
Table 13-4 provides the relationship between the feature code of the BA2 and the output optical
power.
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Boards

Table 13-4 Relationship between the feature code of the BA2 and the output optical power
Board

Feature Code

Output Optical Power

SSN1BA201

01

Dual-channel optical power


amplification: 14 dBm

SSN1BA202

02

Dual-channel optical power


amplification: 17 dBm

SSN1BA203

03

Optical power amplification:


14 dBm

SSN1BA204

04

Optical power amplification:


17 dBm

SSN1BA205

05

Dual-channel optical power


amplification: 14 dBm and 17
dBm

13.1.7 Technical Specifications


The technical specifications of the BA2 include the parameters specified for optical interfaces,
mechanical specifications, and power consumption.

Parameters Specified for Optical Interfaces


Table 13-5 lists the parameters specified for the optical interfaces of the BA2.
Table 13-5 Parameters specified for the optical interfaces of the BA2
Parameter

Value

Nominal bit rate

2488320 kbit/s and 9953280 kbit/s

Application code

V-16.2, U-16.2, L-64.2, V-64.2, and U-64.2

Line code pattern

NRZ

Input wavelength (nm)

BA: 1530 to 1565

Input optical power


(dBm)

BA: -6 to +3

Output optical power


(dBm)

BA: 13 to 15 or 15 to 17

Noise figure (dB)

BA: < 6.5

Mechanical Specifications
The mechanical specifications of the BA2 are as follows:
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Hardware Description
l

Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)

Weight (kg): 1.0

Power Consumption
The maximum power consumption of the BA2 at room temperature (25C) is 20 W.

13.2 BPA
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the BPA (optical booster and pre-amplifier board).
13.2.1 Version Description
The BPA is available in two functional versions, namely, N1 and N2. The N1BPA is no longer
manufactured.
13.2.2 Functions and Features
During the long-haul transmission of optical signals, the attenuation of the signals is high. Hence,
the BA and PA are required to ensure that the optical receiver can receive normal optical signals.
13.2.3 Working Principle and Signal Flow
The BPA consists of the optical part, driving and detecting part, and data processing and
communication part.
13.2.4 Front Panel
The front panel of the BPA has indicators, interfaces, and a laser safety class label.
13.2.5 Valid Slots
The BPA can be installed in slots 28 and 1116 in the subrack.
13.2.6 Feature Code
The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the BPA indicates the output optical power of the optical interfaces.
13.2.7 Technical Specifications
The technical specifications of the BPA include the parameters specified for optical interfaces,
mechanical specifications, and power consumption.

13.2.1 Version Description


The BPA is available in two functional versions, namely, N1 and N2. The N1BPA is no longer
manufactured.
Table 13-6 describes the versions of the BPA.
Table 13-6 Versions of the BPA

13-10

Item

Description

Functional Versions

The BPA is available in two functional versions, namely, N1


and N2.

Differences

The N1BPA consists of two EDFA optical modules, whereas


the N2BPA has only one EDFA optical module.
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Item

Description

Substitution

The two versions can substitute for each other when certain
conditions are met. If the ALS function is required and the
N2BPA is used to substitute for the N1BPA, enable the ALS
function on the N2BPA. If the ALS function is required and the
N1BPA is used to substitute for the N2BPA, enable the ALS
function on the line board. If the ALS function is not required,
this restriction is not applicable.

13.2.2 Functions and Features


During the long-haul transmission of optical signals, the attenuation of the signals is high. Hence,
the BA and PA are required to ensure that the optical receiver can receive normal optical signals.
Figure 13-5 shows the positions of the BA and PA in the optical transmission system.
Figure 13-5 Positions of the BA and PA in the optical transmission system
Transmit

Receive

BA

PA

Transmit

Receive

Table 13-7 provides the functions and features of the BPA.


Table 13-7 Functions and features of the BPA

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Function and
Feature

BPA

Basic functions

Increases the launched optical power of the line board to 13


15 dBm or 1518 dBm. As a result, when the G.652 optical
fiber with a loss of 0.275 dB/km is used, the transmission
distance can be 120 km, 130 km, or above.

Pre-amplification
function

Provides the PA module to pre-amplify the received optical


signals. Increases the power of the small-volume optical
signals by 2225 dB (N1BPA) or 2233 dB (N2BPA) so that
the sensitivity of the receiver increases to 37 dBm.

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Function and
Feature

BPA

Supporting the EDFA

Supports the automatic control of the laser temperature and


optical power of the EDFA module.

Supports the automatic monitoring of the input and output


optical power of the EDFA module and query of the optical
power of the EDFA module.

Supports the protection function of the EDFA module.


When no optical signals are received, the laser is
automatically turned off. When optical signals are received,
the laser is automatically turned on.

Performance events
and alarms
monitoring

Supports the reporting of the performance parameters of the


laser. Reports various alarms and performance events, which
facilitates the management and maintenance of the equipment.

Software upgrade

Supports the software upgrade and expansion without


interrupting services.

13.2.3 Working Principle and Signal Flow


The BPA consists of the optical part, driving and detecting part, and data processing and
communication part.
Figure 13-6 shows the functional block diagram of the N1BPA.
Figure 13-6 Functional block diagram of the N1BPA
Optical input

Optical output

Optical input

Drive
module

Module
temperature
control

Optical
part

EDFA optical module 2

EDFA optical module 1

Pump current
check

Optical output

Input/output
power
check

Pump
Drive
current
module
check

Module
temperature
control

Input
power
check

Output
power
check

Driving
and
detecting
Fixed filter
part

A/D or D/A conversion

SCC

Communication
module

Control
module

Data processing and


communication part

Figure 13-7 shows the functional block diagram of the N2BPA.

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Figure 13-7 Functional block diagram of the N2BPA


Optical input

Optical output

Optical input

Optical output

Optical
part

EDFA optical module

Pump current
check

Drive
module

Module
temperature
control

Input/output
power
check

Pump
Drive
current
module
check

Module
temperature
control

Input/output
power
check

Driving
and
detecting
part

A/D or D/A conversion

SCC

Communication
module

Control
module

Data processing and


communication part

Optical Part
The N1BPA consists of two EDFA optical modules, whereas the N2BPA has only one EDFA
optical module. The EDFA optical module magnifies the optical power.

Driving and Detecting Part


The driving and detecting part provides the EDFA optical module with the driving current. It
also checks the working status of each part in the EDFA optical module. In addition, it predicts
and handles possible faults.
The driving and detecting part performs the following functions: checking the pump current,
driving the optical module, controlling the temperature of the optical module, and checking the
input and output optical power.

Data Processing and Communication Part


The data processing and communication part consists of the CPU and peripheral chips. The data
processing and communication part analyzes the test result of the tested circuit. Then, it adjusts
the driving circuit based on the analysis result so that the gain or output optical power of the
EDFA optical module remains in the range of the rated value. It also classifies the abnormal
states represented by the measured values and reports the abnormal states to the NMS.

13.2.4 Front Panel


The front panel of the BPA has indicators, interfaces, and a laser safety class label.

Diagram of the Front Panel


Figure 13-8 shows the appearance of the front panel of the BPA.

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Hardware Description

Figure 13-8 Front panel of the BPA

BPA
STAT
ACT
PROG
SRV

LASER
RADIATION
DO NOT VIEW DIRECTLY
WITH OPTICAL
INSTRUMENTS

CLASS 1M LASER
PRODUCT

BOUT
BIN
POUT
PIN

BPA

Indicators
The front panel of the board has the following indicators:
l

Board hardware status indicator (STAT) two colors (red and green)

Service activation status indicator (ACT) one color (green)

Board software status indicator (PROG) two colors (red and green)

Service alarm indicator (SRV) three colors (red, green, and yellow)

For the meanings of the status of the indicators, see A Indicators.

Interfaces
The front panel of the BPA has two LC optical interfaces. Table 13-8 describes the types and
usage of the optical interfaces of the BPA.
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Table 13-8 Optical interfaces of the BPA


Interface

Type of
Interface

Usage

BIN

LC

Receives one channel of optical signals for


amplification.

BOUT

LC

Transmits one channel of amplified optical


signals.

PIN

LC

Receives one channel of optical signals for preamplification.

POUT

LC

Transmits one channel of pre-amplified optical


signals.

13.2.5 Valid Slots


The BPA can be installed in slots 28 and 1116 in the subrack.

13.2.6 Feature Code


The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the BPA indicates the output optical power of the optical interfaces.
Table 13-9 provides the relationship between the feature code of the BPA and the output optical
power.
Table 13-9 Relationship between the feature code of the BPA and the output optical power
Board

Feature Code

Description

SSN1BPA01 and
SSN2BPA01

01

The receiver sensitivity of the PA module


is 37 dBm.
The output optical power of the BA
module is 14 dBm.

SSN1BPA02

02

The receiver sensitivity of the PA module


is 37 dBm.
The output optical power of the BA
module is 17 dBm.

13.2.7 Technical Specifications


The technical specifications of the BPA include the parameters specified for optical interfaces,
mechanical specifications, and power consumption.

Parameters Specified for Optical Interfaces


Table 13-10 lists the parameters specified for the optical interfaces of the BPA.
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Table 13-10 Parameters specified for the optical interfaces of the BPA
Parameter

Value

Nominal bit rate

2488320 kbit/s or 9953280 kbit/s

Application code

V-16.2, U-16.2, L-64.2, V-64.2, and U-64.2

Line code pattern

NRZ

Input wavelength (nm)

BA: 1530 to 1565


PA: 1550.12

Input optical power


(dBm)

BA: -6 to +3
PA: -28 to -10 (when the BPA works with the line board at the rate
of 10 Gbit/s)
PA: -38 to -10 (when the BPA works with the line board at the rate
less than 10 Gbit/s)

Output optical power


(dBm)

N1BPA: 13 to 15 or 15 to 17 (BA)

Sensitivity (dBm)

PA: -37

Noise figure (dB)

BA: < 6.5

N2BPA: 13 to 15 (BA)

PA: < 6

NOTE

When you perform a loopback on the PA module of the BPA, prevent the damage caused by high input
optical power to the optical module.

Mechanical Specifications
The mechanical specifications of the BPA are as follows:
l

Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)

Weight of the N1BPA (kg): 1.0

Weight of the N2BPA (kg): 1.2

Power Consumption
The maximum power consumption of the N1BPA at room temperature (25C) is 20 W.
The maximum power consumption of the N2BPA at room temperature (25C) is 11 W.

13.3 COA
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the COA (case-shaped optical amplifier).
13.3.1 Version Description
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The COA is available in three functional versions, namely, 61, 62, and N1.
13.3.2 Functions and Features
The COA integrates the optical amplifier module, the driving circuit, and the communication
circuit in an aluminium case.
13.3.3 Working Principle and Signal Flow
The 61COA and N1COA consist of the EDFA module, control module, communication module,
and DC/DC converter module.
13.3.4 Front Panel
The front panel of the COA has indicators and interfaces.
13.3.5 Valid Slots
The COA adopts the case-shape design. Hence, the COA does not require a slot in the subrack.
13.3.6 Feature Code
The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the 61COA indicates the output optical power of the optical interfaces.
13.3.7 Technical Specifications
The technical specifications of the COA include the parameters specified for optical interfaces,
mechanical specifications, and power consumption.

13.3.1 Version Description


The COA is available in three functional versions, namely, 61, 62, and N1.
The working principle of the 62COA is basically the same as the working principle of the 61COA
or N1COA. The difference between the 62COA and the 61COA (N1COA) is with regard to the
used optical amplifier modules. The 62COA uses the Raman optical amplifier module, whereas
the 61COA and N1COA use the EDFA optical amplifier module.
NOTE

The COA that occurs in the following text includes the 61COA, N1COA, and 62COA. The characteristics
of the COA are the common characteristics of the three types of COAs.

Table 13-11 describes the versions of the COA.


Table 13-11 Versions of the COA
Item

Description

Functional versions

The COA is available in three functional versions, namely, 61, 62,


and N1.

Differences

The 61COA is the EDFA optical amplifier in the 1550 nm fiber


communication window.
The N1COA is the EDFA optical amplifier in the 1530 nm to 1560
nm fiber communication window.
The N1COA does not have a filter and is a multi-wavelength
amplifier.
The 62COA uses the Raman optical amplifier module.

Substitution

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The versions cannot be substituted with each other.

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13.3.2 Functions and Features


The COA integrates the optical amplifier module, the driving circuit, and the communication
circuit in an aluminium case.
The COA is an external and independent amplifier and does not occupy a slot in the subrack.
The COA can work independently. The equipment supports a maximum of two 61COAs, two
N1COAs, or one 62COA.

61COA and N1COA


The 61COA/N1COA is equipped with only one EDFA optical module. The 61COA/N1COA
can work as a power amplifier, a pre-amplifier, or a line amplifier. Figure 13-9 shows the
appearance of the 61COA/N1COA.
The optical characteristics of the 61COA/N1COA are the same as the optical characteristics of
the optical amplifier boards such as the BPA and BA2. The difference between the 61COA/
N1COA and the optical amplifier boards is that the 61COA/N1COA is an external optical
amplifier unit, which does not occupy a slot in the subrack. The 61COA/N1COA can be directly
installed in the cabinet but requires separate power supply.
Figure 13-9 Appearance of the 61COA/N1COA (PA)

The application of the 61COA/N1COA in the optical transmission system is the same as the
application of the BA2 and BPA in the optical transmission system. Table 13-12 provides the
functions and features of the 61COA/N1COA.
Table 13-12 Functions and features of the 61COA/N1COA

13-18

Function and
Feature

61COA/N1COA

Power
amplification
function

The 61COA increases the launched optical power of the line


board to 1315 dBm or 1517 dBm. As a result, the valid
transmission distance of optical signals is extended.

Pre-amplification
function

The N1COA provides the pre-amplification function. The


receiver sensitivity is 38 dBm.

ALS function

Supports the ALS function.


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Function and
Feature

61COA/N1COA

Communication
through serial ports

Communicates with the CXL through the RS-232 serial


port, reports the alarms and performance events of the COA
to the NMS, and receives the configuration commands
issued by the NMS.

62COA
The 62COA is a case-shaped Raman optical amplifier and is used at the receive end of the SDH
equipment.
The 62COA transmits counter-propagated pumping optical signals to fibers for distributed
Raman amplification. The gain medium of distributed Raman amplification is the line fiber that
can realize better noise performance. This is different from the 61COA. Hence, the 62COA can
extend the transmission distance, reduce the signal-to-noise ratio, and realize ultra long hop
transmission for a single span.
Figure 13-10 shows the appearance of the 62COA.
Figure 13-10 Appearance of the 62COA
4

2
3

1. Captive screw
4. ESD jack

2. Ejector lever
5. Power access board

3. COA board

The 62COA is a case-shaped Raman optical amplifier and is used at the receive end of the optical
transmission system. The optical signals are amplified during transmission based on the
stimulated Raman scattering effect of the fiber. The 62COA needs to work with the EDFA to
realize the transmission of optical signals for more than 170 km. For details, see Figure
13-11.
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13 Optical Amplifier Boards and Dispersion Compensation OptiX OSN 3500 II Intelligent Optical Transmission System
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Hardware Description

Figure 13-11 Application of the 62COA


Raman amplifier
Signal light
EDFA

Pump light

Fiber
Transmitting end

Pump light

EDFA

Laser

Coupler

Receiving end

The Raman amplifier amplifies optical signals during transmission by transmitting counterpropagated pumping optical signals to fibers for distributed Raman amplification. As a result,
the phase of optical signals is significantly different from the phase of pump signals. The power
fluctuation of the Raman pumping is offset in the counter-propagation. Hence, the noise caused
by the pump can be effectively suppressed.
Table 13-13 provides the functions and features of the 62COA.
Table 13-13 Functions and features of the 62COA
Function and
Feature

62COA

Basic functions

Is configured at the receive end of the SDH system, and


realizes extra long-haul transmission (more than 170 km)
when working with an EDFA whose output power is 17
dBm at the transmit end.

Pre-amplification
function

The 62COA provides the pre-amplification function. The


receiver sensitivity is 39 dBm.

ALS function

Supports the ALS function.

Communication
through serial ports

Communicates with the CXL through the RS-232 serial


port, reports the alarms and performance events of the COA
to the NMS, and receives the configuration commands
issued by the NMS.

13.3.3 Working Principle and Signal Flow


The 61COA and N1COA consist of the EDFA module, control module, communication module,
and DC/DC converter module.
The working principle of the N1COA is similar to the working principle of the 61COA. The
61COA has the filter unit, whereas the N1COA does not have the filter unit.
Figure 13-12 shows the functional block diagram of the 61COA/N1COA.

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Hardware Description
Boards

Figure 13-12 Functional block diagram of the 61COA/N1COA


Optical output
Optical input
Fixed
filter

For pre-amplification

EDFA optical
module

Pump
power check

Drive
module

Module
temperature
control

Optical part

Input/Output
Power check

Driving and
detecting part

A/D or D/A conversion

SCC

Communication
module

Control
module

Data processing and


communication part

EDFA Module
The optical amplifier unit consists of two EDFA modules. One module is the BA and the other
module is the PA. When the board is used as a PA, an optical filter with 1550.12 nm as the
central wavelength is added to the optical output end of the module. A BA does not have the
filter. A semi-conductor laser bump with 980 nm as the central wavelength is in the erbium fiber
inside the EDFA module. Bump light and input signal light are coupled into the erbium fiber
through an optical coupler. The input and output optical signals of the module are led out by two
fiber splitters according to a specific coupling ratio. Then, the optical signals are converted into
optical current by two PIN photoelectrical diodes. The input and output power of the EDFA
module is determined according to the optical signals. The module also applies optical isolating
measures at the input and output ends to improve the performance of the module.

Control Module
The control module performs the following functions:
l

Detects and drives bump electricity.

Controls the temperature of the bump laser.

Detects the input and output power.

Reports alarms.

The control module consists of the A/D converting unit, D/A converting unit, and CPU. The A/
D converting unit converts the temperature value of the cooling electricity and the input/output
optical power from analog values into digital values. The converted values are sent to the CPU,
which generates performance reporting events or alarms. The A/D converting unit also converts
bump electricity from analog values into digital values. The converted values are also sent to
the CPU. After the CPU processes the converted values, the D/A converting unit precisely
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13 Optical Amplifier Boards and Dispersion Compensation OptiX OSN 3500 II Intelligent Optical Transmission System
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Hardware Description

controls the driving analog circuit of the bump laser of the EDFA optical module. The internal
temperature of the bump laser module remains at 25. The temperature sensor inside the bump
laser outputs temperature change to drive the cooler to keep the internal temperature of the bump
laser module at 25.

Communication Module
The communication module supports Ethernet communication.

DC/DC Converter Module


It converts the 48/60 V power supply into the DC voltages that the modules of the board
require.

13.3.4 Front Panel


The front panel of the COA has indicators and interfaces.

Diagram of the Front Panel


Figure 13-13 shows the appearance of the front panel of the 61COA/N1COA.
Figure 13-13 Front panel of the 61COA/N1COA
9

10

1. ID DIP switch

2. Running indicator

4. RS-232-1
7. MONITOR-2

5. RS-232-2
6. MONITOR-1
8. IN: input optical interface

9. OUT: output optical interface 10. Power switch

11

3. Alarm indicator

11. -48 V power interface

Figure 13-14 shows the appearance of the front panel of the 62COA.

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Boards

Figure 13-14 Front panel of the 62COA

1. SC/PC optical interface (OUT)

2. LSH optical interface (IN)

3. Air filter

4. Fan board

5. RJ-45 interface

6. RS-232-1

7. RS-232-2

8. DIP switch (bits 8-5)

9. DIP switch (bits 4-1)

10. Power input interface

11. Power switch

Indicators
The front panel of the board has the following indicators:
l

Board running status indicator (RUN) one color (green)

Fan alarm indicator (ALM) one color (red)

For the meanings of the status of the indicators, see A Indicators.

Interfaces
The front panel of the 61COA/N1COA has one SC/PC optical interface. The optical interface
receives and transmits one channel of optical signals. The input optical interface of the 62COA
is connected to the LSH flange and the output optical interface is connected to the SC flange.
Figure 13-15 shows the SC/PC fiber connector that the SC/PC optical interfaces of the 61COA
and N1COA use.
Figure 13-15 SC/PC fiber connector

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Hardware Description

Figure 13-16 shows the flange and fiber connector that the input optical interface of the 62COA
uses.
Figure 13-16 LSH flange and fiber connector

NOTE

The protective cap of the LSH fiber jumper is specially designed. When you connect the LSH fiber jumper
to an LSH flange, do not remove the protective cap but insert the LSH fiber jumper into the LSH flange
directly.

The COA has two RS-232 serial ports, which function as the control and communication ports.
The serial ports communicate with the SCC unit and report alarms and performance events.
Table 13-14 provides the pin assignments of the RS-232 serial port.
Table 13-14 Pin assignments of the RS-232 serial port
Front View

Pin of RS-232-2

Definition

Used to receive
data.

Used to transmit
data.

Used for
common
grounding.

Pin of RS-232-1

TIP

To realize the communication between the COA and the CXL, use a serial port control line to connect the
RS-232-1 serial port of the COA to the F&f port of the subrack.

The RS-232-2 serial port is used in the scenario where several COAs are used at a single station.
To enable each COA to communicate with the SCC unit, use a serial port line to connect the
RS-232-2 port of COA 1 to the RS-232-1 port of COA 2, and use another serial port line to
connect the RS-232-2 port of COA 2 to the RS-232-1 port of COA 3. Connect the other COAs
similarly. In this case, each COA communicates with the SCC unit through the RS-232-1 serial
port of COA 1.
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The COA has two MONITOR interfaces. When the 61COA is used alone, the MONITOR-1
interface and MONITOR-2 interface are the alarm output interfaces. In this case, the two
MONITOR interfaces have the same functions. Table 13-15 provides the pin assignments of
the MONITOR interfaces.
Table 13-15 Pin assignments of the MONITOR interfaces
Front View

Pin of
MONITOR-2

Definition

1 and 6

1 and 6

The input optical power of the


EDFA module is very low.

2 and 7

2 and 7

The working current of the pump


laser of the EDFA module
exceeds the threshold.

3 and 8

3 and 8

The cooling current of the pump


laser of the EDFA module
exceeds the threshold.

4 and 9

4 and 9

The ambient temperature of the


EDFA module exceeds the
threshold.

Digital ground

Pin of
MONITOR1

The 62COA has one RJ-45 connector, through which the 62COA is connected to the computer
for software loading. Table 13-16 provides the pin assignments of the RJ-45 connector of the
62COA.
Table 13-16 Pin assignments of the RJ-45 connector of the 62COA
Front View

8 7 6 5 4 3 2 1

Pin

Description

Transmitting (+)

Transmitting ()

Receiving (+)

Not defined

Not defined

Receiving ()

78

Not defined

The COA has one DIP switch.

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Hardware Description
l

The DIP switches of the 61COA/N1COA are in the lower left corner of the front panel.
The DIP switches are used to set the ID of the 61COA/N1COA. When a bit of the DIP
switch is set upwards, the bit is in the OFF position. When the bit is set downwards, the bit
is in the ON position. The SCC identifies a 61COA/N1COA through the ID of the 61COA/
N1COA. The SCC communicates with the 61COAs/N1COAs whose IDs are different in
the master-slave calling mode.

The DIP switch of the 62COA is used to set the ID of the 62COA and the type of fiber.
The DIP switch has eight bits. The bit on the leftmost side is numbered "8" and the bit on
the rightmost side is numbered "1". When a bit of the DIP switch is set upwards, the bit
indicates "0". When the bit is set downwards, the bit indicates "1". The first four bits (1
4) are used to set the board ID, which ranges from 20 to 35. In actual situations, the first
four bits indicate only the range from 20 to 27. The fifth bit is used to set the type of fiber.
When bit 5 indicates "0", the fiber is of the G.652 type. When bit 5 indicates "1", the fiber
is of the G.655 type.

13.3.5 Valid Slots


The COA adopts the case-shape design. Hence, the COA does not require a slot in the subrack.
In the cabinet, the 61COA or N1COA is installed on a special bracket, and the 62COA is installed
directly in the cabinet through the mounting ears. On the NMS, the logical slots of the 61COA,
N1COA, and 62COA are slots 101 and 102.

Installation Position of the 61COA or N1COA


The installation of the 61COA is considered as an example. The bracket is fixed on the crossbars
on both sides of the cabinet. There are guide rails on the bracket. The 61COA is pushed onto
the bracket along the guide rails and is fixed on the bracket. One bracket can hold two 61COAs
horizontally. The front panels of the two 61COAs are on the front side of the cabinet, as shown
in Figure 13-17.
Figure 13-17 Position of the 61COA in the cabinet

Installation Position of the 62COA


The case-shaped 62COA can be installed in the 300 mm or 600 mm cabinet through mounting
ears and screws. If the upward-wiring scheme is applied, the 62COA is installed at the bottom
of the cabinet (positions of the first and third floating nuts). If the downward-wiring scheme is
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applied, the 62COA is installed in any idle place of the 2.6 m high cabinet or in the cabinet that
is not fully configured.

13.3.6 Feature Code


The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the 61COA indicates the output optical power of the optical interfaces.
Table 13-17 provides the relationship between the feature code of the 61COA and the output
optical power.
Table 13-17 Relationship between the feature code of the 61COA and the output optical power
Board

Feature Code

Output Optical Power

SS61COA01

01

14 dBm

SS61COA02

02

17 dBm

13.3.7 Technical Specifications


The technical specifications of the COA include the parameters specified for optical interfaces,
mechanical specifications, and power consumption.

Parameters Specified for Optical Interfaces


Table 13-18 lists the parameters specified for the optical interfaces of the COA.
Table 13-18 Parameters specified for the optical interfaces of the COA
Parameter

Value
61COA

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N1COA

62COA

Line code pattern

NRZ

Operating wavelength
range (nm)

1550

Input optical power


(dBm)

BA: -6 to +3

Output optical power


(dBm)

13 to 15

Pump wavelength
(nm)

NA

1451.2

Maximum on/off gain


(dB)

NA

> 15 (in the case of the G.652


fiber)

Noise figure (dB)

NA

< -1.5

1550.12
-10 to -37

-39 to -20 (2.5 Gbit/s signals


without the FEC function)

15 to 17

NA

PA: -10 to -37

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Hardware Description

Laser Safety Class


The safety class of the laser on the board is Class 1M. The maximum launched optical power of
the optical interfaces is within the range from 10 dBm (10 mW) to 22.15 dBm (164 mW).

Mechanical Specifications
The mechanical specifications of the 61COA and N1COA are as follows:
l

Dimensions (mm): 240 (W) x 190 (D) x 50 (H)

Weight (kg): 3.5

The mechanical specifications of the 62COA are as follows:


l

Dimensions (mm): 294 (W) x 436 (D) x 86 (H)

Weight (kg): 8.0

Power Consumption
The maximum power consumption of the 61COA at room temperature (25C) is 10 W.
The maximum power consumption of the 62COA at room temperature (25C) is 75 W.
The maximum power consumption of the N1COA at room temperature (25C) is 10 W.

13.4 RPC01
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the RPC01 (forward Raman driving board).
13.4.1 Version Description
The RPC01 is available in one functional version, namely, N1.
13.4.2 Functions and Features
The RPC01 supports the online optical performance monitoring function and other functions.
13.4.3 Working Principle and Signal Flow
The RPC01 consists of the Raman pump optical module, driving and detecting module,
communication and control module, and power supply module.
13.4.4 Front Panel
The front panel of the RPC01 has indicators, interfaces, and a laser safety class label.
13.4.5 Valid Slots
The RPC01 is an external forward Raman driving board. Hence, the RPC01 is not installed in
the subrack. The RPC01 is connected to the COM interface of an NE directly or though a hub
to realize the communication with the SCC. The logical slot of the RPC01 on the NMS is slot
104.
13.4.6 Jumpers and DIP Switches
The RPC01 has two groups of jumpers, namely, group J3 and group J4.
13.4.7 Feature Code
The feature code of the RPC01 contains three characters, which indicate the gain of the optical
signal processed by the RPC01.
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13.4.8 Parameter Settings


You can set the parameters for the RPC01 by using the T2000.
13.4.9 Technical Specifications
The technical specifications of the RPC01 include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.

13.4.1 Version Description


The RPC01 is available in one functional version, namely, N1.

13.4.2 Functions and Features


The RPC01 supports the online optical performance monitoring function and other functions.
Table 13-19 provides the functions and features of the RPC01.
Table 13-19 Functions and features of the RPC01
Function and
Feature

RPC01

Basic functions

Generates multi-channel pump light of high power, which provides


energy for the amplification of signals in the fiber.

Realizes the distributed online amplification of signals over long


distance with wide bandwidth and low noise.

Online optical
performance
monitoring function

Provides the online monitoring interface. A small amount of optical


signal can be transmitted to the spectrum analyzer through the
interface so that the spectrum and optical performance of the
multiplexed optical signal can be monitored without a service
interruption.

Performance events
and alarms
monitoring

Detects the pump optical power, temperature control current, pump


current, and back facet current.

13.4.3 Working Principle and Signal Flow


The RPC01 consists of the Raman pump optical module, driving and detecting module,
communication and control module, and power supply module.
The RPC01 is located before the receiver. The RPC01 utilizes the stimulated Raman scattering
effect of the fiber to amplify the optical signals during transmission. The pump light travels in
the reverse direction of the signal light. The RPC01 must work with the EDFA.
Figure 13-18 shows the functional block diagram of the RPC01.

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Hardware Description

Figure 13-18 Functional block diagram of the RPC01 (backward pump)


Splitter Signal light

Signal light

LINE

Pump light
Pump source

Control the
pumping current
and temperature.

SYS
MON

Raman pump optical module

Detect the pump


light power and
current.

PIN

Detect the
temperature.

Driving and detecting module

Control
Memory

CPU

Communication

Communication and control module


Power supply
module
Fuse

Voltages required
by the board

DC power provided
by the backplane

SCC

Backplane
(controlled by
the SCC)

Signal Flow
The pump source of the RPC01 sends the pump light to the WDM side through the LINE optical
interface. On the line, the signals that are amplified through the distributed amplification are
received through the LINE interface. Then, the splitter splits the signals into two channels. The
service optical signals are transmitted through the SYS interface. A few supervisory signals are
transmitted to the test instrument through the MON interface for online optical performance
monitoring. The Ethernet interface of the RPC01 is connected to the COM interface of an NE
directly or through a hub to realize the communication with the SCC.

Functional Modules
l

Raman pump optical module

The laser in the pump source module generates the pump light and sends the pump light
to the optical line for transmission. The Raman pump optical module utilizes the
stimulated Raman scattering effect of the fiber to amplify the optical signals during
transmission.

The splitter splits one channel of optical signals from the pump source module into two
channels of signals of different power. One channel of signals are transmitted through
the SYS interface to the main optical path. The other channel of signals are transmitted
to the MON interface for spectrum detection and supervising.

Driving and detecting module

13-30

Detects the optical power of the service signals in real time.

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Detects the driving current, back facet current, cooling current, and operating
temperature of the pump inside the pump optical module in real time.

Drives the pump laser inside the pump optical module.

Reports alarms and performance events to the logic and control module.

Communication and control module

Controls the operations on the board.

Controls the operations on each module of the board according to the CPU instructions.

Collects the alarms, performance events, working status, and voltage detection
information of each functional module of the board.

Communicates with the SCC.

Power supply module


Converts the DC power provided by the backplane into the power required by each module
of the board.

13.4.4 Front Panel


The front panel of the RPC01 has indicators, interfaces, and a laser safety class label.

Diagram of the Front Panel


Figure 13-19 shows the appearance of the front panel of the RPC01.
Figure 13-19 Front panel of the RPC01

03793010860000002 Y SSE1ROP01

Board manufacturing
information
MON

Board serial
number and name

SYS

LINE

LASER
RADIATION
AVOID EYE OR SKIN
EXPOSURE TO DIRECT OR
SCATTERED RADIATION

CRPC

CLASS 4 LASER
PRODUCT

ALM

RUN

WARNING: FIBERS MUST


BE CONNECTED SEFORE
POWER UP

RS232-1

RS232-2

LAN

Indicators
The front panel of the board has the following indicators:
l

Board running status indicator (RUN) one color (green)

Fan alarm indicator (ALM) one color (red)

For the meanings of the status of the indicators, see A Indicators.


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Hardware Description

Interfaces
The front panel of the RPC01 has six interfaces. Table 13-20 describes the types and usage of
the interfaces of the RPC01.
Table 13-20 Interfaces of the RPC01
Interface

Type of
Interface

Usage

LINE

LSH/APC

Receives the optical signals transmitted from the line.

SYS

LC

Is connected to the BA and transmits the amplified


signals to the fibers.

MON

LC

Monitors the optical performance.


The power of the MON interface is 1/99 of the power
of the SYS interface. That is, the power of the MON
interface is 20 dB less than the power of the SYS
interface.

LAN

RJ-45

Is connected to the COM interface of an NE directly or


through a hub to realize the communication with the
SCC.

RS232-1/
RS232-2

Is an RS-232 communication interface.

13.4.5 Valid Slots


The RPC01 is an external forward Raman driving board. Hence, the RPC01 is not installed in
the subrack. The RPC01 is connected to the COM interface of an NE directly or though a hub
to realize the communication with the SCC. The logical slot of the RPC01 on the NMS is slot
104.

13.4.6 Jumpers and DIP Switches


The RPC01 has two groups of jumpers, namely, group J3 and group J4.
Figure 13-20 shows the jumpers of the RPC01.
Figure 13-20 Jumpers of the RPC01
RPC01

10

J3

J4

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CPU

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To ensure that the board can operate normally, set the jumpers as follows:
l

Short-circuit jumpers 1 and 2 of group J4.

Short-circuit jumpers 3 and 4 of group J4.

Short-circuit jumpers 5 and 6 of group J4.

Short-circuit jumpers 9 and 10 of group J3.

13.4.7 Feature Code


The feature code of the RPC01 contains three characters, which indicate the gain of the optical
signal processed by the RPC01.
Table 13-21 describes the feature code of the RPC01.
Table 13-21 Feature code of the RPC01
Feature Code

Indication

Description

The first character

Is always "G".

The second and third


characters

Gain

Indicates the gain.

Consider the N1RPC01 whose feature code is "G10" as an example. "G10" indicates that the
gain of the optical signal is 10 dB.

13.4.8 Parameter Settings


You can set the parameters for the RPC01 by using the T2000.
You can set the following parameters for the RPC01 by using the T2000:
l

Laser status

Board work type

For the description of each parameter, see F.5 Optical Amplifier Boards.

Interface Display
Table 13-22 shows the serial numbers of the optical interfaces on the front panel of the RPC01
on the NMS.
Table 13-22 Serial numbers of the optical interfaces on the front panel of the RPC01 on the
NMS

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Interface on the Front Panel

Serial Number of the NMS Interface

LINE

SYS

2
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Interface on the Front Panel

Serial Number of the NMS Interface

MON

13.4.9 Technical Specifications


The technical specifications of the RPC01 include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.

Parameters Specified for Optical Interfaces


Table 13-23 lists the parameters specified for the optical interfaces of the RPC01.
Table 13-23 Parameters specified for the optical interfaces of the RPC01
Parameter

Value

Pump wavelength (nm)

1400 to 1500

Operating wavelength (nm)

1529 to 1561

Maximum pump power (dBm)

29

Gain on the G.652 fiber (dB)

10

Gain on the LEAF fiber (dB)

12

Equivalent noise figure on the G.652 fiber (dB)

Equivalent noise figure on the LEAF fiber (dB)

-1

Polarization dependent loss (dB)

0.5

Type of output connector

LSH/APC or LC/PC

Laser Safety Class


The safety class of the laser on the board is Class 4. The maximum launched optical power of
the optical interfaces is more than 27 dBm (500 mW).

Mechanical Specifications
l

Dimensions (mm): 76.0 (W) x 218.5 (D) x 345.0 (H)

Weight (kg): 4.0

Power Consumption
The maximum power consumption of the RPC01 at room temperature (25C) is 70 W.
The maximum power consumption of the RPC01 at room temperature (55C) is 121 W.
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13.5 RPC02
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the RPC02 (backward Raman driving board).
13.5.1 Version Description
The RPC02 is available in one functional version, namely, N1.
13.5.2 Functions and Features
The RPC02 supports the online optical performance monitoring function and other functions.
13.5.3 Working Principle and Signal Flow
The RPC02 consists of the Raman pump optical module, driving and detecting module,
communication and control module, and power supply module.
13.5.4 Front Panel
The front panel of the RPC02 has indicators, interfaces, and a laser safety class label.
13.5.5 Valid Slots
The RPC02 is an external backward Raman driving board. Hence, the RPC02 is not installed in
the subrack. The RPC02 is connected to the COM interface of an NE directly or though a hub
to realize the communication with the SCC. The logical slot of the RPC02 on the NMS is slot
105.
13.5.6 Jumpers and DIP Switches
The RPC02 has two groups of jumpers, namely, group J3 and group J4.
13.5.7 Feature Code
The feature code of the RPC02 contains three characters, which indicate the gain of the optical
signal processed by the RPC02.
13.5.8 Parameter Settings
You can set the parameters for the RPC02 by using the T2000.
13.5.9 Technical Specifications
The technical specifications of the RPC02 include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.

13.5.1 Version Description


The RPC02 is available in one functional version, namely, N1.

13.5.2 Functions and Features


The RPC02 supports the online optical performance monitoring function and other functions.
Table 13-24 provides the functions and features of the RPC02.

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Table 13-24 Functions and features of the RPC02


Function and
Feature

RPC02

Basic functions

Generates multi-channel pump light of high power, which provides


energy for the amplification of signals in the fiber.

Realizes the distributed online amplification of signals over long


distance with wide bandwidth and low noise.

Online optical
performance
monitoring function

Provides the online monitoring interface. A small amount of optical


signal can be transmitted to the spectrum analyzer through the
interface so that the spectrum and optical performance of the
multiplexed optical signal can be monitored without a service
interruption.

Performance events
and alarms
monitoring

Detects the pump optical power, temperature control current, pump


current, and back facet current.

13.5.3 Working Principle and Signal Flow


The RPC02 consists of the Raman pump optical module, driving and detecting module,
communication and control module, and power supply module.
The RPC02 is used at the receive end of the system. The RPC02 utilizes the stimulated Raman
scattering effect of the fiber to amplify the optical signals during transmission.

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Figure 13-21 Functional block diagram of the RPC02 (forward pump)


Splitter Signal light

Signal light

LINE

Pump light
Pump source

Control the
pumping current
and temperature.

SYS
MON

Raman pump optical module

Detect the pump


light power and
current.

PIN

Detect the
temperature.

Driving and detecting module

Control
Memory

CPU

Communication

Communication and control module


Power supply
module
Fuse

Voltages required
by the board

DC power provided
by the backplane

SCC

Backplane
(controlled by
the SCC)

Signal Flow
The signal light is received at the SYS interface and transmitted to the optical line through the
LINE interface. A few supervisory signals are transmitted to the test instrument through the
MON interface for online optical performance monitoring. The pump light that is generated by
the RPC02 is transmitted to the optical line through the LINE interface in the same direction of
the signal light, to realize the distributed amplification of the optical signal. The Ethernet
interface of the RPC02 is connected to the COM interface of an NE directly or through a hub to
realize the communication with the SCC.

Functional Modules
l

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Raman pump optical module

The laser in the pump source module generates the pump light and sends the pump light
to the optical line for transmission. The Raman pump optical module utilizes the
stimulated Raman scattering effect of the fiber to amplify the optical signals during
transmission.

The splitter splits one channel of optical signals from the pump source module into two
channels of signals of different power. One channel of signals are transmitted through
the SYS interface to the main optical path. The other channel of signals are transmitted
to the MON interface for spectrum detection and supervising.

Driving and detecting module


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Detects the optical power of the service signals in real time.

Detects the driving current, back facet current, cooling current, and operating
temperature of the pump inside the pump optical module in real time.

Drives the pump laser inside the pump optical module.

Reports alarms and performance events to the logic and control module.

Communication and control module

Controls the operations on the board.

Controls the operations on each module of the board according to the CPU instructions.

Collects the alarms, performance events, working status, and voltage detection
information of each functional module of the board.

Communicates with the SCC.

Power supply module


Converts the DC power provided by the backplane into the power required by each module
of the board.

13.5.4 Front Panel


The front panel of the RPC02 has indicators, interfaces, and a laser safety class label.

Diagram of the Front Panel


Figure 13-22 shows the appearance of the front panel of the RPC02.
Figure 13-22 Front panel of the RPC02

03793010860000002 Y SSE1ROP01

Board manufacturing
information
MON

Board serial
number and name

SYS

LINE

LASER
RADIATION
AVOID EYE OR SKIN
EXPOSURE TO DIRECT OR
SCATTERED RADIATION

CRPC

CLASS 4 LASER
PRODUCT

ALM

RUN

WARNING: FIBERS MUST


BE CONNECTED SEFORE
POWER UP

RS232-1

RS232-2

LAN

Indicators
The front panel of the board has the following indicators:
l

Board running status indicator (RUN) one color (green)

Fan alarm indicator (ALM) one color (red)

For the meanings of the status of the indicators, see A Indicators.


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Boards

Interfaces
The front panel of the RPC02 has six interfaces. Table 13-25 describes the types and usage of
the interfaces of the RPC02.
Table 13-25 Interfaces of the RPC02
Interface

Type of
Interface

Usage

LINE

LSH/APC

Receives the optical signals transmitted from the line.

SYS

LC

Is connected to the BA and transmits the amplified


signals to the fibers.

MON

LC

Monitors the optical performance.


The power of the MON interface is 1/99 of the power
of the SYS interface. That is, the power of the MON
interface is 20 dB less than the power of the SYS
interface.

LAN

RJ-45

Is connected to the COM interface of an NE directly or


through a hub to realize the communication with the
SCC.

RS232-1/
RS232-2

Is an RS-232 communication interface.

13.5.5 Valid Slots


The RPC02 is an external backward Raman driving board. Hence, the RPC02 is not installed in
the subrack. The RPC02 is connected to the COM interface of an NE directly or though a hub
to realize the communication with the SCC. The logical slot of the RPC02 on the NMS is slot
105.

13.5.6 Jumpers and DIP Switches


The RPC02 has two groups of jumpers, namely, group J3 and group J4.
Figure 13-23 shows the jumpers of the RPC02.
Figure 13-23 Jumpers of the RPC02
RPC02

10

10

J3

J4

CPU

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Hardware Description

To ensure that the board can operate normally, set the jumpers as follows:
l

Short-circuit jumpers 1 and 2 of group J4.

Short-circuit jumpers 3 and 4 of group J4.

Short-circuit jumpers 5 and 6 of group J4.

Do not short-circuit jumpers 9 and 10 of group J3.

13.5.7 Feature Code


The feature code of the RPC02 contains three characters, which indicate the gain of the optical
signal processed by the RPC02.
Table 13-26 describes the feature code of the RPC02.
Table 13-26 Feature code of the RPC02
Feature Code

Indication

Description

The first character

Is always "G".

The second and third


characters

Gain

Indicates the gain.

Consider the N1RPC02 whose feature code is "G10" as an example. "G10" indicates that the
gain of the optical signal is 10 dB.

13.5.8 Parameter Settings


You can set the parameters for the RPC02 by using the T2000.
You can set the following parameters for the RPC02 by using the T2000:
l

Laser status

Board work type

For the description of each parameter, see F.5 Optical Amplifier Boards.

Interface Display
Table 13-27 shows the serial numbers of the optical interfaces on the front panel of the RPC02
on the NMS.
Table 13-27 Serial numbers of the optical interfaces on the front panel of the RPC02 on the
NMS

13-40

Interface on the Front Panel

Serial Number of the NMS Interface

LINE

SYS

2
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Boards

Interface on the Front Panel

Serial Number of the NMS Interface

MON

13.5.9 Technical Specifications


The technical specifications of the RPC02 include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.

Parameters Specified for Optical Interfaces


Table 13-28 lists the parameters specified for the optical interfaces of the RPC02.
Table 13-28 Parameters specified for the optical interfaces of the RPC02
Parameter

Value

Pump wavelength (nm)

1400 to 1500

Operating wavelength (nm)

1529 to 1561

Maximum pump power (dBm)

29.5

Gain on the G.652 fiber (dB)

> 10

Gain on the LEAF fiber (dB)

NA

Equivalent noise figure on the G.652 fiber (dB)

NA

Equivalent noise figure on the LEAF fiber (dB)

NA

Polarization dependent loss (dB)

0.5

Type of output connector

LSH/APC or LC/PC

Laser Safety Class


The safety class of the laser on the board is Class 4. The maximum launched optical power of
the optical interfaces is more than 27 dBm (500 mW).

Mechanical Specifications
The mechanical specifications of the RPC02 are as follows:
l

Dimensions (mm): 76.0 (W) x 218.5 (D) x 345.0 (H)

Weight (kg): 4.2

Power Consumption
The maximum power consumption of the RPC02 at room temperature (25C) is 110 W.
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Hardware Description

13.6 OBU1
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the TN11OBU1 (optical booster amplifier board).
13.6.1 Version Description
The OBU1 is available in one functional version, namely, TN11.
13.6.2 Functions and Features
The OBU1 supports the online optical performance monitoring function, gain lock, transient
control, and other functions.
13.6.3 Working Principle and Signal Flow
The OBU1 consists of the EDFA optical module, driving and detecting module, communication
and control module, and power supply module.
13.6.4 Front Panel
The front panel of the OBU1 has indicators, interfaces, and a laser safety class label.
13.6.5 Valid Slots
The OBU1 can be installed in slots 28 and 1116 in the subrack.
13.6.6 Feature Code
The feature code of the OBU1 contains six characters, which indicate the gain and maximum
nominal input optical power of the optical signals processed by the OBU1.
13.6.7 Parameter Settings
You can set the parameters for the OBU1 by using the T2000.
13.6.8 Technical Specifications
The technical specifications of the OBU1 include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.

13.6.1 Version Description


The OBU1 is available in one functional version, namely, TN11.

13.6.2 Functions and Features


The OBU1 supports the online optical performance monitoring function, gain lock, transient
control, and other functions.
Table 13-29 provides the functions and features of the OBU1.
Table 13-29 Functions and features of the OBU1
Function and
Feature

OBU1

Basic functions

Amplifies a maximum of 40 channels of optical signals with the channel


spacing of 100 GHz at the same time.
Supports the system to transmit services over different fiber spans
without electrical regeneration.

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Hardware Description
Boards

Function and
Feature

OBU1

Typical gain

The typical gain of the OBU101 is 20 dB and the typical gain of the
OBU102 is 23 dB.

Online optical
performance
monitoring
function

Provides the online monitoring interface. A small amount of optical


signal can be transmitted to the spectrum analyzer through the interface
so that the spectrum and optical performance of the multiplexed optical
signal can be monitored without a service interruption.

Gain lock function

The EDFA inside the board has the gain lock function. When one or
more channels are added or dropped, or optical signals of certain
channels fluctuate, the signal gain of other channels is not affected.

Transient control
function

The EDFA inside the board has the transient control function. When
channels are added or dropped, the board can suppress the fluctuation
of the optical power in the path to realize the smooth upgrading and
expansion.

Performance
events and alarms
monitoring

Checks and reports the optical power.


Controls the temperature of the pump laser.
Detects the pump driving current, back facet current, cooling current,
temperature of the pump laser, and ambient temperature of the board.

NOTE

The OBU1 is available in two types, namely, OBU101 and OBU102. The OBU101 is used at the receive
end and the OBU102 is used at the transmit end.

13.6.3 Working Principle and Signal Flow


The OBU1 consists of the EDFA optical module, driving and detecting module, communication
and control module, and power supply module.
Figure 13-24 shows the functional block diagram of the OBU1.

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Hardware Description

Figure 13-24 Functional block diagram of the OBU1

Splitter

EDFA optical module


IN

OUT
Driving
current

MON

Detect the pump


current and
temperature.

PIN

Driving and detecting module

Control
Memory

CPU

Communication

Communication and control module


Power supply
module
Voltages required
by the board

Fuse

DC power provided
by the backplane

Backplane
(controlled
by the
SCC
SCC)

Signal Flow
The OBU1 accesses the multiplexed optical signals, which are amplified by the EDFA optical
module. Then, the OBU1 sends the amplified optical signals to the splitter and transmits the
signals through the OUT interface. The OBU1 also sends a few supervisory signals to the test
instrument for online optical performance monitoring.

EDFA Optical Module


The EDFA optical module amplifies the input optical signals. The EDFA optical module adopts
the gain auto-adjustment technology. Hence, the gain of each operating wavelength signal can
remain in the allowed range.

Splitter
The splitter splits one channel of optical signals from the EDFA optical module into two channels
of signals of different power. One channel of signals are transmitted through the OUT interface
to the main optical path. The other channel of signals are transmitted to the MON interface for
spectrum detection and supervising.
The power of the MON interface is 1/99 of the power of the OUT interface. That is, the power
of the MON interface is 20 dB less than the power of the OUT interface.
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Boards

Communication and Control Module


The communication and control module controls and monitors the functional modules of the
board, and manages the communication.
The communication and control module collects the alarms, performance events, working status,
voltage detection information, and other information of each functional module of the board,
and reports the collected information to the SCC.
The communication and control module receives the commands issued by the SCC to control
and coordinate the operation of each functional module.

13.6.4 Front Panel


The front panel of the OBU1 has indicators, interfaces, and a laser safety class label.

Diagram of the Front Panel


Figure 13-25 shows the appearance of the front panel of the OBU1.
Figure 13-25 Front panel of the OBU1

OBU1
STAT
ACT
PROG
SRV
LASER
RADIATION
DO NOT VIEW DIRECTLY
WITH OPTICAL
INSTRUMENTS

CLASS 1M LASER
PRODUCT

MON
OUT
IN

OBU1

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Boards
Hardware Description

Indicators
The front panel of the board has the following indicators:
l

Board hardware status indicator (STAT) two colors (red and green)

Service activation status indicator (ACT) one color (green)

Board software status indicator (PROG) two colors (red and green)

Service alarm indicator (SRV) three colors (red, green, and yellow)

For the meanings of the status of the indicators, see A Indicators.

Interfaces
The front panel of the OBU1 has three optical interfaces. Table 13-30 describes the types and
usage of the optical interfaces of the OBU1.
Table 13-30 Optical interfaces of the OBU1
Interface

Type of
Interface

Usage

IN

LC

Receives the multiplexed signals to be amplified.

OUT

LC

Transmits the amplified multiplexed signals.

MON

LC

Is connected to the test instrument to monitor the inservice performance.

13.6.5 Valid Slots


The OBU1 can be installed in slots 28 and 1116 in the subrack.

13.6.6 Feature Code


The feature code of the OBU1 contains six characters, which indicate the gain and maximum
nominal input optical power of the optical signals processed by the OBU1.
Table 13-31 describes the feature code of the OBU1.
Table 13-31 Feature code of the OBU1

13-46

Feature Code

Indication

Description

The first character

Is always "G".

The second and third


characters

Gain

Indicates the gain.

The fourth character

Is always "I".

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Feature Code

Indication

Description

The fifth and sixth characters

Maximum nominal input


optical power

Indicates the maximum


nominal input optical power.

Consider the TN11OBU1 whose feature code is "G23I-3" as an example. "G23I-3" indicates
that the gain is 23 dB and the maximum nominal input optical power is 3 dBm.

13.6.7 Parameter Settings


You can set the parameters for the OBU1 by using the T2000.
You can set the following parameters for the OBU1 by using the T2000:
l

Threshold of input power loss

Laser status

Gain

Nominal gain upper threshold

Nominal gain lower threshold

Rated optical power

Configure band

Configure working band parity

Actual band

Actual working band parity

For the description of each parameter, see F.5 Optical Amplifier Boards.

13.6.8 Technical Specifications


The technical specifications of the OBU1 include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.

Parameters Specified for Optical Interfaces


Table 13-32 lists the parameters specified for the optical interfaces of the OBU1.
Table 13-32 Parameters specified for the optical interfaces of the OBU1
Parameter

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Value
OBU1C01

OBU1C02

Operating wavelength range (nm)

1529 to 1561

1529 to 1561

Nominal input optical power


(dBm)

-32 to -4

-32 to -3

Nominal output optical power


(dBm)

-12 to +16

-9 to +20

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Parameter

Value
OBU1C01

OBU1C02

Input power (dBm) of a typical


single wavelength

-20

-19

Maximum nominal output optical


power (dBm) of a single
wavelength

Path gain (dB)

201.5

231.5

Noise figure (dB)

5.5

6.0

Gain flatness (dB)

2.0

2.0

Pre-incline of the gain spectral


form

00.2

1.00.2

Laser Safety Class


The safety class of the laser on the board is Class 1M. The maximum launched optical power of
the optical interfaces is within the range from 10 dBm (10 mW) to 22.15 dBm (164 mW).

Mechanical Specifications
The mechanical specifications of the OBU1 are as follows:
l

Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)

Weight (kg): 1.3

Power Consumption
The maximum power consumption of the OBU101 at room temperature (25C) is 16 W.
The maximum power consumption of the OBU101 at high temperature (55C) is 18 W.
The maximum power consumption of the OBU102 at room temperature (25C) is 18 W.
The maximum power consumption of the OBU102 at high temperature (55C) is 20 W.

13.7 DCU
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the DCU (dispersion compensation board).
13.7.1 Version Description
The DCU is available in two functional versions, namely, N1 and N2. The difference between
the two versions is with regard to the insertion attenuation and compensation.
13.7.2 Functions and Features
The DCU compensates for the dispersion that is accumulated in the fiber during the transmission
of the optical signals in the 10 Gbit/s system and compresses optical signal pulse. In this manner,
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the optical signals that are transmitted can be restored. In addition, the DCU can realize long
haul optical transmission when it works with an optical amplifier board.
13.7.3 Working Principle and Signal Flow
The DCU consists of the dispersion compensation module.
13.7.4 Front Panel
The front panel of the DCU has interfaces, and a laser safety class label.
13.7.5 Valid Slots
The DCU can be installed in slots 28 and 1116 in the subrack.
13.7.6 Feature Code
The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the DCU indicates the compensated dispersion for the optical signals.
13.7.7 Technical Specifications
The technical specifications of the DCU include the parameters specified for optical interfaces,
mechanical specifications, and power consumption.

13.7.1 Version Description


The DCU is available in two functional versions, namely, N1 and N2. The difference between
the two versions is with regard to the insertion attenuation and compensation.
Table 13-33 describes the versions of the DCU.
Table 13-33 Versions of the DCU
Item

Description

Functional versions

The DCU is available in two functional versions, namely, N1 and N2.

Commonness

The working principle of the N1DCU is the same as the working


principle of the N2DCU.

Differences

The insertion loss of the N2DCU is 3 to 5 dB less than the insertion


loss of the N1DCU.
In the case of the N1DCU, two compensation modes are available,
namely, 60 km and 80 km. In the case of the N2DCU, three
compensation modes are available, namely, 40 km, 60 km, and 80
km.

Substitution

Use attenuators to prevent overloaded optical power when you use


the N2DCU to substitute for the N1DCU.

13.7.2 Functions and Features


The DCU compensates for the dispersion that is accumulated in the fiber during the transmission
of the optical signals in the 10 Gbit/s system and compresses optical signal pulse. In this manner,
the optical signals that are transmitted can be restored. In addition, the DCU can realize long
haul optical transmission when it works with an optical amplifier board.
During the long-haul transmission (more than 80 km) of 10 Gbit/s signals, the pulse width of
the optical signals is expanded and the signals are severely distorted because of dispersion. As
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Hardware Description

a result, the optical signals cannot be normally received by the optical receiver. Hence, the DCU
needs to be used to compensate for the dispersion. Figure 13-26 shows the position of the DCU
in the optical transmission system.
Figure 13-26 Position of the DCU in the optical transmission system.
Pulse broading
Optical
transmitter

BA

PA

Pulse compressing

DCU

Optical
receiver

1550.12nm

1550.12nm

NOTE

The operating wavelength of the chirp grating of the DCU is 1550.12 nm. Hence, the central wavelength
of the optical signals transmitted by the optical interface board on the opposite end must also be 1550.12
nm. Otherwise, the dispersion of the optical signals cannot be compensated for and the insertion loss is
high. As a result, no optical signals can be transmitted.

The DCU supports the dispersion compensation for a maximum of two channels of STM-64
optical signals. The DCU can be used with the BA and PA.
Table 13-34 provides the functions and features of the DCU.
Table 13-34 Functions and features of the DCU

13-50

Function
and Feature

N1DCU

N2DCU

Basic
functions

Compensates for the dispersion of a


maximum of two channels of optical
signals at the same time. Supports the
compensated dispersion of 1020 ps/
nm (for the dispersion caused by the
60 km G.652 optical fiber), 1360 ps/
nm (for the dispersion caused by the
80 km G.652 optical fiber), or any
combination.

Compensates for the dispersion of a


maximum of two channels of optical
signals at the same time. Supports the
compensated dispersion of 680 ps/
nm (for the dispersion caused by the
40 km G.652 optical fiber), 1020 ps/
nm (for the dispersion caused by the
60 km G.652 optical fiber), 1360 ps/
nm (for the dispersion caused by the
80 km G.652 optical fiber), or any
combination.

Dispersion
compensatio
n method

Compensates for the dispersion accumulated during the transmission by using


the chirp grating and suppresses the pulse signals to restore the optical signals.

Long haul
transmission
with optical
regeneration

Realizes long haul transmission with optical regeneration when working with
the BA and PA.

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13.7.3 Working Principle and Signal Flow


The DCU consists of the dispersion compensation module.
Figure 13-27 shows the functional block diagram of the DCU.
Figure 13-27 Functional block diagram of the DCU
IN

Dispersion compensation

OUT

module

The dispersion compensation module is used behind the PA to provide optical signals of required
compensation and path penalty.

13.7.4 Front Panel


The front panel of the DCU has interfaces, and a laser safety class label.

Diagram of the Front Panel


Figure 13-28 shows the appearance of the front panel of the one-interface DCU.

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Hardware Description

Figure 13-28 Front panel of the one-interface DCU

DCU

CLASS 1
LASER
PRODUCT

OUT
IN

DCU

Figure 13-29 shows the appearance of the front panel of the two-interface DCU.

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Boards

Figure 13-29 Front panel of the two-interface DCU

DCU

CLASS 1
LASER
PRODUCT

OUT1
IN1
OUT2 IN2

DCU

Interfaces
The front panel of the one-interface DCU has one optical interface. The optical interface
transmits and receives one channel of 10 Gbit/s optical signals.
The front panel of the two-interface DCU has two optical interfaces. The optical interfaces
transmit and receive two channels of 10 Gbit/s optical signals.

WARNING
If the front panel of the one-interface DCU has two LC optical interfaces, only the upper optical
interface (IN1/OUT1) is valid. In the case of the DCU whose front panel has two LC optical
interfaces, determine whether the DCU is a one-interface DCU or a two-interface DCU according
to 13.7.6 Feature Code.
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Table 13-35 describes the type and usage of the optical interface of the one-interface DCU.
Table 13-35 Optical interface of the one-interface DCU
Interface

Type of
Interface

Usage

IN

LC

Receives one channel of optical signals.

OUT

LC

Transmits one channel of optical signals.

Table 13-36 describes the types and usage of the optical interfaces of the two-interface DCU.
Table 13-36 Optical interfaces of the two-interface DCU
Interface

Type of
Interface

Usage

IN1

LC

Receives the first channel of optical signals.

OUT1

LC

Transmits the first channel of optical signals.

IN2

LC

Receives the second channel of optical signals.

OUT2

LC

Transmits the second channel of optical signals.

13.7.5 Valid Slots


The DCU can be installed in slots 28 and 1116 in the subrack.

13.7.6 Feature Code


The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the DCU indicates the compensated dispersion for the optical signals.
Table 13-37 provides the relationship between the feature code of the DCU and the compensated
dispersion.
Table 13-37 Relationship between the feature code of the DCU and the compensated dispersion

13-54

Board

Feature Code

Compensated Dispersion

SSN1DCU01

01

Compensated dispersion for a single channel: 60


km

SSN1DCU02

02

Compensated dispersion for a single channel: 80


km

SSN1DCU03

03

Compensated dispersion for dual channels: 60


km/60 km

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Boards

Board

Feature Code

Compensated Dispersion

SSN1DCU04

04

Compensated dispersion for dual channels: 80


km/80 km

SSN1DCU05

05

Compensated dispersion for dual channels: 60


km/80 km

SSN2DCU01

01

Compensated dispersion for a single channel: 40


km

SSN2DCU02

02

Compensated dispersion for a single channel: 60


km

SSN2DCU03

03

Compensated dispersion for a single channel: 80


km

SSN2DCU04

04

Compensated dispersion for dual channels: 40


km/40 km

SSN2DCU05

05

Compensated dispersion for dual channels: 60


km/60 km

SSN2DCU06

06

Compensated dispersion for dual channels: 80


km/80 km

SSN2DCU07

07

Compensated dispersion for dual channels: 40


km/60 km

SSN2DCU08

08

Compensated dispersion for dual channels: 40


km/80 km

SSN2DCU09

09

Compensated dispersion for dual channels: 60


km/80 km

13.7.7 Technical Specifications


The technical specifications of the DCU include the parameters specified for optical interfaces,
mechanical specifications, and power consumption.

Parameters Specified for Optical Interfaces


Table 13-38 lists the parameters specified for the optical interfaces of the DCU.
Table 13-38 Parameters specified for the optical interfaces of the DCU

Issue 02 (2009-07-30)

Parameter

Value

Nominal bit rate

9953280 kbit/s

Line code pattern

NRZ

Central wavelength
(nm)

1550.120.05

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Parameter

Value

-0.5 dB bandwidth
(nm)

> 0.4

Compensated
dispersion (ps/nm)

680(40 km), 1020(60 km), and 1360(80 km)

Insertion loss (dB)

Less than 8.3 dB in the case of the N1DCU and less than 3 dB in
the case of the N2DCU

Mechanical Specifications
The mechanical specifications of the DCU are as follows:
l

Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)

Weight (kg): 0.4

Power Consumption
The maximum power consumption of the DCU at room temperature (25C) is 0 W.

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Hardware Description

14 Power Boards

14

Power Boards

About This Chapter


14.1 UPM
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the UPM (uninterruptible power module).
14.2 PIU
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the PIU (power interface board).

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14.1 UPM
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the UPM (uninterruptible power module).
14.1.1 Version Description
None.
14.1.2 Functions and Features
The UPM is a special power supply system and is numbered EPS75-4815AF. The UPM can
directly convert 110 V/220 V AC power into 48 V DC power that the transmission equipment
requires. The UPM is suitable for the telecom carriers who cannot provide 48 V DC power for
the equipment.
14.1.3 Working Principle and Signal Flow
The UPM is fed by one 220 V AC mains power supply. The rectifier module converts the input
power into 48 V DC voltage to provide four DC branches and one battery branch.
14.1.4 Front Panel
The front panel of the UPM has indicators and interfaces of many types.
14.1.5 Valid Slots
The UPM is case shaped. Hence, the UPM does not occupy a slot in the subrack.
14.1.6 Technical Specifications
The technical specifications of the UPM include the power parameters and mechanical
specifications.

14.1.1 Version Description


None.

14.1.2 Functions and Features


The UPM is a special power supply system and is numbered EPS75-4815AF. The UPM can
directly convert 110 V/220 V AC power into 48 V DC power that the transmission equipment
requires. The UPM is suitable for the telecom carriers who cannot provide 48 V DC power for
the equipment.
The output power of a single power box is 4000 W. The power box is 3U high. Figure 14-1
shows the appearance of the power box. The power box can be directly installed in the 19-inch
cabinet or the ETSI cabinet.
Figure 14-1 Appearance of the power box

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The storage batteries of the UPM work with one power box. When the external AC power system
supplies power normally, the batteries store power. When the 110 V/220 V AC power supply is
interrupted, the batteries can supply power for three hours (the battery capacity is 65 Ah). To
supply power to the OptiX OSN equipment, only one power box is required to be connected to
the batteries.
The standard maximum configuration of each power box includes five rectifier modules and one
monitoring module.
NOTE

The batteries do not belong to the UPM. Hence, the batteries need to be configured separately. If the batteries
are required, a battery cabinet is provided generally or a dedicated space in the equipment cabinet is reserved
for the batteries.

Table 14-1 provides the functions and features of the UPM.


Table 14-1 Functions and features of the UPM
Function and
Feature

UPM

Hot-swappable
function

The AC/DC rectifier module of the UPM is hot-swappable. When


you replace a faulty rectifier module, the other rectifier module can
still work normally. Therefore, the maintainability of the system is
improved.

Storage battery
protection function

The UPM provides the storage battery protection function. When the
mains supply is interrupted, the power system of the equipment
automatically switches to the storage battery, which ensures that the
equipment operates normally. The battery module provides a
capacity of 40 to 500 Ah. The default capacity is 65 Ah.

Loading capacity

The loading capability of each rectifier module is 800 W.

Lightning-proof
function

The rectifier module is embedded with the lightning-proof protector.


The rectifier module can bear the 1.2/50 us x 6 kV or 8/20 us x 3 kA
lightning surge. When the lightning current enters the rectifier
module along with the power cable, install category-C and categoryB light arresters before you connect the AC mains supply to the
power system to prevent the overvoltage caused by the direct
lightning strike from damaging the rectifier module.

14.1.3 Working Principle and Signal Flow


The UPM is fed by one 220 V AC mains power supply. The rectifier module converts the input
power into 48 V DC voltage to provide four DC branches and one battery branch.
When the UPM works normally, the monitoring module controls the rectifier module, storage
battery loop, and load loop, which work according to the preset parameters or user settings. The
monitoring module also monitors the status and data of the rectifier module, storage battery loop,
and load loop.
In the case of a mains supply failure, the equipment is fed by the storage battery group that is
connected to the UPM. The battery group must be connected to the UPM before the mains supply
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fails. When the batteries start to discharge due to a mains supply failure, the monitoring module
reports the no-mains-supply alarm. With the discharge of the batteries, the battery voltage starts
to drop. When the battery voltage is lower than 45 V, the monitoring module reports the DC
undervoltage alarm. When the battery voltage reaches 43 V, the battery group enables the poweroff protection function to interrupt the connection between the battery group and the equipment.
As a result, the batteries are automatically protected.
When the mains supply is restored, the UPM resumes normal operations.

14.1.4 Front Panel


The front panel of the UPM has indicators and interfaces of many types.

Diagram of the Front Panel


Figure 14-2 shows the rear view of the UPM (subject to the UPM on site).
Figure 14-2 Front panel of the UPM
1

10

11

14

12

13

15

16

1. Control miniature circuit breaker


(MCB) of the AC input (30 A)

2. Control MCB of the battery 3. Control MCB of load 1 (10 A)


branch (80 A)

4. Control MCB of load 2 (30 A)

5. Control MCB of load 3 (40 6. Control MCB of load 4 (40 A)


A)

7. AC phase line terminal

8. AC zero line terminal

9. Negative 48 V terminal of the battery


branch

10. Negative 48 V terminal of the load 11. Positive 48 V terminal of


branch
the battery branch

12. Positive 48 V terminal of the load


branch

13. Connecting terminal of the


protection grounding cable

15. Communication interface (COM)

14. DB44 signal interface

16. Communication test interface


(TEST)

Indicators
The front panel of each rectifier module has the following indicators:

14-4

Running status indicator (RUN) one color (green)

Alarm and protection indicator (ALM) one color (yellow)


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l

14 Power Boards

Faulty state indicator (FAULT) one color (red)

The front panel of the monitoring module has the following indicators:
l

Power supply system fault indicator (ALM) one color (red)

Power supply system status indicator (RUN) one color (green)

For the meanings of the status of the indicators, see A Indicators.

Interfaces
The front panel of the UPM has seven interfaces. Table 14-2 describes the types and usage of
the interfaces of the UPM.
Table 14-2 Interfaces of the UPM

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Interface

Type of Interface

Usage

Power input
interface

Power interface

"7" and "8" indicate the AC mains input


terminals, which access 110 V/220 V AC power.

Power output
interface

Power interface

The power output interfaces are in the lower left


corner on the front panel of the UPM. The
terminals indicated by "9" and "11" form a
battery interface, through which the power box
is connected to the battery input socket at the
back of the storage battery box through a battery
cable. "10" and "12" indicate the output
interfaces of four loads. The output interfaces
can supply power to the OptiX OSN equipment
by using power cables.

Connecting
terminal of the
protection
grounding cable

Power interface

The UPM is grounded through the cabinet.

DB44 signal
interface

DB44

The backplane of the subrack can be connected


to the sensor transfer box (an optional device)
through the DB44 signal interface and to the
monitoring module through the 96-pin DIN
connector. In addition, the sensor transfer box
can be connected to multiple sensors. As a
result, the monitoring function is extended.

Communication
interface (COM)

RJ-45

It is used for communication with the PC. The


COM interface can adopt the RS-485
communication mode or RS-232
communication mode. Three baud rates are
available, namely, 4800 kbit/s, 9600 kbit/s, and
19200 kbit/s. The baud rate can be adjusted and
the default baud rate is 9600 kbit/s.

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Interface

Type of Interface

Usage

Communication
test interface
(TEST)

RJ-45

It is used for internal test.

Switch button

Button

The switch buttons are on the left of the UPM,


as shown in Figure 14-2. "1" indicates the
control MCB of the AC input (30 A), which
enables and disables the input of the AC mains
supply. "2", "3", "4", and "5" indicate the load
control switches, which enable and disable the
load output.

14.1.5 Valid Slots


The UPM is case shaped. Hence, the UPM does not occupy a slot in the subrack.

14.1.6 Technical Specifications


The technical specifications of the UPM include the power parameters and mechanical
specifications.

Power Parameters
Table 14-3 lists the power parameters of the UPM.
Table 14-3 Power parameters of the UPM
Parameter

Value

Voltage range of
the AC input

90-290 V AC

AC input

One single-phase three-wire system: 45-65 Hz

Rated input current

28 A

Output nominal
voltage

53.50.5 V

Rated output
current

DC output branches

Load MCB 1: 10 A
Load MCB 2: 3 0A
Load MCB 3: 40 A
Load MCB 4: 40 A
Battery MCB: 80 A

Total output DC current


Regulated voltage
precision
14-6

37.53 A to 753 A

1%

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Parameter

Value

Non-balance of
load sharing

5% (50%-100% load)

Rated efficiency of
the integrated
equipment

89%

Power factor

0.99 (nominal input or output)

Peak-to-peak noise
voltage

200mV (within the range of 20 MHz)

Electrical network
adjustment rate

0.1%

Lightning
protection
performance

When the UPM works alone, the input end can bear the simulated
lightning surge current whose waveform is 8/20s and amplitude is 5
kA for five times in both directions. The interval between two surges
must not be less than one minute. If the lightning surge current is higher
than the preceding indexes, the UPM may be damaged and cannot work
normally.

Cooling method

The fan that is embedded in the rectifier module cools the module.

Mechanical Specifications
The mechanical specifications of the UPM are as follows:
l

Dimensions of the UPM (mm): 436 (W) x 255 (D) x 133 (H)

Weight: 15 kg

14.2 PIU
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the PIU (power interface board).
14.2.1 Version Description
The PIU is available in one functional version, namely, Q2.
14.2.2 Functions and Features
The PIU is used to access the power supply and to provide the lightning protection function and
filtering function.
14.2.3 Working Principle and Signal Flow
The PIU consists of the protection unit, protection circuit failure detecting unit, filtering unit,
and power detecting unit.
14.2.4 Front Panel
The front panel of the PIU has indicators and power interfaces.
14.2.5 Valid Slots
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The PIU can be installed in slots 1 and 41 in the subrack.


14.2.6 Technical Specifications
The technical specifications of the PIU include the mechanical specifications, power
consumption, and input voltage.

14.2.1 Version Description


The PIU is available in one functional version, namely, Q2.

14.2.2 Functions and Features


The PIU is used to access the power supply and to provide the lightning protection function and
filtering function.
Table 14-4 provides the functions and features of the PIU.
Table 14-4 Functions and features of the PIU
Function and
Feature

PIU

Lightning
protection function

Provides the lightning protection function and reports the alarm that
indicates the failure of the lightning protection function.

Filtering function

Enhances the electromagnetic compatibility of the system by filtering


the power supply interface and shielding the structure of the board.

Power supply
interface

Provides two 50 W power interfaces for external devices such as the


COA.

Power supply of the


FAN

Provides the FAN with normal working voltages.

Alarm monitoring

Reports the board in-position alarm.

Power supply
backup

Supports the 1+1 hot backup. Any one PIU can supply power to the
entire subrack.

NOTE

One PIU can supply power to the entire subrack.

14.2.3 Working Principle and Signal Flow


The PIU consists of the protection unit, protection circuit failure detecting unit, filtering unit,
and power detecting unit.
Figure 14-3 shows the functional block diagram of the PIU.

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Figure 14-3 Functional block diagram of the PIU


COA power supply interface
COA

NEG(-)

NEG(-)
Protection
unit

RTN(+)

Filtering
unit
RTN(+)
Protection circuit
failure detecting unit

AUX

Power
detecting
unit

LED
indication

Filtering Unit
This unit filters the electromagnetic interference signals to ensure that the equipment can operate
stably.

Protection Unit
This unit protects the equipment from overcurrent and lightning.

Protection Circuit Failure Detecting Unit


This unit monitors the protection unit and reports the alarm that indicates the failure of the
protection unit to the AUX.

Power Detecting Unit


This unit checks whether the input power supply is valid, and uses the POWER indicator to
indicate the status of the input power supply.

14.2.4 Front Panel


The front panel of the PIU has indicators and power interfaces.

Diagram of the Front Panel


Figure 14-4 shows the appearance of the front panel of the PIU.
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Figure 14-4 Front panel of the PIU

PIU
POWER

PWS
NEG()
RTN(+)

PIU

Interfaces
The front panel of the PIU has two power interfaces. Table 14-5 describes the types and usage
of the interfaces of the PIU.
Table 14-5 Interfaces of the PIU
Interface

Type of
Interface

Usage

PWR

Input interface for


the 48 V power
supply

Accesses the 48 V power supply.

PWS

Output interface
for the 50 W
power supply

Provides the 50 W power output and can supply


power to the COA.

Table 14-6 provides the pin assignments of the PWS interface of the PIU.

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Table 14-6 Pin assignments of the PWS interface of the PIU


Front View

Pin

Usage

48 V 1

48 V 2

BGND

BGND

14.2.5 Valid Slots


The PIU can be installed in slots 1 and 41 in the subrack.

14.2.6 Technical Specifications


The technical specifications of the PIU include the mechanical specifications, power
consumption, and input voltage.

Mechanical Specifications
The mechanical specifications of the PIU are as follows:
l

Dimensions (mm): 31 (W) x 131 (D) x 220 (H)

Weight: 0.3 kg

Power Consumption
At room temperature (25C), the maximum power consumption of the PIU is 2 W.

Input Voltage
The input voltage range of the PIU is as follows:
l

If the standard voltage of the input power is -48 V, the power voltage ranges from -38.4 V
to -57.6 V.

If the standard voltage of the input power is -60 V, the power voltage ranges from -48 V
to -72 V.

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15

Cables

About This Chapter


This topic describes the cables that the equipment uses, including the fiber jumper, power cable,
alarm cable, management cable, signal cable, and clock cable.
15.1 Fiber Jumper
This topic describes the categories and connectors of the fiber jumpers.
15.2 Power Cable and Grounding Cable
The power cables and grounding cables include the cabinet power cable, subrack power cable,
COA power cable, and grounding cable of the cabinet door.
15.3 Alarm Cable
The alarm cables that the equipment uses include the cabinet indicator cable, alarm cascading
cable, and alarm input/output cable.
15.4 Management Cable
The management cables include the serial port cable, ordinary phone line, COA cascading cable,
and network cable.
15.5 Signal Cable
The signal cables include the E1/E3 signal cable, framed E1 signal cable, and Nx64 kbit/s signal
cable.
15.6 Clock Cable
The clock cables include the clock cable and clock transit cable.

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15.1 Fiber Jumper


This topic describes the categories and connectors of the fiber jumpers.
15.1.1 Categories of the Fiber Jumpers
The OptiX OSN equipment uses various types of fiber jumpers.
15.1.2 Connector
The OptiX OSN equipment uses various types of fiber connectors.

15.1.1 Categories of the Fiber Jumpers


The OptiX OSN equipment uses various types of fiber jumpers.
Table 15-1 lists the categories of the fiber jumpers that the OptiX OSN equipment uses.
Table 15-1 Categories of the fiber jumpers that the OptiX OSN equipment uses
Usage

Connector
1

Connector
2

Fiber

Available Length

Used to connect
the OptiX OSN
equipment to the
ODF or to
connect an
interface board of
the OptiX OSN
equipment to
other equipment

LC/PC

FC/PC

2 mm singlemode fiber

6 m, 10 m, 20 m, 30 m,
and 50 m

2 mm multimode fiber

3 m, 5 m, 10 m, 20 m,
30 m, and 50 m

2 mm singlemode fiber

5 m, 10 m, 20 m, 30 m,
and 50 m

2 mm multimode fiber

10 m, 20 m, 30 m, and
50 m

Used to connect
the OptiX OSN
equipment

LC/PC

SC/PC

SC/PC

SC/PC

2 mm singlemode fiber

2 m, 5 m, 10 m, 20 m,
30 m, 50 m, and 80 m

LC/PC

LC/PC

2 mm singlemode fiber

1.5 m, 3 m, 5 m, 10 m,
20 m, and 30 m

2 mm multimode fiber

3 m, 5 m, 10 m, 20 m,
and 30 m

LC/PC

FC/PC

2 mm singlemode fiber

6 m, 10 m, 20 m, 30 m,
and 50 m

LC/PC

SC/PC

2 mm multimode fiber

5 m, 10 m, 20 m, 30 m,
and 50 m

Select the fiber connector and fiber length according to the on-site survey.

15.1.2 Connector
The OptiX OSN equipment uses various types of fiber connectors.
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The four types of fiber connectors are described as follows:


l

Most of the optical interfaces on the front panels of the boards are the LC/PC optical
interfaces. See Figure 15-1.

The N2OU08 and 61COA provide the SC/PC optical interfaces.

The "IN" interface on the case-shaped 62COA that is externally installed uses the LSH/
APC connector. See Figure 15-4.

Generally, the ODF on the client side provides the FC/PC or SC/PC optical interface.
Figure 15-3 and Figure 15-2 show the corresponding FC/PC and SC/PC fiber connectors.

Table 15-2 describes the four types of fiber connectors.


Table 15-2 Types of fiber connectors
Type of Internal
Fiber Connector

Description

LC/PC

Plug-in square fiber connector/protruding polished

LSH/APC

Connector with a dust-proof cover/protruding polished (eight


degrees)

FC/PC

Round fiber connector/protruding polished

SC/PC

Square fiber connector/protruding polished

LC/PC Fiber Connector


Figure 15-1 shows the appearance of the LC/PC fiber connector.
Figure 15-1 Appearance of the LC/PC fiber connector

The axial operation instead of rotation is required to insert or remove an LC/PC fiber connector.
To insert a fiber jumper that uses an LC/PC connector, align the head of the fiber jumper with
the optical interface and apply proper force. To remove the fiber jumper, first, press the clip,
then, slightly push the fiber connector inward, and finally, pull out the connector.
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SC/PC Fiber Connector


Figure 15-2 shows the appearance of the SC/PC fiber connector.
Figure 15-2 Appearance of the SC/PC fiber connector

FC/PC Fiber Connector


Figure 15-3 shows the appearance of the FC/PC fiber connector.
Figure 15-3 Appearance of the FC/PC fiber connector

LSH/APC Fiber Connector


Figure 15-4 shows the appearance of the LSH/APC fiber connector.
Figure 15-4 Appearance of the LSH/APC fiber connector

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15.2 Power Cable and Grounding Cable


The power cables and grounding cables include the cabinet power cable, subrack power cable,
COA power cable, and grounding cable of the cabinet door.
15.2.1 Power Cable of the Cabinet
The 48 V power cable, BGND power cable, and PGND power cable are used to supply power
to the equipment in a cabinet. One end of the power cable is connected to the power distribution
cabinet and the grounding bar in the equipment room, and the other end is connected to the power
distribution box at the top of the cabinet.
15.2.2 Grounding Cable of the Cabinet Door
The grounding cable of the cabinet door grounds the front door, rear door and side panels of the
cabinet. The grounding cables of the cabinet door are correctly connected before delivery.
15.2.3 Subrack Power Cable
The subrack power cable connects the power distribution box at the top of the cabinet and the
PIU in the subrack. The subrack power cable leads the 48 V power from the top of the cabinet
to the subrack. The subrack power cable is correctly connected before delivery.
15.2.4 COA Power Cable
The PIU can supply power to a maximum of two pieces of external equipment (for example, the
COA).

15.2.1 Power Cable of the Cabinet


The 48 V power cable, BGND power cable, and PGND power cable are used to supply power
to the equipment in a cabinet. One end of the power cable is connected to the power distribution
cabinet and the grounding bar in the equipment room, and the other end is connected to the power
distribution box at the top of the cabinet.

Structure
Figure 15-5 shows the structure of the 48 V/BGND power cable of the cabinet. Figure 15-6
and Figure 15-7 show the structure of the PGND power cable of the cabinet.
Figure 15-5 Structure of the 48 V/BGND power cable of the cabinet
1

3
1. Cord end terminal

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2. Bare crimping terminal type OT

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3. Cable tie

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Figure 15-6 Structure of the PGND power cable of the cabinet (JG2)

1. Bare crimping terminal type OT

2. Cable tie

3. Bare crimping terminal (JG2)

4. Heat shrink tube

5. Main label

6. Wire

7. Heat shrink tube

Figure 15-7 Structure of the PGND power cable of the cabinet (OT)

1. Bare crimping terminal type OT

2. Cable tie

3. Bare crimping terminal (OT)

4. Heat shrink tube

5. Main label

6. Wire

7. Heat shrink tube

Pin Assignments
None.

Technical Specifications
Item
48 V power
cable of the
cabinet
15-6

Description
Terminal 2

Bare crimping terminal type OT 16 mm2 M8 tin


plated round bare terminal

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Item

15 Cables

Description

BGND power
cable of the
cabinet

PGND power
cable of the
cabinet

Terminal 1

Single cord end terminal 16 mm2 0.024 m insertion


depth of 12 mm 80 A green

Cable type

Power cable 450 V/750 V 16 mm2 round and blue


85 A

Terminal 2

Bare crimping terminal type OT 16 mm2 M8 tin


plated round bare terminal

Terminal 1

Single cord end terminal 16 mm2 0.024 m insertion


depth of 12 mm 80 A green

Cable type

Power cable 450 V/750 V 16 mm2 round and black


85 A

Terminal 1

Bare crimping terminal type OT 25 mm2 M8 tin


plated round bare terminal

Terminal 3

Bare crimping terminal JG2 25 mm2 M6 95 A tin


plated, bare crimping terminal JG2 25 mm2 M8 95
A tin plated, or bare crimping terminal type OT 25
mm2 M8 tin plated round bare terminal

Cable type

Power cable 450 V/750 V 25 mm2 round and green


85 A

Fireproof class

CM

Length

10 m, 20 m, and 30 m

15.2.2 Grounding Cable of the Cabinet Door


The grounding cable of the cabinet door grounds the front door, rear door and side panels of the
cabinet. The grounding cables of the cabinet door are correctly connected before delivery.

Structure
Figure 15-8 shows the structure of the grounding cable of the cabinet door.
Figure 15-8 Structure of the grounding cable of the cabinet door

1. Bare crimping terminal type OT

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2. Heat shrink tube

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3. Main label

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15 Cables

Pin Assignments
None.

Technical Specifications
Item

Description

Terminal X1/X2

Bare crimping terminal OT 6 mm2 M6 tin plated round


insulated terminal 12 to 10 AWG

Cable

Type

Wire 600 V UL1015 10 AWG 105-core twisted pair


yellow and green, round 50 A

Fireproof
class

CM

Length

0.35 m

15.2.3 Subrack Power Cable


The subrack power cable connects the power distribution box at the top of the cabinet and the
PIU in the subrack. The subrack power cable leads the 48 V power from the top of the cabinet
to the subrack. The subrack power cable is correctly connected before delivery.

Structure
Figure 15-9 shows the structure of the subrack power cable.
Figure 15-9 Structure of the subrack power cable

1. Cable connector

2. Main label

3. Cable tie

4. Label

5. Cord end terminal

Pin Assignments
Table 15-3 provides the pin assignments of the subrack power cable.
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Table 15-3 Pin assignments of the subrack power cable


Cable
Connector

Bare
Crimping
Terminal

Connection

Color of the Core

X1.A1

X2

A1 is connected to X2.

Blue (48 V power)

X1.A3

X3

A3 is connected to X3.

Black (power ground)

Technical Specifications
Item

Description

Cable connector X1

Cable connector type D 3-pin female without intermediate


male terminals

Bare crimping terminals


X2 and X3

Single cord end terminal 4 mm2 20 A insertion depth of 10


mm grey

Cable

Type

Power cable 600 V 5.26 mm2 10 AWG black (the core is


in blue and black) 41 A

Number of
cores

Fireproof
class

CM

Color

The core is in blue and black.

Length

2.5 m, 3 m, and 3.5 m

15.2.4 COA Power Cable


The PIU can supply power to a maximum of two pieces of external equipment (for example, the
COA).
The COA power cable connects a power interface on the PIU to a power interface of the external
equipment. Both ends of the COA power cable use the 4-pin connector. One end of the COA
power cable is connected to the PIU and the other end is connected to the power interface of the
external equipment (for example, the COA).

Structure
Figure 15-10 shows the structure of the COA power cable.

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15 Cables

Figure 15-10 Structure of the COA power cable


1

A-A

W1

3 1

4 2

X1
A 2
X3

W2
X2
W1.1
W1
W1.2
W2.1

X3

W2
W2.2

1. Common terminal female 2. Common connector 4-pin 3. Main label A-A. Sectional view in direction
A

Pin Assignments
Table 15-4 provides the pin assignments of the COA power cable.
Table 15-4 Pin assignments of the COA power cable
Connectors X1
and X2

Cables W1 and W2

Color

Connector X3

X1.1

W1.1

Brown

X3.1

X2.1

W2.1

X1.3

W1.2

Black

X3.3

X2.3

W2.2

Technical Specifications

15-10

Item

Description

Connector X3

Common connector 4-pin double rows/4.20 mm

Connector X1/X2

Common terminal female 4-pin 18/26 AWG 13.7 mm in


length

Model of wire W1/W2

Symmetrical twisted-pair cable 0 ohms UL2464 0.64 mm


22 AWG one pair black

Number of cores

Fireproof class

CM

Color

Black
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Item

Description

Length

1.8 m

15 Cables

15.3 Alarm Cable


The alarm cables that the equipment uses include the cabinet indicator cable, alarm cascading
cable, and alarm input/output cable.
15.3.1 Cabinet Indicator Cable
The cabinet indicator cable is used to connect the AUX in the subrack to the cabinet indicators.
The cabinet indicator cable leads the indicator signal from the AUX to the cabinet indicators.
15.3.2 Indicator Cascading Cable Between Subracks or Alarm Cascading Cable Between the
OptiX OSN Equipment
The indicator cascading cable between subracks or the alarm cascading cable between the OptiX
OSN equipment cascades the indicator signals or alarm signals between the subracks of the
OptiX OSN equipment.
15.3.3 Alarm Cascading Cable Between the OptiX OSN Equipment and the Other Huawei
Transmission Equipment
The alarm cascading cable cascades the alarm signals of the OptiX OSN equipment and the
alarm signals of the other Huawei transmission equipment such as the OptiX 2500+ and OptiX
OSN 9500.
15.3.4 Alarm Input/Output Cable
The alarm input cable transmits the alarm signals of the external equipment to the OptiX OSN
equipment. The alarm output cable transmits the alarm signals of the OptiX OSN equipment to
the centralized alarm monitoring equipment.

15.3.1 Cabinet Indicator Cable


The cabinet indicator cable is used to connect the AUX in the subrack to the cabinet indicators.
The cabinet indicator cable leads the indicator signal from the AUX to the cabinet indicators.

Structure
Figure 15-11 shows the structure of the cabinet indicator cable.

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15 Cables

Figure 15-11 Structure of the cabinet indicator cable

X2

X3
X1
X4

X5

A-A. Sectional view in direction A

B-B. Sectional view in direction B

Pin Assignments
Table 15-5 provides the pin assignments of the cabinet indicator cable.
Table 15-5 Pin assignments of the cabinet indicator cable
Connector
X1

Connector X2/X3/X4/X5

Relation

Print on the
Label

X1.4

X2.2

Green

X1.5

X2.1

Twisted
pair

X1.1

X3.2

Red

X1.2

X3.1

Twisted
pair

X1.3

X4.2

Orange

X1.6

X4.1

Twisted
pair

X1.7

X5.2

Yellow

X1.8

X5.1

Twisted
pair

Technical Specifications

15-12

Item

Description

Connector X1

Network interface connector 8-pin 8-bit shielded


RJ-45 connector

Connector X2/X3/X4/X5

Common connector 2-pin single row/2.5 mm

Cable type

Symmetrical twisted-pair cable 120 ohms SEYPVPV


0.5 mm 24 AWG 8-core PANTONE 430U

Number of cores

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Item

Description

Fireproof class

CM

Diameter of the core

0.5 mm

Length

2.5 m, 3 m, and 3.5 m

15.3.2 Indicator Cascading Cable Between Subracks or Alarm


Cascading Cable Between the OptiX OSN Equipment
The indicator cascading cable between subracks or the alarm cascading cable between the OptiX
OSN equipment cascades the indicator signals or alarm signals between the subracks of the
OptiX OSN equipment.
Both ends of the cable use the RJ-45 connector. One end of the cable is connected to the LAMP1
of the AUX or ALM02 interface of the SEI in one subrack. The other end of the cable is connected
to the LAMP2 of the AUX or ALM01 interface of the SEI in another subrack.

Structure
Figure 15-12 shows the structure of the indicator cascading cable between subracks or the alarm
cascading cable between the OptiX OSN equipment.
Figure 15-12 Structure of the indicator cascading cable between subracks or the alarm cascading
cable between the OptiX OSN equipment

1. RJ-45 network interface connector

2. Label 1

A-A. Sectional view in direction A

Pin Assignments
Table 15-6 provides the pin assignments of the indicator cascading cable between subracks or
the alarm cascading cable between the OptiX OSN equipment.
Table 15-6 Pin assignments of the indicator cascading cable between subracks or the alarm
cascading cable between the OptiX OSN equipment

Issue 02 (2009-07-30)

Connect
or X1

Connect
or X2

Relation

Alarm Output

X1.1

X2.1

Twisted pair

Critical alarm output and major


alarm output (+)

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15 Cables

Connect
or X1

Connect
or X2

X1.2

X2.2

X1.3

X2.3

X1.6

X2.6

X1.4

X2.4

X1.5

X2.5

X1.7

X2.7

X1.8

X2.8

Relation

Alarm Output
Critical alarm signal output and
major alarm signal output ()

Twisted pair

Minor alarm signal output and


warning alarm signal output (+)
Minor alarm signal output and
warning alarm signal output ()

Twisted pair

Alarm signal output 1 (+)


Alarm signal output 1 ()

Twisted pair

Alarm signal output 2 (+)


Alarm signal output 2 ()

Technical Specifications
Item

Description

Connector X1/
X2

Network interface connector 8-pin 8-bit shielded RJ-45 connector

Cable type

Symmetrical twisted-pair cable 120 ohms SEYPVPV 0.5 mm 24


AWG 8-core PANTONE 430U

Number of cores

Fireproof class

CM

Diameter of the
core

0.5 mm

Length

3 m, 5 m, 10 m, and 20 m

15.3.3 Alarm Cascading Cable Between the OptiX OSN Equipment


and the Other Huawei Transmission Equipment
The alarm cascading cable cascades the alarm signals of the OptiX OSN equipment and the
alarm signals of the other Huawei transmission equipment such as the OptiX 2500+ and OptiX
OSN 9500.
Both ends of the cable use the RJ-45 connector. One end of the cable is connected to the ALM01
or ALM02 interface of the OptiX OSN subrack. The other end of the cable is connected to the
alarm output interface or the alarm cascading interface of the subrack of the other Huawei
transmission equipment.

15-14

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Structure
Figure 15-13 shows the structure of the alarm cascading cable between the OptiX OSN
equipment and the other Huawei transmission equipment.
Figure 15-13 Structure of the alarm cascading cable between the OptiX OSN equipment and
the other Huawei transmission equipment

1. RJ-45 network interface connector 2. Main label 3. Label 1 4. Cable connector type D 9-pin female
L: 5 m, 10 m, and 20 m

Pin Assignments
Table 15-7 provides the pin assignments of the alarm cascading cable between the OptiX OSN
equipment and the other Huawei transmission equipment.
Table 15-7 Pin assignments of the alarm cascading cable between the OptiX OSN equipment
and the other Huawei transmission equipment
Connector X1

Connector X2

Relation

Description

X1.1

X2.7

Twisted pair

Critical alarm signal output (+)

X1.2

X2.3

X1.3

X2.6

X1.6

X2.1

Critical alarm signal output ()


Twisted pair

Major alarm signal output (+)


Major alarm signal output ()

Technical Specifications

Issue 02 (2009-07-30)

Item

Description

Connector
X1

Network interface connector 8-pin 8-bit shielded RJ-45 connector

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Item

Description

Connector
X2

Cable connector type D 9-pin female

Cable type

Symmetrical twisted-pair cable 100 ohms SEYVP 0.48 mm 26 AWG


4-core black

Number of
cores

Fireproof
class

CM

Diameter of
the core

0.5 mm

Length

5 m, 10 m, and 20 m

15.3.4 Alarm Input/Output Cable


The alarm input cable transmits the alarm signals of the external equipment to the OptiX OSN
equipment. The alarm output cable transmits the alarm signals of the OptiX OSN equipment to
the centralized alarm monitoring equipment.
The alarm input/output cable uses an RJ-45 connector at one end to connect to the alarm input/
output interface of the equipment. The other end of the alarm input/output cable is connected to
the external equipment or the centralized alarm monitoring equipment. The connector needs to
be prepared on site as required. Each alarm input/output cable transmits four channels of alarm
signals.

Structure
Figure 15-14 shows the structure of the alarm input/output cable.
Figure 15-14 Structure of the alarm input/output cable

1. RJ-45 network interface connector

15-16

2. Main label

A-A. Sectional view in direction A

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Pin Assignments
Table 15-8 provides the pin assignments of the alarm input/output cable.
Table 15-8 Pin assignments of the alarm input/output cable
Connector
X1

Color

Relation

Alarm Output

Alarm Input

X1.1

Blue

Twisted pair

Critical or major alarm (+)

SW_INPUT 1 +

X1.2

White

Critical or major alarm ()

SW_INPUT 1

X1.3

Orange

Minor or warning alarm (+)

SW_INPUT 2 +

X1.6

White

Minor or warning alarm ()

SW_INPUT 2

X1.4

Green

Alarm signal output 1 (+)

SW_INPUT 3 +

X1.5

White

Alarm signal output 1 ()

SW_INPUT 3

X1.7

Brown

Alarm signal output 2 (+)

SW_INPUT 4 +

X1.8

White

Alarm signal output 2 ()

SW_INPUT 4

Twisted pair

Twisted pair

Twisted pair

Technical Specifications
Item

Description

Connector X1

Network interface connector 8-pin 8-bit shielded RJ-45 connector


Network Interface Connector,8Bit 8-pin,Crystal Plug

Cable type

Twisted-Pair Cable,100ohm, Category 5e UTP, 0.51mm, 24AWG, 8Cores,


PANTONE 430U

Number of
cores

Fireproof class

CM

Core diameter

0.5 mm

15.4 Management Cable


The management cables include the serial port cable, ordinary phone line, COA cascading cable,
and network cable.
15.4.1 OAM Serial Port Cable
The OAM serial port cable is used for the management and remote maintenance of the OptiX
OSN equipment.
15.4.2 Serial 1 to 4/F1/F&f Serial Port Cable
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The serial 14/F1/F&f serial port cable uses an RJ-45 connector at one end to connect to the
serial 14 interfaces, F1 serial port, or F&f serial port, and uses a DB9 connector at the other
end to connect to the external detecting equipment or external managed equipment.
15.4.3 RS-232/RS-422 Serial Port Cable
The RS-232/RS-422 serial port cable is used to transport the management signals between
subnets.
15.4.4 Ordinary Telephone Line
The ordinary telephone line is used to connect the orderwire phone. Both ends of the ordinary
telephone line use the RJ-45 connector. One end of the ordinary telephone line is connected to
the PHONE interface of the equipment, and the other end is connected to the interface of the
orderwire phone.
15.4.5 COA Cascading Cable
When multiple COAs are installed in a cabinet, use COA cascading cables to cascade the COAs.
15.4.6 Straight Through Cable
The straight through cable uses the RJ-45 connector to connect to the equipment at both ends.
The straight through cable is used to connect the OptiX OSN equipment, network management
computer, and Ethernet to realize communication.
15.4.7 Crossover Cable
The crossover cable is used to connect the OptiX OSN equipment to an NM computer.

15.4.1 OAM Serial Port Cable


The OAM serial port cable is used for the management and remote maintenance of the OptiX
OSN equipment.
The OAM serial port cable uses an RJ-45 connector at one end to connect to the OAM interface
of the equipment and uses a DB25 connector at the other end to connect to a laptop computer,
serial NMS, or modem.

Structure
Figure 15-15 shows the structure of the OAM serial port cable (using the DB25 connector).
Figure 15-15 Structure of the OAM serial port cable

1. RJ-45 network
interface connector

15-18

2. Main label 3. Cable connector


DB25 male

A-A. Sectional view in B-B. Sectional view in


direction A
direction B

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Pin Assignments
Table 15-9 provides the pin assignments of the OAM serial port cable.
Table 15-9 Pin assignments of the OAM serial port cable
Connector
X1

Connector X2

Relation

Description

X1.2

X2.20

Single

Data terminal ready (DTR)

X1.3

X2.2

Single

Transmitting data (TD)

X1.6

X2.3

Single

Receiving data (RD)

X1.4

X2.7

Twisted pair

Signaling ground (SG)

X1.5

Technical Specifications
Item

Description

Connector X1

Network interface connector RJ-45 connector 8-pin 8-bit shielded


connector

Connector X2

Cable connector type D 25-pin male, or cable connector type D


9-pin male

Type

Symmetrical twisted-pair cable 120 ohms SEYPVPV 0.5 mm 24


AWG 8-core PANTONE 430U

Number of
cores

Fireproof class

CM

Length

5000 mm

15.4.2 Serial 1 to 4/F1/F&f Serial Port Cable


The serial 14/F1/F&f serial port cable uses an RJ-45 connector at one end to connect to the
serial 14 interfaces, F1 serial port, or F&f serial port, and uses a DB9 connector at the other
end to connect to the external detecting equipment or external managed equipment.
The serial 14/F1/F&f serial port cable performs the following functions:
l

Transparently transmits the environment monitoring data signal.

Manages external devices such as the COA.

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Structure
Figure 15-16 shows the structure of the serial 14/F1/F&f serial port cable.
Figure 15-16 Structure of the serial 14/F1/F&f serial port cable

1. RJ-45 network
interface connector

2. Main label 3. Cable connector


DB9 male

A-A. Sectional view in B-B. Sectional view in


direction A
direction B

Pin Assignments
Table 15-10 provides the pin assignments of the serial 14/F1/F&f serial port cable.
Table 15-10 Pin assignments of the serial 14/F1/F&f serial port cable
Connector X1

Connector X2

Relation

Description

X1.1

X2.8

Twisted pair

RS422RX+

X1.2

X2.9

X1.3

X2.6

X1.6

X2.7

X1.4

X2.3

X1.8

X2.2

X1.5

X2.5

RS422RX
Twisted pair

RS422TX+
RS422TX

Twisted pair

RS232RX
RS232TX

Single

SG

Technical Specifications

15-20

Item

Description

Connector X1

Network interface connector RJ-45 connector 8-pin 8-bit shielded


connector

Connector X2

Cable connector type D 9-pin male


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Item

Description

Cable type

(1) Symmetrical twisted-pair cable 120 ohms SEYPVPV 0.5 mm 24


AWG 8-core PANTONE 430U (2) Symmetrical twisted-pair cable
100 ohms SEYVP 0.48 mm 26 AWG 8-core black

Number of
cores

Fireproof class

CM

Length

15 m in the case of cable type 1 and 3 m in the case of cable type 2

15.4.3 RS-232/RS-422 Serial Port Cable


The RS-232/RS-422 serial port cable is used to transport the management signals between
subnets.
Both ends of the RS-232/RS-422 serial port cable use the RJ-45 connector. One end of the
RS-232/RS-422 serial port cable is connected to the RS-232/RS-422 serial port of the equipment.
The other end is connected to the RS-232/RS-422 serial port of another piece of equipment that
needs to make orderwire calls to the other equipment.

Structure
Figure 15-17 shows the structure of the RS-232/RS4-22 serial port cable.
Figure 15-17 Structure of the RS-232/RS-422 serial port cable

1. RJ-45 network interface connector

2. Main label

A-A. Sectional view in direction A

Pin Assignments
Table 15-11 provides the pin assignments of the RS-232/RS-422 serial port cable.

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Table 15-11 Pin assignments of the RS-232/RS-422 serial port cable


Connector
X1

Connector X2

Relation

Description

X1.3

X2.1

Twisted pair

RX+

X1.6

X2.2

X1.1

X2.3

X1.2

X2.6

X1.5

X2.5

X1.4

X2.8

X1.8

X2.4

RX
Twisted pair

TX+
TX

Twisted pair

SG
232RX

Single

232TX

Technical Specifications
Item

Description

Connector X1/X2

Network interface connector RJ-45 connector 8-pin 8-bit


shielded connector

Cable type

Symmetrical twisted-pair cable 120 ohms SEYPVPV 0.5 mm


24 AWG 8-core PANTONE 430U

Number of cores

Fireproof class

CM

Length

15 m

15.4.4 Ordinary Telephone Line


The ordinary telephone line is used to connect the orderwire phone. Both ends of the ordinary
telephone line use the RJ-45 connector. One end of the ordinary telephone line is connected to
the PHONE interface of the equipment, and the other end is connected to the interface of the
orderwire phone.

Structure
Figure 15-18 shows the structure of the ordinary telephone line.

15-22

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Figure 15-18 Structure of the ordinary telephone line

1. RJ-45 connector

2. Main label

Pin Assignments
Table 15-12 provides the pin assignments of the ordinary telephone line.
Table 15-12 Pin assignments of the ordinary telephone line
Connector X1

Connector X2

Description

X1.1

X2.1

Not connected

X1.2

X2.2

Not connected

X1.3

X2.3

TIP

X1.4

X2.4

RING

X1.5

X2.5

Not connected

X1.6

X2.6

Not connected

Technical Specifications
Item

Description

Connector X1/X2

Network interface connector 6-pin 26 to 28 AWG

Cable type

Power cable 150 V UL20251 0.08 mm2 28 AWG black


1 A 2-core telephone line

Number of cores

Fireproof class

CM

Length

15 m

15.4.5 COA Cascading Cable


When multiple COAs are installed in a cabinet, use COA cascading cables to cascade the COAs.
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Both ends of the COA cascading cable use the DB9 connector. One end of the COA cascading
cable is connected to the RS232-1 serial port of one COA, and the other end is connected to the
RS232-2 serial port of another COA.

Structure
Figure 15-19 shows the structure of the COA cascading cable.
Figure 15-19 Structure of the COA cascading cable

1. Cable connector DB9 male

2. Label

A-A. Sectional view in direction A

Pin Assignments
Table 15-13 provides the pin assignments of the COA cascading cable.
Table 15-13 Pin assignments of the COA cascading cable
Connector X1

Connector X2

Remarks

One pair

Grounding

Technical Specifications

15-24

Item

Description

Connector X1/X2

Cable connector type D 9-pin male

Cable type

Symmetrical twisted-pair cable 100 ohms UL2464 0.32 mm


28 AWG 2P Huawei grey

Number of cores

Two pairs

Fireproof class

CM

Length

0.6 m and 2.5 m

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15.4.6 Straight Through Cable


The straight through cable uses the RJ-45 connector to connect to the equipment at both ends.
The straight through cable is used to connect the OptiX OSN equipment, network management
computer, and Ethernet to realize communication.

Structure
Figure 15-20 shows the structure of the straight through cable.
Figure 15-20 Structure of the straight through cable

1. RJ-45 network interface connector

2. Label 1

3. Main label

4. Label 2

Pin Assignments
Table 15-14 provides the pin assignments of the straight through cable.
Table 15-14 Pin assignments of the straight through cable

Issue 02 (2009-07-30)

Connector X1

Connector X2

Color

Relation

X1.1

X2.1

White/Orange

Twisted pair

X1.2

X2.2

Orange

X1.3

X2.3

White/Green

X1.6

X2.6

Green

X1.4

X2.4

Blue

X1.5

X2.5

White/Blue

X1.7

X2.7

White/Brown

X1.8

X2.8

Brown

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Twisted pair

Twisted pair

Twisted pair

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Hardware Description

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Technical Specifications
Item

Description

Connector X1/X2

Network interface connector RJ-45 connector 8-pin 8-bit


shielded connector 24 to 26 AWG CAT 6/configured with the
SFTP network cable

Cable type

Communication cable 10015 ohms CAT5E SFTP 24 AWG 8core PANTONE 445U

Number of cores

Fireproof class

CM

Length

5 m, 10 m, 20 m, and 30 m

15.4.7 Crossover Cable


The crossover cable is used to connect the OptiX OSN equipment to an NM computer.
Both ends of the crossover cable use the RJ-45 connector. One end of the crossover cable is
connected to the ETH interface of the equipment, and the other end is connected to the network
interface of the NM computer.

Structure
Figure 15-21 shows the structure of the crossover cable.
Figure 15-21 Structure of the crossover cable

1. RJ-45 network interface connector

2. Label 1

3. Main label

4. Network cable

5. Label 2

Pin Assignments
Table 15-15 provides the pin assignments of the crossover cable.
Table 15-15 Pin assignments of the crossover cable

15-26

Connector X1

Connector X2

Color

Relation

X1.6

X2.2

Orange

Twisted pair

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Connector X1

Connector X2

Color

X1.3

X2.1

White/Orange

X1.1

X2.3

White/Green

X1.2

X2.6

Green

X1.4

X2.4

Blue

X1.5

X2.5

White/Blue

X1.7

X2.7

White/Brown

X1.8

X2.8

Brown

Relation

Twisted pair

Twisted pair

Twisted pair

Technical Specifications
Item

Description

Connector X1/X2

Network interface connector RJ-45 connector 8-pin 8-bit


shielded connector 24 to 26 AWG CAT 6/configured with the
SFTP network cable

Cable type

Communication cable 1005 ohms CAT5E SFTP 24 AWG 8core PANTONE 646U

Number of cores

Fireproof class

CM

Length

5 m and 30 m

15.5 Signal Cable


The signal cables include the E1/E3 signal cable, framed E1 signal cable, and Nx64 kbit/s signal
cable.
15.5.1 75-ohm 8xE1 Cable
The 75-ohm 8xE1 cable is used to receive and transmit E1 signals.
15.5.2 120-ohm 8xE1 Cable
The 120-ohm 8xE1 cable is used to receive and transmit E1 signals.
15.5.3 120-ohm 21xE1 Cable
The 120-ohm 21xE1 cable is used to receive and transmit E1 signals.
15.5.4 E3/T3/STM-1 Cable
The E3/T3/STM-1 cable is used to receive and transmit E3/T3/STM-1 electrical signals. The
E3/T3/STM-1 cable uses an SMB connector at one end to connect to the E3/T3/STM-1 electrical
access board. The other end of the E3/T3/STM-1 cable is connected to the DDF. The connector
needs to be prepared on site as required.
15.5.5 Framed E1 Cable
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Hardware Description

15 Cables

The framed E1 cable is connected to the DB44 connector of the DM12 to access eight channels
of framed E1 signals.
15.5.6 Nx64 kbit/s Cable
The Nx64 kbit/s cable is connected to the DB28 connector of the DM12 to access one channel
of Nx64 kbit/s signals.

15.5.1 75-ohm 8xE1 Cable


The 75-ohm 8xE1 cable is used to receive and transmit E1 signals.
The 75-ohm 8xE1 cable uses a DB44 connector at one end to connect to the D75S. The other
end of the 75-ohm 8xE1 cable is connected to the digital distribution frame (DDF). The connector
needs to be prepared on site as required. Each 75-ohm 8xE1 cable can transmit 8xE1 signals.

Structure
Figure 15-22 shows the structure of the 75-ohm 8xE1 cable.
Figure 15-22 Structure of the 75-ohm 8xE1 cable
View A

Pos.1

Pos.44

MO55

Main label
W

1. Cable connector type D 44-pin male

2. Main label

Pin Assignments
Table 15-16 provides the pin assignments of the 75-ohm 8xE1 cable.
Table 15-16 Pin assignments of the 75-ohm 8xE1 cable
Connector

Cable W

Remarks

Core

No.

38

Ring

23

Tip

15-28

R1

Connector

Cable W

Remarks

Core

No.

34

Ring

19

Tip

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Hardware Description

Connector

Cable W

Remarks

15 Cables

Connector

Core

No.

37

Ring

22

Tip

36

Ring

21

Tip

35

Ring

20

Tip

15

Ring

30

Tip

14

Ring

29

Tip

13

Ring

28

Tip

12

Ring

27

Tip

Shell

External braid shield layer/Without Shell


the external braid shield layer

R2

R3

R4

T1

T2

T3

T4

Cable W

Remarks

Core

No.

33

Ring

11

R6

18

Tip

32

Ring

13

R7

17

Tip

31

Ring

15

R8

16

Tip

11

Ring

10

T5

26

Tip

10

Ring

12

T6

25

Tip

Ring

14

T7

24

Tip

Ring

16

T8

Tip
External braid shield layer/
Without the external braid shield
layer

Technical Specifications
The external layer of the 75-ohm E1 cable may be of the shielded type or unshielded type. The
specifications of the 75-ohm E1 cable with the shielded layer are different from the specifications
of the 75-ohm E1 cable with the unshielded layer. Table 15-17 lists the specifications of the 75ohm E1 cable with the external braid shield layer. Table 15-18 lists the specifications of the 75ohm E1 cable without the external braid shield layer.
Table 15-17 Specifications of the 75-ohm E1 cable with the external braid shield layer

Issue 02 (2009-07-30)

Item

Description

Connector X

Connector accessories type D 44-pin male cable welding type


3-row pins

Cable type

Coaxial cable SYFVZP-LC 75-1-1x16 75 ohms 13.10 mm


1.2 mm 0.254 mm Pantone Warm Gray 1U

Fireproof class

Complies with IEC603323C.

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Hardware Description

15 Cables

Item

Description

Number of cores

16 cores, 8xE1

Diameter of the
13.10 mm 1.2 mm 0.254 mm
shielding layer
diameter of the
internal insulation
layer diameter of the
internal conductor
Length

3 m, 10 m, 15 m, 20 m, 25 m, 30 m, 35 m, 40 m, 45 m, and 50 m

Table 15-18 Specifications of the 75-ohm E1 cable without the external braid shield layer
Item

Description

Connector X

Connector accessories type D 44-pin male cable welding type


3-row pins

Cable type

Coaxial cable SYFVZP-LC 75-1-1x16 75 ohms 12.40 mm


1.2 mm 0.254 mm Pantone Warm Gray 1U

Fireproof class

Complies with IEC603323C.

Number of cores

16 cores, 8xE1

Diameter of the
12.40 mm 1.2 mm 0.254 mm
shielding layer
diameter of the
internal insulation
layer diameter of the
internal conductor
Length

5 m, 10 m, 15 m, 20 m, 25 m, 30 m, 35 m, 40 m, 45 m, and 50 m

CAUTION
The pin assignment table is delivered with the 75-ohm 8xE1 cable in a packing bag. You must
keep the table carefully.

15.5.2 120-ohm 8xE1 Cable


The 120-ohm 8xE1 cable is used to receive and transmit E1 signals.
The 120-ohm 8xE1 cable uses a DB44 connector at one end to connect to the 120-ohm E1
electrical interface board. The other end of the 120-ohm 8xE1 cable is connected to the DDF.
The connector needs to be prepared on site as required. Each 120-ohm 8xE1 cable can transmit
8xE1 signals.
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Hardware Description

15 Cables

Structure
Figure 15-23 shows the structure of the 120-ohm 8xE1 cable.
Figure 15-23 Structure of the 120-ohm 8xE1 cable

1. Cable connector type D 44-pin male

2. Label 1, marked with "W1 (TX18)"

3. Label 3, marked with "W2 (RX18)"

4. Main label

Pin Assignments
Table 15-19 provides the pin assignments of the 120-ohm 8xE1 cable.
Table 15-19 Pin assignments of the 120-ohm 8xE1 cable
Connecto
r

Issue 02 (2009-07-30)

Cable W1

Remar
ks

Connecto
r

Cable W2
Core

No.

38

Blue

RX1

23

White

Twisted
pair

37

Orang
e

Twisted
pair

RX2

22

White

36

Green

RX3

21

White

Twisted
pair

35

Brown

Twisted
pair

RX4

20

White

34

Grey

RX5

19

White

Twisted
pair

Core

No.

15

Blue

TX1

30

White

Twisted
pair

14

Orang
e

Twisted
pair

TX2

29

White

13

Green

28

White

12

Brow
n

27

White

11

Grey

26

White

Twisted
pair

TX3

Twisted
pair

TX4

Twisted
pair

TX5

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ks

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OptiX OSN 3500 II Intelligent Optical Transmission System


Hardware Description

15 Cables

Connecto
r

Cable W1

Remar
ks

Connecto
r

Cable W2
Core

No.

33

Blue

RX6

18

Red

Twisted
pair

32

Orang
e

Twisted
pair

RX7

17

Red

31

Green

RX8

16

Red

Twisted
pair

Shell

External braided shield

Core

No.

10

Blue

TX6

25

Red

Twisted
pair

Orang
e

Twisted
pair

TX7

24

Red

Green

Red

Shell

External braided shield

Twisted
pair

TX8

Remar
ks

Technical Specifications
Item

Description

Connector X

Cable connector type D 44-pin male

Cable type

Communication cable 120 ohms SEYPVPV 0.5 mm 24 AWG


16-core PANTONE 430U

Number of cores

16

Diameter of the
internal conductor

0.5 mm

Fireproof class

CM

Length

10 m, 15 m, 20 m, 30 m, and 40 m

15.5.3 120-ohm 21xE1 Cable


The 120-ohm 21xE1 cable is used to receive and transmit E1 signals.
The 120-ohm 21xE1 cable uses a 2 mm FB connector at one end to connect to the 120-ohm E1
electrical interface of the PO1. The other end of the 120-ohm 21xE1 cable is connected to the
DDF. The connector needs to be prepared on site as required. Each 120-ohm 21xE1 cable can
transmit 21xE1 signals.

Structure
Figure 15-24 shows the structure of the 120-ohm 21xE1 cable.

15-32

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Hardware Description

15 Cables

Figure 15-24 Structure of the 120-ohm 21xE1 cable


3

1
A

Pos.73

View A

Pos.96

Pos.4

Pos.72

Pos.25

Pos.48
Pos.1

Pos.24

1. Cable connector

2. Terminal

3. Main label

Pin Assignments
Table 15-20 provides the pin assignments of the 120-ohm 21xE1 cable.
Table 15-20 Pin assignments of the 120-ohm 21xE1 cable
Pin Assignment (1)

Pin Assignment (2)

ST
A
RT
PT

Col
or
of
the
Cor
e

Relati
on

Re
ma
rk
s

X1
.1

Wh
ite

Twiste
d pair

R0

X1
.2

Blu
e

X1
.25

Wh
ite

X1
.26

Ora
nge

X1
.3

Wh
ite

X1
.4

Gre
en

Twiste
d pair

Twiste
d pair

Issue 02 (2009-07-30)

Colo
r of
the
Tape

T0
Blue

R1

Pin Assignment (3)

ST
AR
TP
T

Col
or
of
the
Cor
e

Relati
on

R
e
m
ar
ks

X1.
15

Wh
ite

Twiste
d pair

R
7

X1.
16

Blu
e

X1.
39

Wh
ite

X1.
40

Ora
nge

X1.
17

Wh
ite

X1.
18

Gre
en

Twiste
d pair

Twiste
d pair

Color
of the
Tape

T7
Orang
e

R
8

ST
A
RT
PT

Col
or
of
the
Cor
e

Relati
on

Re
m
ar
ks

X1
.53

Wh
ite

Twiste
d pair

R1
4

X1
.54

Blu
e

X1
.77

Wh
ite

Twiste
d pair

T1
4

X1
.78

Ora
nge

X1
.55

Wh
ite

Twiste
d pair

R1
5

X1
.56

Gre
en

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Tape

Green

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OptiX OSN 3500 II Intelligent Optical Transmission System


Hardware Description

15 Cables

Pin Assignment (1)

Pin Assignment (2)

ST
A
RT
PT

Col
or
of
the
Cor
e

Relati
on

Re
ma
rk
s

X1
.27

Wh
ite

Twiste
d pair

T1

X1
.28

Bro
wn

X1
.5

Wh
ite

X1
.6

Gra
y

X1
.29

Red

X1
.30

Blu
e

X1
.7

Red

X1
.8

Ora
nge

X1
.31

Red

X1
.32

Gre
en

X1
.9

Red

X1
.10

Bro
wn

X1
.33

Red

X1
.34

Gra
y

X1
.11

Bla
ck

X1
.12

Blu
e

15-34

Twiste
d pair

Twiste
d pair

Twiste
d pair

Twiste
d pair

Twiste
d pair

Twiste
d pair

Twiste
d pair

R2

T2

R3

T3

R4

T4

R5

Colo
r of
the
Tape

Pin Assignment (3)

ST
AR
TP
T

Col
or
of
the
Cor
e

Relati
on

R
e
m
ar
ks

X1.
41

Wh
ite

Twiste
d pair

T8

X1.
42

Bro
wn

X1.
19

Wh
ite

X1.
20

Gra
y

X1.
43

Red

X1.
44

Blu
e

X1.
21

Red

X1.
22

Ora
nge

X1.
45

Red

X1.
46

Gre
en

X1.
23

Red

X1.
24

Bro
wn

X1.
47

Red

X1.
48

Gra
y

X1.
49

Bla
ck

X1.
50

Blu
e

Twiste
d pair

Twiste
d pair

Twiste
d pair

Twiste
d pair

Twiste
d pair

Twiste
d pair

Twiste
d pair

R
9

T9

R
10

T1
0

R
11

T1
1

R
12

Color
of the
Tape

ST
A
RT
PT

Col
or
of
the
Cor
e

Relati
on

Re
m
ar
ks

X1
.79

Wh
ite

Twiste
d pair

T1
5

X1
.80

Bro
wn

X1
.57

Wh
ite

Twiste
d pair

R1
6

X1
.58

Gra
y

X1
.81

Red

Twiste
d pair

T1
6

X1
.82

Blu
e

X1
.59

Red

Twiste
d pair

R1
7

X1
.60

Ora
nge

X1
.83

Red

Twiste
d pair

T1
7

X1
.84

Gre
en

X1
.61

Red

Twiste
d pair

R1
8

X1
.62

Bro
wn

X1
.85

Red

Twiste
d pair

T1
8

X1
.86

Gra
y

X1
.63

Bla
ck

Twiste
d pair

R1
9

X1
.64

Blu
e

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of the
Tape

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Hardware Description

Pin Assignment (1)

Pin Assignment (2)

ST
A
RT
PT

Col
or
of
the
Cor
e

Relati
on

Re
ma
rk
s

X1
.35

Bla
ck

Twiste
d pair

T5

X1
.36

Ora
nge

X1
.13

Bla
ck

X1
.14

Gre
en

X1
.37

Bla
ck

X1
.38

Bro
wn

Twiste
d pair

Twiste
d pair

15 Cables

Colo
r of
the
Tape

R6

T6

Pin Assignment (3)

ST
AR
TP
T

Col
or
of
the
Cor
e

Relati
on

R
e
m
ar
ks

X1.
73

Bla
ck

Twiste
d pair

T1
2

X1.
74

Ora
nge

X1.
51

Bla
ck

X1.
52

Gre
en

X1.
75

Bla
ck

X1.
76

Bro
wn

Twiste
d pair

Twiste
d pair

R
13

T1
3

Color
of the
Tape

ST
A
RT
PT

Col
or
of
the
Cor
e

Relati
on

Re
m
ar
ks

X1
.87

Bla
ck

Twiste
d pair

T1
9

X1
.88

Ora
nge

X1
.65

Bla
ck

Twiste
d pair

R2
0

X1
.66

Gre
en

X1
.89

Bla
ck

Twiste
d pair

T2
0

X1
.90

Bro
wn

Color
of the
Tape

Technical Specifications
Item

Description

Connector X

Cable connector Anea 96 pins straight female suite of female


connector and shielding case cable crimping type for 24 to 26 AWG
solid wire

Cable type W

Symmetrical twisted-pair cable 120 ohms SEYVP 0.4 mm 26 AWG


42 pairs PANTONE 430U

Number of
cores

84

Diameter of
the internal
conductor

0.4 mm

Fireproof class

CM

Length

5 m, 10 m, 15 m, 20 m, 25 m, 30 m, 35 m, 40 m, 45 m, and 50 m

15.5.4 E3/T3/STM-1 Cable


The E3/T3/STM-1 cable is used to receive and transmit E3/T3/STM-1 electrical signals. The
E3/T3/STM-1 cable uses an SMB connector at one end to connect to the E3/T3/STM-1 electrical
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15 Cables

access board. The other end of the E3/T3/STM-1 cable is connected to the DDF. The connector
needs to be prepared on site as required.

Structure
Figure 15-25 shows the structure of the E3/T3/STM-1 cable.
Figure 15-25 Structure of the E3/T3/STM-1 cable

1. Coaxial connector SMB

2. Main label

3. Coaxial cable

Pin Assignments
None.

Technical Specifications
Item

Description

Connector

Coaxial connector SMB connector 75 ohms straight female

Cable I

Coaxial cable 75 ohms 3.9 mm 2.1 mm 0.34 mm shielded


Diameter of the shielding layer diameter of the internal insulation layer
diameter of the internal conductor: 3.9 mm 2.1 mm 0.34 mm
Length: 10 m, 15 m, 20 m, and 30 m

Cable II

Coaxial cable 75 ohms 4.4 mm 2.4 mm 0.4 mm shielded grey


Diameter of the shielding layer diameter of the internal insulation layer
diameter of the internal conductor: 4.4 mm 2.4 mm 0.4 mm
Length: 15 m, 20 m, 25 m, 30 m, and 40 m

Cable III

Coaxial cable 75 ohms 6.7 mm 3.8 mm 0.61 mm shielded


grey
Diameter of the shielding layer diameter of the internal insulation layer
diameter of the internal conductor: 6.7 mm 3.8 mm 0.61 mm
Length: 15 m, 20 m, 25 m, 30 m, and 130 m

Cable IV

Coaxial cable 75 ohms 5.80 mm 3.71 mm 0.643 mm black


Diameter of the shielding layer diameter of the internal insulation layer
diameter of the internal conductor: 5.80 mm 3.71 mm 0.643 mm

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Hardware Description

Item

15 Cables

Description
Length: 30 cm

Fireproof class

CM

15.5.5 Framed E1 Cable


The framed E1 cable is connected to the DB44 connector of the DM12 to access eight channels
of framed E1 signals.
The framed E1 cables are available in two types, namely, 75-ohm framed E1 cable and 120-ohm
framed E1 cable.
l

For the structure, pin assignments, and technical specifications of the 75-ohm framed E1
cable, see the topic that describes the 75-ohm 8xE1 cable.

For the structure, pin assignments, and technical specifications of the 120-ohm framed E1
cable, see the topic that describes the 120-ohm 8xE1 cable.

15.5.6 Nx64 kbit/s Cable


The Nx64 kbit/s cable is connected to the DB28 connector of the DM12 to access one channel
of Nx64 kbit/s signals.
Table 15-21 provides the pin assignments of the DB28 connector.
Table 15-21 Pin assignments of the DB28 connector of the DM12

Issue 02 (2009-07-30)

Pin

Signal

Direction

Description

TXD+

--->

Transmits data.

TXD

--->

Transmits data.

TXC+

<-->

Transmits the clock signal provided by the


DCE to the DTE.

TXC

<-->

Transmits the clock signal provided by the


DCE to the DTE.

NC

GND

-----

Circuit_GND

MODE0

<---

Receives the signal that identifies the type of


cable.

MODE1

<---

Receives the signal that identifies the type of


cable.

MODE2

<---

Receives the signal that identifies the type of


cable.

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Hardware Description

15 Cables

Pin

Signal

Direction

Description

10

MODE_DC
E

<---

Receives the signal that identifies the type of


DCE/DTE cable.

11

DCD+

<-->

Detects the carrier.

12

DCD

<-->

Detects the carrier.

13

RTS+

--->

Requests for transmission.

14

RTS

--->

Requests for transmission.

15

TXCE+

--->

Transmits the data clock in the case of the


DCE and loops back the clock in the case of
the DTE.

16

TXCE

--->

Transmits the data clock in the case of the


DCE and loops back the clock in the case of
the DTE.

17

RXC+

<---

Receives clock signals.

18

RXC

<---

Receives clock signals.

19

RXD+

<---

Receives data.

20

RXD

<---

Receives data.

21

GND

-----

Shield_GND

22

LL

<-->

Receives the loopback control signal.

23

CTS+

<---

Permits the transmission.

24

CTS

<---

Permits the transmission.

25

DSR+

<---

Receives the DCE ready signal.

26

DSR

<---

Receives the DCE ready signal.

27

DTR+

--->

Transmits the DTE ready signal.

28

DTR

--->

Transmits the DTE ready signal.

The Nx64 kbit/s cables are classified into the following categories according to the protocol,
which the Nx64 kbit/s signals comply with:

15-38

V.35 DCE cable

V.35 DTE cable

V.24 DCE cable

V.24 DTE cable

X.21 DCE cable

X.21 DTE cable


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Hardware Description
l

RS-449 DCE cable

RS-449 DTE cable

RS-530 DCE cable

RS-530 DTE cable

15 Cables

V.35 DCE Cable


Figure 15-26 shows the structure of the V.35 DCE cable.
Figure 15-26 Structure of the V.35 DCE cable
A-A

B-B

Pos.28
W

Pos.1
A

X1

X2

M
S
W
AA
EE
KK

K
P
U
Y
CC
HH
MM

1. Cable connector D28 male

D
J
N
T
X
BB
FF
LL

B
F
L
R
V
Z
DD
JJ
NN

2. Main label

3. Cable connector D34 female + D34 plastic shell

Table 15-22 provides the pin assignments of the V.35 DCE cable.
Table 15-22 Pin assignments of the V.35 DCE cable

Issue 02 (2009-07-30)

Connector X1

Connector X2

Relation

19

Twisted pair

20

15

16

AA

17

18

W
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Twisted pair

Twisted pair

Twisted pair

Twisted pair

15-39

OptiX OSN 3500 II Intelligent Optical Transmission System


Hardware Description

15 Cables

Connector X1

Connector X2

Relation

11

22

23

13

25

27

21

6+7+8

Pins 6, 7, and 8 are shortcircuited.

The technical specifications of the V.35 DCE cable are as follows.


Item

Description

Connector X1

Cable connector type-D dualedge subassembly 28-pin straight


male cable welding type spacing 0.80 mm matching with 28 to
30 AWG, exclusively used by the OEM

Connector X2

Cable connector V35 plug 34-pin molding shell kit, exclusively


used by the OEM
Cable connector V35 DCE plug 34-pin female cable crimping
type housing core, exclusively used by the OEM

Cable type

Symmetrical twisted-pair cable 100 ohms 0.38 mm 28 AWG 5


pairs 8 cores PANTONE 296U exclusively used by the OEM

Number of cores

Five pairs and eight cores

Diameter of the
core

0.32 mm

Length

3m

V.35 DTE Cable


Figure 15-27 shows the structure of the V.35 DTE cable.

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Figure 15-27 Structure of the V.35 DTE cable


A-A

B-B

Pos.28

Pos.1

X1

X2

1. Cable connector D28 male 2. Main label


4. Ordinary terminal

A
B
C
D
E
F
H
J
L N K M
R T P S
V X U W
Z BB Y AA
DD FF CC EE
JJ LL HH KK
NN MM

3. Cable connector D34 plastic shell

5. Cable connector D34 male

Table 15-23 provides the pin assignments of the V.35 DTE cable.
Table 15-23 Pin assignments of the V.35 DTE cable

Issue 02 (2009-07-30)

Connector X1

Connector X2

Relation

Twisted pair

19

20

17

18

AA

15

16

11

22

13

23

27

25

21

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Twisted pair

Twisted pair

Twisted pair

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15 Cables

Connector X1

Connector X2

Relation

6 + 10 + 7 + 8

Pins 6, 7, 8, and 10 are shortcircuited.

The technical specifications of the V.35 DTE cable are as follows.


Item

Description

Connector X1

Cable connector type-D dualedge subassembly 28-pin straight male


cable welding type spacing 0.80 mm matching with 28 to 30 AWG,
exclusively used by the OEM

Connector X2

Cable connector V35 plug 34-pin molding shell kit, exclusively used
by the OEM
Cable connector V35 DTE plug 34-pin female cable crimping type
housing core, exclusively used by the OEM

Cable type

Symmetrical twisted-pair cable 100 ohms 0.38 mm 28 AWG 5 pairs


8 cores PANTONE 296U exclusively used by the OEM

Number of
cores

Five pairs and eight cores

Diameter of
the core

0.32 mm

Length

3m

V.24 DCE Cable


Figure 15-28 shows the structure of the V.24 DCE cable.
Figure 15-28 Structure of the V.24 DCE cable
A-A

B-B

Pos.25
Pos.1

Pos.28
Pos.1

X1

X2

1. Cable connector D25 female

2. Main label

3. Cable connector D28 male

Table 15-24 provides the pin assignments of the V.24 DCE cable.
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Table 15-24 Pin assignments of the V.24 DCE cable


Connector X1

Connector X2

Relation

19

Twisted pair

23

13

25

20

27

11

22

18

15

17

24

15

17

21

Single

6+7

Pins 6 and 7 are shortcircuited.

Twisted pair

Twisted pair

Twisted pair

Twisted pair

The technical specifications of the V.24 DCE cable are as follows.


Table 15-25 Technical specifications of the V.24 DCE cable

Issue 02 (2009-07-30)

Item

Description

Connector X1

Cable connector type-D dualedge subassembly 28-pin straight


male cable welding type spacing 0.80 mm matching with 28 to 30
AWG, exclusively used by the OEM

Connector X2

Cable connector type D 25-pin female cable welding type

Cable type

Symmetrical twisted-pair cable 100 ohms 0.38 mm 28 AWG 5 pairs


8 cores PANTONE 296U exclusively used by the OEM

Number of
cores

Five pairs and eight cores

Diameter of the
core

0.32 mm

Length

3m

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V.24 DTE Cable


Figure 15-29 shows the structure of the V.24 DTE cable.
Figure 15-29 Structure of the V.24 DTE cable
A-A

B-B
1

Pos.1
Pos.1

Pos.28
Pos.25

X1

X2

1. Cable connector D25 male

2. Main label

3. Cable connector D28 male

Table 15-26 provides the pin assignments of the V.24 DTE cable.
Table 15-26 Pin assignments of the V.24 DTE cable
Connector X1

Connector X2

Relation

Twisted pair

19

13

23

27

20

25

11

22

18

15

15

24

17

17

21

Single

6 + 10 + 7

Pins 6, 10, and 7 are shortcircuited.

Twisted pair

Twisted pair

Twisted pair

Twisted pair

The technical specifications of the V.24 DTE cable are as follows.


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Table 15-27 Technical specifications of the V.24 DTE cable


Item

Description

Connector X1

Cable connector type-D dualedge subassembly 28-pin straight male


cable welding type spacing 0.80 mm matching with 28 to 30 AWG,
exclusively used by the OEM

Connector X2

Cable connector type D 25-pin male cable welding type

Cable type

Symmetrical twisted-pair cable 100 ohms 0.38 mm 28 AWG 5 pairs


8 cores PANTONE 296U exclusively used by the OEM

Number of
cores

Five pairs and eight cores

Diameter of the
core

0.32 mm

Length

3m

X.21 DCE Cable


Figure 15-30 shows the structure of the X.21 DCE cable.
Figure 15-30 Structure of the X.21 DCE cable
A-A

B-B
2

Pos.15

Pos.1

Pos.28

Pos.1

X1

X2

1. Cable connector D15 female

2. Main label

3. Cable connector D28 male

Table 15-28 provides the pin assignments of the X.21 DCE cable.
Table 15-28 Pin assignments of the X.21 DCE cable

Issue 02 (2009-07-30)

Connector X1

Connector X2

Relation

13

Twisted pair

14

12

23

24

10
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15 Cables

Connector X1

Connector X2

Relation

19

Twisted pair

20

11

15

16

13

21

6+9

Pins 6 and 9 are shortcircuited.

Twisted pair

Twisted pair

The technical specifications of the X.21 DCE cable are as follows.


Table 15-29 Technical specifications of the X.21 DCE cable
Item

Description

Connector X1

Cable connector type-D dualedge subassembly 28-pin straight male


cable welding type spacing 0.80 mm matching with 28 to 30 AWG,
exclusively used by the OEM

Connector X2

Cable connector type D 15-pin female cable welding type

Cable type

Symmetrical twisted-pair cable 100 ohms 0.38 mm 28 AWG 5 pairs


8 cores PANTONE 296U exclusively used by the OEM

Number of
cores

Five pairs and eight cores

Diameter of
the core

0.32 mm

Length

3m

X.21 DTE Cable


Figure 15-31 shows the structure of the X.21 DTE cable.

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15 Cables

Figure 15-31 Structure of the X.21 DTE cable


A-A

B-B
2

Pos.1

Pos.1

Pos.28

Pos.15

X2

X1

1. Cable connector D15 male

2. Main label

3. Cable connector D28 male

Table 15-30 provides the pin assignments of the X.21 DTE cable.
Table 15-30 Pin assignments of the X.21 DTE cable
Connector X1

Connector X2

Relation

13

Twisted pair

14

10

23

24

12

19

20

11

15

16

13

17

18

13

21

6 + 10 + 9

Pins 6, 10, and 9 are shortcircuited.

Twisted pair

Twisted pair

Twisted pair

Twisted pair

Twisted pair

The technical specifications of the X.21 DTE cable are as follows.

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Table 15-31 Technical specifications of the X.12 DTE cable


Item

Description

Connector X1

Cable connector type-D dualedge subassembly 28-pin straight


male cable welding type spacing 0.80 mm matching with 28 to 30
AWG, exclusively used by the OEM

Connector X2

Cable connector type D 15-pin male cable welding type

Cable type

Symmetrical twisted-pair cable 100 ohms 0.38 mm 28 AWG 5 pairs


8 cores PANTONE 296U exclusively used by the OEM

Number of
cores

Five pairs and eight cores

Diameter of the
core

0.32 mm

Length

3m

RS-449 DCE Cable


Figure 15-32 shows the structure of the RS-449 DCE cable.
Figure 15-32 Structure of the RS-449 DCE cable
A-A

B-B
2

Pos.1

Pos.1

Pos.28

Pos.15

X2

X1

1. Cable connector D28 male

2. Main label

3. Cable connector D37 female I

Table 15-32 provides the pin assignments of the RS-449 DCE cable.
Table 15-32 Pin assignments of the RS-449 DCE cable

15-48

Connector X1

Connector X2

Relation

27

11

Twisted pair

28

29

25

12

26

30
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15 Cables

Connector X1

Connector X2

Relation

13

Twisted pair

14

27

23

24

25

11

13

12

31

19

20

22

24

15

16

26

17

17

18

35

23

22

10

21

6+8

19

Pins 6 and 8 are shortcircuited.

Twisted pair

Twisted pair

Twisted pair

Twisted pair

Twisted pair

Twisted pair

Twisted pair

The technical specifications of the RS-449 DCE cable are as follows.


Table 15-33 Technical specifications of the RS-449 DCE cable

Issue 02 (2009-07-30)

Item

Description

Connector X1

Cable connector type-D dualedge subassembly 28-pin straight


male cable welding type spacing 0.80 mm matching with 28 to
30 AWG, exclusively used by the OEM

Connector X2

Cable connector type D 37-pin female cable welding type,


exclusively used by the OEM

Cable type

Symmetrical twisted-pair cable 100 ohms communication cable


0.32 mm 28 AWG 26-core PANTONE 296U exclusively used
by the OEM
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Item

Description

Number of cores

26

Diameter of the
core

0.32 mm

Length

3m

RS-449 DTE Cable


Figure 15-33 shows the structure of the RS-449 DTE cable.
Figure 15-33 Structure of the RS-449 DTE cable
A-A

B-B
1

3
Pos.37

Pos.28

Pos.1

X1
X2

1. Cable connector D28 male

2. Main label

Pos.1

3. Cable connector D37 male I

Table 15-34 provides the pin assignments of the RS-449 DTE cable.
Table 15-34 Pin assignments of the RS-449 DTE cable

15-50

Connector X1

Connector X2

Relation

27

12

Twisted pair

28

30

25

11

26

29

13

14

25

23

24

27

11

13

12

31
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Twisted pair

Twisted pair

Twisted pair

Twisted pair

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15 Cables

Connector X1

Connector X2

Relation

19

Twisted pair

20

24

22

15

17

16

35

17

18

26

23

22

10

21

6 + 8 + 10

19

Pins 6, 8, and 10 are shortcircuited.

Twisted pair

Twisted pair

Twisted pair

Twisted pair

The technical specifications of the RS-449 DTE cable are as follows.


Table 15-35 Technical specifications of the RS-449 DTE cable

Issue 02 (2009-07-30)

Item

Description

Connector X1

Cable connector type-D dualedge subassembly 28-pin straight male


cable welding type spacing 0.80 mm matching with 28 to 30 AWG,
exclusively used by the OEM

Connector X2

Cable connector type D SUB plug 37-pin straight male cable


welding type two rows, standard installation holes, exclusively used by
the OEM

Cable type

Symmetrical twisted-pair cable 100 ohms communication cable 0.32


mm 28 AWG 26-core PANTONE 296U exclusively used by the
OEM

Number of
cores

26

Diameter of
the core

0.32 mm

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RS-530 DCE Cable


Figure 15-34 shows the structure of the RS-530 DCE cable.
Figure 15-34 Structure of the RS-530 DCE cable
A-A
Pos.25

B-B
3

Pos.1

X1
Pos.1

Pos.28

X2

1. Cable connector D25 female

2. Main label

3. Cable connector D28 male

Table 15-36 provides the pin assignments of the RS-530 DCE cable.
Table 15-36 Pin assignments of the RS-530 DCE cable

15-52

Connector X1

Connector X2

Relation

28

22

Twisted pair

27

26

23

25

20

24

19

23

22

18

Single

21

Single

20

14

Twisted pair

19

18

11

17

24

16

15

17

14

13

13

5
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Twisted pair

Twisted pair

Twisted pair

Twisted pair

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15 Cables

Connector X1

Connector X2

Relation

12

10

Twisted pair

11

12

15

16

6+7+9

Twisted pair

Twisted pair

Pins 6, 7, and 9 are shortcircuited.

The technical specifications of the RS-530 DCE cable are as follows.


Table 15-37 Technical specifications of the RS-530 DCE cable
Item

Description

Connector X1

Cable connector type-D dualedge subassembly 28-pin straight


male cable welding type spacing 0.80 mm matching with 28 to 30
AWG, exclusively used by the OEM

Connector X2

Cable connector type D 25-pin female cable welding type

Cable type

Symmetrical twisted-pair cable 100 ohms communication cable 0.32


mm 28 AWG 26-core PANTONE 296U exclusively used by the
OEM

Number of
cores

26

Diameter of the
core

0.32 mm

Length

3m

RS-530 DTE Cable


Figure 15-35 shows the structure of the RS-530 DTE cable.

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Figure 15-35 Structure of the RS-530 DTE cable


B-B

A-A
1

Pos.1
Pos.1

X1

Pos.28

X2

Pos.25

1. Cable connector D25 male

2. Main label

3. Cable connector D28 male

Table 15-38 provides the pin assignments of the RS-530 DTE cable.
Table 15-38 Pin assignments of the RS-530 DTE cable

15-54

Connector X1

Connector X2

Relation

27

20

Twisted pair

28

23

25

26

22

13

14

19

23

24

13

11

12

10

19

20

16

14

15

24

16

11

17

17

18

15
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Twisted pair

Twisted pair

Twisted pair

Twisted pair

Twisted pair

Twisted pair

Twisted pair

Twisted pair

Twisted pair
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15 Cables

Connector X1

Connector X2

Relation

12

22

18

21

6 + 7 + 9 + 10

Pins 6, 7, 9, and 10 are shortcircuited.

The technical specifications of the RS-530 DTE cable are as follows.


Table 15-39 Technical specifications of the RS-530 DTE cable
Item

Description

Connector X1

Cable connector type-D dualedge subassembly 28-pin straight male


cable welding type spacing 0.80 mm matching with 28 to 30 AWG,
exclusively used by the OEM

Connector X2

Cable connector type D 25-pin male cable welding type

Cable type

Symmetrical twisted-pair cable 100 ohms communication cable 0.32


mm 28 AWG 26-core PANTONE 296U exclusively used by the
OEM

Number of
cores

26

Diameter of the
core

0.32 mm

Length

3m

15.6 Clock Cable


The clock cables include the clock cable and clock transit cable.
15.6.1 Clock Cable
The clock cables are available in two types, namely, 75-ohm clock cable and 120-ohm clock
cable. The clock cable is used to receive and transmit external clock signals. In the case of the
75-ohm clock cable, the cable uses an SMB connector at one end to connect to the external clock
interface of the OptiX OSN equipment. The other end of the cable is connected to the external
clock equipment. The connector needs to be prepared on site as required. In the case of the 120ohm clock cable, the cable uses an RJ-45 connector at one end to connect to the external clock
interface of the OptiX OSN equipment. The other end of the cable is connected to the external
clock equipment. The connector needs to be prepared on site as required.
15.6.2 One-Channel Clock Transit Cable and Two-Channel Clock Transit Cable
The clock transit cables are available in two types, namely, one-channel 75-ohm-to-120-ohm
clock transit cable and two-channel 75-ohm-to-120-ohm clock transit cable.
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15.6.1 Clock Cable


The clock cables are available in two types, namely, 75-ohm clock cable and 120-ohm clock
cable. The clock cable is used to receive and transmit external clock signals. In the case of the
75-ohm clock cable, the cable uses an SMB connector at one end to connect to the external clock
interface of the OptiX OSN equipment. The other end of the cable is connected to the external
clock equipment. The connector needs to be prepared on site as required. In the case of the 120ohm clock cable, the cable uses an RJ-45 connector at one end to connect to the external clock
interface of the OptiX OSN equipment. The other end of the cable is connected to the external
clock equipment. The connector needs to be prepared on site as required.

Structure
Figure 15-36 shows the structure of the 75-ohm clock cable. Figure 15-37 shows the structure
of the 120-ohm clock cable.
Figure 15-36 Structure of the 75-ohm clock cable

1. Coaxial connector SMB

2. Label

Figure 15-37 Structure of the 120-ohm clock cable


A-A
8
1

X1

1. Network interface connector RJ-45

2. Main label

3. Communication cable

Pin Assignments
Table 15-40 provides the pin assignments of the 120-ohm clock cable.
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Table 15-40 Pin assignments of the 120-ohm clock cable


X1

Remarks

X1.1

Blue

R1

X1.2

White

X1.3

Orange

X1.6

White

X1.4

Green

X1.5

White

X1.7

Brown

X1.8

White

R2

T1

T2

Technical Specifications
Item
75-ohm
clock
cable

120ohm
clock
cable

Description
Connector
Cable

Coaxial connector SMB 75 ohms straight


female
Model

Coaxial cable 75 ohms 3.9 mm 2.1 mm


0.34 mm shielded

Diameter

Diameter of the shielding layer diameter of the


internal insulation layer diameter of the internal
conductor: 3.9 mm 2.1 mm 0.34 mm

Length

10 m, 15 m, 20 m, and 30 m

Connector X1
Cable

Network interface cable 8-pin 8-bit shielded


crystal model connector
Model

Twisted pair 120 ohms SEYVP 24 AWG


4 pairs PANTONE 430U

Diameter of the
internal
conductor

0.5 mm/24 AWG

Length

10 m, 20 m, and 30 m

15.6.2 One-Channel Clock Transit Cable and Two-Channel Clock


Transit Cable
The clock transit cables are available in two types, namely, one-channel 75-ohm-to-120-ohm
clock transit cable and two-channel 75-ohm-to-120-ohm clock transit cable.
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Structure
Figure 15-38 shows the structure of the one-channel 75-ohm-to-120-ohm clock transit
cable.Figure 15-39 shows the structure of the two-channel 75-ohm-to-120-ohm clock transit
cable.
Figure 15-38 Structure of the one-channel 75-ohm-to-120-ohm clock transit cable

1. Coaxial connector SMB 75 ohms straight/plug


female

2. Main label 3. 75-ohm-to-120-ohm transit PCB

Figure 15-39 Structure of the two-channel 75-ohm-to-120-ohm clock transit cable

1. Coaxial connector SMB 75 ohms straight/plug female 2. Label 1: "1#" 3. Label 2: "2#" 4. Main label
5. 75-ohm-to-120-ohm transit PCB

6. Label 3: "1#" 7. Label 4: "2#"

Pin Assignments
Table 15-41 provides the pin assignments of the two-channel 75-ohm-to-120-ohm clock transit
cable.
Table 15-41 Pin assignments of the two-channel 75-ohm-to-120-ohm clock transit cable
Connector

75-ohm Cable

Color

120-ohm Cable

X1

Core

Blue

W3

Shielding layer

White

Core

Blue

Shielding layer

White

X2

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15 Cables

Technical Specifications
Item

Description

One
channel

Connector: coaxial connector SMB 75 ohms straight female


75-ohm cable: coaxial cable 75 ohms 3.9 mm 2.1 mm 0.34 mm shielded
75-ohm cable: diameter of the shielding layer (3.9 mm) diameter of the
internal insulation layer (2.1 mm) diameter of the internal conductor (0.34
mm)
120-ohm cable: symmetrical twisted-pair cable 120 ohms SEYPVPV 0.4
mm 26 AWG 2 pairs PANTONE 430U
Diameter of the internal conductor of the 120-ohm cable: 0.4 mm/26 AWG
Length: 30 m

Two
channels

Connector X1/X2: coaxial connector SMB 75 ohms straight female


75-ohm cable: coaxial cable 75 ohms 3.9 mm 2.1 mm 0.34 mm shielded
75-ohm cable: diameter of the shielding layer (3.9 mm) diameter of the
internal insulation layer (2.1 mm) diameter of the internal conductor (0.34
mm)
120-ohm cable: symmetrical twisted-pair cable 120 ohms SEYPVPV 0.4
mm 26 AWG 2 pairs PANTONE 430U
Diameter of the internal conductor of the 120-ohm cable: 0.4 mm/26 AWG
Length: 30 m

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A Indicators

Indicators

This topic describes the indicators on the OptiX OSN equipment and the indicators on the boards
of the OptiX OSN equipment.
A.1 Indicators on the Cabinet
This topic describes the indicators on the cabinet of the OptiX OSN equipment.
A.2 Alarm Indicators on the Boards
This topic describes the alarm indicators on the boards.

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A Indicators

A.1 Indicators on the Cabinet


This topic describes the indicators on the cabinet of the OptiX OSN equipment.
Indicator

Description

Power indicator Power (green)

On: Power is supplied to the equipment.


Off: Power is not supplied to the equipment.

Critical alarm indicator Critical (red)

On: A critical alarm occurs on the equipment.


Off: No critical alarm occurs on the equipment.

Major alarm indicator Major (orange)

On: A major alarm occurs on the equipment.


Off: No major alarm occurs on the equipment.

Minor alarm indicator Minor


(yellow)

On: A minor alarm occurs on the equipment.


Off: No minor alarm occurs on the equipment.

A.2 Alarm Indicators on the Boards


This topic describes the alarm indicators on the boards.

Board Hardware Status Indicator (STAT)


Status

Meaning

On (green)

The board operates normally.

On (red)

The hardware of the board is faulty or does not match


the equipment.

Off

The board is not powered on or does not start to work.

Service Activation Status Indicator (ACT)


Status

Meaning

On (green)

The services are activated. The board is in the


working state.

In TPS protection mode, the board is in the active


state.

The services are not activated.

In TPS protection mode, the board is in the standby


state.

Off

A-2

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A Indicators

Board Software Status Indicator (PROG)


Status

Meaning

On (green)

The board software or FPGA in the flash is


successfully loaded and stored, or the board software
is successfully initiated.

On for 100 ms and off for 100 ms


repeatedly (green)

The board software is being loaded to the flash or the


FPGA software is being loaded to the FPGA.

On for 300 ms and off for 300 ms


repeatedly (green)

The board software is being initialized and is in the


BIOS boot state.

The board is in the BIOS state because the board


is reset for three times in five minutes.

The board software or FPGA in the flash is lost.

The board software fails to be loaded.

The board software fails to be initialized.

No power is accessed.

The high-power-consumption board enters the


low-power-consumption mode.

On (red)

Off

Service Alarm Indicator (SRV)

Issue 02 (2009-07-30)

Type of Board

Status

Meaning

Service board

On (green)

The services are normal and no


service alarm is generated.

On (red)

A critical or major alarm occurs in


the services.

On (yellow)

A minor or remote alarm occurs in


the services.

Off

The services are not configured and


no alarm is generated, or no power is
supplied to the board.

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OptiX OSN 3500 II Intelligent Optical Transmission System


Hardware Description

A Indicators

Synchronization Clock Status Indicator (SYNC)


Status

Meaning

On (green)

The clock works in free-run mode and the system


clock priority list is not set. By default, the system
clock priority list contains only internal sources.

The clock works in locked mode and is tracing a


clock source other than the internal sources in the
priority list.

The system clock priority list is set. All the clock


sources, however, are lost except for the internal
clock sources. The clock works in holdover mode or
free-run mode.

On (red)

Alarm Mute Indicator (ALMC)


Status

Meaning

On (yellow)

The board is in the alarm mute state.

Off

When an alarm is generated, the equipment emits an alarm


sound.

Power Monitoring Indicators


Indicator

Status

Meaning

48 V power supply indicator of


channel A (PWRA)

On (green)

The 48 V power supply of channel


A is normal.

On (red)

The 48 V power supply of channel


A is faulty (lost or failed).

On (green)

The 48 V power supply of channel B


is normal.

On (red)

The 48 V power supply of channel B


is faulty (lost or failed).

On (green)

The +3.3 V backup power supply of


the system is normal.

On (red)

The +3.3 V backup power supply of


the system is lost.

48 V power supply indicator of


channel B (PWRB)

+3.3 V backup power supply


indicator of the system (PWRC)

A-4

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OptiX OSN 3500 II Intelligent Optical Transmission System


Hardware Description

A Indicators

Ethernet Indicators
Indicator

Status

Meaning

Connection status indicator


LINK (green)

On

The fiber cable is successfully


connected to the equipment.

Off

The fiber cable is not connected to the


equipment.

Flashing

The Ethernet interface is receiving or


transmitting data.

Off

The Ethernet interface is not receiving


or transmitting data.

Data receiving and


transmission indicator ACT
(orange)

Service Activation Status Indicator of the Cross-Connect Unit (ACTX)


Status

Meaning

On (green)

The cross-connect unit is in the active state.

Off

The cross-connect unit is in the standby state.

Active/Standby State Indicator of the SCC Unit (ACTC)


Status

Meaning

On (green)

The SCC unit is in the active state.

Off

The SCC unit is in the standby state.

Service Alarm Indicator of the Line Unit (SRVL)

Issue 02 (2009-07-30)

Status

Meaning

On (green)

The line services are normal and no alarm is


generated.

On (red)

A critical or major alarm occurs in the line services.

On (yellow)

A minor or remote alarm occurs in the line services.

Off

The line services are not configured and no alarm is


generated, or no power is supplied to the unit.

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OptiX OSN 3500 II Intelligent Optical Transmission System


Hardware Description

A Indicators

FAN Running Status Indicator (STATE)


Status

Meaning

On (green)

The fan operates normally.

On (red)

The fan, fan power supply board, or fan control board


is abnormal.

On (yellow)

The fan stops when the temperature is very low.

Indicators on the Front Panel of the COA


Indicator

Status

Meaning

Running indicator
RUN (green)

Flashing once every two


seconds (green)

The COA operates normally.

Flashing once every four


seconds (green)

The COA is in database protection mode.


The communication between the COA
and the SCC is interrupted.

Flashing five times every


second (green)

The program is being started or loaded.

On (red)

Errors occur during the memory selfcheck.

Flashing thrice every other


second (red)

A critical alarm occurs.

Flashing twice every other


second (red)

A major alarm occurs.

Flashing once every other


second (red)

A minor alarm occurs.

Alarm indicator
ALM

Indicators on the UPM


Module

Indicator

Status

Meaning

Rectifier
module

RUN (green)

On

The rectifier module operates normally.

Off

The rectifier module is faulty or is disabled.

Off

The rectifier module operates normally.

On

An alarm and revertive protection occur on


the module.

Flashing

The communication is interrupted.

ALM
(yellow)

A-6

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OptiX OSN 3500 II Intelligent Optical Transmission System


Hardware Description

Module

Monitoring
module

A Indicators

Indicator

Status

Meaning

FAULT
(red)

On

The rectifier module is faulty.

RUN

Flashing
(green)

Flashing slowly (on for 1s and off for 1s


repeatedly): The entire power system is
normal.
Flashing quickly (on for 125 ms and off for
125 ms repeatedly): The power system is not
registered or the communication is
interrupted.

ALM

On (red)

The entire power system is faulty. In normal


situations, the indicator is off.

Indicators on the Microwave Boards


Indicator

Status

Meaning

Connection status indicator 1


(LINK1) two colors (red and
green)

On (green)

The link at the microwave layer is


normal.

On (red)

The link at the microwave layer is


faulty.

Connection status indicator 2


(LINK2) two colors (red and
green)

On (green)

The link at the microwave layer is


normal.

On (red)

The link at the microwave layer is


faulty.

Active/Standby state
indicator (ACT1) one color
(green)

On (green)

The board is in the active state when


the board is in the 1+1 protection
system.
The board is activated when the board
is not protected.

Off

The board is in the standby state when


the board is in the 1+1 protection
system.
The board is not activated when the
board is not protected.

On (green)

The board is in the active state when


the board is in the 1+1 protection
system.
The board is activated when the board
is not protected.

Active/Standby state
indicator (ACT2) one color
(green)

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A-7

OptiX OSN 3500 II Intelligent Optical Transmission System


Hardware Description

A Indicators

Indicator

A-8

Status

Meaning

Off

The board is in the standby state when


the board is in the 1+1 protection
system.
The board is not activated when the
board is not protected.

Working indicator of ODU 1


(ODU1) two colors (red and
green)

On (green)

ODU 1 operates normally.

On (red)

ODU 1 is faulty.

Working indicator of ODU 2


(ODU2) two colors (red and
green)

On (green)

ODU 2 operates normally.

On (red)

ODU 2 is faulty.

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OptiX OSN 3500 II Intelligent Optical Transmission System


Hardware Description

B Labels

Labels

This topic describes the safety labels, optical module labels, and engineering labels on the OptiX
OSN equipment.
B.1 Safety Labels
Various safety labels are affixed to the equipment. This topic provides the indications and
positions of the safety labels.
B.2 Optical Module Labels
The optical module labels are used to identify different types of optical modules. The optical
module label is affixed to the optical module.
B.3 Engineering Labels
The engineering labels should be prepared according to the local engineering specifications or
Huawei engineering specifications.

Issue 02 (2009-07-30)

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B-1

OptiX OSN 3500 II Intelligent Optical Transmission System


Hardware Description

B Labels

B.1 Safety Labels


Various safety labels are affixed to the equipment. This topic provides the indications and
positions of the safety labels.
B.1.1 Label Description
Labels, such as the ESD protection label, grounding label, and fan warning label are affixed to
the subrack.
B.1.2 Label Position
The ESD protection label and grounding label are affixed to the subrack. The laser safety class
label and APD warning label are affixed to the front panel of the board.

B.1.1 Label Description


Labels, such as the ESD protection label, grounding label, and fan warning label are affixed to
the subrack.
Table B-1 Labels on the equipment
Label

LASER
RADIATION

CLASS 1
LASER
PRODUCT

Label Name

Indication

ESD protection label

The equipment is sensitive to


static electricity.

Laser safety class label

The power class of the laser


source

Grounding label

The grounding position

Periodic cleaning label

The air filter should be


cleaned periodically.

Fan warning label

The fan blades should not be


touched when the fan is
rotating.

APD warning label

The overload point of the


indicator is 9 dBm.

DO NOT VIEW DIRECTLY


WITH OPTICAL
INSTRUMENTS

CLASS 1M
LASER
PRODUCT

! ATTENTION
CLEAN PERIODICALLY

DON'T TOUCH THE


FANLEAVESBEFORE
THEYSLOW DOWN !

APD

Receiver
MAX:-9dBm

B-2

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OptiX OSN 3500 II Intelligent Optical Transmission System


Hardware Description

Label

/QUALIFICATION CARD

B Labels

Label Name

Indication

RoHS label

The equipment meets the


RoHS-related environmentfriendly requirements.

Product nameplate label

The product name and


certification

Certificate of
qualification label

The equipment is qualified.

Permit to work label

No activities to be undertaken
within this rack unless a valid
permit to work is in operation.

HUAWEI

HUAWEI TECHNOLOGIES CO.,LTD.

MADE IN CHINA

B.1.2 Label Position


The ESD protection label and grounding label are affixed to the subrack. The laser safety class
label and APD warning label are affixed to the front panel of the board.

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B-3

OptiX OSN 3500 II Intelligent Optical Transmission System


Hardware Description

B Labels

Figure B-1 Positions of the labels affixed to the OptiX OSN 3500 II subrack
/QUALIFICATION CARD

HUAWEI

HUAWEI TECHNOLOGIES CO.,LTD.

MADE IN CHINA

OptiX OSN 3500 II


POWER RATING:

-48 -60V ; 28.4A

This device complies with Part 15 of the FCC Rules.


Operation is subject to the following two conditions:
(1) this device may not cause harmful interference,
and (2) this device must accept any interference
received, including interference that may cause
undesired operation.
N14036

HUAWEI TECHNOLOGIES CO.,LTD.

MADE IN CHINA

DON'T TOUCH THE


FAN LEAVES BEFORE
THEY SLOW DOWN !

ATTENTION
CLEAN PERIODICALLY

B-4

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OptiX OSN 3500 II Intelligent Optical Transmission System


Hardware Description

B Labels

Figure B-2 Positions of the labels affixed to the cabinet


Figure B-3 Positions of the labels affixed to the board
SL16

CLASS 1
LASER
PRODUCT

APD

Receiver
MAX:-9dBm

BA2

LASER
RADIATION
DO NOT VIEW DIRECTLY
WITH OPTICAL
INSTRUMENTS
CLASS 1M LASER
PRODUCT

B.2 Optical Module Labels


The optical module labels are used to identify different types of optical modules. The optical
module label is affixed to the optical module.
Figure B-4 shows an optical module label.
Figure B-4 Optical module label

Different types of optical modules have different part numbers. Table B-2 provides the part
numbers and descriptions of the optical modules used on the OptiX OSN equipment.
Issue 02 (2009-07-30)

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B-5

OptiX OSN 3500 II Intelligent Optical Transmission System


Hardware Description

B Labels

Table B-2 Part numbers and descriptions of the optical modules used on the OptiX OSN
equipment

B-6

Part Number

Description

34060288

Optical transceiver module, ESFP (internal and external alignment), 1310


nm, STM-16, 10 to 3 dBm, 21 dBm, LC, 2 km

34060278

Optical transceiver module, ESFP (internal and external alignment), 1310


nm, STM-16, 5 to 0 dBm, 21 dBm, LC, 15 km

34060289

Optical transceiver module, ESFP (internal and external alignment), 1310


nm, STM-16, 2 to +3 dBm, 30 dBm, LC, 40 km

34060279

Optical transceiver module, ESFP (internal and external alignment), 1550


nm, STM-16, 2 to +3 dBm, 30 dBm, LC, 80 km

34060277

Optical transceiver, ESFP (internal and external alignment), 1310 nm,


STM-4, 15 to 8 dBm, 31 dBm, LC, 15 km

34060280

Optical transceiver, ESFP (internal and external alignment), 1310 nm,


STM-4, 3 to +2 dBm, 30 dBm, LC, 40 km

34060284

Optical transceiver, ESFP (internal and external alignment), 1550 nm,


STM-4, 3 to +2 dBm, 30 dBm, LC, 80 km

34060285

Optical transceiver, ESFP (internal and external alignment), 1550 nm,


STM-4, 3 to +2 dBm, 36 dBm, LC, 100 km

34060276

Optical transceiver, ESFP (internal and external alignment), 1310 nm,


STM-1, 15 to 8 dBm, 31 dBm, LC, 15 km

34060281

Optical transceiver, ESFP (internal and external alignment), 1310 nm,


STM-1, 5 to 0 dBm, 37 dBm, LC, 40 km

34060282

Optical transceiver, ESFP (internal and external alignment), 1550 nm,


STM-1, 5 to 0 dBm, 37 dBm, LC, 80 km

34060299

Optical transceiver module, ESFP (internal and external alignment), 1310


nm, STM-1, 15 to 8 dBm, 31 dBm, LC (dedicated), 15 km

34060286

Optical transceiver, ESFP (internal and external alignment), 850 nm,


2.125 Gbit/s multi-rate, 9.5 to 2.5 dBm, 17 dBm, LC, 0.5 km

34060219

Optical transceiver, ESFP (internal and external alignment), 1310 nm,


1.25 Gbit/s, 9.5 to 3 dBm, 20 dBm, LC, 10 km

34060298

Optical transceiver, ESFP (internal and external alignment), 1310 nm,


1.25 Gbit/s, 5 to 0 dBm, 23 dBm, LC, SM, 40 km

34060274

Optical transceiver, ESFP (internal and external alignment), 1550 nm,


1.25 Gbit/s, 2 to +5 dBm, 23 dBm, LC, 80 km

34060325

Optical transceiver, ESFP (internal and external alignment), 850 nm,


2.125 Gbit/s multi-rate, 9.5 to 2.5 dBm, 17 dBm, LC (dedicated),
multi-mode, 0.5 km

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OptiX OSN 3500 II Intelligent Optical Transmission System


Hardware Description

B Labels

Part Number

Description

34060049

Optical transceiver, SFP, 850 nm, 1.25 Gbit/s, 0 dBm, 9.5 dBm, 17
dBm, LC, 0.55 km

34060050

Optical transceiver, SFP, 1310 nm, 1.25 Gbit/s, 9 dBm, 3 dBm, 20


dBm, LC, 10 km

34060207

Optical transceiver, SFP, 1310 nm, 1.25 Gbit/s, 2 to +5 dBm, 23 dBm,


LC, 40 km

34060051

Optical transceiver, SFP, 1550 nm, 1.25 Gbit/s, 4 dBm, 2 dBm, 22


dBm, LC, 70 km

34060287

Optical transceiver, SFP, 1310 nm, STM-1, 19 to 14 dBm, 30 dBm,


LC (TX disabled), 2 km

34060053

Optical transceiver, SFP, 1310 nm, STM-1, 15 dBm, 8 dBm, 28 dBm,


LC, 15 km

34060209

Optical transceiver, SFP, 1310 nm, STM-1, 5 dBm, 0 dBm, 34 dBm,


LC, 40 km

B.3 Engineering Labels


The engineering labels should be prepared according to the local engineering specifications or
Huawei engineering specifications.
For information on how to prepare and affix labels, see the OptiX OSN 3500 II Intelligent Optical
Transmission System Installation Guide.

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B-7

OptiX OSN 3500 II Intelligent Optical Transmission System


Hardware Description

C Power Consumption and Weight of Each Board

Power Consumption and Weight of Each


Board
Different boards have different power consumption and weight.
Table C-1 lists the power consumption and weight of each board.
Table C-1 Power consumption and weight of each board
Board

Power
Consumption
(W)

Weight
(kg)

Board

Power
Consumption
(W)

Weight
(kg)

SDH boards

Issue 02 (2009-07-30)

N1SL64

22

1.1

N1SF64

33

1.1

N1SF64A

33

1.1

N1SL16,
N2SL16
and
N2SL16A

20

1.1

N1SLQ16

20

0.9

N1SL16A

20

0.6

N2SLQ16

35

1.3

N3SL16A

22

0.6

N1SL4

17

0.6

N3SL16

22

1.1

N1SL4A

17

0.6

N1SLD16

23

0.9

N2SLD4

15

1.0

N2SL4

15

1.0

N1SLQ4

17

1.0

N1SLD4

17

0.6

N1SLQ4A

17

1.0

N1SLD4A

17

0.6

N1SL1

17

0.6

N2SLQ4

16

1.0

N1SL1A

17

0.6

N2SL1

14

1.0

N1SLQ1A

15

1.0

N1SLQ1

15

1.0

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C Power Consumption and Weight of Each Board

OptiX OSN 3500 II Intelligent Optical Transmission System


Hardware Description

Board

Power
Consumption
(W)

Weight
(kg)

Board

Power
Consumption
(W)

Weight
(kg)

N2SLO1

26

1.1

N2SLQ1

15

1.0

N3SLO1

20

1.2

N1SEP1

17

1.0

N1SLT1

22

1.3

N3SLQ41

12

0.6

N4SL64

23

1.2

N4SF64

23

1.2

N4SLQ16

14

0.9

N3SLH41

47

1.5

N1SLH1B

21

1.1

PDH boards
N1PQM

22

1.0

N1PL3

15

1.0

N2PQ1

13

1.0

N1PL3A

15

1.0

N1PQ1

19

1.0

N2PL3

12

0.9

N1PD3

19

1.1

N2PL3A

12

0.9

N2PD3

12

0.9

N1SPQ4

24

0.9

N2PQ3

13

0.9

N2SPQ4

24

0.9

N2PO1

32

2.0

Interface boards and switching and bridging boards


N1EU08

11

0.4

N1D75S

0.4

N1OU08
and
N2OU08

0.4

N1DM12

0.5

N1EU04

0.4

N1D12B

0.3

N1MU04

0.4

N1D12S

0.4

N1DXA

10

0.8

N1TSB8

0.3

N1DX1

15

1.0

N1TSB4

0.3

N1D34S

0.4

N1C34S

0.3

N1ETF8

0.4

N1ETS8

0.4

N1EFF8

0.4

N1EFF8A

15

0.4

N1ETF8A

11

0.4

Data boards

C-2

N1EFS0A

32

0.7

N1EFS0

35

1.0

N2EGS2

43

1.0

N2EFS0

35

1.0

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OptiX OSN 3500 II Intelligent Optical Transmission System


Hardware Description

C Power Consumption and Weight of Each Board

Board

Power
Consumption
(W)

Weight
(kg)

Board

Power
Consumption
(W)

Weight
(kg)

N3EGS2

25

0.6

N4EFS0

35

1.0

N1EGS4

70

1.1

N5EFS0

22

1.0

N4EGS4

34

0.7

N1EFS4

30

1.0

N1EGT2

29

0.9

N2EFS4

30

1.0

N2EGT2

15

0.9

N3EFS4

18

0.6

N2EMR0

50

1.2

N1EFT8A

26

1.0

N1EMS2

40

0.7

N1EFT8

26

1.0

N1EMS4

65

1.1

N1IDQ1

41

1.0

N2EGR2

40

1.1

N1IDL4

41

1.0

N1IDQ1A

46

1.5

N1IDL4A

60

1.5

N1ADL4

41

0.9

N1ADQ1

41

1.0

N1MST4

26

0.9

N1EGS2A

50

1.0

N1EFP0

25

1.0

Cross-connect boards and system control boards


Q5CXLLN
and
Q5CXLQ4
1

32

1.0

Q6CXLLN
and
Q6CXLQ4
1

48

1.5

Q5CXS

28

0.8

Other boards

Issue 02 (2009-07-30)

TN11MR2

0.9

N1BA2

20

1.0

TN11CMR
2

0.8

N1BPA

20

1.0

TN11CMR
4

0.9

N2BPA

11

1.2

TN11MR4

0.9

Q1AUX

10

1.1

N1FIB

0.4

N1FAN

16 x 3

1.5 x 3

N1MR2A

1.0

TN11OBU
1

16

1.3

N1MR2C

1.0

R1EOW

10

0.4

N1LWX

30

1.1

N1SEI

0.9

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C-3

C Power Consumption and Weight of Each Board

C-4

OptiX OSN 3500 II Intelligent Optical Transmission System


Hardware Description

Board

Power
Consumption
(W)

Weight
(kg)

Board

Power
Consumption
(W)

Weight
(kg)

Q2PIU

0.3

N1IFSD1

24

1.1

N1RPWR

60

1.4

N1RPC01

70

4.0

N1RPC02

110

4.2

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OptiX OSN 3500 II Intelligent Optical Transmission System


Hardware Description

D Compatibility of Board Versions with the Products

Compatibility of Board Versions with the


Products
This topic provides information on whether a board of a specific version is supported by the
OptiX OSN products.
Table D-1 provides information on whether a board of a specific version is supported by the
OptiX OSN products.
Table D-1 Information on whether a board of a specific version is supported by the OptiX OSN
products

Issue 02 (2009-07-30)

Product

OptiX
OSN
7500

OptiX
OSN
3500

OptiX
OSN
3500 II

OptiX
OSN
2500

OptiX
OSN
2500
REG

OptiX
OSN
1500A

OptiX
OSN
1500B

N1SL64

N2SL64

T2SL64

T2SL64A

N1SF64

N1SF64A

N1SLD64

N1SL16

N2SL16

N3SL16

N1SL16A

N2SL16A

N3SL16A

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D-1

D Compatibility of Board Versions with the Products

D-2

OptiX OSN 3500 II Intelligent Optical Transmission System


Hardware Description

Product

OptiX
OSN
7500

OptiX
OSN
3500

OptiX
OSN
3500 II

OptiX
OSN
2500

OptiX
OSN
2500
REG

OptiX
OSN
1500A

OptiX
OSN
1500B

N1SLD16

N1SLQ16

N2SLQ16

N1SLO16

N1SF16

N3SLQ41

N1SL4

N2SL4

N1SL4A

R1SL4

R3SL4

N1SLQ4

N2SLQ4

N1SLQ4A

N1SLD4

N2SLD4

N1SLD4A

R1SLD4

R3SLD4

N1SLT1

N1SLQ1

N2SLQ1

N1SLQ1A

R1SLQ1

R3SLQ1

N1SL1

N2SL1

N1SL1A

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D Compatibility of Board Versions with the Products

Product

OptiX
OSN
7500

OptiX
OSN
3500

OptiX
OSN
3500 II

OptiX
OSN
2500

OptiX
OSN
2500
REG

OptiX
OSN
1500A

OptiX
OSN
1500B

R1SL1

R3SL1

N1SLH1

N1SLH1B

N1SEP1

N2SLO1

N3SLO1

R1PL1

R1PD1

R2PD1

R3PD1

N1PQ1

N2PQ1

N2PO1

N1PQM

N1PL3

N2PL3

N1PL3A

N2PL3A

N1PD3

N2PD3

N2PQ3

N1DX1

N1DXA

N1SPQ4

N2SPQ4

R1EFT4

N1EFT8

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D-3

D Compatibility of Board Versions with the Products

D-4

OptiX OSN 3500 II Intelligent Optical Transmission System


Hardware Description

Product

OptiX
OSN
7500

OptiX
OSN
3500

OptiX
OSN
3500 II

OptiX
OSN
2500

OptiX
OSN
2500
REG

OptiX
OSN
1500A

OptiX
OSN
1500B

N1EFT8A

N1EGT2

N1EFS0

N2EFS0

N4EFS0

N5EFS0

N1EFS0A

N1EFS4

N2EFS4

N3EFS4

N2EGS2

N3EGS2

N1EMS4

N1EMS2

N1EGS4

N3EGS4

N2EGR2

N2EMR0

N1EAS2

N1ADL4

N1ADQ1

N1IDL4

N1IDL4A

N1IDQ1

N1IDQ1A

N1MST4

N1EU08

N1OU08

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Hardware Description

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D Compatibility of Board Versions with the Products

Product

OptiX
OSN
7500

OptiX
OSN
3500

OptiX
OSN
3500 II

OptiX
OSN
2500

OptiX
OSN
2500
REG

OptiX
OSN
1500A

OptiX
OSN
1500B

N2OU08

N1D75S

N1MU04

N1D34S

N1C34S

N1EU04

N1D12S

N1D12B

R1L12S

R1L75S

N1EFF8

N1ETF8

N1ETS8

N1DM12

N1TSB4

N1TSB8

Q2CXL1

Q3CXL1

Q2CXL4

Q3CXL4

Q2CXL16

Q3CXL16

R1CXLLN

R2CXLLN

Q5CXLLN

Q6CXLLN

R1CXLD41

R1CXLQ41

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D Compatibility of Board Versions with the Products

D-6

OptiX OSN 3500 II Intelligent Optical Transmission System


Hardware Description

Product

OptiX
OSN
7500

OptiX
OSN
3500

OptiX
OSN
3500 II

OptiX
OSN
2500

OptiX
OSN
2500
REG

OptiX
OSN
1500A

OptiX
OSN
1500B

R2CXLQ41

Q5CXLQ41

Q6CXLQ41

Q5CXS

T1GXCSA

N1GXCSA

T1EXCSA

N1EXCSA

T2UXCSA

N1UXCSA

N1UXCSB

T1SXCSA

T2SXCSA

N1SXCSA

N1SXCSB

T1IXCSA

N1IXCSA

N1IXCSB

N1XCE

N1GSCC

N2GSCC

N3GSCC

N4GSCC

CRG

T1EOW

R1EOW

T1AUX

N1AUX

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Hardware Description

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D Compatibility of Board Versions with the Products

Product

OptiX
OSN
7500

OptiX
OSN
3500

OptiX
OSN
3500 II

OptiX
OSN
2500

OptiX
OSN
2500
REG

OptiX
OSN
1500A

OptiX
OSN
1500B

R1AUX

R2AUX

Q1AUX

R1AMU

Q1SAP

Q2SAP

Q1SEI

N1SEI

N1FAN

R1FAN

N1FANA

N1FANB

TN11CMR2

TN11CMR4

TN11MR2

TN11MR4

N1MR2A

N1MR2B

N1MR2C

N1LWX

N1IFSD1

N1RPWR

TN11OBU1

N1FIB

N1BA2

N1BPA

N2BPA

61COA

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D Compatibility of Board Versions with the Products

OptiX OSN 3500 II Intelligent Optical Transmission System


Hardware Description

Product

OptiX
OSN
7500

OptiX
OSN
3500

OptiX
OSN
3500 II

OptiX
OSN
2500

OptiX
OSN
2500
REG

OptiX
OSN
1500A

OptiX
OSN
1500B

62COA

N1COA

N1RPC01

N1RPC02

N1DCU

N2DCU

UPM
(GIE4805S)

UPM
(EPS75-4815A
F)

T1PIU

N1PIU

N1PIUA

Q1PIU

Q1PIUA

Q2PIU

R1PIU

R1PIUA

R1PIUB

R1PIUC

NOTE
"Y" indicates that the OptiX OSN equipment supports the board and "N" indicates that the OptiX OSN
equipment does not support the board.
This table provides information on whether a specific type of board is supported by a specific type of OptiX
OSN equipment. For example, the N3GSCC is supported by the OptiX OSN 7500 and OptiX OSN 3500
but not supported by the other equipment such as the OptiX OSN 3500 II.

D-8

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OptiX OSN 3500 II Intelligent Optical Transmission System


Hardware Description

E Loopback Capability of the Boards

Loopback Capability of the Boards

The SDH boards, PDH boards, and data boards of the OptiX OSN equipment support various
types of loopbacks.
Table E-1 provides the loopback capability of the SDH boards of the OptiX OSN equipment.
Table E-1 Loopback capability of the SDH boards

Issue 02 (2009-07-30)

Board

Inloop at an
Interface

Outloop at
an
Interface

Inloop on a
VC-4 Path

Outloop on
a VC-4 Path

Outloop on
a VC-3 or
VC-12 Path

Q2SL1

Supported

Supported

Supported

Not
supported

Not
supported

Q2SL4

Supported

Supported

Supported

Not
supported

Not
supported

Q2SL16

Supported

Supported

Supported

Not
supported

Not
supported

N1SL64

Supported

Supported

Supported

Supported

Not
supported

N2SL64

Supported

Supported

Not
supported

Not
supported

Not
supported

T2SL64

Supported

Supported

Not
supported

Not
supported

Not
supported

T2SL64A

Supported

Supported

Not
supported

Not
supported

Not
supported

N1SF64

Supported

Supported

Supported

Supported

Not
supported

N1SF64A

Supported

Supported

Supported

Supported

Not
supported

N1SLD64

Supported

Supported

Supported

Supported

Not
supported

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OptiX OSN 3500 II Intelligent Optical Transmission System


Hardware Description

E Loopback Capability of the Boards

E-2

Board

Inloop at an
Interface

Outloop at
an
Interface

Inloop on a
VC-4 Path

Outloop on
a VC-4 Path

Outloop on
a VC-3 or
VC-12 Path

N1SL16

Supported

Supported

Supported

Not
supported

Not
supported

N2SL16

Supported

Supported

Not
supported

Not
supported

Not
supported

N3SL16

Supported

Supported

Supported

Supported

Not
supported

N1SL16A

Supported

Supported

Supported

Not
supported

Not
supported

N2SL16A

Supported

Supported

Not
supported

Not
supported

Not
supported

N3SL16A

Supported

Supported

Supported

Supported

Not
supported

N1SLD16

Supported

Supported

Supported

Supported

Not
supported

N1SLQ16

Supported

Supported

Supported

Supported

Not
supported

N2SLQ16

Supported

Supported

Not
supported

Not
supported

Not
supported

N1SLO16

Supported

Supported

Supported

Supported

Not
supported

N1SF16

Supported

Supported

Supported

Not
supported

Not
supported

N3SLQ41

Supported

Supported

Supported

Supported

Not
supported

N1SL4

Supported

Supported

Supported

Not
supported

Not
supported

N1SL4A

Supported

Supported

Supported

Supported

Not
supported

N2SL4

Supported

Supported

Not
supported

Not
supported

Not
supported

R1SL4

Supported

Supported

Supported

Not
supported

Not
supported

R3SL4

Supported

Supported

Supported

Supported

Not
supported

N1SLQ4

Supported

Supported

Supported

Not
supported

Not
supported

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Hardware Description

Issue 02 (2009-07-30)

E Loopback Capability of the Boards

Board

Inloop at an
Interface

Outloop at
an
Interface

Inloop on a
VC-4 Path

Outloop on
a VC-4 Path

Outloop on
a VC-3 or
VC-12 Path

N1SLQ4A

Supported

Supported

Supported

Supported

Not
supported

N2SLQ4

Supported

Supported

Not
supported

Not
supported

Not
supported

N1SLD4

Supported

Supported

Supported

Not
supported

Not
supported

N1SL4DA

Supported

Supported

Supported

Supported

Not
supported

N2SLD4

Supported

Supported

Not
supported

Not
supported

Not
supported

R1SLD4

Supported

Supported

Supported

Not
supported

Not
supported

R3SLD4

Supported

Supported

Supported

Supported

Not
supported

N1SLT1

Supported

Supported

Supported

Supported

Not
supported

N1SLQ1

Supported

Supported

Supported

Not
supported

Not
supported

N1SLQ1A

Supported

Supported

Supported

Supported

Not
supported

N2SLQ1

Supported

Supported

Not
supported

Not
supported

Not
supported

R1SLQ1

Supported

Supported

Supported

Not
supported

Not
supported

R3SLQ1

Supported

Supported

Supported

Supported

Not
supported

N1SL1

Supported

Supported

Supported

Not
supported

Not
supported

N1SL1A

Supported

Supported

Supported

Supported

Not
supported

N2SL1

Supported

Supported

Not
supported

Not
supported

Not
supported

R1SL1

Supported

Supported

Supported

Not
supported

Not
supported

R3SL1

Supported

Supported

Supported

Supported

Not
supported

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E-3

OptiX OSN 3500 II Intelligent Optical Transmission System


Hardware Description

E Loopback Capability of the Boards

Board

Inloop at an
Interface

Outloop at
an
Interface

Inloop on a
VC-4 Path

Outloop on
a VC-4 Path

Outloop on
a VC-3 or
VC-12 Path

N1SLH1

Supported

Supported

Supported

Supported

Not
supported

N1SLH1B

Supported

Supported

Supported

Supported

Not
supported

N1SEP1

Supported

Supported

Supported

Not
supported

Not
supported

N2SLO1

Supported

Supported

Not
supported

Not
supported

Not
supported

N3SLO1

Supported

Supported

Supported

Supported

Not
supported

Table E-2 provides information on whether each SDH board of the OptiX OSN equipment
supports the insertion of the AU_AIS when the board is looped back.
Table E-2 Information on whether each SDH board of the OptiX OSN equipment supports the
insertion of the AU_AIS when the board is looped back

E-4

Board

Insertion of
the AU_AIS
to the Port
Side (Inloop
at an
Interface)

Insertion of
the AU_AIS to
the CrossConnect Side
(Outloop at an
Interface)

Insertion of
the AU_AIS
to the CrossConnect Side
(Inloop on a
VC-4 Path)

Insertion of
the AU_AIS
to the Port
Side
(Outloop on
a VC-4 Path)

Q2SL1

Not supported

Supported

Not supported

Not supported

Q2SL4

Not supported

Supported

Not supported

Not supported

Q2SL16

Not supported

Supported

Not supported

Not supported

N1SL64

Supported

Supported

Supported

Supported

N2SL64

Not supported

Supported

Not supported

Not supported

T2SL64

Not supported

Supported

Not supported

Not supported

T2SL64A

Not supported

Supported

Not supported

Not supported

N1SF64

Supported

Supported

Supported

Supported

N1SF64A

Supported

Supported

Supported

Supported

N1SLD64

Supported

Supported

Supported

Supported

N1SL16

Not supported

Supported

Not supported

Not supported

N2SL16

Not supported

Supported

Not supported

Not supported

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Hardware Description

Issue 02 (2009-07-30)

E Loopback Capability of the Boards

Board

Insertion of
the AU_AIS
to the Port
Side (Inloop
at an
Interface)

Insertion of
the AU_AIS to
the CrossConnect Side
(Outloop at an
Interface)

Insertion of
the AU_AIS
to the CrossConnect Side
(Inloop on a
VC-4 Path)

Insertion of
the AU_AIS
to the Port
Side
(Outloop on
a VC-4 Path)

N3SL16

Supported

Supported

Supported

Supported

N1SL16A

Not supported

Supported

Not supported

Not supported

N2SL16A

Not supported

Supported

Not supported

Not supported

N3SL16A

Supported

Supported

Supported

Supported

N1SLD16

Supported

Supported

Supported

Supported

N1SLQ16

Supported

Supported

Supported

Supported

N2SLQ16

Not supported

Supported

Not supported

Not supported

N1SLO16

Supported

Supported

Supported

Supported

N1SF16

Not supported

Supported

Not supported

Not supported

N1SL4

Not supported

Supported

Not supported

Not supported

N1SL4A

Supported

Supported

Supported

Supported

N2SL4

Not supported

Supported

Not supported

Not supported

R1SL4

Not supported

Supported

Not supported

Not supported

R3SL4

Supported

Supported

Supported

Supported

N1SLQ4

Not supported

Supported

Not supported

Not supported

N1SLQ4A

Supported

Supported

Supported

Supported

N2SLQ4

Not supported

Supported

Not supported

Not supported

N1SLD4

Not supported

Supported

Not supported

Not supported

N1SLD4A

Supported

Supported

Supported

Supported

N2SLD4

Not supported

Supported

Not supported

Not supported

R3SLD4

Supported

Supported

Supported

Supported

R1SLD4

Not supported

Supported

Not supported

Not supported

N1SLT1

Supported

Supported

Supported

Supported

N1SLQ1

Not supported

Supported

Not supported

Not supported

N1SLQ1A

Supported

Supported

Supported

Supported

N2SLQ1

Not supported

Supported

Not supported

Not supported

R1SLQ1

Not supported

Supported

Not supported

Not supported

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E-5

OptiX OSN 3500 II Intelligent Optical Transmission System


Hardware Description

E Loopback Capability of the Boards

Board

Insertion of
the AU_AIS
to the Port
Side (Inloop
at an
Interface)

Insertion of
the AU_AIS to
the CrossConnect Side
(Outloop at an
Interface)

Insertion of
the AU_AIS
to the CrossConnect Side
(Inloop on a
VC-4 Path)

Insertion of
the AU_AIS
to the Port
Side
(Outloop on
a VC-4 Path)

R3SLQ1

Supported

Supported

Supported

Supported

N1SL1

Not supported

Supported

Not supported

Not supported

N1SL1A

Supported

Supported

Supported

Supported

N2SL1

Not supported

Supported

Not supported

Not supported

R1SL1

Not supported

Supported

Not supported

Not supported

R3SL1

Supported

Supported

Supported

Supported

N1SLH1

Supported

Supported

Supported

Supported

N1SLH1B

Supported

Supported

Supported

Supported

N1SEP1

Not supported

Supported

Not supported

Not supported

N2SLO1

Not supported

Supported

Not supported

Not supported

N3SLO1

Supported

Supported

Supported

Supported

Table E-3 provides the loopback capability of the PDH boards of the OptiX OSN equipment.
Table E-3 Loopback capability of the PDH boards

E-6

Board

Inloop at an
Interface

Outloop at an
Interface

R1PL1

Supported

Supported

R1PD1

Supported

Supported

R3PD1

Supported

Supported

N1PQ1

Supported

Supported

N2PO1

Supported

Supported

N1PQM

Supported

Supported

N1PD3

Supported

Supported

N1PL3

Supported

Supported

N2PQ3

Supported

Supported

N2SPQ4

Supported

Supported

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E Loopback Capability of the Boards

Table E-4 provides the loopback capability of the data boards of the OptiX OSN equipment.
Table E-4 Loopback capability of the data boards of the OptiX OSN equipment

Issue 02 (2009-07-30)

Board

Outloop
at the
MAC
Layer

Inloop at
the MAC
Layer

Outloop
at the
PHY
Layer

Inloop at
the PHY
Layer

Inloop
and
Outloop
on a
VC-4
Path

Inloop
and
Outloop
on a VC-3
Path

N1EFS4

Not
supported

Supported

Not
supported

Supported

Not
supported

Supported

N2EFS4

Not
supported

Supported

Not
supported

Supported

Not
supported

Supported

N3EFS4

Not
supported

Supported

Not
supported

Supported

Not
supported

Not
supported

N1EFS0

Not
supported

Supported

Not
supported

Supported

Not
supported

Supported

N2EFS0

Not
supported

Supported

Not
supported

Supported

Not
supported

Supported

N4EFS0

Not
supported

Supported

Not
supported

Supported

Not
supported

Supported

N5EFS0

Not
supported

Supported

Not
supported

Supported

Not
supported

Not
supported

N1EFS0A

Not
supported

Supported

Not
supported

Supported

Not
supported

Not
supported

N1EGT2

Not
supported

Supported

Not
supported

Supported

Not
supported

Not
supported

N2EGT2

Not
supported

Supported

Not
supported

Supported

Not
supported

Not
supported

N1EFT8

Not
supported

Supported

Not
supported

Supported

Not
supported

Supported

N1EFT8A

Not
supported

Supported

Not
supported

Supported

Not
supported

Supported

R1EFT4

Not
supported

Supported

Not
supported

Supported

Not
supported

Supported

N1EMS4

Not
supported

Not
supported

Not
supported

Supported

Not
supported

Not
supported

N1EMS2

Not
supported

Supported

Not
supported

Supported

Not
supported

Not
supported

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E-7

OptiX OSN 3500 II Intelligent Optical Transmission System


Hardware Description

E Loopback Capability of the Boards

Board

Outloop
at the
MAC
Layer

Inloop at
the MAC
Layer

Outloop
at the
PHY
Layer

Inloop at
the PHY
Layer

Inloop
and
Outloop
on a
VC-4
Path

Inloop
and
Outloop
on a VC-3
Path

N1EGS4

Not
supported

Not
supported

Not
supported

Supported

Not
supported

Not
supported

N3EGS4

Not
supported

Not
supported

Not
supported

Supported

Not
supported

Not
supported

N2EGS4

Not
supported

Not
supported

Not
supported

Supported

Not
supported

Not
supported

N2EGS2

Not
supported

Not
supported

Not
supported

Supported

Not
supported

Supported

N3EGS2

Not
supported

Supported

Not
supported

Supported

Not
supported

Not
supported

N2EGR2

Not
supported

Supported

Not
supported

Supported

Not
supported

Not
supported

N1EAS2

Not
supported

Supported

Not
supported

Supported

Not
supported

Not
supported

N2EMR0

Not
supported

Supported

Not
supported

Supported

Not
supported

Not
supported

N1EMS2

Not
supported

Not
supported

Not
supported

Supported

Not
supported

Not
supported

N1MST4

Not
supported

Not
supported

Not
supported

Supported

Not
supported

Not
supported

Table E-5 provides the loopback capability of the ATM/IMA boards of the OptiX OSN
equipment.
Table E-5 Loopback capability of the ATM/IMA boards of the OptiX OSN equipment

E-8

Board

Outloop at an
External
Interface

Inloop at an
External
Interface

Outloop at an
Internal
Interface

Inloop at an
Internal
Interface

N1ADL4

Not supported

Supported

Supported

Supported

N1ADQ1

Not supported

Supported

Supported

Supported

N1IDL4

Not supported

Supported

Supported

Supported

N1IDL4A

Not supported

Supported

Supported

Supported

N1IDQ1

Not supported

Supported

Supported

Supported

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Hardware Description

Issue 02 (2009-07-30)

E Loopback Capability of the Boards

Board

Outloop at an
External
Interface

Inloop at an
External
Interface

Outloop at an
Internal
Interface

Inloop at an
Internal
Interface

N1IDQ1A

Not supported

Supported

Supported

Supported

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E-9

OptiX OSN 3500 II Intelligent Optical Transmission System


Hardware Description

F Parameter Settings

Parameter Settings

You can set the parameters for the SDH boards, PDH boards, data boards, WDM boards, optical
amplifier boards, and cross-connect and timing unit by using the T2000.
F.1 SDH Processing Boards
The parameters that need to be set for the SDH processing boards include the J0 byte, J1 byte,
J2 byte, and C2 byte.
F.2 PDH Boards
The parameters that need to be set for the PDH boards include the J1 byte, C2 byte, J2 byte, V5
byte, and tributary loopback.
F.3 Data Boards
The parameters that need to be set for the data boards include the SDH parameters, Ethernet
parameters, and ATM parameters.
F.4 WDM Boards
The parameters that need to be set for the WDM boards include the path use status, optical
interface loopback, service type, client service bearer rate (M), laser status, automatic laser
shutdown, current bearer rate (M), actual wavelength no./wavelength (nm)/frequency (THz),
actual band type, configure wavelength no./wavelength (nm)/frequency (THz), configure band
type, and SD trigger condition.
F.5 Optical Amplifier Boards
The parameters that need to be set for the optical amplifier boards include the laser status, board
work type, configure band, configure working band parity, actual band, actual working band
parity, threshold of input power loss, gain, rated optical power, nominal gain upper threshold,
and nominal gain lower threshold.
F.6 Cross-Connect and Timing Units
The parameters that need to be set for the cross-connect and timing units include the clock source
parameters and clock subnet parameters.

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F-1

OptiX OSN 3500 II Intelligent Optical Transmission System


Hardware Description

F Parameter Settings

F.1 SDH Processing Boards


The parameters that need to be set for the SDH processing boards include the J0 byte, J1 byte,
J2 byte, and C2 byte.

J0 Byte
The J0 byte is used to transmit repetitively a section access point identifier so that a section
receiver can verify its continued connection to the intended transmitter. It is recommended that
you set the J0 byte to the single-byte "".

J1 Byte
J1 is the higher order path trace byte. This byte is used to transmit repetitively a path access
point identifier so that a path receiving terminal can verify its continued connection to the
intended transmitter. When a J1 mismatch is detected at the receive end, the corresponding VC-4
path generates an HP_TIM alarm.
In the case of the SLO1, it is recommended that you set the J1 byte to " HuaWei SBS ". In
the case of the other boards, it is recommended that the J1 byte uses the default value, namely,
single-byte "".
NOTE

The J1 byte was set to " HuaWei SBS " by default. In the character string " HuaWei SBS
one blank space before "HuaWei" and five blank spaces after "SBS".

", there is

J2 Byte
J2 is the lower order path trace byte. This byte is used to transmit repetitively a low order path
access point identifier so that a path receiving terminal can verify its continued connection to
the intended transmitter.
To set and query the J2 byte to be received, enable the lower order monitoring function.
NOTE

In the case of the SDH processing boards, the J2 byte to be sent cannot be set.

C2 Byte
C2 is the signal label byte, which is used to indicate the multiplexing structure of the VC frames
and the payload property. The C2 byte to be sent must match the C2 byte to be received. When
a C2 mismatch is detected, the corresponding VC-4 path at the local end generates an HP_SLM
alarm.
Table F-1 shows the relation between the service type and the value of the C2 byte.
Table F-1 Relation between the service type and the value of the C2 byte

F-2

Service Type

Value of the C2 Byte (Hexadecimal)

TUG structure

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Hardware Description

F Parameter Settings

Service Type

Value of the C2 Byte (Hexadecimal)

34M/45M into C-3

04

140M into C-4

12

Unequipped

00

F.2 PDH Boards


The parameters that need to be set for the PDH boards include the J1 byte, C2 byte, J2 byte, V5
byte, and tributary loopback.

J1 Byte
J1 is the path trace byte. This byte is used to transmit repetitively a path access point identifier
so that a path receiving terminal can verify its continued connection to the intended transmitter.
When a J1 mismatch is detected at the receive end, the corresponding VC-4 path generates an
HP_TIM alarm.
The J1 byte is set to the single-byte "" by default.
NOTE

The J1 byte was set to " HuaWei SBS

" by default.

C2 Byte
C2 is the signal label byte, which is used to indicate the multiplexing structure of the VC frames
and the payload property. The C2 byte to be sent must match the C2 byte to be received. When
a C2 mismatch is detected, the corresponding VC-4 path at the local end generates an HP_SLM
alarm.
Table F-2 shows the relation between the service type and the value of the C2 byte.
Table F-2 Relation between the service type and the value of the C2 byte
Service Type

Value of the C2 Byte (Hexadecimal)

TUG structure

02

34M/45M into C-3

04

140M into C-4

12

Unequipped

00

J2 Byte
J2 is the VC-12 path trace byte. This byte is used to transmit repetitively a low order path access
point identifier so that a path receiving terminal can verify its continued connection to the
intended transmitter.
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F-3

OptiX OSN 3500 II Intelligent Optical Transmission System


Hardware Description

F Parameter Settings

V5 Byte
V5 is the path status and signal label byte. This byte is used to detect bit errors and indicate
remote errors or remote failures on lower order paths. The LP_REI and LP_RFI alarms are
generated accordingly. Table F-3 shows the relation between the service type and the value of
the V5 byte.
Table F-3 Relation between the service type and the value of the V5 byte
Service Type

Value of the V5 Byte (Hexadecimal)

Asynchronous

02

Byte synchronization

04

HDLC/PPP mapping

0A

Unequipped or supervisoryunequipped

00

Equipping Indication
When a service channel only carries the service and does not process the service, select
Unequipped or Supervisory-Unequipped.
When a service channel carries the service and also processes the service, select EquippedUnspecific Payload.

Tributary Loopback
The tributary loopback function is used to locate faults in the service channels.
The tributary loopback is also a diagnosis function. When the tributary loopback is performed,
related services are interrupted.

Path Service Type


This parameter is set to specify service type for the channel.
l

Select E1 or T1 for E1/T1 processing boards according to the actual service type in the
channel.

Select E3 or T3 for E3/T3 processing boards according to the actual service type in the
channel.

Serial Port Protocol Mode


For the DX1, select the protocol mode of the N x 64 kbit/s signals. The protocol mode includes
V.35, V.24, X.21, RS449, RS530 and RS530A.

DDN Clock Source Management


The timing scheme and working clock source can be set for the DX1.
F-4

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F Parameter Settings

Set the timing scheme of the DDN channels 1012 and 1416 to the DCE internal scheme,
DCE slave scheme or DTE external scheme.

Set the timing scheme of the DDN channels 9 and 13 to the DCE internal scheme, DCE
slave scheme, DTE external scheme, DTE internal scheme, DTE slave scheme or DCE
external scheme. By default, the timing scheme is the DCE internal scheme for channels 9
and 13 is the DCE internal scheme.

F.3 Data Boards


The parameters that need to be set for the data boards include the SDH parameters, Ethernet
parameters, and ATM parameters.
F.3.1 SDH Parameters
The SDH parameters that need to be set for the data boards include the J1 byte, C2 byte, J2 byte,
and V5 byte.
F.3.2 Ethernet Parameters
The Ethernet parameters that need to be set for the data boards include the working mode and
LCAS.
F.3.3 ATM Parameters
The ATM parameters that need to be set for the ATM boards include the port type and traffic
type.

F.3.1 SDH Parameters


The SDH parameters that need to be set for the data boards include the J1 byte, C2 byte, J2 byte,
and V5 byte.

J1 Byte
J1 is the path trace byte. Successive transmission of the J1 byte at the transmit end helps the
receive end learn that its connection with the specified transmit end is in the continuous
connection state.
When a J1 mismatch is detected at the receive end, the VC-3 path generates an LP_TIM_VC3
alarm and the VC-4 path generates an HP_TIM alarm.
When the J1 byte is set to the single-byte "" by default, the alarms are not reported.
NOTE

In the case of the N1EFS4 and MST4, the J1 byte is set to " HuaWei SBS
of the other boards, the J1 byte is set to the single-byte "" by default.

" by default. In the case

In the case of the EMS4 and EGS4, it is recommended that you set the J1 byte to " HuaWei SBS

".

C2 Byte
C2 is the signal label byte, which is used to indicate the multiplexing structure of the VC frames
and the payload property. The C2 byte to be sent must match the C2 byte to be received.
When a C2 mismatch is detected, the VC-3 path generates an LP_SLM_VC3 alarm and the
VC-4 path generates an HP_SLM alarm.
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Hardware Description

F Parameter Settings

J2 Byte
J2 is the VC-12 path trace byte. This byte is used to transmit repetitively a low order path access
point identifier so that a path receiving terminal can verify its continued connection to the
intended transmitter.
When a J2 mismatch is detected, the VC-12 path generates an LP_TIM_VC12 alarm.
When the J2 byte is set to the single-byte "" by default, the alarms are not reported.

V5 Byte
V5 is the path status and signal label byte. This byte is used to detect bit errors and indicate
remote errors or remote failures on lower order paths. The LP_REI and LP_RFI alarms are
generated accordingly.
When a V5 mismatch is detected at the receive end, the VC-12 path generates an LP_SLM_VC12
alarm.
Table F-4 shows the relation between the service type and the value of the V5 byte.
Table F-4 Relation between the service type and the value of the V5 byte
Service Type

Value of the V5 Byte (Hexadecimal)

Asynchronous

02

Byte synchronization

04

HDLC/PPP mapping

0A

Unequipped or supervisoryunequipped

00

F.3.2 Ethernet Parameters


The Ethernet parameters that need to be set for the data boards include the working mode and
LCAS.

Working Mode
Generally, the Ethernet interfaces of the interconnected equipment are required to work in the
same fixed working mode. If the working modes on two sides do not match, packets may be lost
or the bit rate may decrease. In the case of large volume of traffic, services may be completely
interrupted.
Currently, the Ethernet boards support the following working modes: auto-negotiation, 10M
half-duplex, 10M full-duplex, 100M half-duplex, 100M full-duplex, 10M/100M full-duplex,
1000M full-duplex, and 10G full-duplex

LCAS
This parameter specifies whether to enable the LCAS function.
F-6

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Hardware Description

F Parameter Settings

Maximum Frame Length


This parameter needs to be set in the case of external interfaces. By default, the maximum frame
length is 1522 bytes.

Mapping Protocol
This parameter needs to be set to consistent values in the case of the interconnected equipment.
Currently, the Ethernet boards support the following mapping protocols:
l

HDLC, LAPS, or GFP. It is recommended that you adopt the default value "GFP".

GFP-F

LAPS or GFP. It is recommended that you adopt the default value "GFP".

GFP-T

TAG
This parameter is used to identify the type of packets. This parameter can be set to "tag aware",
"access", or "hybrid".
1.

When this parameter is set to "tag aware", the interface transparently transmits the packets
that contain a TAG and discards the packets that do not contain a TAG.

2.

When this parameter is set to "access", the interface adds a TAG to the packets that do not
contain a TAG according to the default VLAN ID of the interface, and discards the packets
that contain a TAG.

3.

When this parameter is set to "hybrid", the interface processes both the packets that contain
a TAG and the packets that do not contain a TAG. The interface adds a TAG to the packets
that do not contain a TAG according to the default VLAN ID of the interface.

VLAN ID
This parameter specifies the VLAN ID of the interface.

Port Type
In the case of the boards that support the MPLS function, the ports are available in two types,
namely, provider (P) and provider edge (PE). The port of type P indicates a core network port
of a service provider. The port of type PE indicates an edge port of a service provider. You need
to set this parameter when you configure EVPL services or EVPLAN services. In the case of an
external port, set this parameter to "PE". In the case of an internal port, set this parameter to "P".

Encapsulation Format
This parameter can be set to "MartinioE" or "stack VLAN". When the port type parameter is set
to "P", this parameter becomes valid. In the case of EVPL services, set this parameter to
"MartinioE". In the case of EVPLAN services, set this parameter to "stack VLAN".

Port Attributes
In the case of the board that supports the QinQ function, you can set this parameter. This
parameter can be set to "UNI", "NNI", "N-UNI", "S-aware", or "C-aware".
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Hardware Description

F Parameter Settings

F.3.3 ATM Parameters


The ATM parameters that need to be set for the ATM boards include the port type and traffic
type.

Port Type
The port types include NNI and UNI. The default port type is UNI.

Traffic Type
The traffic type must meet the requirements of the port.

Service Type
Five service types are available, namely, CBR, rt-VBR, nrt-VBR, UBR, and UBR+.

Peak Cell Rate


Set the peak cell rate of the ATM services. This parameter must be set for each service type.

Sustainable Cell Rate


Set the sustainable cell rate of the ATM services. In the case of the rt-VBR and nrt-VBR services,
set this parameter.

MBS
Set the MBS of the ATM services. In the case of the rt-VBR and nrt-VBR services, set this
parameter.

CDVT
Set the CDVT of the ATM services. In the case of the CBR, rt-VBR, and UBR services, set this
parameter.

F.4 WDM Boards


The parameters that need to be set for the WDM boards include the path use status, optical
interface loopback, service type, client service bearer rate (M), laser status, automatic laser
shutdown, current bearer rate (M), actual wavelength no./wavelength (nm)/frequency (THz),
actual band type, configure wavelength no./wavelength (nm)/frequency (THz), configure band
type, and SD trigger condition.

Path Use Status

F-8

Item

Description

Parameter description

Used to set the path use status

Parameter values

Used and Unused

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F Parameter Settings

Item

Description

Parameter value description

Default value: Used

Recommended value

Used

Application scenarios

In configuration, commissioning, and


maintenance stages

Impact on the system

When the Path Use Status of an optical interface


is set to Unused, service alarms at this interface
are suppressed, which disables the automatic laser
turn on function.

Relevant boards

LWX

Configuration requirements

When the channel is not required, its Path Use


Status can be set to Unused. In this case, a
command should be issued to shut down the laser
of this path; otherwise, an alarm indicates that the
laser is forcibly turned on is reported.

Optical Interface Loopback


Item

Description

Parameter description

Used to set the loopback mode of the current


optical interface.

Parameter values

Non-Loopback, Outloop, and Inloop

Parameter value description

Default value: Non-Loopback


Non-Loopback: indicates that the equipment is in
normal state. Optical interface loopback is not
required when the equipment normally operates.
Inloop: indicates a mode that signals to be output
from the output interface of the local-end
equipment are looped back to the signal input
interface of this equipment. Inloop is used to test
the signal processing on the board.
Outloop: indicates a mode that unprocessed
signals accessed to the local-end equipment are
directly looped back to the corresponding output
interface without the signal structure changed.
Outloop is used to test connections between fiber
lines and connectors.

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Recommended value

Non-Loopback

Application scenarios

In commissioning and maintenance stages

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F Parameter Settings

Item

Description

Impact on the system

When the loopback mode is set to Inloop or


Outloop, services are interrupted.

Relevant boards

RPC01 and RPC02

Configuration requirements

None

Item

Description

Parameter description

Used to set the type of services at a client-side


optical interface.

Parameter values

LWX: GE, FE, STM-1, STM-16, OC-3, OC-12,


OC-48, FC-100, FC-200 FICON, FICON
Express, DVB-ASI DVB-SDI, and ESCON

Parameter value description

Default value: Any

Recommended value

None

Application scenarios

In configuration, commissioning, and


maintenance stages

Impact on the system

None

Relevant boards

LWX

Configuration requirements

The type of actually accessed services must be the


same as the type of configured services.
Otherwise, the services are not available.

Service Type

Client Service Bearer Rate (M)

F-10

Item

Description

Parameter description

Used to set the bearer rate of client-side services.

Parameter values(M)

16 to 2500

Parameter value
description

The bearer rate of client-side services can be set only when the
client-side services are of Any type. The set value should equal
to the maximum rate of actually accessed services.

Recommended value

None

Application scenarios

In configuration, commissioning, and maintenance stages

Impact on the system

A SPEED_OVER alarm is reported when the rate of actually


accessed services exceeds the set value.

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F Parameter Settings

Item

Description

Relevant boards

LWX

Configuration
requirements (the set
value of bearer rate
should be the same as the
rate of actually accessed
services)

Actually
accessed
services

Set value
(M)

Actually
accessed
services

Set value (M)

STM-1

155.5

GE

1250

STM-4

622

FE

125

STM-16

2488.3

FC100

1062

OC3

155.5

FC200

2124

OC12

622

FICON

1062

OC48

2488.3

FICON
Express

2124

HDTV

270

ESCON

200

DVB-SDI

270

FDDI

125

DVB-ASI

270

Laser Status

Issue 02 (2009-07-30)

Item

Description

Parameter description

Used to set the laser Open/Close status.

Parameter values

Open and Close


Default value: Open

Parameter value description

Open: The laser is turned on to start transmitting


services.
Close: The laser is turned off to stop service
transmitting.

Recommended value

Open

Application scenarios

In configuration, commissioning, and


maintenance stages

Impact on the system

When the laser is set to Close, services are


interrupted.

Relevant boards

LWX

Configuration requirements

When an optical interface is unused or is not


connected to a fiber, the laser at this interface
should be set to Open.

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F Parameter Settings

Automatic Laser Shutdown


Item

Description

Parameter description

Used to set whether to enable automatic laser


shutdown (ALS) of the downstream laser of the
local board in the case of loss of received signals.
If ALS is enabled, when the received signals are
lost, the laser is automatically shut down and stops
transmitting signals. ALS prolongs the service life
of a laser and avoids personal injury from the laser.

Parameter values

Enabled and Disabled

Parameter value description

By default, ALS of optical interfaces on client


sides is set to Enabled and ALS of optical
interfaces on WDM sides is set to Disabled.

Recommended value

ALS of optical interfaces on client sides is set to


Enabled and ALS of optical interfaces on WDM
sides is set to Disabled.

Application scenarios

In configuration and maintenance stages

Impact on the system

None

Relevant boards

LWX

Configuration requirements

If the optical interface on a WDM side does not


use the ESC as the network management channel
or no fiber is connected, you can set ALS of the
optical interface to Enabled to prolong the service
life of the laser.

Current Bearer Rate (M)

F-12

Item

Description

Parameter description

Used to query the current bearer rate of client-side


services.

Parameter values

Can only be queried

Parameter value description

None

Recommended value

None

Application scenarios

In configuration, commissioning, and


maintenance stages

Impact on the system

None

Relevant boards

LWX

Configuration requirements

None

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F Parameter Settings

Actual Wavelength No./Wavelength (nm)/Frequency (THz)


Item

Description

Parameter description

Used to query the operating wavelength at the


WDM-side optical interface of a board.

Parameter values

Can only be queried

Parameter value description

None

Recommended value

None

Application scenarios

In configuration, commissioning, and


maintenance stages

Impact on the system

None

Relevant boards

LWX

Configuration requirements

None

Actual Band Type


Item

Description

Parameter description

Used to query the band type.

Parameter values

Can only be queried

Parameter value description

None

Recommended value

None

Application scenarios

In commissioning and maintenance stages

Impact on the system

None

Relevant boards

LWX

Configuration requirements

None

Configure Wavelength No./Wavelength (nm)/Frequency (THz)

Issue 02 (2009-07-30)

Item

Description

Parameter description

Used to configure the operating wavelength at the


WDM-side optical interface of a board.

Parameter values

C-band wavelength spacing: 100G


(192.100-196.00 THz)
CWDM-band wavelength spacing: 20 nm
(1271-1611 nm)

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F Parameter Settings

Item

Description

Parameter value description

The operating wavelength of a fixed-wavelength


OTU should be set to the actual wavelength of the
OTU. The operating wavelength of a tunablewavelength OTU should be set according to the
network wavelength planning.

Recommended value

None

Application scenarios

In configuration stage

Impact on the system

The same wavelength should be used for a


service in the receive and transmit directions.

If a service travels through multiple


regenerating stations, it is recommended that
these regenerating sections use the same
wavelength.

It is recommended that the active and standby


channels use the same wavelength when the
inter-board channel protection or client-side
path protection is adopted.

Relevant boards

LWX

Configuration requirements

The configured logic wavelength must be the same


as the actual physical wavelength. Otherwise, a
CFGDATA_OUTRANGE alarm is reported. In
the case of tunable optical modules, issuing the
captioned command directly changes their
physical wavelengths (but does not change the
band). In the case of non-tunable optical modules,
issuing this command changes their logic
wavelengths only.

Configure Band Type

F-14

Item

Description

Parameter description

Used to configure the band type.

Parameter values(dBm)

C and CWDM

Parameter value description

None

Recommended value

None

Application scenarios

In configuration, commissioning, and


maintenance stages

Impact on the system

None

Relevant boards

LWX

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F Parameter Settings

Item

Description

Configuration requirements

The configured logic band must be the same as


the actual physical band. Otherwise, a
CFGDATA_OUTRANGE alarm is reported.

SD Trigger Condition
Item

Description

Parameter description

Used to configure the trigger condition to perform


SD switching on the board.

Parameter values(dBm)

B1_SD, OTUk_DEG, ODUk_PM_DEG, and


None

Parameter value description

B1_SD: Regeneration section (B1) signal


degrade
OTUk_DEG: OTUk signal degrade
ODUk_PM_DEG: ODUk_PM signal degrade
None: No condition is configured for SD
switching.

Recommended value

Set the value to None.

Application scenarios

In commissioning and maintenance stages

Impact on the system

When the B1_SD, OTUk_DEG, or


ODUk_PM_DEG alarm occurs, the protection
group might be triggered to perform protection
switching.

Relevant boards

LWX

Configuration requirements

Set the value to B1_SD, OTUk_DEG, or


ODUk_PM_DEG if the protection mechanism
needs such a trigger condition.

F.5 Optical Amplifier Boards


The parameters that need to be set for the optical amplifier boards include the laser status, board
work type, configure band, configure working band parity, actual band, actual working band
parity, threshold of input power loss, gain, rated optical power, nominal gain upper threshold,
and nominal gain lower threshold.

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Hardware Description

F Parameter Settings

Laser Status
Item

Description

Parameter description

Used to set the laser Open/Close status.

Parameter values

Open and Close


Default value of the OBU1: Open
Default value of the RPC01/RPC02: Close

Recommended value

Close

Application scenarios

In configuration, commissioning, and


maintenance stages

Impact on the system

When the laser is set to Close, services are


interrupted.

Relevant boards

OBU1, RPC01, and RPC02

Configuration requirements

When services are normal, the laser of the optical


amplifying unit should be set to Open.

Board Work Type


Item

Description

Parameter description

Used to query and set the Board Work Type.

Parameter values

C, C+L, and L

Parameter value description

None

Recommended value

Application scenarios

In configuration, commissioning, and


maintenance stages

Impact on the system

None

Relevant boards

RPC01 and RPC02

Configuration requirements

None

Configure Band

F-16

Item

Description

Parameter description

Used to configure the type of the working band of


a board.

Parameter values

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F Parameter Settings

Item

Description

Parameter value description

Supports only C band.

Recommended value

None

Application scenarios

In configuration, commissioning, and


maintenance stages

Impact on the system

None

Relevant boards

OBU1, RPC01, and RPC02

Configuration requirements

None

Configure Working Band Parity


Item

Description

Parameter description

Selects the required parity of the working band.

Parameter values

All, Even, and Odd

Parameter value description

All: All 192.10 THz to 196.05 THz odd and even


wavelengths at 50 GHz channel spacing in C band.
There are 80 wavelengths in total. It is applicable
for the OBU1, RPC01, and PRC02 boards.
Even: All 192.10 THz to 196.00 THz even
wavelengths at 100 GHz channel spacing. There
are 40 wavelengths in total. It is applicable for the
RPC01 and PRC02 boards.
Odd: All 192.15 THz to 196.05 THz odd
wavelengths at 100 GHz channel spacing. There
are 40 wavelengths in total. It is applicable for the
RPC01 and PRC02 boards.

Issue 02 (2009-07-30)

Recommended value

Corresponding wavelengths are used according to


different requirements.

Application scenarios

In commissioning and maintenance stages

Impact on the system

None

Relevant boards

OBU1, RPC01, and RPC02

Configuration requirements

When configuring the parity of wavelengths,


make sure that the parity configured is consistent
with the parity of the actual working wavelengths.

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F Parameter Settings

Actual Band
Item

Description

Parameter description

Used to query the actual working band of the


board.

Parameter values

Can only be queried

Parameter value description

None

Recommended value

None

Application scenarios

In commissioning and maintenance stages

Impact on the system

None

Relevant boards

OBU1

Configuration requirements

None

Actual Working Band Parity


Item

Description

Parameter description

Used to query the parity of the actual working band


of the board.

Parameter values

Can only be queried

Parameter value description

None

Recommended value

None

Application scenarios

In commissioning and maintenance stages

Impact on the system

None

Relevant boards

OBU1, RPC01, and RPC02

Configuration requirements

None

Threshold of Input Power Loss (dBm)

F-18

Item

Description

Parameter description

Indicates the lower threshold of input optical


power loss (an MUT_LOS alarm is reported).

Parameter values

Can only be queried

Parameter value description

The default value varies with the boards and


subjects to the on-site queried result.

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F Parameter Settings

Item

Description

Recommended value

None

Application scenarios

In commissioning and maintenance stages

Impact on the system

None

Relevant boards

OBU1

Configuration requirements

None

Item

Description

Parameter description

Used to query the optical power gain of the current


optical amplifying unit.

Parameter values

Can only be queried

Parameter value description

None

Recommended value

None

Application scenarios

In configuration, commissioning, and


maintenance stages

Impact on the system

None

Relevant boards

OBU1

Configuration requirements

Normally, the queried result should range from the


nominal gain minus 2.5 dB to the nominal gain
plus 2.5 dB.

Gain (dB)

Nominal Gain Upper Threshold (dB)

Issue 02 (2009-07-30)

Item

Description

Parameter description

Used to query the nominal gain upper threshold.

Parameter values

Can only be queried

Parameter value description

None

Recommended value

None

Application scenarios

In commissioning and maintenance stages

Impact on the system

None

Relevant boards

OBU1

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F Parameter Settings

Item

Description

Configuration requirements

None

Nominal Gain Lower Threshold (dB)


Item

Description

Parameter description

Used to query the nominal gain lower threshold.

Parameter values

Can only be queried

Parameter value description

None

Recommended value

None

Application scenarios

In commissioning and maintenance stages

Impact on the system

None

Relevant boards

OBU1

Configuration requirements

None

Rated Optical Power (dBm)


Item

Description

Parameter description

Used to set and query the single-wavelength rated


optical power as the reference value for automatic
optical power adjustment.

Parameter values (dBm)

30.0 to 30.0

Parameter value description

Default value at the input optical interface: 19


dBm
Default value at the output optical interface: 4
dBm

Recommended value

OBUC01: input interface: 20 dBm; output


interface: 0 dBm
OBUC03: input interface: 19 dBm; output
interface: 4 dBm

F-20

Application scenarios

In configuration, commissioning, and


maintenance stages

Impact on the system

None

Relevant boards

OBU1

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F Parameter Settings

Item

Description

Configuration requirements

The rated input and output optical power should


be configured by referring to the actual
configurable input and output range of the optical
amplifying unit and should be the same as the
input and output values measured when the
optical amplifying unit operates normally.

F.6 Cross-Connect and Timing Units


The parameters that need to be set for the cross-connect and timing units include the clock source
parameters and clock subnet parameters.
Table F-5 lists the parameters that need to be set for the cross-connect and timing units.
Table F-5 Parameters that need to be set for the cross-connect and timing units
Domain

Parameter

Value

Configuration

Clock
source
priority

Clock source

The clock sources currently used by


the NE are listed in sequence. The top
clock source is of the highest priority.

External clock
source mode

2 MHz and 2 Mbit/


s

Select the mode only for the input


external clock source.

Synchronous
status byte

Sa4, Sa5, Sa6,


Sa7, and Sa8

Select the synchronous status byte


only for the input external clock
source that is in 2 Mbit/s mode.

AlS alarm
generated

Selected and not


selected

This parameter specifies the


condition for determining the clock
source switching. When an AIS alarm
occurs on an NE, the NE determines
whether to perform the clock source
switching.

B1 BER
thresholdcrossing
generated

Selected and not


selected

This parameter specifies the


condition for determining the clock
source switching. When the B1 BER
on an NE crosses the threshold, the
NE determines whether to perform
the clock source switching.

RLOS, RLOF and


OOF alarms
generated

Selected

When an R_LOS, R_LOF, or OOF


alarm occurs on an NE, the NE
considers that the corresponding
clock source fails.

Clock
source
switching
condition

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F Parameter Settings

F-22

Domain

Parameter

Value

Configuration

Phaselocked
source
output by
external
clock

External clock
output mode
when 2M output
synchronous
source is invalid

Synchronization
quality
unavailable,
output AIS, and
shut off

This parameter is used to set the


operation to be performed by the
system when the output of the
synchronous clock (that is, 2M phaselocked source) fails.

Default value:
Shut off
Output mode of
external clock
source 1

2 Mbit/s and 2
MHz

The NE provides two external clock


outputs. This parameter is used to set
the output mode for external clock
source 1.

Output mode of
external clock
source 2

2 Mbit/s and 2
MHz

The NE provides two external clock


outputs. This parameter is used to set
the output mode for external clock
source 2.

Clock source
threshold

No threshold
value, G.813 SDH
equipment timing
source (SETS)
signal, G.812
local clock signal,
G.812 transit
clock signal, G.
811 clock signal,
and unknown

Set a threshold for the 2M


synchronous output sources. The
threshold is set for the clock
protection function of the S1 byte.
The NE clock system uses this
threshold as the basis for ensuring the
quality of the output clock. If a clock
is of a quality higher than the
threshold, the clock system transmits
clock signals.

Clock
source
switching

Lock status

Lockout and
unlock

This parameter is used to set whether


the clock source switching is allowed.

Switching
operation

Forced switching,
manual switching,
and clear
switching

This parameter specifies the


switching operation to be performed
on the clock source.

Clock
source
reversion
parameter

Higher priority
clock source
reversion mode

Auto-revertive
and non-revertive

When the clock source of a higher


priority degrades, the NE
automatically switches to the clock
source of a lower priority. When this
parameter is set to "Auto-revertive",
the NE automatically switches back
to the clock source of a higher priority
when the clock source of the higher
priority is restored. When this
parameter is set to "Non-revertive",
the NE does not automatically switch
back to the clock source of a higher
priority when the clock source of the
higher priority is restored.

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Domain

Parameter

Value

Configuration

Clock source
WTR time

0 to 12 minutes

This parameter is used to set the


period from the time when the
recovery of the clock is detected to
the time when the clock selector
responds. This setting prevents
repeated switching from occurring in
the case of unstable signals.

Affiliated subnet

Default value: 0

This parameter is used to set the


subnet ID.

Protection status

Start extended
SSM protocol,
start standard
SSM protocol, and
stop SSM protocol

This parameter specifies whether to


start up the SSM protocol.

Clock source ID

1 to 15

Huawei equipment uses the first four


bits of the S1 byte to identify the
clock source. Hence, the subnet clock
source ID is the four bits.

SSM
output
control

Line port

All the line ports


of the current NE

This parameter displays the line ports


that can be controlled.

Control status

Enabled and
disabled

This parameter specifies whether the


line port allows the output of the
quality information carried by the S1
byte. Generally, set this parameter to
"Disabled" at edges of a network to
prevent impact on the other
equipment.

Clock
quality

Configuration
quality

Unknown
synchronization
quality, G.811
clock signal, G.
812 transit clock
signal, G.812
local clock signal,
G.813 SDH
equipment timing
source (SETS)
signal, do not use
for
synchronization,
and automatic
extraction
Default value:
Automatic
extraction

This parameter is used to set the clock


quality. Specify the clock quality of
the clock source listed in the priority
table. If an option other than
"Automatic extraction" is selected,
the NE considers the specified clock
quality (other than the actual clock
quality) as the criteria.

Clock
subnet

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F Parameter Settings

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F Parameter Settings

Domain

Clock ID
status

F-24

Parameter

Value

Configuration

Clock quality

Unknown
synchronization
quality, G.811
clock signal, G.
812 transit clock
signal, G.812
local clock signal,
G.813 SDH
equipment timing
source (SETS)
signal, do not use
for
synchronization,
and automatic
extraction

The clock source quality information


actually received by the NE is
extracted by the NE from the S1 byte
of each clock source. When the
customer queries the actual clock
quality and the NE successfully
returns the result, the quality can be
displayed. Otherwise, it displays "no
information".

Line port

All the line ports


of the current NE

This parameter displays the line ports


that can be configured with the clock
ID.

Enabled status

Enabled and
disabled
Default value:
Enabled

This parameter specifies whether to


enable the setting of the clock ID.

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G Glossary

Glossary

This document defines the following terms:


1
1:N protection

A 1:N protection architecture has N normal traffic signals, N


working SNCs/trails and one protection SNC/trail. It may have
one extra traffic signal.

1+1 protection

A 1+1 protection architecture has one normal traffic signal, one


working SNC/trail, one protection SNC/trail and a permanent
bridge.

100BASE-TX

Physical Layer specification for a 100 Mbit/s CSMA/CD local


area network over two pairs of Category 5 unshielded twistedpair (UTP) or shielded twisted-pair (STP) wire.

10BASE-T

Physical Layer specification for a 10 Mb/s CSMA/CD local area


network over two pairs of twisted-pair telephone wire.

19-inch cabinet

A cabinet which is 19 inches in width and 600mm in depth,


compliant with the standards of the IEC297.

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Add/Drop Multiplexer

A multiplexer capable of extracting and inserting lower-rate


signals from a higher-rate multiplexed signal without
completely demultiplexing the signal.

ADM

add/drop multiplexer. see add/drop multiplexer.

Administrator

A user who has authority to access all the Management Domains


of the EML Core product. He has access to the whole network
and to all the management functionalities.

AIS

Alarm Indication Signal. A signal sent downstream in a digital


network if an upstream failure has been detected and persists for
a certain time.

Alarm cable

The cable which is used to transmit alarm signals.

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G Glossary

Alarm

A visible or an audible indication to notify the person concerned


that a failure or an emergency has occurred. See also Event.

AMI

Alternate Mark Inversion. The line-coding format in


transmission systems where successive ones (marks) are
alternatively inverted (sent with polarity opposite that of the
preceding mark).

APD

Avalanche Photodiode. A semiconductor photodetector with


integral detection and amplification stages. Electrons generated
at a p/n junction are accelerated in a region where they free an
avalanche of other electrons. APDs can detect faint signals but
require higher voltages than other semiconductor electronics.

Asynchronous

A network where transmission system payloads are not


synchronized and each network terminal runs on its own clock.

ATM

Asynchronous Transfer Mode. A transfer mode in which the


information is organized into cells. It is asynchronous in the
sense that the recurrence of cells containing information from
an individual user is not necessarily periodic. It is a protocol
within the OSI layer 1. An ATM cell consists of a 5 octet header
followed by 48 octets of data.

Attenuation

Reduction of signal magnitude or signal loss, usually expressed


in decibels.

Attenuator

A passive component that attenuates an electrical or optical


signal.

Attribute

Property of an object.

ATPC

Automatic Transmit Power Control. A method of automatically


adjusting the transmit power at the opposite end based on the
transmit signal detected at the receiver.

AU

administrative unit. see administrative unit

Auto-negotiation

The rate/work mode of the communication party set as selfnegotiation is specified through negotiation according to the
transmission rate of the opposite party.

G-2

Back up

A method to copy the important data into a backing storage in


case that the original is damaged or corrupted.

Backplane

A PCB circuit board in the subrack, which is connected with all


the boards in position.

Bandwidth

Information-carrying capacity of a communication channel.


Analog bandwidth is the range of signal frequencies that can be
transmitted by a communication channel or network.

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G Glossary

BITS

Building Integrated Timing Supply. A building timing supply


that minimises the number of synchronization links entering an
office. Sometimes referred to as a synchronization supply unit.

Board Version
Replacement Function

A function that enables a board supporting several board IDs.


Generally, a board of an old version is used to the NE also of an
old version, which does not support the board of a new version.
When a board of a new version is used to replace a board of an
old version, the former should work with the ID of the board of
the old version. The board of a new version works on the NE of
a new version with the ID of the board of new version. In this
way, the board of the new version has several board IDs.

Bridge

The action of transmitting identical traffic (SPE contents) on


both the working and protection channels.

Broadcast

The act of sending a frame addressed to all stations on the


network

Issue 02 (2009-07-30)

Cable tie

The tape used to bind the cables.

CBR

Constant Bit Rate. The Constant Bit Rate service category is


used by connections that request a static amount of bandwidth
that is continuously available during the connection lifetime.
This amount of bandwidth is characterized by a peak cell Rate
(PCR) value.

CDVT

Cell Delay Variation Tolerance. Information sent in the forward


and backward direction to determine the upper bound of the
tolerance admitted for the time interval between cells pertaining
to a given cell flow. The backward CDVT values included in
the IAM and MOD shall be interpreted as maximum acceptable
values for the cell flow in the backward direction.

Channel spacing

The center to center difference in frequency or wavelength


between adjacent channels in a WDM device.

Channel

The smallest subdivision of a circuit that provides a type of


communication service; usually a path with only one direction.

Circuit

A communications path or network; usually a pair of channels


providing bi-directional communication.

Client

A kind of terminal (PC or workstation) connected to a network


that can send instructions to a server and get results through a
user interface. See also server.

Coded Mark Inversion

This is the STS-3 line code. This is a two level non-return to


zero code. A binary 1 is coded by either of the amplitude levels,
+A or -A, for one full unit time interval (T) in such a way that
the level alternates for successive binary ones. For a binary zero
there is always a positive transition (-A to +A) at the mid point
of the binary unit interval (T/2).

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G Glossary

Configuration data

The data that configures the NE hardware for coordination


between this NE and other NEs in the entire network, and for
operation of specified services. Configuration data is the
instruction file of NEs, and it is a key element to ensure that the
network runs efficiently. The typical configuration data includes
board configuration, clock configuration and protection
relationship.

Configure

To set the basic parameters of an operation object.

Connection

A "transport entity" which consists of an associated pair of


"unidirectional connections" capable of simultaneously
transferring information in opposite directions between their
respective inputs and outputs.

Convergence

The process of developing a model of the echo path which will


be used in the echo estimator to produce the estimate of the
circuit echo.

Conversion

In the context of message handling, a transmittal event in which


an MTA transforms parts of a message content from one
encoded information type to another, or alters a probe so it
appears that the described messages were so modified.

Cyclic Redundancy
Check

A technique for using overhead bits to detect transmission


errors.

G-4

DDF

Digital Distribution Frame. A frame which is used to transfer


cables.

Dense Wavelength
Division Multiplexing

The higher capacity version of WDM, which is a means of


increasing the capacity of fiber-optic data transmission systems
through the multiplexing of multiple wavelengths of light.
Commercially available DWDM systems support the
multiplexing of from 8 to 40 wavelengths of light.

Drop

The port on a network element where the service to an end


customer may be connected, e.g., a tributary card on a SONET
ADM. For example, a drop for a DS1 customer service may be
provided by a VT1.5 card terminating a VT1.5 trail.

Dual-Fed

A description of a ring that has entry nodes that add traffic to


the ring via the bridging function.

DWDM

Dense Wavelength Division Multiplexing. The technology


utilizes the characteristics of broad bandwidth and low
attenuation of single mode optical fiber, employs multiple
wavelengths with specific frequency spacing as carriers, and
allows multiple channels to transmit simultaneously in the same
fiber.

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G Glossary

E
E13

A function used to multiplex E1 signals into E3 signals or to


demultiplex E3 signals into E1 signals.

ECC

Embedded Control Channel. An ECC provides a logical


operations channel between SDH NEs, utilizing a data
communications channel (DCC) as its physical layer.

EDFA

Erbium-Doped Fiber Amplifier. The optical amplifier that its


fiber doped with the rare earth element erbium, which can
amplify at 1530 to 1610 nm when the optical amplifier is
pumped by an external light source.

Ejector lever

A component at the two ends of the front panel of a board, which


is used for inserting or removing the board.

Encapsulation

In 1000BASE-X, the process by which a MAC packet is


enclosed within a PCS code-group stream

EPL

Ethernet Private Line. An EPL service is a point-to-point


interconnection between two UNIs without SDH bandwidth
sharing. Transport bandwidth is never shared between different
customers.

ESCON

Enterprise System Connection. A path protocol which connects


the host with various control units in an storage system. It is a
serial bit stream transmission protocol. The transmission rate is
200 Mbit/s.

ESD jack

Electrostatic discharge jack. A hole in the cabinet or subrack,


which connect the subrack or cabinet to the insertion of ESD
wrist strap.

ESD

Electrostatic Discharge. The phenomena the energy being


produced by electrostatic resource discharge instantly.

Ethernet

A data link level protocol comprising the OSI model's bottom


two layers. It is a broadcast networking technology that can use
several different physical media, including twisted pair cable
and coaxial cable. Ethernet usually uses CSMA/CD. TCP/IP is
commonly used with Ethernet networks.

ETSI

European Telecommunications Standards Institute

EVPL

Ethernet Virtual Private Line. An EVPL service is a service that


is both a line service and a virtual private service.

Eye pattern

A graphic presentation formed by the superimposition of the


waveforms of all possible pulse sequences.

F
Fan tray assembly

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A module which contains fans used for heat dissipation.

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G Glossary

Fault

A fault is the inability of a function to perform a required action.


This does not include an inability due to preventive
maintenance, lack of external resources, or planned actions.

FC

Fiber Channel. A standard of data storage network for


transmitting signals at 100 Mbit/s to 4.25Gbit/s over fiber or (at
slow speeds) copper.

FD

Frequency Diversity. Two or more microwave frequencies with


certain frequency space are used to transmit/receive the same
signal and selection is then performed between the two signals
to ease the impact of fading.

Fiber connector

A device mounted on the end of a fiber-optic cable, light source,


receiver, or housing that mates to a similar device to couple light
into and out of optical fibers. A connector joins two fiber ends,
or one fiber end and a light source or detector.

Fiber jumper

The fiber which is used to connect the subrack with the ODF.

FICON

Fibre Connect. A new generation connection protocol which


connects the host with various control units. It carries single byte
command protocol through the physical path of fiber channel,
and provides higher rate and better performance than ESCON.

Flow

An aggregation of packets that have the same characteristics.


On the T2000 or NE software, flow is a group of classification
rules. On boards, it is a group of packets that have the same
quality of service (QoS) operation. At present, two flows are
supported: port flow and port + VLAN flow. Port flow is based
on port ID and port + VLAN flow is based on port ID and VLAN
ID. The two flows cannot coexist in the same port.

Frame

A cyclic set of consecutive time slots in which the relative


position of each time slot can be identified.

Free-run mode

An operating condition of a clock, the output signal of which is


strongly influenced by the oscillating element and not controlled
by servo phase-locking techniques. In this mode the clock has
never had a network reference input, or the clock has lost
external reference and has no access to stored data, that could
be acquired from a previously connected external reference.
Free-run begins when the clock output no longer reflects the
influence of a connected external reference, or transition from
it. Free-run terminates when the clock output has achieved lock
to an external reference.

Full duplex

Pertaining to both parties that can send and receive data at the
same time on the communication link.

G-6

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G Glossary

Gain

The ratio between the optical power from the input optical
interface of the optical amplifier and the optical power from the
output optical interface of the jumper fiber, which expressed in
dB.

Grooming

Consolidating or segregating traffic for efficiency.

Guide rail

A groove in the subrack, which ensures the correct connection


of a board to the backplane.

H
Half duplex

Pertaining to, both parties that only one party can send data,
while the other party can only receive data on the
communication link.

HSB

Hot Standby.

I
IMA frame

The IMA frame is used as the unit of control in the IMA protocol.
It is a logical frame defined as M consecutive cells, numbered
0 to M-l, transmitted on each of the N links in an IMA group.

IMA

Inverse Multiplexing for ATM. The ATM inverse multiplexing


technique involves inverse multiplexing and de-multiplexing of
ATM cells in a cyclical fashion among links grouped to form a
higher bandwidth logical link whose rate is approximately the
sum of the link rates. This is referred to as an IMA group.

Interface board area

The area for the interface boards on the subrack.

Isolation

A nonreciprocal optical device intended to suppress backward


reflections along an optical fiber transmission line while having
minimum insertion loss in the forward direction.

J
Jitter

Short waveform variations caused by vibration, voltage


fluctuations, control system instability, etc.

Issue 02 (2009-07-30)

Label

A mark on a cable, a subrack, or a cabinet for identification.

Laser

The device that generates the directional light covering a narrow


range of wavelengths. Laser light is more coherent than ordinary
light. Semiconductor diode lasers are the used light source in
fiber-optic system.

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G Glossary

Layer

A concept used to allow the transport network functionality to


be described hierarchically as successive levels; each layer
being solely concerned with the generation and transfer of its
characteristic information.

LCAS

Link Capacity Adjustment Scheme. A solution features flexible


bandwidth and dynamic adjustment. In addition, it provides a
failure tolerance mechanism, which enhances the viability of
virtual concatenations and enables the dynamic adjustment to
bandwidth (non-service affecting).

Link

A "topological component" that provides transport capacity


between two endpoints in different subnetworks via a fixed (i.e.,
inflexible routing) relationship. The endpoints are "subnetwork
termination point pools" for SONET, and link termination
points for ATM. Multiple links may exist between a pair of
subnetworks. A link also represents a set of "link connections".

Loopback

The fault of each path on the optical fiber can be located by


setting loopback for each path of the line. There are three kinds
of loopback modes: No loopback, Outloop, Inloop.

Lower subrack

The subrack close to the bottom of the cabinet when a cabinet


contains several subracks.

G-8

M13

A function used to multiplex T1 signals into T3 signals or to


demultiplex T3 signals into T1 signals.

MAC

Media Access Control. The data link sublayer that is responsible


for transferring data to and from the Physical Layer.

Mapping

A procedure by which tributaries are adapted into virtual


containers at the boundary of an SDH network.

Mean launched power

The average power of a pseudo-random data sequence coupled


into the fiber by the transmitter.

Mounting ear

A component on the side of a subrack, which is used to install


the subrack in a cabinet.

MPLS

Multiprotocol Label Switching. Multi-protocol label switching.


It is a standard routing and switching technology platform,
capable of supporting various high level protocols and services.
The data transmission over an MPLS network is independent of
route calculating. MPLS, as a connection-oriented transmission
technology, guarantees QoS effectively, supports various
network level technologies, and is independent of the link layer.

MSP

The MSP function provides capability for switching a signal


between and including two MST functions, from a working to
a protection channel.

Multicast

Transmission of a frame to stations specified by a group address.

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G Glossary

Multiplex section
protection

A function provides capability for switching a signal between


and including two MST functions, from a working to a
protection channel.

Multiplex

To transmit two or more signals over a single channel.

Multiplexer

An equipment which combines a number of tributary channels


onto a fewer number of aggregate bearer channels, the
relationship between the tributary and aggregate channels being
fixed.

Multiplexing

A procedure by which multiple lower order path layer signals


are adapted into a higher order path or the multiple higher order
path layer signals are adapted into a multiplex section.

N
NNI

Network Node Interface. NNI identifies the interface between


the ATM network nodes. Compare SDH NNI.

Noise figure

The specification to scale the random signal in the system


presenting in addition to any wanted signal.

Non-revertive

In non-revertive mode, when a protection switch occurs, the


working service will be switched to the protection service and
the status will remain after it returns normal.

NRZ

Non Return to Zero. A digital code in which the signal level is


low for a 0 bit and high for a 1 bit and dose not return to 0
between successive 1 bits.

Issue 02 (2009-07-30)

OADM

Optical Add/Drop Multiplexer. A device that can be used to add


the optical signals of various wavelengths to one channel and
drop the optical signals of various wavelengths from one
channel.

ODF

Optical Distribution Frame. A frame which is used to transfer


and spool fibers.

ODU

Outdoor Unit. The outdoor unit implements frequency


conversion and amplification for RF signals.

ONE

Optical Network Element. A stand-alone physical entity in an


optical transmission network that supports at least network
element functions.

Optical add/drop
multiplexing

A process that add the optical signals of various wavelengths to


one channel and drop the optical signals of various wavelengths
from one channel.

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OptiX OSN 3500 II Intelligent Optical Transmission System


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G Glossary

Optical Amplifier

A device or subsystem in which optical signals can be amplified


by means of stimulated emission taking place in an suitable
active medium. It is used to amplify the optical signal of the
optical transmission system.

Optical connector

A component normally attached to an optical cable or piece of


apparatus for the purpose of providing frequent optical
interconnection/disconnection of optical fibers or cables.

Optical interface

A device to allow two or more corresponding optical


transmitting units to be connected.

OTM

Optical Terminal Multiplexer. A device that multiplex or


demultiplex optical signals into a transmission link or into the
client side.

OTU

Optical Transponder Unit. A device that access service signals


compliant with standards at the client side and convert them into
standard DWDM or CWDM wavelengths.

Output optical power

The ranger of optical energy level of output signals.

Overhead

Extra bits in a digital stream used to carry information besides


traffic signals. Orderwire, for example, would be considered
overhead information.

G-10

Packing case

A case which is used for packing the board or subrack.

Paired Slots

Two slots of which the overheads can be passed through by


using the bus on the backplane. When the SCC unit is faulty or
offline, the overheads can be passed through between the paired
slots by using the directly connected overhead bus. When two
SDH boards form an MSP ring, the boards need to be inserted
in paired slots so that the K bytes can be passed through.

Pass-Through

The action of transmitting by a node exactly what is received by


that node for any given direction of transmission. A passthrough can be unidirectional or bidirectional. For BLSRs, a
pass-through refers to the K1 and the K2 bytes and the protection
channels. Three types of pass-through are used in BLSRs: K
byte pass through, unidirectional full pass-through, and
bidirectional full pass-through.

Path protection

The working principle of path protection: When the system


works in path protection mode, the PDH path uses the dual-fed
and signal selection mode. Through the tributary unit and crossconnect unit, the tributary signal is sent simultaneously to the
east and west lines. Meanwhile, the cross-connect matrix sends
the signal dually sent from the opposite end to the tributary board
through the active and standby buses, and the hardware of the
tributary board automatically and selectively receive the signal
from the two groups of buses automatically according to the AIS
number of the lower order path.

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Hardware Description

G Glossary

Path

A logical connection between the point at which a standard


frame format for the signal at the given rate is assembled, and
the point at which the standard frame format for the signal is
disassembled.

PCR

Peak Cell Rate. An upper limit on the rate at which cells can be
submitted on an ATM connection.

PDH

Plesiochronous Digital Hierarchy. PDH is the digital


networking hierarchy that was used before the advent of Sonet/
SDH.

PIN

Photodiode. A semiconductor detector with an intrinsic (i)


region separating the p- and n-doped regions. It has fast linear
response and is used in fiber-optic receivers.

Plesiochronous

A network with nodes timed by separate clock sources with


almost the same timing.

Pointer

An indicator whose value defines the frame offset of a virtual


container with respect to the frame reference of the transport
entity on which it is supported.

Power unit

A direct current power distribution unit at the upper part of a


cabinet, which supplies power for the subracks in the cabinet.

PRBS

When there are cross-connections between a line board and a


tributary/data board, many alarms are raised on the tributary/
data board if alarms are raised on the line board. These alarms
are all reported to the T2000. Such a large number of alarms can
disturb the troubleshooting and affect the problem solution
efficiency. Therefore, the inter-board alarm suppression
function is used to solve this problem.

Private line

Both communication parties are connected permanently.

Procedure

A generic term for an action.

Process

A generic term for a collection of actions.

Processing board area

An area for the processing boards on the subrack.

Provisioning

The process of making available various telecommunications


resources (such as switching systems and transport facilities) for
telecommunication services. Provisioning includes forecasting
the demand for services, determining the additions or changes
to the network that will be needed, determining where and when
they will be needed, and installing all the necessary network
elements to provide such services.

Pseudo wire

A mechanism that bears the simulated services between PEs on


the network.

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Hardware Description

G Glossary

Receiver overload

Receiver overload is the maximum acceptable value of the


received average power at point R to achieve a 1 x 10-10 BER.

Receiver sensitivity

Receiver sensitivity is defined as the minimum acceptable value


of average received power at point R to achieve a 1 x 10-10 BER.

Reference clock

A clock of very high stability and accuracy that may be


completely autonomous and whose frequency serves as a basis
of comparison for the frequency of other clocks.

REG

A device that performs regeneration.

Regeneration

The process of receiving and reconstructing a digital signal so


that the amplitudes, waveforms and timing of its signal elements
are constrained within specified limits.

Revertive switching

In revertive switching, there is a working and protection line,


board and so on. Services always revert back to the original
working line or board if the switch requests are terminated; that
is, when the working line or board has recovered from the fault
or the external request is cleared.

RPR

Resilient Packet Ring. A metropolitan area network (MAN)


technology supporting data transfer among stations
interconnected in a dual-ring configuration.

RS232

In the asynchronous transfer mode and there is no hand-shaking


signal. It can communicate with RS232 and RS422 of other
stations in point-to-point mode and the transmission is
transparent. Its highest speed is 19.2 kbit/s.

G-12

S1 byte

The byte defined in ITU-T to transmit the network


synchronization status information.

SAN

Storage Area Network. A dedicated high-speed data storage


network which interconnects multiple independent storage
systems with multiple servers through fiber path switch or other
switch equipment.

SD

Space Diversity. Two or more antennas separated by a specific


distance transmit/receive the same signal and selection is then
performed between the two signals to ease the impact of fading.
Currently, only receive SD is used.

SDH

Synchronous Digital Hierarchy. A hierarchical set of digital


transport structures, standardized for the transport of suitably
adapted payloads over physical transmission networks.

Section

The portion of a SONET transmission facility, including


terminating points, between (i) a terminal network element and
a regenerator or (ii) two regenerators. A terminating point is the
point after signal regeneration at which performance monitoring
is (or may be) done.

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Hardware Description

G Glossary

Settings

Parameters of an operation that can be selected by the user.

SF

Signal fail. See signal fail.

SFP

Small form-factor pluggable. See small form-factor pluggable.

Side mode suppression


ratio

The ratio of the largest peak of the total source spectrum to the
second largest peak.

Side panel

The panel on the side of the cabinet.

Signal cable

The cable which is used to transmit electrical signals, different


from the power cable or fiber.

Signal fail

A signal indicating the associated data has failed in the sense


that a near-end defect condition (not being the degraded defect)
is active.

SNCP

SubNetwork Connection Protection. A working subnetwork


connection is replaced by a protection subnetwork connection
if the working subnetwork connection fails, or if its performance
falls below a required level.

SNCMP

Subnetwork Connection Multi-protection. The source


broadcasts services to multiple paths, and the sink determines
which service to receive according to the service priority and
then the service quality.

SNCTP

Subnetwork Connection Tunnel Protection. It provides


protection paths at the VC-4 level. When the working path is
faulty, all services in the working path are switched to the
protection path.

Span

The set of SONET lines between two adjacent nodes on a ring.

SSM

Synchronization Status Message. ITU-T defines S1 byte to


transmit the network synchronization status information. It uses
the lower four bits of the multiplex section overhead S1 byte to
indicate 16 types of synchronization quality grades.

Synchronous

A network where transmission system payloads are


synchronized to a master (network) clock and traced to a
reference clock.

T
T2000

Issue 02 (2009-07-30)

The T2000 is a subnet management system (SNMS). In the


telecommunication management network architecture, the
T2000 is located between the NE level and network level, which
can supports all NE level functions and part of the network level
management functions. See also NM.

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OptiX OSN 3500 II Intelligent Optical Transmission System


Hardware Description

G Glossary

TCM

Tandem Connection Monitor. In the SDH transport hierarchy,


the TCM is located between the AU/TU management layer and
HP/LP layer. It uses the N1/N2 byte of POH overhead to monitor
the quality of the transport channels on a transmission section
(TCM section).

TPS

Tributary Protection Switching. A function provided by the


equipment, is intended to protect N tributary processing boards
through a standby tributary processing board.

Tray

A discal component in the cabinet, which is used to place the


chassis or other equipment.

Tributary loopback

A fault location method. A fault can be located for each service


path by performing loopback on each path of the tributary board.
There are three types of loopback modes: Non-loopback,
Outloop and Inloop.

TUG

Tributary unit group. See tributary unit group.

U
Upload

To report all or part of the configuration data of the NE to the


T2000 and overwrite the configuration data saved in the NE
layer on the T2000.

Upper subrack

The subrack close to the top of the cabinet when a cabinet


contains several subracks.

V
VC

virtual container. see virtual container.

Virtual concatenation

The payload whose transmission bandwidth is bigger than VC4.


Virtual concatenation combines multiple VC4 payloads
(successive or non-successive) to form a virtual large structure
VC4-Xv in cascade mode for transmission. The transmission of
the broadband cascaded payload is implemented via the virtual
cascade, thus improving the SDH transmission payload
bandwidth capability from VC4 to VC4-4C.

VLAN

Virtual local area network. A subset of the active topology of a


Bridged Local Area Network. Associated with each VLAN is a
VLAN Identifier (VID).

VPN

Virtual Private Network. Enables IP service to be transmitted


securely over a public TCP/IP network by encrypting all service
from one network to another.

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Wavelength Division
Multiplexing

Issue 02 (2009-07-30)

G Glossary

A means of increasing the capacity of fiber-optic data


transmission systems through the multiplexing of multiple
wavelengths of light. WDM systems support the multiplexing
of as many as four wavelengths.

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Hardware Description

H Acronyms and Abbreviations

Acronyms and Abbreviations

A
ADM

Add/Drop Multiplexer

AMI

Alternate Mark Inversion

APS

Automatic Protection Switching

ATM

Asynchronous Transfer Mode

ATPC

Automatic Transmit Power Control

B
BITS

Building Integrated Timing Supply

C
CAR

Committed Access Rate

CBR

Constant Bit Rate

CC

Continuity Check

CMI

Coded Mark Inversion

COA

Case-shaped Optical Amplifier

CPU

Central Processing Unit

CRC

Cyclic Redundancy Check

Issue 02 (2009-07-30)

DC

Direct Current

DCC

Data Communication Channel

DCE

Data Circuit-terminal Equipment


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H Acronyms and Abbreviations

OptiX OSN 3500 II Intelligent Optical Transmission System


Hardware Description

DCU

Dispersion Compensation Unit

DDF

Digital Distribution Frame

DTR

Data Terminal Ready

DVB-ASI

Digital Video Broadcast-Asynchronous Serial Interface

DWDM

Dense Wavelength Division Multiplexing

E
ECC

Embedded Control Channel

EDFA

Erbium-Doped Fiber Amplifier

EMC

Electromagnetic Compatibility

EMI

Electromagnetic Interference

EPL

Ethernet Private Line

EPLAN

Ethernet Private LAN

ESCON

Enterprise Systems Connection

ETS

European Telecommunication Standards

ETSI

European Telecommunications Standards Institute

EVPL

Ethernet Virtual Private Line

EVPLAN

Ethernet Virtual Private LAN

F
FC

Fiber Channel

FD

Frequency Diversity

FE

Fast Ethernet

FEC

Forward Error Correction

FICON

Fiber Connection

FPGA

Field Programmable Gate Array

G
GE

Gigabit Ethernet

GFP

Generic Framing Procedure

H-2

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Hardware Description

H Acronyms and Abbreviations

HDB3

High Density Bipolar of order 3 code

HDLC

High level Data Link Control

HSB

Hot Standby

I
IEEE

Institute of Electrical and Electronics Engineers

IF

Intermediate Frequency

IS-IS

Intermediate System-Intermediate System

ITU-T

International Telecommunication Union - Telecommunication


Standardization Sector

L
LAPS

Link Access Procedure-SDH

LB

Loopback

LCAS

Link Capacity Adjustment Scheme

LCT

Local Craft Terminal

M
MPLS

Multi-Protocol Label Switch

MSP

Multiplex Section Protection

MLM

Multi-Longitudinal Mode

N
NA

Not Applicable

NRZ

Non Return to Zero

O
OAM

Operation Administration and Maintenance

ODU

Outdoor Unit

OSPF

Open Shortest Path First

P
PA
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Power Amplifier
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H Acronyms and Abbreviations

OptiX OSN 3500 II Intelligent Optical Transmission System


Hardware Description

PDH

Plesiochronous Digital Hierarchy

PRBS

Pseudo-Random Binary Sequence

PW

Pseudo Wire

R
RAM

Random-Access Memory

RD

Receive Data

RIP

Routing Information Protocol

RSTP

Rapid Spanning Tree Protocol

S
SD

Space Diversity

SDH

Synchronous Digital Hierarchy

SG

Signaling Ground

SLM

Single-Longitudinal Mode

SNCP

Sub-Network Connection Protection

SNCMP

Subnetwork Connection Multi-Protection

SNCTP

Subnetwork Connection Tunnel Protection

SSM

Synchronization Status Message

T
TD

Transmit Data

TPS

Tributary Protection Switching

U
UBR

Unspecified Bit Rate

UPM

Uninterruptible Power Module

H-4

VBR

Variable Bit Rate

VLAN

Virtual Local Area Network

VPN

Virtual Private Network

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H Acronyms and Abbreviations

W
WDM

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Wavelength Division Multiplexing

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