Beruflich Dokumente
Kultur Dokumente
SLAS491A AUGUST 2005 REVISED OCTOBER 2005
D
D
D
D
D
D
D
D
D
D Brownout Detector
D Serial Onboard Programming,
D
D
D
D
Product Preview
description
The Texas Instruments MSP430 family of ultralow power microcontrollers consist of several devices featuring
different sets of peripherals targeted for various applications. The architecture, combined with five low power
modes is optimized to achieve extended battery life in portable measurement applications. The device features
a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that attribute to maximum code efficiency.
The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 1s.
The MSP430x20xx series is an ultralow-power mixed signal microcontroller with a built-in 16-bit timer, and ten
I/O pins. In addition the MSP430x20x1 has a versatile analog comparator. The MSP430x20x2 and
MSP430x20x3 have built-in communication capability using synchronous protocols (SPI or I2C), and a 10-bit
A/D converter (MSP430x20x2) or a 16-bit sigma-delta A/D converter (MSP430x20x3).
Typical applications include sensor systems that capture analog signals, convert them to digital values, and then
process the data for display or for transmission to a host system. Stand alone RF sensor front end is another
area of application.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SLAS491A AUGUST 2005 REVISED OCTOBER 2005
AVAILABLE OPTIONS
PACKAGED DEVICES
PLASTIC
14-PIN TSSOP
(PW)
PLASTIC
14-PIN DIP
(N)
PLASTIC
16-PIN QFN
(RSA)
MSP430F2001IPW
MSP430F2011IPW
MSP430F2002IPW
MSP430F2012IPW
MSP430F2003IPW
MSP430F2013IPW
MSP430F2001IN
MSP430F2011IN
MSP430F2002IN
MSP430F2012IN
MSP430F2003IN
MSP430F2013IN
MSP430F2001IRSA
MSP430F2011IRSA
MSP430F2002IRSA
MSP430F2012IRSA
MSP430F2003IRSA
MSP430F2013IRSA
TA
40C to 85C
Product Preview
14
13
VSS
XIN/P2.6/TA1
P1.1/TA0/CA1
12
XOUT/P2.7
P1.2/TA1/CA2
11
TEST/SBWTCK
P1.3/CAOUT/CA3
10
P1.4/SMCLK/CA4/TCK
P1.5/TA0/CA5/TMS
RST/NMI/SBWTDIO
P1.7/CAOUT/CA7/TDO/TDI
P1.6/TA1/CA6/TDI/TCLK
NC
VSS
15 14
11
XOUT/P2.7
P1.2/TA1/CA2
10
TEST/SBWTCK
P1.3/CAOUT/CA3
9
P1.7/CAOUT/CA7/TDO/TDI
P1.1/TA0/CA1
P1.6/TA1/CA6/TDI/TCLK
XIN/P2.6/TA1
P1.5/TA0/CA5/TMS
12
P1.0/TACLK/ACLK/CA0
P1.4/SMCLK/CA4/TCK
2
NC
VCC
RSA PACKAGE
(TOP VIEW)
RST/NMI/SBWTDIO
SLAS491A AUGUST 2005 REVISED OCTOBER 2005
14
13
VSS
XIN/P2.6/TA1
P1.1/TA0/A1
12
XOUT/P2.7
P1.2/TA1/A2
11
TEST/SBWTCK
P1.3/ADC10CLK/A3/VREF/VeREF
10
P1.4/SMCLK/A4/VREF+/VeREF+/TCK
P1.5/TA0/A5/SCLK/TMS
RST/NMI/SBWTDIO
P1.7/A7/SDI/SDA/TDO/TDI
P1.6/TA1/A6/SDO/SCL/TDI/TCLK
15 14
AVSS
DVSS
AVCC
DVCC
RSA PACKAGE
(TOP VIEW)
11
XOUT/P2.7
P1.2/TA1/A2
10
TEST/SBWTCK
P1.3/ADC10CLK/A3/VREF/VeREF
RST/NMI/SBWTDIO
P1.7/A7/SDI/SDA/TDO/TDI
P1.4/SMCLK/A4/VREF+/VeREF+/TCK
P1.1/TA0/A1
P1.6/TA1/A6/SDO/SCL/TDI/TCLK
XIN/P2.6/TA1
P1.5/TA0/A5/SCLK/TMS
12
P1.0/TACLK/ACLK/A0
SLAS491A AUGUST 2005 REVISED OCTOBER 2005
14
13
VSS
XIN/P2.6/TA1
P1.1/TA0/A0/A4+
12
XOUT/P2.7
P1.2/TA1/A1+/A4
11
TEST/SBWTCK
P1.3/VREF/A1
10
P1.4/SMCLK/A2+/TCK
P1.5/TA0/A2/SCLK/TMS
RST/NMI/SBWTDIO
P1.7/A3/SDI/SDA/TDO/TDI
P1.6/TA1/A3+/SDO/SCL/TDI/TCLK
AVSS
DVSS
15 14
11
XOUT/P2.7
P1.2/TA1/A1+/A4
10
TEST/SBWTCK
P1.3/VREF/A1
P1.7/A3/SDI/SDA/TDO/TDI
P1.1/TA0/A0/A4+
P1.5/TA0/A2/SCLK/TMS
XIN/P2.6/TA1
P1.6/TA1/A3+/SDO/SCL/TDI/TCLK
12
P1.0/TACLK/ACLK/A0+
P1.4/SMCLK/A2+/TCK
4
AVCC
DVCC
RSA PACKAGE
(TOP VIEW)
RST/NMI/SBWTDIO
SLAS491A AUGUST 2005 REVISED OCTOBER 2005
VSS
P2.x &
XIN/XOUT
2
XOUT
XIN
Basic Clock
System+
ACLK
SMCLK
MCLK
Flash
RAM
2kB
1kB
128B
128B
Comparator
_A+
8 channel
input mux
Port P1
Port P2
8 I/O
Interrupt
capability,
pullup/down
resistors
2 I/O
Interrupt
capability,
pullup/down
resistors
MAB
16MHz
CPU
incl. 16
Registers
MDB
Emulation
(2BP)
JTAG
Interface
Watchdog
WDT+
Brownout
Protection
15/16Bit
Timer_A2
2 CC
Registers
SpyBi Wire
RST/NMI
VSS
P2.x &
XIN/XOUT
2
XOUT
XIN
Basic Clock
System+
ADC10
ACLK
SMCLK
MCLK
16MHz
CPU
incl. 16
Registers
Flash
RAM
2kB
1kB
128B
128B
10bit
8 Channels
Autoscan
DTC
Port P1
Port P2
8 I/O
Interrupt
capability,
pullup/down
resistors
2 I/O
Interrupt
capability,
pullup/down
resistors
MAB
MDB
Emulation
(2BP)
JTAG
Interface
USI
Watchdog
WDT+
Brownout
Protection
15/16Bit
Timer_A2
2 CC
Registers
SpyBi Wire
Universal
Serial
Interface
SPI, I2C
RST/NMI
SLAS491A AUGUST 2005 REVISED OCTOBER 2005
VSS
XOUT
XIN
Basic Clock
System+
16MHz
CPU
incl. 16
Registers
Port P1
Port P2
8 I/O
Interrupt
capability,
pullup/down
resistors
2 I/O
Interrupt
capability,
pullup/down
resistors
SD16_A
ACLK
SMCLK
MCLK
Flash
RAM
2kB
1kB
128B
128B
16bit
Sigma
Delta A/D
Converter
MAB
MDB
Emulation
(2BP)
JTAG
Interface
USI
Watchdog
WDT+
Brownout
Protection
15/16Bit
Timer_A2
2 CC
Registers
SpyBi Wire
RST/NMI
P2.x &
XIN/XOUT
2
Universal
Serial
Interface
SPI, I2C
SLAS491A AUGUST 2005 REVISED OCTOBER 2005
RSA
NO.
NO.
P1.0/TACLK/ACLK/CA0
I/O
P1.1/TA0/CA1
I/O
P1.2/TA1/CA2
I/O
P1.3/CAOUT/CA3
I/O
P1.4/SMCLK/C4/TCK
I/O
P1.5/TA0/CA5/TMS
I/O
P1.6/TA1/CA6/TDI/TCLK
I/O
P1.7/CAOUT/CA7/TDO/TDI
I/O
XIN/P2.6/TA1
13
12
I/O
XOUT/P2.7
12
11
I/O
RST/NMI/SBWTDIO
10
TEST/SBWTCK
11
10
Selects test mode for JTAG pins on Port1. The device protection fuse is
connected to TEST.
Spy-Bi-Wire test clock input during programming and test
VCC
VSS
16
Supply voltage
14
14
Ground reference
NC
NA
13, 15
QFN Pad
NA
Package
Pad
NAME
DESCRIPTION
I/O
Not connected
NA
SLAS491A AUGUST 2005 REVISED OCTOBER 2005
RSA
NO.
NO.
P1.0/TACLK/ACLK/A0
I/O
P1.1/TA0/A1
I/O
P1.2/TA1/A2
I/O
P1.3/ADC10CLK/
A3/VREF/VeREF
I/O
P1.4/SMCLK/A4/VREF+/VeREF+/
TCK
I/O
P1.5/TA0/A5/SCLK/TMS
I/O
P1.6/TA1/A6/SDO/SCL/TDI/TCLK
I/O
P1.7/A7/SDI/SDA/TDO/TDI
I/O
XIN/P2.6/TA1
13
12
I/O
XOUT/P2.7
12
11
I/O
RST/NMI/SBWTDIO
10
TEST/SBWTCK
11
10
Selects test mode for JTAG pins on Port1. The device protection fuse is
connected to TEST.
Spy-Bi-Wire test clock input during programming and test
VCC
VSS
NA
Supply voltage
14
NA
Ground reference
NAME
DESCRIPTION
I/O
SLAS491A AUGUST 2005 REVISED OCTOBER 2005
RSA
NO.
NO.
DVCC
NA
16
AVCC
DVSS
NA
15
NA
14
AVSS
QFN Pad
NA
13
NA
Package
Pad
NAME
DESCRIPTION
I/O
RSA
NO.
NO.
P1.0/TACLK/ACLK/A0+
I/O
P1.1/TA0/A0/A4+
I/O
P1.2/TA1/A1+/A4
I/O
P1.3/VREF/A1
I/O
P1.4/SMCLK/A2+/TCK
I/O
P1.5/TA0/A2/SCLK/TMS
I/O
P1.6/TA1/A3+/SDO/SCL/TDI/TCLK
I/O
P1.7/A3/SDI/SDA/TDO/TDI
I/O
NAME
DESCRIPTION
I/O
SLAS491A AUGUST 2005 REVISED OCTOBER 2005
RSA
NO.
NO.
XIN/P2.6/TA1
13
12
I/O
XOUT/P2.7
12
11
I/O
RST/NMI/SBWTDIO
10
TEST/SBWTCK
11
10
Selects test mode for JTAG pins on Port1. The device protection fuse is
connected to TEST.
Spy-Bi-Wire test clock input during programming and test
VCC
VSS
NA
Supply voltage
14
NA
Ground reference
DVCC
NA
16
AVCC
DVSS
NA
15
NA
14
AVSS
QFN Pad
NA
13
NA
Package
Pad
NAME
DESCRIPTION
I/O
NA
10
SLAS491A AUGUST 2005 REVISED OCTOBER 2005
short-form description
CPU
The MSP430 CPU has a 16-bit RISC architecture
that is highly transparent to the application. All
operations, other than program-flow instructions,
are performed as register operations in
conjunction with seven addressing modes for
source operand and four addressing modes for
destination operand.
Program Counter
PC/R0
Stack Pointer
SP/R1
SR/CG1/R2
Status Register
Constant Generator
CG2/R3
General-Purpose Register
R4
General-Purpose Register
R5
General-Purpose Register
R6
General-Purpose Register
R7
General-Purpose Register
R8
General-Purpose Register
R9
General-Purpose Register
R10
General-Purpose Register
R11
General-Purpose Register
R12
General-Purpose Register
R13
General-Purpose Register
R14
General-Purpose Register
R15
R4 + R5 > R5
e.g. CALL
PC >(TOS), R8> PC
e.g. JNE
R8
Jump-on-equal bit = 0
S D
SYNTAX
EXAMPLE
OPERATION
Register
F F
MOV Rs,Rd
MOV R10,R11
Indexed
F F
MOV X(Rn),Y(Rm)
MOV 2(R5),6(R6)
F F
MOV EDE,TONI
Absolute
F F
MOV &MEM,&TCDAT
R10
> R11
M(2+R5)> M(6+R6)
Indirect
MOV @Rn,Y(Rm)
MOV @R10,Tab(R6)
Indirect
autoincrement
MOV @Rn+,Rm
MOV @R10+,R11
MOV #X,TONI
MOV #45,TONI
Immediate
NOTE: S = source
#45
> M(TONI)
D = destination
11
SLAS491A AUGUST 2005 REVISED OCTOBER 2005
operating modes
The MSP430 has one active mode and five software selectable low-power modes of operation. An interrupt
event can wake up the device from any of the five low-power modes, service the request and restore back to
the low-power mode on return from the interrupt program.
The following six operating modes can be configured by software:
CPU is disabled
ACLK and SMCLK remain active. MCLK is disabled
CPU is disabled
ACLK and SMCLK remain active. MCLK is disabled
DCOs dc-generator is disabled if DCO not used in active mode
CPU is disabled
MCLK and SMCLK are disabled
DCOs dc-generator remains enabled
ACLK remains active
CPU is disabled
MCLK and SMCLK are disabled
DCOs dc-generator is disabled
ACLK remains active
12
CPU is disabled
ACLK is disabled
MCLK and SMCLK are disabled
DCOs dc-generator is disabled
Crystal oscillator is stopped
SLAS491A AUGUST 2005 REVISED OCTOBER 2005
INTERRUPT FLAG
SYSTEM INTERRUPT
WORD ADDRESS
PRIORITY
Power-up
External reset
Watchdog Timer+
Flash key violation
PC out-of-range (see Note 1)
PORIFG
RSTIFG
WDTIFG
KEYV
(see Note 2)
Reset
0FFFEh
31, highest
NMI
Oscillator fault
Flash memory access violation
NMIIFG
OFIFG
ACCVIFG
(see Notes 2 & 4)
(non)-maskable,
(non)-maskable,
(non)-maskable
0FFFCh
30
0FFFAh
29
0FFF8h
28
maskable
0FFF6h
27
Watchdog Timer+
WDTIFG
maskable
0FFF4h
26
Timer_A2
maskable
0FFF2h
25
Timer_A2
TACCR1 CCIFG.
TAIFG (see Notes 2 & 3)
maskable
0FFF0h
24
0FFEEh
23
0FFECh
22
0FFEAh
21
maskable
SD16CCTL0 SD16OVIFG,
SD16CCTL0 SD16IFG
(see Notes 2 & 3)
maskable
USI
(MSP430x20x2, MSP430x20x3 only)
USIIFG, USISTTIFG
(see Notes 2 & 3)
maskable
0FFE8h
20
I/O Port P2
(two flags)
P2IFG.6 to P2IFG.7
(see Notes 2 & 3)
maskable
0FFE6h
19
I/O Port P1
(eight flags)
P1IFG.0 to P1IFG.7
(see Notes 2 & 3)
maskable
0FFE4h
18
0FFE2h
17
0FFE0h
16
15 ... 0, lowest
(see Note 5)
NOTES: 1.
2.
3.
4.
5.
A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h01FFh).
Multiple source flags
Interrupt flags are located in the module
(non)-maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt enable cannot.
The interrupt vectors at addresses 0FFDEh to 0FFC0h are not used in this device and can be used for regular program code if
necessary.
13
SLAS491A AUGUST 2005 REVISED OCTOBER 2005
0h
ACCVIE
NMIIE
rw-0
WDTIE:
OFIE:
NMIIE:
ACCVIE:
Address
1
OFIE
rw-0
0
WDTIE
rw-0
rw-0
Watchdog Timer interrupt enable. Inactive if watchdog mode is selected. Active if Watchdog Timer
is configured in interval timer mode.
Oscillator fault enable
(Non)maskable interrupt enable
Flash access violation interrupt enable
7
01h
02h
NMIIFG
RSTIFG
PORIFG
OFIFG
rw-0
WDTIFG:
OFIFG:
RSTIFG:
PORIFG:
NMIIFG:
Address
rw-(0)
rw:
rw-0,1:
rw-(0,1):
14
rw-(0)
Set on Watchdog Timer overflow (in watchdog mode) or security key violation.
Reset on VCC power-up or a reset condition at RST/NMI pin in reset mode.
Flag set on oscillator fault
External reset interrupt flag. Set on a reset condition at RST/NMI pin in reset mode. Reset on VCC
power-up
Power-On Reset interrupt flag. Set on VCC power-up.
Set via RST/NMI-pin
03h
Legend
rw-1
rw-(1)
0
WDTIFG
SLAS491A AUGUST 2005 REVISED OCTOBER 2005
memory organization
MSP430F200x
MSP430F201x
Memory
Main: interrupt vector
Main: code memory
Size
Flash
Flash
1KB Flash
0FFFFh0FFC0h
0FFFFh0FC00h
2KB Flash
0FFFFh0FFC0h
0FFFFh0F800h
Information memory
Size
Flash
256 Byte
010FFh 01000h
256 Byte
010FFh 01000h
Size
128 Byte
027Fh 0200h
128 Byte
027Fh 0200h
16-bit
8-bit
8-bit SFR
01FFh 0100h
0FFh 010h
0Fh 00h
01FFh 0100h
0FFh 010h
0Fh 00h
RAM
Peripherals
flash memory
The flash memory can be programmed via the Spy-Bi-Wire/JTAG port, or in-system by the CPU. The CPU can
perform single-byte and single-word writes to the flash memory. Features of the flash memory include:
D Flash memory has n segments of main memory and four segments of information memory (A to D) of 64
bytes each. Each segment in main memory is 512 bytes in size.
D Segments 0 to n may be erased in one step, or each segment may be individually erased.
D Segments A to D can be erased individually, or as a group with segments 0n.
Segments A to D are also called information memory.
D Segment A contains calibration data. After reset segment A is protected against programming and erasing.
It can be unlocked but care should be taken not to erase this segment if the device-specific calibration data
is required.
15
SLAS491A AUGUST 2005 REVISED OCTOBER 2005
peripherals
Peripherals are connected to the CPU through data, address, and control busses and can be handled using
all instructions. For complete module descriptions, refer to the MSP430x2xx Family Users Guide.
D Auxiliary clock (ACLK), sourced either from a 32768-Hz watch crystal or the internal LF oscillator.
D Main clock (MCLK), the system clock used by the CPU.
D Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules.
DCO Calibration Data (provided from factory in flash info memory segment A)
DCO Frequency
Calibration Register
Size
1 MHz
CALBC1_1MHz
byte
010FFh
CALDCO_1MHz
byte
010FEh
8 MHz
12 MHz
16 MHz
Address
CALBC1_8MHz
byte
010FDh
CALDCO_8MHz
byte
010FCh
CALBC1_12MHz
byte
010FBh
CALDCO_12MHz
byte
010FAh
CALBC1_16MHz
byte
010F9h
CALDCO_16MHz
byte
010F8h
brownout
The brownout circuit is implemented to provide the proper internal reset signal to the device during power on
and power off.
digital I/O
There is one 8-bit I/O port implementedport P1and two bits of I/O port P2:
D
D
D
D
D
16
SLAS491A AUGUST 2005 REVISED OCTOBER 2005
timer_A2
Timer_A2 is a 16-bit timer/counter with two capture/compare registers. Timer_A2 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_A2 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
Timer_A2 Signal Connections (MSP43020x1 only)
Input
Pin Number
PW, N
RSA
2 - P1.0
1 - P1.0
Device
Input Signal
Module
Input Name
TACLK
TACLK
ACLK
ACLK
SMCLK
SMCLK
Module
Block
Timer
Module
Output Signal
Output
Pin Number
PW, N
RSA
NA
2 - P1.0
1 - P1.0
TACLK
INCLK
3 - P1.1
2 - P1.1
TA0
CCI0A
3 - P1.1
2 - P1.1
ACLK (internal)
CCI0B
7 - P1.5
6 - P1.5
4 - P1.2
3 - P1.2
4 - P1.2
3 - P1.2
VSS
VCC
TA1
GND
VCC
CCI1A
CAOUT (internal)
CCI1B
VSS
VCC
GND
CCR0
CCR1
TA0
TA1
8 - P1.6
7 - P1.6
13 - P2.6
12 - P2.6
VCC
RSA
2 - P1.0
1 - P1.0
Device
Input Signal
Module
Input Name
TACLK
TACLK
ACLK
ACLK
SMCLK
SMCLK
TACLK
INCLK
Module
Block
Timer
Module
Output Signal
Output
Pin Number
PW, N
RSA
NA
2 - P1.0
1 - P1.0
3 - P1.1
2 - P1.1
TA0
CCI0A
3 - P1.1
2 - P1.1
7 - P1.5
6 - P1.5
ACLK (internal)
CCI0B
7 - P1.5
6 - P1.5
VSS
VCC
GND
4 - P1.2
3 - P1.2
4 - P1.2
3 - P1.2
8 - P1.6
7 - P1.6
TA1
VCC
CCI1A
TA1
CCI1B
VSS
VCC
GND
CCR0
CCR1
TA0
TA1
8 - P1.6
7 - P1.6
13 - P2.6
12 - P2.6
VCC
17
SLAS491A AUGUST 2005 REVISED OCTOBER 2005
18
SLAS491A AUGUST 2005 REVISED OCTOBER 2005
ADC control 0
ADC control 1
ADC memory
ADC10CTL0
ADC10CTL0
ADC10MEM
01B0h
01B2h
01B4h
General Control
Channel 0 Control
Interrupt vector word register
Channel 0 conversion memory
SD16CTL
SD16CCTL0
SD16IV
SD16MEM0
0100h
0102h
0110h
0112h
Timer_A
Capture/compare register
Capture/compare register
Timer_A register
Capture/compare control
Capture/compare control
Timer_A control
Timer_A interrupt vector
TACCR1
TACCR0
TAR
TACCTL1
TACCTL0
TACTL
TAIV
0174h
0172h
0170h
0164h
0162h
0160h
012Eh
Flash Memory
Flash control 3
Flash control 2
Flash control 1
FCTL3
FCTL2
FCTL1
012Ch
012Ah
0128h
Watchdog Timer+
Watchdog/timer control
WDTCTL
0120h
Analog enable
ADC10AE
04Ah
SD16INCTL0
SD16AE
0B0h
0B7h
USI
(MSP430x20x2 and
MSP430x20x3 only)
USI control 0
USI control 1
USI clock control
USI bit counter
USI shift register
USICTL0
USICTL1
USICKCTL
USICNT
USISR
078h
079h
07Ah
07Bh
07Ch
Comparator_A+
(MSP430x20x1 only)
CAPD
CACTL2
CACTL1
05Bh
05Ah
059h
BCSCTL3
BCSCTL2
BCSCTL1
DCOCTL
053h
058h
057h
056h
Port P2
P2REN
P2SEL
P2IE
P2IES
P2IFG
P2DIR
P2OUT
P2IN
02Fh
02Eh
02Dh
02Ch
02Bh
02Ah
029h
028h
Port P1
P1REN
P1SEL
P1IE
P1IES
P1IFG
P1DIR
P1OUT
P1IN
027h
026h
025h
024h
023h
022h
021h
020h
Special Function
IFG2
IFG1
IE2
IE1
003h
002h
001h
000h
19
SLAS491A AUGUST 2005 REVISED OCTOBER 2005
NOM
MAX
UNITS
1.8
3.6
2.2
3.6
40
85
VCC = 1.8 V,
Duty Cycle = 50% 10%
dc
VCC = 2.7 V,
Duty Cycle = 50% 10%
dc
12
VCC 3.3 V,
Duty Cycle = 50% 10%
dc
16
MHz
16 MHz
12 MHz
6 MHz
1.8 V
2.2 V
2.7 V
3.3 V
Legend:
3.6 V
Supply Voltage V
NOTE: Minimum processor frequency is defined by system clock. Flash program or erase operations require a minimum VCC of 2.2 V.
20
SLAS491A AUGUST 2005 REVISED OCTOBER 2005
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
active mode supply current (into VCC) excluding external current (see Notes 1 and 2)
PARAMETER
IAM, 1MHz
IAM, 1MHz
IAM, 4kHz
IAM,100kHz
TEST CONDITIONS
VCC
MIN
TYP
MAX
2.2 V
220
270
3V
300
370
2.2 V
190
UNIT
3V
260
2.2 V
1.2
3V
1.6
2.2 V
37
50
3V
40
55
NOTES: 1. All inputs are tied to 0 V or VCC. Outputs do not source or sink any current.
2. The currents are characterized with a Micro Crystal CC4VT1A SMD cyrstal with a load capacitance of 9 pF.
The internal and external load capacitance is chosen to closely match the required 9pF.
fDCO = 16 MHz
4.0
5.0
3.0
fDCO = 12 MHz
2.0
1.0
fDCO = 8 MHz
TA = 25 C
2.0
2.0
2.5
3.0
3.5
4.0
TA = 25 C
1.0
VCC = 2.2 V
0.0
0.0
VCC = 3 V
TA = 85 C
fDCO = 1 MHz
0.0
1.5
TA = 85 C
3.0
4.0
8.0
12.0
16.0
21
SLAS491A AUGUST 2005 REVISED OCTOBER 2005
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
low power mode supply currents (into VCC) excluding external current (see Notes 1 and 2)
PARAMETER
TEST CONDITIONS
VCC
Low-power mode
0 (LPM0) current,
see Note 3
fMCLK = 0MHz,
fSMCLK = fDCO = 1MHz,
fACLK = 32,768Hz,
BCSCTL1 = CALBC1_1MHz,
DCOCTL = CALDCO_1MHz,
CPUOFF = 1, SCG0 = 0, SCG1 = 0, OSCOFF = 0
Low-power mode
ILPM0,100kHz 0 (LPM0) current,
see Note 3
fMCLK = 0MHz,
fSMCLK = fDCO(0, 0) 100kHz,
fACLK = 0Hz,
RSELx = 0, DCOx = 0,
CPUOFF = 1, SCG0 = 0, SCG1 = 0, OSCOFF = 1
Low-power mode
1 (LPM2) current,
see Note 4
ILPM0, 1MHz
ILPM2
Low-power mode
3 (LPM3) current,
ILPM3,LFXT1
see Note 4
ILPM3,VLO
ILPM4
Low-power mode
3 current, (LPM3)
see Note 4
Low-power mode
4 (LPM4) current,
see Note 5
TA = 40C
TA = 25C
2.2 V
TA = 40C
TA = 25C
TA = 85C
65
80
85
100
2.2 V
37
48
3V
41
52
2.2 V
22
29
3V
25
32
0.7
1.2
0.7
1.0
1.4
2.3
0.9
1.2
0.9
1.2
1.6
2.8
0.4
0.7
0.5
0.7
1.0
1.6
0.5
0.9
0.6
0.9
1.3
1.8
0.1
0.5
0.1
0.5
0.8
1.5
2.2 V
3V
2.2 V
3V
2.2 V/3 V
NOTES: 1. All inputs are tied to 0 V or VCC. Outputs do not source or sink any current.
2. The currents are characterized with a Micro Crystal CC4VT1A SMD crystal with a load capacitance of 9 pF.
The internal and external load capacitance is chosen to closely match the required 9pF.
3. Current for brownout and WDT clocked by SMCLK included.
4. Current for brownout and WDT clocked by ACLK included.
5. Current for brownout included.
22
UNIT
TA = 40C
TA = 25C
MAX
3V
TA = 85C
TA = 40C
TA = 25C
TA = 85C
TYP
TA = 85C
TA = 40C
TA = 25C
TA = 85C
MIN
SLAS491A AUGUST 2005 REVISED OCTOBER 2005
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
Schmitt-trigger inputs Ports P1 and P2
PARAMETER
VIT+
VIT
TEST CONDITIONS
Vhys
RPull
Pull-up/pull-down resistor
CI
Input Capacitance
VCC
MIN
TYP
MAX
UNIT
VCC
0.45
0.75
2.2 V
1.00
1.65
3V
1.35
2.25
0.25
0.55
2.2 V
0.55
1.20
3V
0.75
1.65
2.2 V
0.2
1.0
3V
0.3
1.0
20
35
50
V
VCC
V
V
kW
pF
TEST CONDITIONS
Port P1, P2: P1.x to P2.x, External
trigger puls width to set interrupt
flag, (see Note 1)
VCC
2.2 V/3 V
MIN
TYP
MAX
20
UNIT
ns
NOTES: 1. An external signal sets the interrupt flag every time the minimum interrupt puls width t(int) is met. It may be set even with trigger signals
shorter than t(int).
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
Ilkg(Px.x)
High-impedance leakage current
see Notes 1 and 2
2.2 V/3 V
50
nA
NOTES: 1. The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted.
2. The leakage of the digital port pins is measured individually. The port pin is selected for input and the pull-up/pull-down resistor is
disabled.
23
SLAS491A AUGUST 2005 REVISED OCTOBER 2005
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
outputs Ports P1 and P2
PARAMETER
VOH
VOL
High-level output
voltage
Low-level output
voltage
TEST CONDITIONS
VCC
MIN
2.2 V
VCC0.25
VCC0.6
VCC
VCC
3V
VCC0.25
VCC0.6
VCC
VCC
VSS+0.25
VSS+0.6
VSS+0.25
2.2 V
3V
2.2 V
2.2 V
VSS
VSS
3V
VSS
TYP
MAX
UNIT
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
2.2 V
10
MHz
3V
12
MHz
P2.0/ACLK, P1.4/SMCLK, CL = 20 pF
(see Note 2)
2.2 V
12
MHz
3V
16
MHz
NOTES: 1. A resistive divider with 2 times 0.5 kW between VCC and VSS is used as load. The output is connected to the center tap of the divider.
2. The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency.
24
SLAS491A AUGUST 2005 REVISED OCTOBER 2005
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
typical characteristics outputs
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
VCC = 2.2 V
P1.7
TA = 25C
25.0
TA = 85C
20.0
15.0
10.0
5.0
0.0
0.0
0.5
1.0
1.5
2.0
30.0
VCC = 3 V
P1.7
40.0
TA = 85C
30.0
20.0
10.0
0.0
0.0
2.5
0.5
1.5
2.0
2.5
3.0
3.5
Figure 5
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
0.0
I OH Typical High-Level Output Current mA
1.0
Figure 4
VCC = 2.2 V
P1.7
5.0
10.0
15.0
TA = 85C
20.0
25.0
0.0
TA = 25C
TA = 25C
0.5
1.0
1.5
2.0
2.5
VCC = 3 V
P1.7
10.0
20.0
30.0
TA = 85C
40.0
TA = 25C
50.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
Figure 6
Figure 7
25
SLAS491A AUGUST 2005 REVISED OCTOBER 2005
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
POR/brownout reset (BOR) (see Notes 1 and 2)
PARAMETER
TEST CONDITIONS
VCC(start)
(see Figure 8)
dVCC/dt 3 V/s
V(B_IT)
Vhys(B_IT)
dVCC/dt 3 V/s
dVCC/dt 3 V/s
td(BOR)
(see Figure 8)
t(reset)
(see Figure 8)
VCC
MIN
TYP
MAX
0.7 V(B_IT)
70
2.2 V/3 V
130
UNIT
V
1.71
180
mV
2000
s
s
NOTES: 1. The current consumption of the brownout module is already included in the ICC current consumption data. The voltage level V(B_IT)
+ Vhys(B_IT) is 1.8V.
2. During power up, the CPU begins code execution following a period of td(BOR) after VCC = V(B_IT) + Vhys(B_IT). The default
DCO settings must not be changed until VCC VCC(min), where VCC(min) is the minimum supply voltage for the desired
operating frequency.
VCC
Vhys(B_IT)
V(B_IT)
VCC(start)
0
t d(BOR)
26
SLAS491A AUGUST 2005 REVISED OCTOBER 2005
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
typical characteristics POR/brownout reset (BOR)
VCC
3V
VCC(drop) V
VCC = 3 V
Typical Conditions
t pw
1.5
1
VCC(drop)
0.5
0
0.001
1000
1 ns
1 ns
tpw Pulse Width s
Figure 9. VCC(drop) Level With a Square Voltage Drop to Generate a POR/Brownout Signal
VCC
VCC(drop) V
2
1.5
t pw
3V
VCC = 3 V
Typical Conditions
1
VCC(drop)
0.5
0
0.001
tf = tr
1
1000
tf
tr
Figure 10. VCC(drop) Level With a Triangle Voltage Drop to Generate a POR/Brownout Signal
27
SLAS491A AUGUST 2005 REVISED OCTOBER 2005
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
main DCO characteristics
D All ranges selected by RSELx overlap with RSELx + 1: RSELx = 0 overlaps RSELx = 1, ... RSELx = 14
overlaps RSELx = 15.
D DCO control bits DCOx have a step size as defined by parameter SDCO.
D Modulation control bits MODx select how often fDCO(RSEL,DCO+1) is used within the period of 32 DCOCLK
cycles. The frequency fDCO(RSEL,DCO) is used for the remaining cycles. The frequency is an average equal
to:
f average +
MOD
32 f DCO(RSEL,DCO) f DCO(RSEL,DCO)1)
f DCO(RSEL,DCO))(32*MOD) f DCO(RSEL,DCO)1)
DCO frequency
PARAMETER
Vcc
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
RSELx < 14
1.8
3.6
RSELx = 14
2.2
3.6
RSELx = 15
3.0
3.6
fDCO(0,0)
fDCO(0,3)
2.2 V/3 V
0.06
0.14
MHz
2.2 V/3 V
0.07
0.17
MHz
fDCO(1,3)
fDCO(2,3)
2.2 V/3 V
0.10
0.20
MHz
2.2 V/3 V
0.14
0.28
MHz
fDCO(3,3)
fDCO(4,3)
2.2 V/3 V
0.20
0.40
MHz
2.2 V/3 V
0.28
0.54
MHz
fDCO(5,3)
fDCO(6,3)
2.2 V/3 V
0.39
0.77
MHz
2.2 V/3 V
0.54
1.06
MHz
fDCO(7,3)
fDCO(8,3)
2.2 V/3 V
0.80
1.50
MHz
2.2 V/3 V
1.10
2.10
MHz
fDCO(9,3)
fDCO(10,3)
2.2 V/3 V
1.60
3.00
MHz
2.2 V/3 V
2.50
4.30
MHz
fDCO(11,3)
fDCO(12,3)
2.2 V/3 V
3.00
5.50
MHz
2.2 V/3 V
4.30
7.30
MHz
fDCO(13,3)
fDCO(14,3)
2.2 V/3 V
6.00
9.60
MHz
2.2 V/3 V
8.60
13.9
MHz
fDCO(15,3)
fDCO(15,7)
3V
12.0
18.5
MHz
3V
16.0
26.0
MHz
SRSEL
SRSEL
f =
/fDCO(RSEL,DCO)
DCO(RSEL+1,DCO)
2.2 V/3 V
SDCO
SDCO
f=
/fDCO(RSEL,DCO)
DCO(RSEL,DCO+1)
2.2 V/3 V
1.05
1.08
1.12
Measured at P1.4/SMCLK
2.2 V/3 V
40
50
60
Duty Cycle
28
1.55
ratio
SLAS491A AUGUST 2005 REVISED OCTOBER 2005
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
calibrated DCO frequencies tolerance at calibration
PARAMETER
TEST CONDITIONS
TA
25C
VCC
MIN
TYP
MAX
UNIT
3V
0.2
+1
25C
3V
0.990
1.010
MHz
fCAL(1MHz)
BCSCTL1= CALBC1_1MHz;
DCOCTL = CALDCO_1MHz
Gating time: 5ms
fCAL(8MHz)
BCSCTL1= CALBC1_8MHz;
DCOCTL = CALDCO_8MHz
Gating time: 5ms
25C
3V
7.920
8.080
MHz
fCAL(12MHz)
BCSCTL1= CALBC1_12MHz;
DCOCTL = CALDCO_12MHz
Gating time: 5ms
25C
3V
11.88
12
12.12
MHz
fCAL(16MHz)
BCSCTL1= CALBC1_16MHz;
DCOCTL = CALDCO_16MHz
Gating time: 2ms
25C
3V
15.84
16
16.16
MHz
VCC
MIN
MAX
UNIT
TA
0C +85C
3.0 V
2.5
0.5
+2.5
0C +85C
3.0 V
2.5
1.0
+2.5
0C +85C
3.0 V
2.5
1.0
+2.5
0C +85C
3.0 V
3.0
2.0
+3.0
2.2 V
0.970
1.030
MHz
3.0 V
0.975
1.025
MHz
3.6 V
0.970
1.030
MHz
2.2 V
7.760
8.400
MHz
3.0 V
7.800
8.200
MHz
3.6 V
7.600
8.240
MHz
2.2 V
11.70
12
12.30
MHz
3.0 V
11.70
12
12.30
MHz
3.6 V
11.70
12
12.30
MHz
3.0 V
15.52
16
16.48
MHz
3.6 V
15.00
16
16.48
MHz
fCAL(1MHz)
fCAL(8MHz)
fCAL(12MHz)
fCAL(16MHz)
TEST CONDITIONS
BCSCTL1= CALBC1_1MHz;
DCOCTL = CALDCO_1MHz
Gating time: 5ms
BCSCTL1= CALBC1_8MHz;
DCOCTL = CALDCO_8MHz
Gating time: 5ms
0C
0
C +85
+85C
C
0C
0
C +85
+85C
C
BCSCTL1= CALBC1_12MHz;
DCOCTL = CALDCO_12MHz
Gating time: 5ms
0C
0
C +85
+85C
C
BCSCTL1= CALBC1_16MHz;
DCOCTL = CALDCO_16MHz
Gating time: 2ms
0C +85C
TYP
29
SLAS491A AUGUST 2005 REVISED OCTOBER 2005
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
calibrated DCO frequencies tolerance over supply voltage VCC
PARAMETER
TEST CONDITIONS
TA
25C
VCC
MIN
TYP
MAX
UNIT
1.8 V 3.6 V
2.5
+2.5
25C
1.8 V 3.6 V
2.5
+2.5
25C
2.2 V 3.6 V
2.5
+2.5
25C
3.0 V 3.6 V
+3
25C
1.8 V 3.6 V
0.970
1.030
MHz
fCAL(1MHz)
BCSCTL1= CALBC1_1MHz;
DCOCTL = CALDCO_1MHz
Gating time: 5ms
fCAL(8MHz)
BCSCTL1= CALBC1_8MHz;
DCOCTL = CALDCO_8MHz
Gating time: 5ms
25C
1.8 V 3.6 V
7.760
8.240
MHz
fCAL(12MHz)
BCSCTL1= CALBC1_12MHz;
DCOCTL = CALDCO_12MHz
Gating time: 5ms
25C
2.2 V 3.6 V
11.64
12
12.36
MHz
fCAL(16MHz)
BCSCTL1= CALBC1_16MHz;
DCOCTL = CALDCO_16MHz
Gating time: 2ms
25C
3.0 V 3.6 V
15.00
16
16.48
MHz
VCC
MIN
MAX
UNIT
TA
40C +85C
1.8 V 3.6 V
+5
40C +85C
1.8 V 3.6 V
+5
40C +85C
2.2 V 3.6 V
+5
40C +85C
3.0 V 3.6 V
+6
40C +85C
1.8 V 3.6 V
0.950
1.050
MHz
TEST CONDITIONS
TYP
fCAL(1MHz)
BCSCTL1= CALBC1_1MHz;
DCOCTL = CALDCO_1MHz
Gating time: 5ms
fCAL(8MHz)
BCSCTL1= CALBC1_8MHz;
DCOCTL = CALDCO_8MHz
Gating time: 5ms
40C +85C
1.8 V 3.6 V
7.600
8.400
MHz
fCAL(12MHz)
BCSCTL1= CALBC1_12MHz;
DCOCTL = CALDCO_12MHz
Gating time: 5ms
40C +85C
2.2 V 3.6 V
11.40
12
12.60
MHz
fCAL(16MHz)
BCSCTL1= CALBC1_16MHz;
DCOCTL = CALDCO_16MHz
Gating time: 2ms
40C +85C
3.0 V 3.6 V
15.00
16
17.00
MHz
30
SLAS491A AUGUST 2005 REVISED OCTOBER 2005
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
typical characteristics calibrated 1MHz DCO frequency
1.03
1.02
VCC = 1.8 V
Frequency MHz
1.01
VCC = 2.2 V
1.00
VCC = 3.0 V
0.99
VCC = 3.6 V
0.98
0.97
50.0
25.0
0.0
25.0
50.0
75.0
100.0
TA Temperature C
Frequency MHz
1.02
1.01
TA = 85 C
1.00
TA = 25 C
0.99
TA = 40 C
0.98
0.97
1.5
2.0
2.5
3.0
3.5
4.0
31
SLAS491A AUGUST 2005 REVISED OCTOBER 2005
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
wake-up from lower power modes (LPM3/4)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
BCSCTL1= CALBC1_1MHz;
DCOCTL = CALDCO_1MHz
2.2 V/3 V
BCSCTL1= CALBC1_8MHz;
DCOCTL = CALDCO_8MHz
2.2 V/3 V
1.5
BCSCTL1= CALBC1_12MHz;
DCOCTL = CALDCO_12MHz
2.2 V/3 V
BCSCTL1= CALBC1_16MHz;
DCOCTL = CALDCO_16MHz
3V
UNIT
ss
1/fMCLK +
tClock,LPM3/4
NOTES: 1. The DCO clock wake-up time is measured from the edge of an external wake-up signal (e.g. port interrupt) to the first clock edge
observable externally on a clock pin (MCLK or SMCLK).
2. Parameter applicable only if DCOCLK is used for MCLK.
tCPU,LPM3/4
10.00
RSELx = 0...11
RSELx = 12...15
1.00
0.10
0.10
1.00
10.00
32
SLAS491A AUGUST 2005 REVISED OCTOBER 2005
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
crystal oscillator, LFXT1, low frequency modes (see Note 4)
PARAMETER
fLFXT1,LF
OALF
CL,eff
TEST CONDITIONS
VCC
XTS = 0, LFXT1Sx = 0 or 1
1.8 V 3.6 V
XTS = 0, LFXT1Sx = 3
1.8 V 3.6 V
MIN
TYP
MAX
32,768
10,000
XTS = 0, LFXT1Sx = 0;
fLFXT1,LF = 32,768 kHz,
CL,eff = 6 pF
XTS = 0, LFXT1Sx = 0;
fLFXT1,LF = 32,768 kHz,
CL,eff = 12 pF
32,768
UNIT
Hz
50,000
Hz
500
kW
200
kW
XTS = 0, XCAPx = 0
pF
XTS = 0, XCAPx = 1
5.5
pF
XTS = 0, XCAPx = 2
8.5
pF
XTS = 0, XCAPx = 3
11
pF
Duty Cycle
LF mode
XTS = 0, Measured at
P1.4/ACLK, fLFXT1,LF = 32,768
Hz
2.2 V/3 V
30
fFault,LF
XTS = 0, LFXT1Sx = 3
(see Note 2)
2.2 V/3 V
10
50
70
10,000
Hz
NOTES: 1. Includes parasitic bond and package capacitance (approximately 2pF per pin).
Since the PCB adds additional capacitance it is recommended to verify the correct load by measuring the ACLK frequency. For a
correct setup the effective load capacitance should always match the specification of the used crystal.
2. Measured with logic level input frequency but also applies to operation with crystals.
3. Frequencies below the MIN specification will set the fault flag, frequencies above the MAX specification will not set the fault flag.
Frequencies in between might set the flag.
4. To improve EMI on the LFXT1 oscillator the following guidelines should be observed.
Keep as short of a trace as possible between the device and the crystal.
Design a good ground plane around the oscillator pins.
Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.
If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.
Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other
documentation. This signal is no longer required for the serial programming adapter.
TEST CONDITIONS
VLO frequency
VCC
2.2 V/3 V
(see Note 1)
2.2 V/3 V
1.8V...3.6V
MIN
4
TYP
MAX
12
20
UNIT
kHz
0.5
%/C
%/V
33
SLAS491A AUGUST 2005 REVISED OCTOBER 2005
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
Timer_A
PARAMETER
TEST CONDITIONS
fTA
tTA,cap
VCC
MIN
TYP
MAX
2.2 V
10
3V
16
UNIT
MHz
TA0, TA1
2.2 V/3 V
20
ns
TEST CONDITIONS
VCC
External: SCLK;
Duty Cycle = 50% 10%;
SPI Slave Mode
fUSI
VOL,I2C
MIN
TYP
MAX
2.2 V
10
3V
16
UNIT
MHz
2.2 V/3 V
VSS
VSS+0.4
typical characteristics USI low-level output voltage on SDA and SCL (MSP430x20x2, MSP430x20x3 only)
5.0
5.0
3.0
TA = 85C
2.0
1.0
0.2
0.4
0.6
0.8
1.0
TA = 25C
4.0
0.0
0.0
4.0
TA = 85C
3.0
2.0
1.0
0.0
0.0
0.2
0.4
0.6
0.8
34
TA = 25C
VCC = 3 V
VCC = 2.2 V
1.0
SLAS491A AUGUST 2005 REVISED OCTOBER 2005
TEST CONDITIONS
I(DD)
I(Refladder/RefDiode)
CAON=1, CARSEL=0,
CAREF=1/2/3,
no load at P1.0/CA0 and P1.1/CA1
V(IC)
V(Ref025)
V(Ref050)
Common-mode input
voltage
Voltage @ 0.25 V
CC
V
Voltage @ 0.5V
V
CC
CC
node
CC
MIN
TYP
MAX
2.2 V
25
40
3V
45
60
2.2 V
30
50
3V
45
71
CAON=1
2.2 V/3 V
VCC1
2.2 V/3 V
0.23
0.24
0.25
2.2 V/3 V
0.47
0.48
0.5
2.2 V
390
480
540
490
550
UNIT
A
A
V
3V
400
Offset voltage
2.2 V/3 V
30
30
mV
Input hysteresis
CAON=1
2.2 V/3 V
0.7
1.4
mV
2.2 V
80
165
300
3V
70
120
240
V(RefVT)
V(offset)
Vhys
t(response)
node
VCC
Response time
(lowhigh and highlow)
mV
ns
35
SLAS491A AUGUST 2005 REVISED OCTOBER 2005
CAF
CAON
To Internal
Modules
V+
V
1
CAOUT
Set CAIFG
Flag
2.0 s
VCAOUT
Overdrive
V
400 mV
t(response)
V+
CASHORT
CA0
CA1
1
VIN
IOUT = 10A
Comparator_A+
CASHORT = 1
36
SLAS491A AUGUST 2005 REVISED OCTOBER 2005
650
VCC = 2.2 V
V(REFVT) Reference Volts mV
600
Typical
550
500
450
400
45
25
15
35
55
75
600
Typical
550
500
450
400
45
95
25
15
35
55
75
95
TA Free-Air Temperature C
TA Free-Air Temperature C
100.00
VCC = 3 V
VCC = 1.8V
VCC = 2.2V
VCC = 3.0V
10.00
VCC = 3.6V
1.00
0.0
0.2
0.4
0.6
0.8
1.0
37
SLAS491A AUGUST 2005 REVISED OCTOBER 2005
TEST CONDITIONS
VCC
TYP
MAX
VCC
VAx
2.2 V
0.52
1.05
IADC10
3V
0.6
1.2
2.2 V/3 V
0.25
0.4
IREF+
IREFB
CI
RI
NOTES: 1.
2.
3.
4.
38
Input capacitance
VSS = 0 V
All Ax terminals.
Analog inputs selected in ADC10AE
register.
MIN
UNIT
2.2
3.6
VCC
mA
mA
mA
3V
2.2 V/3 V
1.1
1.4
mA
2.2 V/3 V
0.46
0.55
mA
27
pF
The leakage current is defined in the leakage current table with Px.x/Ax parameter.
The analog input voltage range must be within the selected reference voltage range VR+ to VR for valid conversion results.
The internal reference supply current is not included in current consumption parameter IADC10.
The internal reference current is supplied via terminal VCC. Consumption is independent of the ADC10ON control bit, unless a
conversion is active. The REFON bit enables the built-in reference to settle before starting an A/D conversion.
SLAS491A AUGUST 2005 REVISED OCTOBER 2005
VCC,REF+
TEST CONDITIONS
VREF+
ILD,VREF+
VCC
TYP
2.2
VREF++0.15
VREF++0.15
MAX
UNIT
VCC
VCC
2.2 V/3 V
1.41
1.5
VCC
1.59
3V
2.35
2.5
2.65
2.2 V
MIN
0.5
3V
mA
2.2 V/3 V
LSB
3V
LSB
3V
400
IVREF+ =
100A900A,
VAx 0.5 x VREF+
Error of conversion
result 1 LSB
ADC10SR=0
ns
ADC10SR=1
3V
2000
100
CVREF+
IVREF+ 1mA,
REFON=1, REFOUT=1
2.2 V/3 V
TCREF+
Temperature coefficient
2.2 V/3 V
tREFON
tREFBURST
pF
100 ppm/C
3.6 V
30
ADC10SR=0
2.2 V
ADC10SR=1
2.2 V
2.5
NOTES: 1. The capacitance applied to the internal buffer operational amplifier, if switched to terminal P2.4/TA2/A4/VREF+/VeREF+ (REFOUT=1),
must be limited; the reference buffer may become unstable otherwise.
2. The condition is that the error in a conversion started after tREFON or tRefBuf is less than 0.5 LSB.
39
SLAS491A AUGUST 2005 REVISED OCTOBER 2005
VeREF+
TEST CONDITIONS
TYP
MAX
UNIT
1.4
VCC
1.4
3.0
1.2
1.4
VCC
VeREF
MIN
VeREF
IVeREF+
VCC
0V VeREF+ VCC,
SREF1 = 1, SREF0 = 0
2.2 V/3 V
2.2 V/3 V
IVeREF
Static input current into VeREF
0V VeREF VCC
2.2 V/3 V
1
A
NOTES: 1. The external reference is used during conversion to charge and discharge the capacitance array. The input capacitance, CI, is also
the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the
recommendations on analog-source impedance to allow the charge to settle for 10-bit accuracy.
2. The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced
accuracy requirements.
3. Under this condition the external reference is internally buffered. The reference buffer is active and requires the reference buffer
supply current IREFB. The current consumption can be limited to the sample and conversion period with REBURST = 1.
4. The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced
accuracy requirements.
5. The accuracy limits the minimum external differential reference voltage. Lower differential reference voltage levels may be applied
with reduced accuracy requirements.
40
SLAS491A AUGUST 2005 REVISED OCTOBER 2005
fADC10CLK
fADC10OSC
tCONVERT
TEST CONDITIONS
For specified
performance of
ADC10 linearity
parameters
Conversion time
VCC
MIN
TYP
MAX
UNIT
ADC10SR=0
2.2 V/3 V
0.45
6.3
ADC10SR=1
2.2 V/3 V
0.45
1.5
ADC10DIVx=0, ADC10SSELx = 0
fADC10CLK = fADC10OSC
2.2 V/3 V
3.7
6.3
MHz
2.2 V/3 V
2.06
3.51
MHz
13
ADC10DIV
1/fADC10CLK
tADC10ON
Turn on settling time of the ADC
(see Note 1)
100
ns
NOTES: 1. The condition is that the error in a conversion started after tADC10ON is less than 0.5 LSB. The reference and input signal are already
settled.
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
EI
ED
2.2 V/3 V
LSB
2.2 V/3 V
LSB
EO
Offset error
LSB
EG
Gain error
2.2 V/3 V
1.1
LSB
ET
2.2 V/3 V
LSB
2.2 V/3 V
41
SLAS491A AUGUST 2005 REVISED OCTOBER 2005
TEST CONDITIONS
REFON = 0, INCHx = 0Ah,
TA = 25_C
TCSENSOR
VSensor
VCC
MIN
TYP
MAX
2.2 V
40
120
3V
60
160
3.55
3.66
mV/C
100
mV
2.2 V/3 V
3.44
100
2.2 V/3 V
TBD
TBD
TBD
2.2 V/3 V
TBD
TBD
TBD
2.2 V/3 V
935
985
1035
2.2 V/3 V
30
IVMID
VMID
UNIT
A
A
mV
2.2 V
NA
3V
NA
2.2 V
1.06
1.1
1.14
3V
1.46
1.5
1.54
A
A
V
42
SLAS491A AUGUST 2005 REVISED OCTOBER 2005
ISD16
fSD16
TEST CONDITIONS
VCC
MIN
TYP
2.5
MAX
3.6
SD16LP = 0,
fSD16 = 1 MHz,
SD16OSR = 256
GAIN: 1,2
3V
730
1050
GAIN: 4,8,16
3V
810
1150
GAIN: 32
3V
1160
1700
SD16LP = 1,
fSD16 = 0.5 MHz,
SD16OSR = 256
GAIN: 1
3V
720
1030
GAIN: 32
3V
810
1150
1.1
SD16LP = 0
(Low power mode disabled)
3V
0.03
SD16LP = 1
(Low power mode enabled)
3V
0.03
0.5
UNIT
V
MHz
VID,FSR
VID
TEST CONDITIONS
VCC
SD16REFON=1
MIN
TYP
MAX
UNIT
(VREF/2)/
GAIN
+(VREF/2)/
GAIN
mV
+(VREF/2)/
GAIN
mV
SD16GAINx=1
500
SD16GAINx=2
250
SD16GAINx=4
125
SD16GAINx=8
62
SD16GAINx=16
31
mV
15
SD16GAINx=32
SD16GAINx=1
3V
200
SD16GAINx=32
3V
75
SD16GAINx=1
3V
300
400
SD16GAINx=32
3V
100
150
ZI
Input impedance
(one input pin to AVSS)
fSD16 = 1MHz
ZID
fSD16 = 1MHz
VI
AVSS
-0.1V
AVCC
VIC
AVSS
-0.1V
AVCC
k
k
NOTES: 1. The analog input range depends on the reference voltage applied to VREF. If VREF is sourced externally, the full-scale range
is defined by VFSR+ = +(VREF/2)/GAIN and VFSR = (VREF/2)/GAIN. The analog input range should not exceed 80% of
VFSR+ or VFSR.
43
SLAS491A AUGUST 2005 REVISED OCTOBER 2005
TEST CONDITIONS
SD16GAINx = 1,
Signal Amplitude: VIN = 500mV,
Signal Frequency: fIN = 100Hz
SD16GAINx = 2,
Signal Amplitude: VIN = 250mV,
Signal Frequency: fIN = 100Hz
SINAD1024
SD16GAINx = 4,
Signal Amplitude: VIN = 125mV,
Signal Frequency: fIN = 100Hz
SD16GAINx = 8,
Signal Amplitude: VIN = 62mV,
Signal Frequency: fIN = 100Hz
SD16GAINx = 16,
Signal Amplitude: VIN = 31mV,
Signal Frequency: fIN = 100Hz
SD16GAINx = 32,
Signal Amplitude: VIN = 15mV,
Signal Frequency: fIN = 100Hz
VCC
MIN
RSA
TYP
MIN
TYP
3V
84
85
TBD
TBD
3V
82
83
TBD
TBD
3V
78
79
TBD
TBD
UNIT
dB
3V
73
74
TBD
TBD
3V
68
69
TBD
TBD
3V
62
63
TBD
TBD
SD16_A, SINAD performance (fSD16 = 1MHz, SD16OSRx = 256, SD16REFON = 1, MSP430x20x3 only)
PW, or N
PARAMETER
TEST CONDITIONS
SD16GAINx = 1,
Signal Amplitude: VIN = 500mV,
Signal Frequency: fIN = 100Hz
SD16GAINx = 2,
Signal Amplitude: VIN = 250mV,
Signal Frequency: fIN = 100Hz
SINAD256
SD16GAINx = 4,
Signal Amplitude: VIN = 125mV,
Signal Frequency: fIN = 100Hz
SD16GAINx = 8,
Signal Amplitude: VIN = 62mV,
Signal Frequency: fIN = 100Hz
SD16GAINx = 16,
Signal Amplitude: VIN = 31mV,
Signal Frequency: fIN = 100Hz
SD16GAINx = 32,
Signal Amplitude: VIN = 15mV,
Signal Frequency: fIN = 100Hz
44
VCC
MIN
RSA
TYP
MIN
TYP
3V
80
81
TBD
TBD
3V
74
75
TBD
TBD
3V
69
70
TBD
TBD
UNIT
dB
3V
63
64
TBD
TBD
3V
58
59
TBD
TBD
3V
52
53
TBD
TBD
SLAS491A AUGUST 2005 REVISED OCTOBER 2005
SINAD dB
85.0
80.0
75.0
70.0
65.0
60.0
PW, or N
55.0
50.0
10.00
100.00
1000.00
OSR
Figure 22. SINAD performance over OSR, fSD16 = 1MHz, SD16REFON = 1, SD16GAINx = 1
SD16_A, performance (fSD16 = 1MHz, SD16OSRx = 256, SD16REFON = 1, MSP430x20x3 only)
PARAMETER
TEST CONDITIONS
1.02
SD16GAINx = 2
3V
1.90
1.96
2.02
SD16GAINx = 4
3V
3.76
3.86
3.96
SD16GAINx = 8
3V
7.36
7.62
7.84
SD16GAINx = 16
3V
14.56
15.04
15.52
SD16GAINx = 32
3V
27.20
28.35
29.76
3V
dG/dVCC
EOS
dEOS/dT
MAX
1.00
PSRR
TYP
0.97
MIN
3V
dG/dT
CMRR
VCC
SD16GAINx = 1
2.5V-3.6V
15
UNIT
ppm/_C
0.35
%/V
SD16GAINx = 1
3V
0.2
SD16GAINx = 32
3V
1.5
%FSR
SD16GAINx = 1
3V
20
SD16GAINx = 32
3V
20
100
ppm
FSR/_C
3V
>90
SD16GAINx = 1,
Common-mode input signal:
VID = 500 mV, fIN = 50 Hz, 100 Hz
SD16GAINx = 32,
Common-mode input signal:
VID = 16 mV, fIN = 50 Hz, 100 Hz
SD16GAINx = 1
dB
3V
>75
3V
>80
dB
45
SLAS491A AUGUST 2005 REVISED OCTOBER 2005
TEST CONDITIONS
TCSensor
Sensor temperature coefficient
VOffset,Sensor Sensor offset voltage
VSensor
VCC
MIN
See Note 1
1.18
See Note 1
100
TYP
1.32
MAX
1.46
mV/K
100
mV
3V
435
475
515
3V
355
395
435
320
360
400
UNIT
mV
TEST CONDITIONS
VCC
MIN
MAX
UNIT
VREF
IREF
SD16REFON = 1, SD16VMIDON = 0
3V
1.20
1.26
SD16REFON = 1, SD16VMIDON = 0
3V
190
280
TC
Temperature coefficient
SD16REFON = 1, SD16VMIDON = 0
3V
18
50
ppm/K
CREF
SD16REFON = 1, SD16VMIDON = 0
(see Note 1)
ILOAD
SD16REFON = 1; SD16VMIDON = 0
tON
Turn on time
PSRR
Line regulation
SD16REFON = 0 1;
SD16VMIDON = 0;
CREF = 100nF
SD16REFON = 1; SD16VMIDON = 0
1.14
TYP
100
nF
200
3V
nA
3V
ms
3V
10
uV/V
NOTES: 1. There is no capacitance required on VREF. However, a capacitance of at least 100nF is recommended to reduce any reference
voltage noise.
TEST CONDITIONS
VCC
MIN
TYP
VREF,BUF
SD16REFON = 1, SD16VMIDON = 1
3V
1.2
IREF,BUF
SD16REFON = 1, SD16VMIDON = 1
3V
385
CREF(O)
SD16REFON = 1, SD16VMIDON = 1
ILOAD,Max
Maximum load current on VREF
Maximum voltage variation vs. load current
tON
Turn on time
MAX
V
600
470
SD16REFON = 1, SD16VMIDON = 1
3V
|ILOAD| = 0 to 1mA
3V
SD16REFON = 0 1;
SD16VMIDON = 1;
CREF = 470nF
3V
UNIT
A
nF
15
mA
+15
mV
s
100
46
TEST CONDITIONS
VCC
SD16REFON = 0
3V
Input current
SD16REFON = 0
3V
MIN
1.0
TYP
1.25
MAX
UNIT
1.5
50
nA
SLAS491A AUGUST 2005 REVISED OCTOBER 2005
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
Flash Memory
PARAMETER
VCC(PGM/
ERASE)
TEST CONDITIONS
VCC
MIN
TYP
2.2
fFTG
IPGM
2.2 V/3.6 V
257
1
IERASE
tCPT
2.2 V/3.6 V
2.2 V/3.6 V
tCMErase
2.2 V/3.6 V
Program/Erase endurance
tRetention
TJ = 25C
tWord
tBlock, 0
tBlock, 1-63
tBlock, End
tMass Erase
tSeg Erase
20
104
MAX
UNIT
3.6
476
kHz
mA
mA
10
ms
ms
105
cycles
100
years
30
25
18
see Note 2
tFTG
6
10593
4819
NOTES: 1. The cumulative program time must not be exceeded when writing to a 64-byte flash block. This parameter applies to all programming
methods: individual word/byte write and block write modes.
2. These values are hardwired into the Flash Controllers state machine (tFTG = 1/fFTG).
RAM
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V(RAMh)
RAM retention supply voltage (see Note 1)
CPU halted
1.6
V
NOTE 1: This parameter defines the minimum supply voltage VCC when the data in RAM remains unchanged. No program execution should
happen during this supply voltage condition.
47
SLAS491A AUGUST 2005 REVISED OCTOBER 2005
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
JTAG and Spy-Bi-Wire Interface
TEST
CONDITIONS
PARAMETER
fSBW
tSBW,Low
VCC
MIN
TYP
MAX
UNIT
2.2 V / 3 V
20
MHz
2.2 V / 3 V
0.025
15
us
tSBW,En
2.2 V/ 3 V
us
tSBW,Ret
2.2 V/ 3 V
15
100
2.2 V
MHz
3V
10
MHz
fTCK
us
RInternal
Internal pull-down resistance on TEST
2.2 V/ 3 V
25
60
90
k
NOTES: 1. Tools accessing the Spy-Bi-Wire interface need to wait for the maximum tSBW,En time after pulling the TEST/SBWCLK pin high
before appling the first SBWCLK clock edge.
2. fTCK may be restricted to meet the timing requirements of the module selected.
PARAMETER
VCC(FB)
VFB
IFB
tFB
TA = 25C
VCC
MIN
MAX
2.5
6
TYP
UNIT
V
100
mA
ms
NOTES: 1. Once the fuse is blown, no further access to the JTAG/Test, Spy-Bi-Wire, and emulation feature is possible and JTAG is switched
to bypass mode.
48
SLAS491A AUGUST 2005 REVISED OCTOBER 2005
P1.1/TA0/CA1
P1.2/TA1/CA2
FUNCTION
0 P1.0 Input/Output
Timer_A2.TACLK/INCLK
P1SEL.x
CAPD.x
0/1
ACLK
0/1
Timer_A2.CCI0A
Timer_A2.TA0
0/1
1 P1.1 Input/Output
2 P1.2 Input/Output
Timer_A2.CCI1A
P1.3/CAOUT/CA3
P1DIR.x
Timer_A2.TA1
0/1
N/A
CAOUT
3 P1.3 Input/Output
1
Default after reset (PUC/POR)
NOTES: 1. N/A: Not available or not applicable.
2. X: Dont care.
3. Setting the CAPD.x bit disables the output driver as well as the input schmitt trigger to prevent parasitic cross currents when applying
analog signals. Selecting the CAx input pin to the comparator multiplexer with the P2CAx bits automatically disables the input buffer
for that pin, regardless of the state of the associated CAPD.x bit.
49
SLAS491A AUGUST 2005 REVISED OCTOBER 2005
P1DIR.x
Module X OUT
DVCC
Direction
0: Input
1: Output
P1OUT.x
DVSS
P1.0/TACLK/ACLK/CA0
P1.1/TA0/CA1
P1.2/TA1/CA2
P1.3/CAOUT/CA3
Bus
Keeper
P1SEL.x
EN
P1IN.x
EN
Module X IN
P1IE.x
EN
P1IRQ.x
Q
P1IFG.x
P1SEL.x
P1IES.x
Set
Interrupt
Edge
Select
FUNCTION
P2CA4
P2CA0
P2CA3
P2CA2
P2CA1
N/A
N/A
N/A
P1.0/TACLK/ACLK/CA0
CA0
P1.1/TA0/CA1
CA1
P1.2/TA1/CA2
CA2
P1.3/CAOUT/CA3
CA3
N/A
N/A
50
OR
SLAS491A AUGUST 2005 REVISED OCTOBER 2005
FUNCTION
P1DIR.x
P1SEL.x
CAPD.x
JTAG Mode
0/1
N/A
SMCLK
4 P1.4 Input/Output
P1.6/TA1/CA6/
TDI
P1.7/CAOUT/CA7/
TDO/TDI
5 P1.5 Input/Output
N/A
0/1
Timer_A2.TA0
6 P1.6 Input/Output
0/1
N/A
Timer_A2.TA1
7 P1.7 Input/Output
0/1
N/A
CAOUT
1
Default after reset (PUC/POR)
NOTES: 1. N/A: Not available or not applicable.
2. X: Dont care.
3. Setting the CAPD.x bit disables the output driver as well as the input schmitt trigger to prevent parasitic cross currents when applying
analog signals. Selecting the CAx input pin to the comparator multiplexer with the P2CAx bits automatically disables the input buffer
for that pin, regardless of the state of the associated CAPD.x bit.
4. In JTAG mode the internal pull-up/down resistors are disabled.
5. Function controlled by JTAG
51
SLAS491A AUGUST 2005 REVISED OCTOBER 2005
P1DIR.x
Module X OUT
DVCC
Direction
0: Input
1: Output
P1OUT.x
DVSS
P1.4/SMCLK/CA4/TCK
P1.5/TA0/CA5/TMS
P1.6/TA1/CA6/TDI
Bus
Keeper
P1SEL.x
EN
P1IN.x
EN
Module X IN
P1IE.x
P1IRQ.x
EN
Q
P1IFG.x
P1SEL.x
P1IES.x
Set
Interrupt
Edge
Select
To JTAG
From JTAG
FUNCTION
P2CA3
P2CA2
P2CA1
P1.4/SMCLK/CA4/TCK
CA4
P1.5/TA0/CA5/TMS
CA5
P1.6/TA1/CA6/TDI
CA6
52
SLAS491A AUGUST 2005 REVISED OCTOBER 2005
P1DIR.7
Module X OUT
DVCC
Direction
0: Input
1: Output
P1OUT.7
DVSS
P1.7/CAOUT/CA7/TDO/TDI
Bus
Keeper
P1SEL.7
EN
P1IN.7
EN
Module X IN
P1IE.7
P1IRQ.7
EN
Q
P1IFG.7
P1SEL.7
P1IES.7
Set
Interrupt
Edge
Select
To JTAG
From JTAG
From JTAG
From JTAG (TDO)
FUNCTION
P1.7/CAOUT/CA7/TDO/TDI
CA7
P2CA3
P2CA2
P2CA1
53
SLAS491A AUGUST 2005 REVISED OCTOBER 2005
BCSCTL3.LFXT1Sx = 11
P2.7/XOUT
LFXT1 off
LFXT1CLK
P2SEL.7
Pad Logic
P2REN.6
P2DIR.6
Module X OUT
DVCC
Direction
0: Input
1: Output
P2OUT.6
DVSS
P2.6/XIN/TA1
Bus
Keeper
P2SEL.6
EN
P2IN.6
EN
Module X IN
P2IE.6
P2IRQ.6
EN
Q
P2IFG.6
P2SEL.6
P2IES.6
Set
Interrupt
Edge
Select
FUNCTION
P2DIR.x
P2SEL.x
0/1
Timer_A2.TA1
6 P2.6 Input/Output
54
SLAS491A AUGUST 2005 REVISED OCTOBER 2005
BCSCTL3.LFXT1Sx = 11
LFXT1 off
LFXT1CLK
From P2.6/XIN
P2.6/XIN/TA1
Pad Logic
P2SEL.6
P2REN.7
P2DIR.7
Module X OUT
DVCC
Direction
0: Input
1: Output
P2OUT.7
DVSS
P2.7/XOUT
Bus
Keeper
P2SEL.7
EN
P2IN.7
EN
Module X IN
P2IE.7
P2IRQ.7
EN
Q
P2IFG.7
Set
Interrupt
Edge
Select
P2SEL.7
P2IES.7
FUNCTION
7 P2.7 Input/Output
P2DIR.x
P2SEL.x
0/1
DVSS
1
Default after reset (PUC/POR)
NOTES: 1. N/A: Not available or not applicable.
2. X: Dont care.
3. If the pin P2.7/XOUT is used as an input a current can flow until P2SEL.7 is cleared due to the oscillator output driver connection
to this pin after reset.
55
SLAS491A AUGUST 2005 REVISED OCTOBER 2005
FUNCTION
0 P1.0 Input/Output
Timer_A2.TACLK/INCLK
P1.1/TA0/A1
P1.2/TA1/A2
P1DIR.x
P1SEL.x
ADC10AE.x
INCHx
0/1
N/A
N/A
N/A
ACLK
A0 (see Note 3)
1 P1.1 Input/Output
0/1
N/A
Timer_A2.CCI0A
N/A
Timer_A2.TA0
N/A
A1 (see Note 3)
2 P1.2 Input/Output
0/1
N/A
N/A
N/A
Timer_A2.CCI1A
Timer_A2.TA1
A2 (see Note 3)
2
Default after reset (PUC/POR)
NOTES: 1. N/A: Not available or not applicable.
2. X: Dont care.
3. Setting the ADC10AE.x bit disables the output driver as well as the input schmitt trigger to prevent parasitic cross currents when
applying analog signals.
56
SLAS491A AUGUST 2005 REVISED OCTOBER 2005
P1DIR.x
Module X OUT
DVCC
Direction
0: Input
1: Output
P1OUT.x
DVSS
Bus
Keeper
P1SEL.x
P1.0/TACLK/ACLK/A0
P1.1/TA0/A1
P1.2/TA1/A2
EN
P1IN.x
EN
Module X IN
P1IE.x
P1IRQ.x
EN
Q
P1IFG.x
P1SEL.x
P1IES.x
Set
Interrupt
Edge
Select
57
SLAS491A AUGUST 2005 REVISED OCTOBER 2005
To ADC 10 VR
Pad Logic
A3
INCHx = 3
ADC10AE.3
P1REN.3
P1DIR.3
P1OUT.3
0
1
0
1
Direction
0: Input
1: Output
Module X OUT
DVSS
DVCC
P1.3/ADC10CLK/
A3/VREF/VeREF
Bus
Keeper
P1SEL.3
EN
P1IN.3
EN
Module X IN
P1IE.3
P1IRQ.3
EN
Q
P1IFG.3
Set
Interrupt
Edge
Select
P1SEL.3
P1IES.3
FUNCTION
3 P1.3 Input/Output
N/A
P1DIR.x
P1SEL.x
ADC10AE.x
INCHx
0/1
N/A
N/A
N/A
ADC10CLK
A3 (see Note 3)
N/A
58
SLAS491A AUGUST 2005 REVISED OCTOBER 2005
FUNCTION
4 P1.4 Input/Output
N/A
P1.6/TA1/SDO/SCL/A6/
TDI
P1.7/SDI/SDA/A7/
TDO/TDI
INCHx
JTAG
Mode
N/A
N/A
N/A
N/A
P1SEL.x
0/1
0
SMCLK
A4 (see Note 3)
VREF+/VeREF+
(see Notes 3, 4)
ADC10AE.x
P1DIR.x
5 P1.5 Input/Output
N/A
USIP.x
N/A
0/1
N/A
N/A
Timer_A2.TA0
N/A
SCLK
N/A
A5 (see Note 3)
0/1
N/A
Timer_A2.CCI1B
N/A
Timer_A2.TA1
N/A
N/A
A6 (see Note 3)
7 P1.7 Input/Output
0/1
N/A
N/A
N/A
DVSS
N/A
N/A
A7 (see Note 3)
6 P1.6 Input/Output
59
SLAS491A AUGUST 2005 REVISED OCTOBER 2005
P1DIR.4
Module X OUT
DVCC
P1.4/SMCLK/A4/VREF+/VeREF+/TCK
Bus
Keeper
P1SEL.4
EN
EN
Module X IN
P1IE.4
P1IRQ.4
EN
Q
P1IFG.4
P1SEL.4
P1IES.4
Set
Interrupt
Edge
Select
To JTAG
From JTAG
60
Direction
0: Input
1: Output
P1OUT.4
DVSS
SLAS491A AUGUST 2005 REVISED OCTOBER 2005
P1DIR.5
P1OUT.5
Module X OUT
DVSS
DVCC
Direction
0: Input
1: Output
P1.5/TA0/SCLK/A5/TMS
Bus
Keeper
EN
P1IN.5
EN
Module X IN
P1IE.5
P1IRQ.5
EN
Q
P1IFG.5
P1SEL.5
P1IES.5
Set
Interrupt
Edge
Select
To JTAG
From JTAG
61
SLAS491A AUGUST 2005 REVISED OCTOBER 2005
P1REN.6
P1SEL.6
USIPE6
P1DIR.6
P1OUT.6
Module X OUT
DVSS
DVCC
Direction
0: Input
1: Output
P1.6/TA1/SDO/SCL/A6/TDI
P1IN.6
EN
Module X IN
P1IE.6
P1IRQ.6
EN
Q
P1IFG.6
P1SEL.6
P1IES.6
Set
Interrupt
Edge
Select
To JTAG
From JTAG
62
SLAS491A AUGUST 2005 REVISED OCTOBER 2005
P1DIR.7
P1OUT.7
Module X OUT
DVSS
DVCC
Direction
0: Input
1: Output
P1.7/SDI/SDA/A7/TDO/TDI
P1IN.7
EN
Module X IN
P1IE.7
P1IRQ.7
EN
Q
P1IFG.7
P1SEL.7
P1IES.7
Set
Interrupt
Edge
Select
To JTAG
From JTAG
From JTAG
From JTAG (TDO)
63
SLAS491A AUGUST 2005 REVISED OCTOBER 2005
BCSCTL3.LFXT1Sx = 11
P2.7/XOUT
LFXT1 off
LFXT1CLK
P2SEL.7
Pad Logic
P2REN.6
P2DIR.6
Module X OUT
DVCC
Direction
0: Input
1: Output
P2OUT.6
DVSS
P2.6/XIN/TA1
Bus
Keeper
P2SEL.6
EN
P2IN.6
EN
Module X IN
P2IE.6
P2IRQ.6
EN
Q
P2IFG.6
P2SEL.6
P2IES.6
Set
Interrupt
Edge
Select
FUNCTION
P2DIR.x
P2SEL.x
0/1
Timer_A2.TA1
6 P2.6 Input/Output
64
SLAS491A AUGUST 2005 REVISED OCTOBER 2005
BCSCTL3.LFXT1Sx = 11
LFXT1 off
LFXT1CLK
From P2.6/XIN
P2.6/XIN/TA1
Pad Logic
P2SEL.6
P2REN.7
P2DIR.7
Module X OUT
DVCC
Direction
0: Input
1: Output
P2OUT.7
DVSS
P2.7/XOUT
Bus
Keeper
P2SEL.7
EN
P2IN.7
EN
Module X IN
P2IE.7
P2IRQ.7
EN
Q
P2IFG.7
Set
Interrupt
Edge
Select
P2SEL.7
P2IES.7
FUNCTION
7 P2.7 Input/Output
P2DIR.x
P2SEL.x
0/1
DVSS
1
Default after reset (PUC/POR)
NOTES: 1. N/A: Not available or not applicable.
2. X: Dont care.
3. If the pin P2.7/XOUT is used as an input a current can flow until P2SEL.7 is cleared due to the oscillator output driver connection
to this pin after reset.
65
SLAS491A AUGUST 2005 REVISED OCTOBER 2005
FUNCTION
0 P1.0 Input/Output
Timer_A2.TACLK/INCLK
P1.1/TA0/A0/A4+
SD16AE.x
INCHx
N/A
N/A
N/A
0/1
N/A
Timer_A2.CCI0A
N/A
Timer_A2.TA0
N/A
A0 (see Notes 3, 4)
1 P1.1 Input/Output
0/1
N/A
Timer_A2.CCI1A
N/A
Timer_A2.TA1
N/A
2 P1.2 Input/Output
A4 (see Notes 3, 4)
P1.3/VREF/A1
P1SEL.x
0/1
ACLK
P1DIR.x
3 P1.3 Input/Output
VREF
0/1
N/A
N/A
A1 (see Notes 3, 4)
X
X
1
1
Default after reset (PUC/POR)
NOTES: 1. N/A: Not available or not applicable.
2. X: Dont care.
3. Setting the SD16AE.x bit disables the output driver as well as the input schmitt trigger to prevent parasitic cross currents when
applying analog signals.
4. With SD16AE.x = 0 the negative inputs are connected to VSS if the corresponding input is selected.
66
SLAS491A AUGUST 2005 REVISED OCTOBER 2005
Pad Logic
A0+
SD16AE.0
P1REN.0
P1DIR.0
Module X OUT
DVCC
Direction
0: Input
1: Output
P1OUT.0
DVSS
P1.0/TACLK/ACLK/A0+
Bus
Keeper
P1SEL.0
EN
P1IN.0
EN
Module X IN
P1IE.0
P1IRQ.0
EN
Q
Set
P1IFG.0
P1SEL.0
P1IES.0
Interrupt
Edge
Select
67
SLAS491A AUGUST 2005 REVISED OCTOBER 2005
Pad Logic
A4+
INCH=0
0
A0
AV SS
SD16AE.1
P1REN.1
P1DIR.1
Module X OUT
0
1
P1.1/TA0/A0/A4+
Bus
Keeper
P1SEL.1
EN
P1IN.1
EN
Module X IN
P1IE.1
P1IRQ.1
EN
Q
Set
P1IFG.1
P1SEL.1
P1IES.1
68
Direction
0: Input
1: Output
P1OUT.1
DVSS
DVCC
Interrupt
Edge
Select
SLAS491A AUGUST 2005 REVISED OCTOBER 2005
Pad Logic
A1+
INCH=4
0
A4
AV SS
SD16AE.2
P1REN.2
P1DIR.2
Module X OUT
0
1
Direction
0: Input
1: Output
P1OUT.2
DVSS
DVCC
P1.2/TA1/A1+/A4
Bus
Keeper
P1SEL.2
EN
P1IN.2
EN
Module X IN
P1IE.2
P1IRQ.2
EN
Q
Set
P1IFG.2
P1SEL.2
P1IES.2
Interrupt
Edge
Select
69
SLAS491A AUGUST 2005 REVISED OCTOBER 2005
AV SS
SD16AE.3
P1REN.3
P1DIR.3
0
1
Direction
0: Input
1: Output
P1OUT.3
DVSS
DVCC
0
1
P1.3/VREF/A1
Bus
Keeper
P1SEL.3
EN
P1IN.3
P1IE.3
P1IRQ.3
EN
Q
Set
P1IFG.3
P1SEL.3
P1IES.3
70
Interrupt
Edge
Select
SLAS491A AUGUST 2005 REVISED OCTOBER 2005
P1.5/TA0/SCLK/A2/
TMS
P1.6/TA1/SDO/SCL/A3+/
TDI
P1.7/SDI/SDA/A3/
TDO/TDI
FUNCTION
4 P1.4 Input/Output
N/A
P1DIR.x
P1SEL.x
USIP.x
SD16AE.x
INCHx
JTAG
Mode
0/1
N/A
N/A
N/A
N/A
SMCLK
N/A
N/A
N/A
N/A
5 P1.5 Input/Output
0/1
N/A
N/A
N/A
Timer_A2.TA0
N/A
SCLK
N/A
A2 (see Notes 3, 4)
6 P1.6 Input/Output
0/1
N/A
Timer_A2.CCI1B
N/A
Timer_A2.TA1
N/A
N/A
7 P1.7 Input/Output
0/1
N/A
N/A
N/A
DVSS
N/A
N/A
A3 (see Notes 3, 4)
71
SLAS491A AUGUST 2005 REVISED OCTOBER 2005
Pad Logic
A2+
SD16AE.4
P1REN.4
P1DIR.4
Module X OUT
DVCC
P1.4/SMCLK/A2+/TCK
Bus
Keeper
P1SEL.4
EN
P1IN.4
EN
Module X IN
D
P1IE.4
EN
P1IRQ.4
Q
Set
P1IFG.4
P1SEL.4
P1IES.4
Interrupt
Edge
Select
To JTAG
From JTAG
72
Direction
0: Input
1: Output
P1OUT.4
DVSS
SLAS491A AUGUST 2005 REVISED OCTOBER 2005
AV SS
SD16AE.5
P1REN.5
P1SEL.5
USIPE5
P1DIR.5
P1OUT.5
Module X OUT
DVSS
DVCC
Direction
0: Input
1: Output
P1.5/TA0/SCLK/A2/TMS
Bus
Keeper
EN
P1IN.5
EN
Module X IN
P1IE.5
P1IRQ.5
EN
Q
Set
P1IFG.5
P1SEL.5
P1IES.5
Interrupt
Edge
Select
To JTAG
From JTAG
73
SLAS491A AUGUST 2005 REVISED OCTOBER 2005
INCH=3
A3+
SD16AE.6
P1REN.6
P1SEL.6
USIPE6
P1DIR.6
P1OUT.6
Module X OUT
DVSS
DVCC
Direction
0: Input
1: Output
P1.6/TA1/SDO/SCL/A3+/TDI
P1IN.6
EN
Module X IN
P1IE.6
P1IRQ.6
EN
Q
Set
P1IFG.6
P1SEL.6
P1IES.6
Interrupt
Edge
Select
To JTAG
From JTAG
74
SLAS491A AUGUST 2005 REVISED OCTOBER 2005
AV SS
SD16AE.x
P1REN.x
P1SEL.x
USIPE7
P1DIR.x
P1OUT.x
Module X OUT
DVSS
DVCC
Direction
0: Input
1: Output
P1.7/SDI/SDA/A3/TDO/TDI
P1IN.x
EN
Module X IN
P1IE.x
P1IRQ.x
EN
Q
Set
P1IFG.x
P1SEL.x
P1IES.x
Interrupt
Edge
Select
To JTAG
From JTAG
From JTAG
From JTAG (TDO)
75
SLAS491A AUGUST 2005 REVISED OCTOBER 2005
BCSCTL3.LFXT1Sx = 11
P2.7/XOUT
LFXT1 off
LFXT1CLK
P2SEL.7
Pad Logic
P2REN.6
P2DIR.6
Module X OUT
DVCC
Direction
0: Input
1: Output
P2OUT.6
DVSS
P2.6/XIN/TA1
Bus
Keeper
P2SEL.6
EN
P2IN.6
EN
Module X IN
P2IE.6
P2IRQ.6
EN
Q
P2IFG.6
P2SEL.6
P2IES.6
Set
Interrupt
Edge
Select
FUNCTION
P2DIR.x
P2SEL.x
0/1
Timer_A2.TA1
6 P2.6 Input/Output
76
SLAS491A AUGUST 2005 REVISED OCTOBER 2005
BCSCTL3.LFXT1Sx = 11
LFXT1 off
LFXT1CLK
From P2.6/XIN
P2.6/XIN/TA1
Pad Logic
P2SEL.6
P2REN.7
P2DIR.7
Module X OUT
DVCC
Direction
0: Input
1: Output
P2OUT.7
DVSS
P2.7/XOUT
Bus
Keeper
P2SEL.7
EN
P2IN.7
EN
Module X IN
P2IE.7
P2IRQ.7
EN
Q
P2IFG.7
Set
Interrupt
Edge
Select
P2SEL.7
P2IES.7
FUNCTION
7 P2.7 Input/Output
P2DIR.x
P2SEL.x
0/1
DVSS
1
Default after reset (PUC/POR)
NOTES: 1. N/A: Not available or not applicable.
2. X: Dont care.
3. If the pin P2.7/XOUT is used as an input a current can flow until P2SEL.7 is cleared due to the oscillator output driver connection
to this pin after reset.
77
SLAS491A AUGUST 2005 REVISED OCTOBER 2005
Summary
Preliminary PRODUCT PREVIEW datasheet release.
MSP430x20x3 production datasheet release.
Updated specification and added characterization graphs.
NOTE: The referring page and figure numbers are referred to the respective document revision.
78
MECHANICAL DATA
MTSS001C JANUARY 1995 REVISED FEBRUARY 1999
PW (R-PDSO-G**)
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
7
0 8
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
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