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IEEE TRANSACTIONS ON ENERGY CONVERSION, VOL. 30, NO. 1, MARCH 2015
Development of Power Interface With FPGABased Adaptive Control for PEMFC System
Alben Cardenas, Member, IEEE, Kodjo Agbossou, Senior Member, IEEE, and Nilson Henao, Student Member, IEEE
Abstract—This paper presents the development of a power in terface for a fuel cell (FC) system supplying an ac load. The pro posed system comprises a two stages conditioning system, includ ing a switched capacitor dc–dc boost converter and a full bridge insulatedgate bipolar transistor (IGBT) singlephase inverter (dc–ac converter). A fully digital control structure is proposed to manage both power converters using the same control device. The control strategy takes advantage of the parallelism of the ﬁeld pro grammable gate arrays (FPGA) technology to share in realtime the controller’s information addressing the common problem of low frequency ripple of FC current when supplying ac loads. The con trol system has been implemented and evaluated by cosimulation, and by experimentation with a proton exchange membrane fuel cell (PEMFC) system. The results show that the proposed system allows a safe operation of the FC by limiting the current ripple under 3%. These results also conﬁrm that the transient response of the conversion system permits to correctly supply the ac load.
Index Terms—Current ripple, energy conversion, fuel cells (FCs), neural networks, power electronics, programmable logic arrays.
I. INTRODUCTION
F UEL CELLS (FCs) are nowadays proposed as clean en ergy sources for stationary and mobile power applications.
Commonly stationary applications of FC are standalone and gridtied power systems [1], [2]. Power conditioning systems (PCSs) are employed to interface FC voltage with ac loads. The PCS includes a dc–dc boost converter to adapt the FC dc output voltage, which is normally below 50 V, to a higher dc voltage, and a dc–ac converter in order to produce the ac voltage to supply the load. Lowfrequency current ripple is a commonly related problem in the literature, which appears when FC systems are employed to supply ac loads. Several studies have proven that the cur rent ripple affects the FC life duration, as well as the available output power and its efﬁciency [3]–[6]. Those studies on one hand reveal that an energyefﬁcient operation of an FC system imposes that the current ripple must be limited to 20%. On the
Manuscript received February 3, 2014; revised May 30, 2014 and August
11, 2014; accepted August 13, 2014. Date of publication September 4, 2014; date of current version February 16, 2015. This work was supported in part
the
“Bureau de l’efﬁcacite´ et de l’innovation energ´ etiques´ du Quebec,”´ and the Natural Science and Engineering Research Council of Canada. Paper no. TEC
000752014.
The authors are with the Departement´ de Genie´ electrique´ et Genie´ In formatique, Hydrogen Research Institute, University of Quebec at Trois Rivieres (UQTR), TroisRivieres, QC G9A 5H7, Canada (email: Alben. cardenasgonzalez@uqtr.ca; kodjo.agbossou@uqtr.ca; Nilson.Henao@uqtr.ca). Color versions of one or more of the ﬁgures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identiﬁer 10.1109/TEC.2014.2349653
by the “Laboratoire des Technologies de l’ Energie” LTEHydroQuebec,´
´
other hand, in order to reduce the impact of the current ripple on the FC conditions, the ripple must be controlled below 4%. Current ripple can be reduced by adding intermediary stor age systems including capacitors, ultra capacitors or batteries. However, this option increases the overall cost of the PCS. Alter natively, design strategies of voltage and current feedback loops and power electronics circuitry have been proposed to reduce the lowfrequency ripple of FC current [7]–[14]. It is to remark, that most of the strategies, proposed to reduce the current ripple, have been only analyzed on steadystate operation. Recently, progress in very large scale integration (VLSI) tech nologies have permitted the introduction of ﬁeld programmable gate arrays (FPGAs) as new target devices for a wide variety of applications, including signal processing, information technol ogy, telecommunication, and control. FPGAs are semiconductor devices with high density of programmable resources, includ ing memory and logic operators, arranged as conﬁgurable logic blocks (CLBs), which can be reconﬁgured allowing the parallel processing of different functions. The FPGA is considered a promising technology in control and signal processing applica tions [15]–[18], mainly because it permits the implementation of several applications inside a single device, allowing multi threats and multicore processing systems, eliminating the real time communication constraints of multiple processors control systems. This paper presents the development and control of a power electronics interface for an FC power source supplying an ac load; the developed system includes the power electronics cir cuits and the FPGA implementation of the control algorithms for the PCS. The proposed control algorithms, embedded in one FPGA device, offer good transient response and a signif icant reduction of the FC current ripple. Hardwareintheloop (HIL) cosimulation and experimental results are provided to corroborate the validity of the proposed system. This paper is organized as follows. Section II presents the developed power electronics system. Section III describes the proposed control algorithms. Sections IV and V present the HIL cosimulation and the experimental results. Section VI provides some concluding remarks.
_{I}_{I}_{.} _{P}_{O}_{W}_{E}_{R} ELECTRONICS INTERFACE FOR PROTON EXCHANGE
MEMBRANE FUEL CELL (PEMFC)
Fig. 1 illustrates blocks diagram of the PCS used to interface a PEMFC with an ac load. As previously mentioned, FC systems present low output voltage, normally up to tens of volts, and the peak ac voltage of hundreds of volts. The output voltage of the FC system (Hydrogenics HyPM XR 8 FC power module) used in this study varies between 20 and
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297
Fig. 1.
Block diagram of FC interface.
Fig. 2.
Minimal dc–dc gain for different FC voltage.
40 V according to its operational characteristics (output power, temperature, etc.) [19]. The development of highgain boost dc–dc converters is essential to integrate green power sources with low output voltage, like the renewables and FCs, into the utility grid or to directly supply highvoltage loads
[20]–[28].
The minimum input voltage V _{d}_{c} for a the singlephase inverter can be deﬁned by
V _{D}_{C}_{L} > ^{√} 2 · V _{a}_{c} · cos(θ _{R} ) (1)
where V _{a}_{c} is the rootmeansquare (rms) ac voltage and θ _{R} is the rated phase angle. This relation must be satisﬁed to maintain the sinusoidal current waveform [29]. Normally, V _{d}_{c} is set higher
than ^{√} 2 · V _{a}_{c} , above 170 V for a 120V singlephase inverter. So the minimum gain of the dc–dc converter can vary according to the FC voltage as illustrated in Fig. 2. The dc–dc converters without intermediary storage system employ a highvoltage capacitor (HVC). This capacitor must be well chosen to allow enough energy storage to ensure a proper operation of the inverter. The inverter input voltage is supplied by this capacitor and must be kept within the low and high operating limits V _{D}_{C}_{L} and V _{D}_{C}_{H} , respectively. The discharging time (τ _{D} ) of the HVC from the high to the low dc voltage limits V _{D}_{C}_{H} and V _{D}_{C}_{L} can be computed by
_{τ} D _{>} (1/2)C _{H}_{V}_{C} ^{} V
2
DCH ^{−} ^{V} DCL
2
(2)
P FC − P ac − P L where P _{F}_{C} is the power coming from the FC, P _{a}_{c} is the power of the ac load, and P _{L} corresponds to the conversion losses. The difference between the P _{F}_{C} and the P _{a}_{c} + P _{L} corresponds to the discharging power. The discharging times computed for different discharging power, different V _{D}_{C}_{H} values, V _{D}_{C}_{L} = 180 V, and C _{H}_{V}_{C} = 2650 μF are plotted in Fig. 3. The results show that, if V _{D}_{C}_{H} is 195 V and the discharging power is higher than 500 W, the
Fig. 3.
V _{D}_{C}_{L} = 180 V and C _{H}_{V}_{C} = 2650 μ F.
Discharging time for different discharging power and different V _{D}_{C}_{H} ,
Fig. 4. Comparison of discharging time for C _{H}_{V}_{C} = 2650 μF and C _{H}_{V}_{C} = 6000 μ F. Different discharging power, different V _{D}_{C}_{H} , and V _{D}_{C}_{L} = 180 V.
dc voltage falls below V _{D}_{C}_{L} within one electric cycle. On the
other hand, if V _{D}_{C}_{H} is 220 V and the discharging power is the same, the dc voltage falls below V _{D}_{C}_{L} within 2.7 electric
cycles.
A comparison of the discharging times for C _{H}_{V}_{C} = 2650 μF
and C _{H}_{V}_{C} = 6000 μF is presented in Fig. 4. It is observed that
the discharging times obtained using 2650 μF at V _{D}_{C}_{H} = 220 V
are similar to the ones using 6000 μF at V _{D}_{C}_{H} = 200 V.
In this study, the PEMFC is interfaced by means of a high
gain, lowripple dc–dc switched capacitor boost converter as proposed in [20]–[23] and a developed insulatedgate bipo lar transistor (IGBT) inverter as illustrated in Fig. 5. The main characteristics of the conversion system are presented in Table I. The basic operation of the switched capacitor boost converter (SCBC) has been discussed in detail in [23], where the authors demonstrate that this converter topology is well adapted when requiring low input current ripple, low output voltage ripple, and high voltage gain, as required in our case. The static gain of
the SCBC can be computed using the duty cycle (D) by
2
(3)
G = _{1} _{−} _{D} .
The control of the dc–dc and dc–ac power electronics con
verters when the system operates as autonomous power source must allow a good transient response and a steadystate behav
ior according to the standards [30]; moreover, as mentioned ear
lier, the lowfrequency ripple of FC current must be controlled
to be below 4%. In particular, the 120Hz oscillation must be
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Fig. 5.
General diagram of the developed power electronics interface for PEMFC system.
TABLE I
SYSTEM CHARACTERISTICS
Description
Value
PEMFC
Hydrogenics—HyPMXR8
Rated power DC output voltage DC–DC converter Type
Working input voltage range Maximum output voltage Input capacitor (LVC) Input inductors (L _{1} , L _{2} ) Switched capacitors (SC1, SC2) Output capacitor (C3)
Filter inductor (L _{3} ) Filter capacitor (HVC) Switching frequency Power switching devices: Ultrafast diode IGBT DC–AC Converter Bridge Type Rated voltage/current Nominal dcsource voltage Operating voltage/frequency Switching frequency Filter and Line Impedance
8 kW ^{∗} 20–35 V
OneStage Switched Capacitor Boost Converter 20–35 V 250 V 1000 μF 1.4 mH 1000 μF 10 μF 0.8 mH 2650 μF 6 kHz FFH60UP40S APT75GN120LG
IGBT Power Module (PS21A7A) 600 V/30 A 200 V 120 V/60 Hz 10 kHz
Filter 
inductor (L _{D} _{1} + L _{D} _{2} ) 
1.6 mH 
Filter capacitor (C _{f} ) 
20 μF 

Coupling Inductor (Lo) Line impedance (L, R) 
1 mH 1.17 μH, 17.6 mΩ ^{∗}^{∗} 
^{∗} In this study, the output power of the FC system is limited to 3 kW. ^{∗}^{∗} Line impedance corresponds to load connection cable.
Fig. 6.
on VFADALINE with FLL [31].
Simpliﬁed diagram of the control structure of dc–ac converter based
limited. This ripple limitation is necessary to prevent damage or premature degradation of the FC.
III. PROPOSED VOLTAGE AND CURRENT CONTROL
The control of power electronics interface is divided in two parts, the ﬁrst one is the ac voltage control and the second one is the dc voltage and current control.
A. AC Voltage Control
The ac voltage control implemented in this study is based on the ADALINE&FLL [31]. This control scheme offers good transient and steadystate behavior and has been previously eval uated with linear and nonlinear loads. A simpliﬁed diagram of the control structure is presented in Fig. 6. In this voltage control structure, the instantaneous signal er ror (ε _{S} ) is computed as the difference between the reference
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299
and the measured signal (4), and compensated by means of a proportional controller with gain K _{P}_{a}_{c} (5)
(4)
(5)
The error of the orthogonal components of voltage (ε _{W} _{0} and ε _{W} _{1} ) is compensated by means of a proportional and integral (PI) controller with gains K _{P}_{d}_{c} and K _{I}_{d}_{c} .
ε _{S} (k) = V _{R}_{E}_{F} (k) − V _{C} (k)
C _{S} (k) = K _{P}_{a}_{c} · ε _{S} (k).
C _{W} _{0} (k) = K _{P}_{d}_{c} · ε _{W} _{0} (k) + K _{I}_{d}_{c}
k
ρ=0
ε
_{W}
_{0} (ρ)
(6)
C _{W} _{1} (k) = K _{P}_{d}_{c} · ε _{W} _{1} (k) + K _{I}_{d}_{c}
k
ρ=0
ε
_{W}
_{1} (ρ).
(7)
The compensation signal [see (8)] is then the result of the partial compensations of (5), (6), and (7)
C T (k) = ^{} C _{S} (k)
+C _{W} _{0} (k) · sin(2π · f · k · T _{S} )
)
+C _{W} _{1} (k) · cos(2π · f · k · T _{S}
(8)
where the sines and cosines signals are generated by the VF DDS. The modulating signal V _{P}_{W}_{M} can be obtained from the reference voltage and the signal compensation using the follow ing:
(9)
V _{P}_{W}_{M} (k) = V _{R}_{E}_{F} (k) + C _{T} (k).
B. DC Voltage and Current Control
This section focuses on the control stage, which is devoted to maintain the output voltage of the dc–dc converter at a desired value (input voltage of the inverter) in order to guarantee a correct operation of whole system, even if the FC voltage and the load power change. The voltage control of the dc–dc converter can be obtained by means of two modiﬁed PI controllers as illustrated in Fig. 7. The ﬁrst one acts as a voltage controller (10), and the second one as current controller (11). The rms current absorbed by the ac load I _{r}_{m}_{s} is estimated by means of the VFADALINE&FLL, and it is fed back and used to anticipate the current set point for the dc–dc converter
I FCR =
D =
(V DCR − V DCM ) · K PV + K ^{I}^{V}
_{s}
(I _{F}_{C}_{R} − I _{F}_{C}_{M} ) · K _{P}_{I} + ^{K} ^{I}^{I}
s
+ I rms · G dc
(10)
(11)
where G _{d}_{c} is the actual dc gain of system computed by using the actual FC and dclink voltages using
G dc =
V DCM
.
V FC
(12)
As illustrated in Fig. 7, the feedback variables, like the dc link voltage (V _{d}_{c} ), the load current (I _{r}_{m}_{s} ), and the FC current and voltage (I _{F}_{C} , V _{F}_{C} ), are ﬁltered by means of the auxiliary ADALINE lowpass ﬁlter bank (ADALINELPF). This ﬁlter bank is synchronized with the ac load frequency by means
Fig. 7. Proposed control structure of dc–dc and dc–ac converters for the ac voltage control of an FC system.
of the ADALINE&FLL permitting to eliminate the harmonic components present on the measured signals and improving the transient and the steadystate controller behavior. The estimated signal using the ADALINELPF can be represented by
(13)
yˆ(k) = W(k) ^{T} · X(k)
where X is the input pattern vector considering a number N of harmonics and deﬁned by
X(k) =
⎡
⎢
⎢
⎢
⎢
⎢
⎢
⎢
⎢
⎣
1
sin(2π · f · k · T _{S} )
cos(2π · f
.
.
sin(2π · N · f · k · T _{S} )
cos(2π · N · f · k · T _{S} )
· k · T _{S} )
⎤
⎥
⎥
⎥
⎥
⎥
⎥
⎥
⎥
⎦
(14)
where T _{s} is the sampling period of the direct digital synthesis block (DDS); W is the weight vector, which is updated consid ering the estimation error e(k) and the learning factor α using
α
W (k + 1) = W (k) + _{N} · e(k) · X(k)
_{.}
_{(}_{1}_{5}_{)}
The mean or dc signal can be the computed by
yˆ _{d}_{c} (k) = W (0,k) · X(0,k) (16)
eliminating the ac components present on the measured signal, which are directly related with the harmonics of the ac load current.
300
The proposed method, as other proposed techniques, permits to reduce the ripple of the FC current by subtracting the low frequency components of the feedback voltage signal; however, the accurate load frequency tracking and the harmonics de composition are special characteristics of the ADALINELPF allowing a much better reduction of the ripple present on the feedback signals and without negative impact on the dynamic performance of the controller. In contrast to classic solutions as using proportionalresonant (PR) controllers or bandpass ﬁlters (BPFs), tuned at a ﬁxed frequency [7], [11], the adaptive prop erty of the method proposed in this study permits to operate the system at a ﬁxed load frequency or at a variable frequency; consequently, it can be widely used for a standalone microgrid or connected to the main grid mode. It is to highlight that classic solutions only consider the 120 Hz (or 100 Hz) as the component to be attenuated or eliminated. Some techniques permit to eliminate the 120 Hz component but generate other harmonic components [13]. Additionally, modern ac loads may introduce other nonnegligible harmonic compo nents which must be also eliminated of the feedback signals.
C. DC Voltage Droop Scheme
As illustrated in Figs. 3 and 4, the HVC discharging and charging times are mainly dependent on two parameters: the capacity and the voltage. Hence, if lowcapacity and ﬁxed V _{d}_{c} are employed, the capacitor voltage regulation can be largely affected by the load ﬂuctuations if the FC transient re sponse is not fast enough. A dc voltage droop scheme is pro posed to improve the transient response of converter without increasing the capacity of HVC. This voltage droop scheme can be deﬁned by
V DCR = V DCN + m dc (P NOM − P ac ) (17)
where V _{D}_{C}_{R} is the set point of V _{d}_{c} ; V _{D}_{C}_{N} is the nominal value of V _{d}_{c} ; P _{a}_{c} is the measured load ac power; P _{N}_{O}_{M} is the rated power of the FC (or dc–ac converter); and m _{d}_{c} is the droop coefﬁcient (in volts per watt). In the dcdroop scheme, the operating voltage at the rated power corresponds to the nominal value, and higher operating voltages are set for operating powers under the rated power. In other words, if the system is working at very low power the dclink voltage is “set” at its highest value; consequently, if the power demand increases the dclink voltage naturally falls down. Otherwise, when the system is working at its maximum power the dclink voltage is “set” at its lowest value; thus, if the power demand falls down the dclink voltage naturally rises. The controllers’ gains can be obtained ofﬂine from the trans fer function of the system by means of the SISO design or PID tuner graphical user interfaces (GUIs) of MATLAB soft ware (MATLABSISOTool or MATLABPIDTool); tuning of PI controller can be also obtained online by automatic tuning techniques [32].
IV. HIL COSIMULATION RESULTS
The proposed control system of FC power electronic inter face has been implemented and evaluated by HIL cosimulation using the Xilinx Virtex5 XC5VLX110T FPGA as target device
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TABLE II
MAIN CHARACTERISTICS OF MEASUREMENT SYSTEM
Description (Units) 
Value 

Measurement and Control System Sample time of measurement system (μs) FPGA clock period (ns) ADALINEFLL Number of analyzed harmonics DDS sample time – T _{0} (μs) Number of implemented WVU – T _{0} WVU – T _{0} learning factor 
10 

10 

32 

1 

3 

0.1 

FLL 
gain G _{F}_{L}_{L} 
3.5 
FLL sampling period – T _{F}_{L}_{L} (μs) FLL error threshold – ε _{M}_{I}_{N} FLL sliding window period – T _{S}_{W} (ms) 
10 μs 

0.1 

20 
Fig. 8. HIL cosimulation results of (a) current and (b) voltage ripple when the mean FC current is 90 A. Controllers use tuning 1.
[33]. The main characteristics of the measurement system and the implemented ADALINEFLL are presented in Table II. The operation of the FC system has been evaluated for dif ferent loading conditions. Fig. 8 shows the plot of FC cur rent and dclink voltage waveforms when the system supply a 3kW ac load with 120 V/60 Hz voltage. In order to analyze the performance of the proposed control structure, the ripple factor of the FC current γ is computed by using
γ = I Ripple−rms
I
FC−mean
× 100%
(18)
where I _{F}_{C}_{−}_{m}_{e}_{a}_{n} is the mean value of the FC current and I _{R}_{i}_{p}_{p}_{l}_{e}_{−}_{r}_{m}_{s} is the rms value of the FC current ripple. In the same way, the dclink voltage ripple factor is also computed. Two different tunings of the integral gain for the current con troller (K _{I}_{I} ) have been used. Using the characteristics presented in Table III, tuning 1 offers faster response than tuning 2. The HIL cosimulation results of Fig. 8 are obtained using tuning 1,
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301
TABLE III
SETUP OF CONTROLLERS USED IN THE HIL COSIMULATION
Description 
Tunning 1 
Tunning 2 

DC 
Voltage Controller 

DC 
current controller (K _{P} _{I} , K _{I} _{I} ) 
0.005, 5 
0.005, 1 

DC 
voltage controller (K _{P} _{V} , K _{I} _{V} ) 
1, 0.01 
1, 0.01 

V _{d}_{c} nominal 
200 V 
200 V 

Operating V _{d}_{c} (V _{m}_{i}_{n} – 
V _{m}_{a}_{x} ) 
170–240 V 
170–240 V 

DC voltage droop (m _{d}_{c} ) 
3.3 mV/W 
3.3 mV/W 

Controller sample time 
10 μs 
10 μs 

AC Voltage Controller 

Signal error controller (K _{P}_{a}_{c} ) Orthogonal components controller (K _{P}_{d}_{c} , K _{I} _{d}_{c} ) 
11 

0.0432, 42.35 
0.0432, 42.35 
Controller sample time Switching frequency
250 μs
6 kHz
250 μs
6 kHz
Fig. 9. HIL cosimulation results of (a) current and (b) voltage for different power of ac load. Controllers use tuning 2.
the ripple factor of FC current and voltage are 2.95% and 2.1%, respectively. Fig. 9 shows the results for the transient response of the FC system using tuning 2; in this test, the inverter is started at t = 100 ms with an initial ac load of 100 W; also at the times t = 300 ms, t = 800 ms, and t = 1.3 s, the load power is increased each time of 500 W. Fig. 9(a) shows the FC current, and Fig. 9(b) shows the dclink voltage (at HVC). The effect of the voltage droop scheme on the dclink voltage, following the variations of the output power of the system, is well illustrated in this ﬁgure. These results show a good behavior of the controller. Fig. 10 shows the results of the ripple factor of the FC current for different load power and considering the two different tunings of the integral gain of current controller (K _{I}_{I} ). According to these results, the ripple factor is always under 3% and meet
Fig. 10.
HIL cosimulation results of current ripple for different ac load power.
TABLE IV
COMPARISON OF FC CURRENT RIPPLE AND CAPACITOR SIZE
Description 
References [8], [9] 
This study 
Low voltage capacitor (LVC) Switching capacitors (SC1 + 
6600 μF 
1000 μF 
– 
2000 μF 

SC2) 

HVC Rated power (static converters) LVC + SC capacitor/power HVC capacitor/power Steadystate current ripple 
2200 μF 
2650 μF 
1.20 kW 
3 kW 

5.5 μF/W 
1 μF/W 0.88 μF/W 2.95% (Tuning 1) 2.05% (Tuning 2) 

1.83 μF/W 

2.0% 
the recommended ripple limits (γ < 4%) to reduce the negative impact of the inverter load on the FC conditions [7].
As illustrated in Fig. 10, the current ripple can be attenuated by reducing the speed of the current compensator, which is pos sible by reducing the gain K _{I}_{I} , as in the tuning 2 case. However,
it is to highlight that the speed of the current compensator must
remain high enough to warrant the safe operation of the system. Table IV shows a comparison of the results obtained by using the proposed control structure with the ones obtained in [8] and [9]. It is appropriate to remark that in this study the sizes of the LVC and the HVC have been reduced to 18% and 48%, respectively, compared to the ones used in [8], [9]. In order to provide a better indication of the different avail able solutions of ripple mitigation, a summary of some recently
published methods with a brief description of achievements and the characteristics of each one is given in Table V.
V. EXPERIMENTAL RESULTS
The proposed control for an FC system has been evaluated experimentally using a watercooled PEMFC system connected to the developed PCS (switched capacitor boost converter and IGBT inverter prototypes) and a measurement system based on Xilinx Virtex5 development board [33]. The system supplies
a variable power load represented by a set of commercial light bulbs. Fig. 11 presents a real view of the implemented SCBC, and Fig. 12 shows the whole test bench.
A. Static Gain of DC–DC Converter
The developed prototype of dc–dc converter has been prelim inary tested using a dc load in order to verify the steadystate
302 

TABLE V 

SUMMARY OF RECENTLY PROPOSED CURRENT RIPPLE MITIGATION TECHNIQUES 

Year 
Technique 
Characteristics 
2010 
Dualloop dc–dc converter control with BPF [11] 
Experiments show that the technique permits to reduce the current ripple to 4%. The dc–dc converter used in this study consists of a current fed push–pull converter with auxiliary circuit (ﬂyback converter). 
2010 
DCactive ﬁlter with a center tap 
With this technique, the ripple current can be decreased to 20% compared to the conventional circuit (without compensation). Experiments show an input current total harmonic distortion (THD) over 10%, depending on the output power. 
[12]. 

2013 
Waveform control [13]. 
Experiments show a 100 Hz current ripple of 11.9% for a dc current of 1.84 A. A 200 Hz current ripple of 8.9% appears. THD of ac voltage is slightly increased. Ripple of dclink voltage (or FC voltage) is not presented. 
2014 
Feedforward control scheme 
The 120 Hz component of input current is reduced to 0.3%. Peaktopeak ripple current is 1.32 A (3.2% of 14.4 A). DClink voltage ripple is 27 V (7.63% of 250 V). 
[14]. 
Fig. 11.
Real view of the implemented SCBC.
voltage gain (G) for different duty cycle (D). The experimen tal results of the static gain of the dc–dc converter are plotted in Fig. 13 for the openloop operation, and in Fig. 14, for the closed loop. The obtained experimental values are close to those of the theory obtained by using (3). The experimental gain is lower than the theoretical value, which can be explained by the converter losses.
B. Inverter Load Operation
The operation of the FC system has been validated with dif ferent ac load conditions. The ﬁrst test has been carried out by using optimal tuning of classic PI controllers for the current and voltage loops obtained by the classic Ziegler–Nichols rule with
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Fig. 12.
Real view of the implemented test bench of FC power system.
Fig. 13. 
Experimental dc–dc static gain of converter prototype operating in 
open loop. 
Fig. 14.
closed loop at two different operation points, V _{d}_{c} = 180 V and V _{d}_{c} = 200 V.
Experimental results of static gain of the dc–dc converter working in
MATLABSISOTool. Fig. 15 presents the results of FC and ac load currents; it is observed that the current ripple is over 4% even if, in that case, the power is low (I _{a}_{c}_{−}_{r}_{m}_{s} = 4.2 A). The proposed controller, illustrated in Fig. 7, has been also evaluated for different operating powers; the current ripple has been computed for each case by postprocessing using MATLAB software from data collected by means of the user interface (WindowsMATLABXilinx). Fig. 16 presents a summary of the experimental results of FC current ripple for different ac load power corresponding to different mean FC current (limited to 40 A). It is to remark that the ripple factor remains well under 4% and near to 2% conﬁrming the results obtained by cosimulation.
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303
Fig. 15. Experimental results of inverter load operation at low load power (I _{a}_{c}_{−}_{r}_{m}_{s} = 4.2 A) (classic control with optimal controller tuning using Ziegler Nichols rule with MATLAB SISOTool).
Fig. 16. Experimental results of current ripple for different ac load power (the proposed control scheme using tuning 2).
Fig. 17. Experimental results of inverter load operation at low load power (I _{a}_{c}_{−}_{r}_{m}_{s} = 7 A, I _{F}_{C}_{−}_{m}_{e}_{a}_{n} = 25.6 A). (a) Voltage waveforms and (b) current waveforms with the proposed control scheme using tuning 2.
Fig. 17 provides the plots of the measured voltages (dc link, FC, and ac load) and currents (dc–dc converter, FC, and ac
load), when the mean FC current is 25.6 A (corresponding to a sinusoidal load current of 7 A rms); in this case, the computed FC current ripple is 1.85%. The plots of the measured voltages and currents when the mean FC current is 39.9 A (corresponding
to 
a sinusoidal load current of 11 A rms) are shown in Fig. 18; 
in 
this case, the computed FC current ripple is 1.99%. 
C. 
Evaluation of the Conversion Efﬁciency 
The efﬁciency of the power electronics converter has been experimentally evaluated for different operating powers; the re sults, plotted in Fig. 19, show a mean efﬁciency of over 94%.
D. Evaluation of Dynamic Performance
The dynamic performance of the proposed strategy has been
experimentally veriﬁed conﬁrming that the transient response
of the voltage controller is kept fast enough to maintain the dc
link voltage and to warrant a correct ac load supply. Figs. 20 and 21 show the experimental results applying a transient load power by switching ON (see Fig. 20) and OFF (see Fig. 21) a
commercial light bulb. The reference of dclink voltage was in tentionally set to 196 V (<< 220 V) considering the lowpower transient used in the test, and as expected, according to Fig. 3, the dclink voltage was maintained over 180 V when the transient load power was introduced. This behavior can be only achieved
if the time response of the voltage controller is fast enough to
start a corrective action within one electric cycle (<17 ms).
A better response of voltage regulation will be obtained if the
reference of the dclink voltage is set to 220 V as suggested in Fig. 4. As observed in Fig. 20(a), the dclink voltage regulation is rapidly achieved (within 20 ms) without any overshoot or os cillation. The voltage is once again set at the working value with a settling time of 35 ms (considering a 2% of error). As the commercial light bulbs used in this test present very low impedance when switched ON, their startup power demand is three times higher than their nominal power; this fact permits to introduce a power transient near to 500 W using a single 150W lamp. The results presented in Fig. 21 conﬁrm the transient response of the proposed voltage controller when the load power falls down. For the power decreasing case, the dclink voltage is well regulated, preventing from undesired overshoots or oscillations; and similarly to the previous case, the FC current is adjusted within a short time (<20 ms) following the ac load variations. In order to evaluate the dynamic response of the proposed controller face to the variations of the reference voltage, a square signal of 10 V at 1 Hz has been momentarily applied in a short period of time to the actual reference voltage. The results of the dclink voltage tracking response are presented in Fig. 22(a); here the reference of dclink voltage and the “mean” dclink voltage obtained through the ADALINE lowpass ﬁlter bank (ADALINELPF) and used as the feedback signal are plotted. Fig. 22(b) shows the current and the voltage of the FC during the same time interval. The results of the step response of the entire conversion sys tem have been used to compute the settling time. This computa tion has been carried out by means of the MATLAB “lsiminfo”
304
Fig. 18. Experimental results of inverter load operation at low load power (I _{F}_{C}_{−}_{m}_{e}_{a}_{n} = 39.9 A). (a) Voltage waveforms and (b) current waveforms with the proposed control scheme using tuning 2.
Fig. 19.
scheme using tuning 2).
Experimental results of converter’s efﬁciency (the proposed control
function; the obtained result is 96 ms, which corresponds to a time constant of 24.6 ms (considering a ﬁrstorder approxima tion and a tacking error of 2%). In the results, it is important to remark that the system presents a time constant lower than two electric cycles. Also, it must be highlighted that in this study the bandwidth of the voltage control loop was set to 5 Hz, which permits a good tracking of the reference voltage; most of literature works use bandwidths lower than 10 Hz (much lower than 120 Hz) for the voltage control loop, e.g., the strategy of ripple reduction proposed in [8] and [9] has been evaluated with a bandwidth of voltage control loop of 1.2, 2, and 4 Hz, and the best results were obtained when 1.2 Hz was employed. In this study, a higher bandwidth is possible due to the use of the ADALINE low pass ﬁlter bank, which permits to reduce the 120 Hz ripple of the voltage feedback signal without important delay improving
IEEE TRANSACTIONS ON ENERGY CONVERSION, VOL. 30, NO. 1, MARCH 2015
Fig. 20.
tion, and (b) FC current and voltage. Power transient of −150 W by switching OFF a commercial light bulb.
Experimental results of transient response (a) dclink voltage regula
Fig. 21.
tion, and (b) FC current and voltage. Power transient of +150 W by switching ON a commercial light bulb.
Experimental results of transient response (a) dclink voltage regula
CARDENAS et al.: DEVELOPMENT OF POWER INTERFACE WITH FPGABASED ADAPTIVE CONTROL FOR PEMFC SYSTEM
305
Fig. 22. Experimental results of voltage controller response face to steps on the reference voltage: (a) dclink voltage response; and (b) FC current and voltage.
the transient response and mitigating the steadystate ripple of the FC current.
VI. CONCLUSION
The development of a power interface for an FC system sup plying an ac load has been presented. The proposed system includes a prototype of dc–dc and dc–ac converters, and all the control is implemented in FPGA. The proposed control includes the ADALINE&FLL structure implemented in hardware, which is used to control in parallel both the inverter and the SCBC. Additionally, a dc voltage droop scheme is adopted to improve the response of the dc–dc converter even with the low size of the HVC. The proposed system has been experimentally validated showing many advantages compared with classic solutions some of them are the low current ripple, the fast transient response, and a reduced dclink capacitor compared to the classic and recently proposed alternative solutions. All control blocks have been embedded in a single FPGA device, working in parallel and sharing in real time the main variables information. This fact demonstrates the validity and potential of the proposed system by using modern digital control systems.
ACKNOWLEDGMENT
The authors would like to thank the Xilinx University Pro gram for the hardware, software, and technical support.
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Alben Cardenas (S’09–M’12) received the B.S. degree in electronic engineering from the Antonio Narino˜ University, Villavicencio, Colombia, in 2003, and the M.S. and PhD. degrees in electrical engineer ing from the Universite´ du Quebec´ a` TroisRivieres` (UQTR), TroisRivieres,` QC, Canada, in 2008 and 2012, respectively. He is currently a Researcher at the Hydrogen Re search Institute (HRI), and a Lecturer in the Electri cal and Computer Engineering Department, UQTR. His current research interests include renewable en ergy, distributed generation, power electronics, and very large scale integration (VLSI) technologies for energy conversion and power quality applications. Dr. Cardenas is a Member of the Ordre des Ingenieurs´ du Quebec,´ and a Member of the IEEE Power and Energy Society and the IEEE Industrial Elec tronics Society.
IEEE TRANSACTIONS ON ENERGY CONVERSION, VOL. 30, NO. 1, MARCH 2015
Kodjo Agbossou (M’98–SM’01) received the B.S., M.S., and Ph.D. degrees in electronic measurements from the Universite´ de Nancy I, Nancy, France, in 1987, 1989, and 1992, respectively. He is currently the Head of the Engineer ing School, Universite´ du Quebec´ a` TroisRivieres` (UQTR), TroisRivieres,` QC, Canada. He was a Post doctoral Research Fellow in the Electrical Engineer ing Department, UQTR (1993–1994), where he was a Lecturer (1997–1998). Since 1998, he has been an Associate Professor, and since 2004, he has been a Full Professor in the Electrical and Computer Engineering Department, UQTR. He was the Head of the Electrical and Computer Engineering Department. He was also the Director of Graduate Studies in Electrical Engineering. He is the author or coauthor of more than 180 publications and has 4 patents. His current research include in the areas of renewable energy, smart grid, integration of hydrogen production, storage and electrical energy generation system, hybrid electrical vehicle, control, and measurements. He is a member of the Hydrogen Research Institute and Research group “Group de reserche en electronique´ in dustrielle (GREI)”, UQTR. Dr. Agbossou is a Member of the IEEE Power and Energy Society, the In dustry Applications Societies, the Communications Society, and the Industrial Electronics Society Technical Committee on Renewable Energy Systems. He was the Chair of the IEEE Section Saint Maurice, QC, Canada. He is a Profes sional Engineer and joined the Ordre des Ingenieurs´ du Quebec´ in 1998.
Nilson Henao (S’14) received the B.S. degree in electronics engineering from the Universidad de los Llanos, Villavicencio, Colombia, in 2010, and the M.Sc. degree in electrical engineering from the Uni versity of Quebec at TroisRivieres (UQTR), Trois Rivieres, QC, Canada in 2013, where he is currently working toward the Ph.D. degree with the Depart ment of Electrical and Computer Engineering. His current research interests include fuel cell con trol and optimization, and energy management for hy brid electric vehicles. He is currently involved in ma chine learning techniques for nonintrusive appliance load monitoring (NIALM) to disaggregate and track device electrical signatures.
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