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IEEE TRANSACTIONS ON ENERGY CONVERSION, VOL. 30, NO. 1, MARCH 2015

Development of Power Interface With FPGA-Based Adaptive Control for PEM-FC System

Alben Cardenas, Member, IEEE, Kodjo Agbossou, Senior Member, IEEE, and Nilson Henao, Student Member, IEEE

Abstract—This paper presents the development of a power in- terface for a fuel cell (FC) system supplying an ac load. The pro- posed system comprises a two stages conditioning system, includ- ing a switched capacitor dc–dc boost converter and a full bridge insulated-gate bipolar transistor (IGBT) single-phase inverter (dc–ac converter). A fully digital control structure is proposed to manage both power converters using the same control device. The control strategy takes advantage of the parallelism of the field pro- grammable gate arrays (FPGA) technology to share in real-time the controller’s information addressing the common problem of low- frequency ripple of FC current when supplying ac loads. The con- trol system has been implemented and evaluated by co-simulation, and by experimentation with a proton exchange membrane fuel cell (PEM-FC) system. The results show that the proposed system allows a safe operation of the FC by limiting the current ripple under 3%. These results also confirm that the transient response of the conversion system permits to correctly supply the ac load.

Index Terms—Current ripple, energy conversion, fuel cells (FCs), neural networks, power electronics, programmable logic arrays.

I. INTRODUCTION

F UEL CELLS (FCs) are nowadays proposed as clean en- ergy sources for stationary and mobile power applications.

Commonly stationary applications of FC are stand-alone and grid-tied power systems [1], [2]. Power conditioning systems (PCSs) are employed to interface FC voltage with ac loads. The PCS includes a dc–dc boost converter to adapt the FC dc output voltage, which is normally below 50 V, to a higher dc voltage, and a dc–ac converter in order to produce the ac voltage to supply the load. Low-frequency current ripple is a commonly related problem in the literature, which appears when FC systems are employed to supply ac loads. Several studies have proven that the cur- rent ripple affects the FC life duration, as well as the available output power and its efficiency [3]–[6]. Those studies on one hand reveal that an energy-efficient operation of an FC system imposes that the current ripple must be limited to 20%. On the

Manuscript received February 3, 2014; revised May 30, 2014 and August

11, 2014; accepted August 13, 2014. Date of publication September 4, 2014; date of current version February 16, 2015. This work was supported in part

the

“Bureau de l’efficacite´ et de l’innovation energ´ etiques´ du Quebec,”´ and the Natural Science and Engineering Research Council of Canada. Paper no. TEC-

00075-2014.

The authors are with the Departement´ de Genie´ electrique´ et Genie´ In- formatique, Hydrogen Research Institute, University of Quebec at Trois- Rivieres (UQTR), Trois-Rivieres, QC G9A 5H7, Canada (e-mail: Alben. cardenasgonzalez@uqtr.ca; kodjo.agbossou@uqtr.ca; Nilson.Henao@uqtr.ca). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TEC.2014.2349653

by the “Laboratoire des Technologies de l’ Energie” LTE-Hydro-Quebec,´

´

other hand, in order to reduce the impact of the current ripple on the FC conditions, the ripple must be controlled below 4%. Current ripple can be reduced by adding intermediary stor- age systems including capacitors, ultra capacitors or batteries. However, this option increases the overall cost of the PCS. Alter- natively, design strategies of voltage and current feedback loops and power electronics circuitry have been proposed to reduce the low-frequency ripple of FC current [7]–[14]. It is to remark, that most of the strategies, proposed to reduce the current ripple, have been only analyzed on steady-state operation. Recently, progress in very large scale integration (VLSI) tech- nologies have permitted the introduction of field programmable gate arrays (FPGAs) as new target devices for a wide variety of applications, including signal processing, information technol- ogy, telecommunication, and control. FPGAs are semiconductor devices with high density of programmable resources, includ- ing memory and logic operators, arranged as configurable logic blocks (CLBs), which can be reconfigured allowing the parallel processing of different functions. The FPGA is considered a promising technology in control and signal processing applica- tions [15]–[18], mainly because it permits the implementation of several applications inside a single device, allowing multi- threats and multicore processing systems, eliminating the real- time communication constraints of multiple processors control systems. This paper presents the development and control of a power electronics interface for an FC power source supplying an ac load; the developed system includes the power electronics cir- cuits and the FPGA implementation of the control algorithms for the PCS. The proposed control algorithms, embedded in one FPGA device, offer good transient response and a signif- icant reduction of the FC current ripple. Hardware-in-the-loop (HIL) co-simulation and experimental results are provided to corroborate the validity of the proposed system. This paper is organized as follows. Section II presents the developed power electronics system. Section III describes the proposed control algorithms. Sections IV and V present the HIL co-simulation and the experimental results. Section VI provides some concluding remarks.

II. POWER ELECTRONICS INTERFACE FOR PROTON EXCHANGE

MEMBRANE FUEL CELL (PEM-FC)

Fig. 1 illustrates blocks diagram of the PCS used to interface a PEM-FC with an ac load. As previously mentioned, FC systems present low output voltage, normally up to tens of volts, and the peak ac voltage of hundreds of volts. The output voltage of the FC system (Hydrogenics HyPM XR 8 FC power module) used in this study varies between 20 and

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WITH FPGA-BASED ADAPTIVE CONTROL FOR PEM-FC SYSTEM 297 Fig. 1. Block diagram of FC interface. Fig.

Fig. 1.

Block diagram of FC interface.

FOR PEM-FC SYSTEM 297 Fig. 1. Block diagram of FC interface. Fig. 2. Minimal dc–dc gain

Fig. 2.

Minimal dc–dc gain for different FC voltage.

40 V according to its operational characteristics (output power, temperature, etc.) [19]. The development of high-gain boost dc–dc converters is essential to integrate green power sources with low output voltage, like the renewables and FCs, into the utility grid or to directly supply high-voltage loads

[20]–[28].

The minimum input voltage V dc for a the single-phase inverter can be defined by

V DCL > 2 · V ac · |cos(θ R )| (1)

where V ac is the root-mean-square (rms) ac voltage and θ R is the rated phase angle. This relation must be satisfied to maintain the sinusoidal current waveform [29]. Normally, V dc is set higher

than 2 · V ac , above 170 V for a 120-V single-phase inverter. So the minimum gain of the dc–dc converter can vary according to the FC voltage as illustrated in Fig. 2. The dc–dc converters without intermediary storage system employ a high-voltage capacitor (HVC). This capacitor must be well chosen to allow enough energy storage to ensure a proper operation of the inverter. The inverter input voltage is supplied by this capacitor and must be kept within the low and high operating limits V DCL and V DCH , respectively. The discharging time (τ D ) of the HVC from the high to the low dc voltage limits V DCH and V DCL can be computed by

τ D > (1/2)C HVC V

2

DCH V DCL

2

(2)

P FC P ac P L where P FC is the power coming from the FC, P ac is the power of the ac load, and P L corresponds to the conversion losses. The difference between the P FC and the P ac + P L corresponds to the discharging power. The discharging times computed for different discharging power, different V DCH values, V DCL = 180 V, and C HVC = 2650 μF are plotted in Fig. 3. The results show that, if V DCH is 195 V and the discharging power is higher than 500 W, the

is 195 V and the discharging power is higher than 500 W, the Fig. 3. V

Fig. 3.

V DCL = 180 V and C HVC = 2650 μ F.

Discharging time for different discharging power and different V DCH ,

different discharging power and different V D C H , Fig. 4. Comparison of discharging time

Fig. 4. Comparison of discharging time for C HVC = 2650 μF and C HVC = 6000 μ F. Different discharging power, different V DCH , and V DCL = 180 V.

dc voltage falls below V DCL within one electric cycle. On the

other hand, if V DCH is 220 V and the discharging power is the same, the dc voltage falls below V DCL within 2.7 electric

cycles.

A comparison of the discharging times for C HVC = 2650 μF

and C HVC = 6000 μF is presented in Fig. 4. It is observed that

the discharging times obtained using 2650 μF at V DCH = 220 V

are similar to the ones using 6000 μF at V DCH = 200 V.

In this study, the PEM-FC is interfaced by means of a high-

gain, low-ripple dc–dc switched capacitor boost converter as proposed in [20]–[23] and a developed insulated-gate bipo- lar transistor (IGBT) inverter as illustrated in Fig. 5. The main characteristics of the conversion system are presented in Table I. The basic operation of the switched capacitor boost converter (SCBC) has been discussed in detail in [23], where the authors demonstrate that this converter topology is well adapted when requiring low input current ripple, low output voltage ripple, and high voltage gain, as required in our case. The static gain of

the SCBC can be computed using the duty cycle (D) by

2

(3)

G = 1 D .

The control of the dc–dc and dc–ac power electronics con-

verters when the system operates as autonomous power source must allow a good transient response and a steady-state behav-

ior according to the standards [30]; moreover, as mentioned ear-

lier, the low-frequency ripple of FC current must be controlled

to be below 4%. In particular, the 120-Hz oscillation must be

298

IEEE TRANSACTIONS ON ENERGY CONVERSION, VOL. 30, NO. 1, MARCH 2015

ON ENERGY CONVERSION, VOL. 30, NO. 1, MARCH 2015 Fig. 5. General diagram of the developed

Fig. 5.

General diagram of the developed power electronics interface for PEM-FC system.

TABLE I

SYSTEM CHARACTERISTICS

Description

Value

PEM-FC

Hydrogenics—HyPMXR8

Rated power DC output voltage DC–DC converter Type

Working input voltage range Maximum output voltage Input capacitor (LVC) Input inductors (L 1 , L 2 ) Switched capacitors (SC1, SC2) Output capacitor (C3)

Filter inductor (L 3 ) Filter capacitor (HVC) Switching frequency Power switching devices: Ultrafast diode IGBT DC–AC Converter Bridge Type Rated voltage/current Nominal dc-source voltage Operating voltage/frequency Switching frequency Filter and Line Impedance

8 kW 20–35 V

One-Stage Switched Capacitor Boost Converter 20–35 V 250 V 1000 μF 1.4 mH 1000 μF 10 μF 0.8 mH 2650 μF 6 kHz FFH60UP40S APT75GN120LG

IGBT Power Module (PS21A7A) 600 V/30 A 200 V 120 V/60 Hz 10 kHz

Filter

inductor (L D 1 + L D 2 )

1.6 mH

Filter capacitor (C f )

20 μF

Coupling Inductor (Lo) Line impedance (L, R)

1 mH 1.17 μH, 17.6 mΩ

In this study, the output power of the FC system is limited to 3 kW. Line impedance corresponds to load connection cable.

∗ Line impedance corresponds to load connection cable. Fig. 6. on VF-ADALINE with FLL [31]. Simplified

Fig. 6.

on VF-ADALINE with FLL [31].

Simplified diagram of the control structure of dc–ac converter based

limited. This ripple limitation is necessary to prevent damage or premature degradation of the FC.

III. PROPOSED VOLTAGE AND CURRENT CONTROL

The control of power electronics interface is divided in two parts, the first one is the ac voltage control and the second one is the dc voltage and current control.

A. AC Voltage Control

The ac voltage control implemented in this study is based on the ADALINE&FLL [31]. This control scheme offers good transient and steady-state behavior and has been previously eval- uated with linear and nonlinear loads. A simplified diagram of the control structure is presented in Fig. 6. In this voltage control structure, the instantaneous signal er- ror (ε S ) is computed as the difference between the reference

CARDENAS et al.: DEVELOPMENT OF POWER INTERFACE WITH FPGA-BASED ADAPTIVE CONTROL FOR PEM-FC SYSTEM

299

and the measured signal (4), and compensated by means of a proportional controller with gain K Pac (5)

(4)

(5)

The error of the orthogonal components of voltage (ε W 0 and ε W 1 ) is compensated by means of a proportional and integral (PI) controller with gains K Pdc and K Idc .

ε S (k) = V REF (k) V C (k)

C S (k) = K Pac · ε S (k).

C W 0 (k) = K Pdc · ε W 0 (k) + K Idc

k

ρ=0

ε

W

0 (ρ)

(6)

C W 1 (k) = K Pdc · ε W 1 (k) + K Idc

k

ρ=0

ε

W

1 (ρ).

(7)

The compensation signal [see (8)] is then the result of the partial compensations of (5), (6), and (7)

C T (k) = C S (k)

+C W 0 (k) · sin(2π · f · k · T S )

)

+C W 1 (k) · cos(2π · f · k · T S

(8)

where the sines and cosines signals are generated by the VF- DDS. The modulating signal V PWM can be obtained from the reference voltage and the signal compensation using the follow- ing:

(9)

V PWM (k) = V REF (k) + C T (k).

B. DC Voltage and Current Control

This section focuses on the control stage, which is devoted to maintain the output voltage of the dc–dc converter at a desired value (input voltage of the inverter) in order to guarantee a correct operation of whole system, even if the FC voltage and the load power change. The voltage control of the dc–dc converter can be obtained by means of two modified PI controllers as illustrated in Fig. 7. The first one acts as a voltage controller (10), and the second one as current controller (11). The rms current absorbed by the ac load I rms is estimated by means of the VF-ADALINE&FLL, and it is fed back and used to anticipate the current set point for the dc–dc converter

I FCR =

D =

(V DCR V DCM ) · K PV + K IV

s

(I FCR I FCM ) · K PI + K II

s

+ I rms · G dc

(10)

(11)

where G dc is the actual dc gain of system computed by using the actual FC and dc-link voltages using

G dc =

V DCM

.

V FC

(12)

As illustrated in Fig. 7, the feedback variables, like the dc- link voltage (V dc ), the load current (I rms ), and the FC current and voltage (I FC , V FC ), are filtered by means of the auxiliary ADALINE low-pass filter bank (ADALINE-LPF). This filter bank is synchronized with the ac load frequency by means

bank is synchronized with the ac load frequency by means Fig. 7. Proposed control structure of

Fig. 7. Proposed control structure of dc–dc and dc–ac converters for the ac voltage control of an FC system.

of the ADALINE&FLL permitting to eliminate the harmonic components present on the measured signals and improving the transient and the steady-state controller behavior. The estimated signal using the ADALINE-LPF can be represented by

(13)

yˆ(k) = W(k) T · X(k)

where X is the input pattern vector considering a number N of harmonics and defined by

X(k) =

1

sin(2π · f · k · T S )

cos(2π · f

.

.

sin(2π · N · f · k · T S )

cos(2π · N · f · k · T S )

· k · T S )

(14)

where T s is the sampling period of the direct digital synthesis block (DDS); W is the weight vector, which is updated consid- ering the estimation error e(k) and the learning factor α using

α

W (k + 1) = W (k) + N · e(k) · X(k)

.

(15)

The mean or dc signal can be the computed by

yˆ dc (k) = W (0,k) · X(0,k) (16)

eliminating the ac components present on the measured signal, which are directly related with the harmonics of the ac load current.

300

The proposed method, as other proposed techniques, permits to reduce the ripple of the FC current by subtracting the low- frequency components of the feedback voltage signal; however, the accurate load frequency tracking and the harmonics de- composition are special characteristics of the ADALINE-LPF allowing a much better reduction of the ripple present on the feedback signals and without negative impact on the dynamic performance of the controller. In contrast to classic solutions as using proportional-resonant (PR) controllers or bandpass filters (BPFs), tuned at a fixed frequency [7], [11], the adaptive prop- erty of the method proposed in this study permits to operate the system at a fixed load frequency or at a variable frequency; consequently, it can be widely used for a stand-alone microgrid or connected to the main grid mode. It is to highlight that classic solutions only consider the 120 Hz (or 100 Hz) as the component to be attenuated or eliminated. Some techniques permit to eliminate the 120 Hz component but generate other harmonic components [13]. Additionally, modern ac loads may introduce other non-negligible harmonic compo- nents which must be also eliminated of the feedback signals.

C. DC Voltage Droop Scheme

As illustrated in Figs. 3 and 4, the HVC discharging and charging times are mainly dependent on two parameters: the capacity and the voltage. Hence, if low-capacity and fixed V dc are employed, the capacitor voltage regulation can be largely affected by the load fluctuations if the FC transient re- sponse is not fast enough. A dc voltage droop scheme is pro- posed to improve the transient response of converter without increasing the capacity of HVC. This voltage droop scheme can be defined by

V DCR = V DCN + m dc (P NOM P ac ) (17)

where V DCR is the set point of V dc ; V DCN is the nominal value of V dc ; P ac is the measured load ac power; P NOM is the rated power of the FC (or dc–ac converter); and m dc is the droop coefficient (in volts per watt). In the dc-droop scheme, the operating voltage at the rated power corresponds to the nominal value, and higher operating voltages are set for operating powers under the rated power. In other words, if the system is working at very low power the dc-link voltage is “set” at its highest value; consequently, if the power demand increases the dc-link voltage naturally falls down. Otherwise, when the system is working at its maximum power the dc-link voltage is “set” at its lowest value; thus, if the power demand falls down the dc-link voltage naturally rises. The controllers’ gains can be obtained offline from the trans- fer function of the system by means of the SISO design or PID tuner graphical user interfaces (GUIs) of MATLAB soft- ware (MATLAB-SISOTool or MATLAB-PIDTool); tuning of PI controller can be also obtained online by automatic tuning techniques [32].

IV. HIL CO-SIMULATION RESULTS

The proposed control system of FC power electronic inter- face has been implemented and evaluated by HIL co-simulation using the Xilinx Virtex-5 XC5VLX110T FPGA as target device

IEEE TRANSACTIONS ON ENERGY CONVERSION, VOL. 30, NO. 1, MARCH 2015

TABLE II

MAIN CHARACTERISTICS OF MEASUREMENT SYSTEM

Description (Units)

Value

Measurement and Control System Sample time of measurement system (μs) FPGA clock period (ns) ADALINE-FLL Number of analyzed harmonics DDS sample time – T 0 (μs) Number of implemented WVU – T 0 WVU – T 0 learning factor

10

10

32

1

3

0.1

FLL

gain G FLL

3.5

FLL sampling period – T FLL (μs) FLL error threshold – ε MIN FLL sliding window period – T SW (ms)

10 μs

0.1

20

period – T S W (ms) 10 μ s 0.1 20 Fig. 8. HIL co-simulation results

Fig. 8. HIL co-simulation results of (a) current and (b) voltage ripple when the mean FC current is 90 A. Controllers use tuning 1.

[33]. The main characteristics of the measurement system and the implemented ADALINE-FLL are presented in Table II. The operation of the FC system has been evaluated for dif- ferent loading conditions. Fig. 8 shows the plot of FC cur- rent and dc-link voltage waveforms when the system supply a 3-kW ac load with 120 V/60 Hz voltage. In order to analyze the performance of the proposed control structure, the ripple factor of the FC current γ is computed by using

γ = I Ripplerms

I

FCmean

× 100%

(18)

where I FCmean is the mean value of the FC current and I Ripplerms is the rms value of the FC current ripple. In the same way, the dc-link voltage ripple factor is also computed. Two different tunings of the integral gain for the current con- troller (K II ) have been used. Using the characteristics presented in Table III, tuning 1 offers faster response than tuning 2. The HIL co-simulation results of Fig. 8 are obtained using tuning 1,

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TABLE III

SETUP OF CONTROLLERS USED IN THE HIL CO-SIMULATION

Description

 

Tunning 1

Tunning 2

DC

Voltage Controller

DC

current controller (K P I , K I I )

0.005, 5

0.005, 1

DC

voltage controller (K P V , K I V )

1, 0.01

1, 0.01

V dc nominal

 

200 V

200 V

Operating V dc (V min

V max )

170–240 V

170–240 V

DC voltage droop (m dc )

3.3 mV/W

3.3 mV/W

Controller sample time

10 μs

10 μs

AC Voltage Controller

 

Signal error controller (K Pac ) Orthogonal components controller (K Pdc , K I dc )

11

0.0432, 42.35

0.0432, 42.35

Controller sample time Switching frequency

250 μs

6 kHz

250 μs

6 kHz

time Switching frequency 250 μ s 6 kHz 250 μ s 6 kHz Fig. 9. HIL

Fig. 9. HIL co-simulation results of (a) current and (b) voltage for different power of ac load. Controllers use tuning 2.

the ripple factor of FC current and voltage are 2.95% and 2.1%, respectively. Fig. 9 shows the results for the transient response of the FC system using tuning 2; in this test, the inverter is started at t = 100 ms with an initial ac load of 100 W; also at the times t = 300 ms, t = 800 ms, and t = 1.3 s, the load power is increased each time of 500 W. Fig. 9(a) shows the FC current, and Fig. 9(b) shows the dc-link voltage (at HVC). The effect of the voltage droop scheme on the dc-link voltage, following the variations of the output power of the system, is well illustrated in this figure. These results show a good behavior of the controller. Fig. 10 shows the results of the ripple factor of the FC current for different load power and considering the two different tunings of the integral gain of current controller (K II ). According to these results, the ripple factor is always under 3% and meet

these results, the ripple factor is always under 3% and meet Fig. 10. HIL co-simulation results

Fig. 10.

HIL co-simulation results of current ripple for different ac load power.

TABLE IV

COMPARISON OF FC CURRENT RIPPLE AND CAPACITOR SIZE

Description

References [8], [9]

This study

Low voltage capacitor (LVC) Switching capacitors (SC1 +

6600 μF

1000 μF

2000 μF

SC2)

HVC Rated power (static converters) LVC + SC capacitor/power HVC capacitor/power Steady-state current ripple

2200 μF

2650 μF

1.20 kW

3 kW

5.5 μF/W

1 μF/W 0.88 μF/W 2.95% (Tuning 1) 2.05% (Tuning 2)

1.83 μF/W

2.0%

the recommended ripple limits (γ < 4%) to reduce the negative impact of the inverter load on the FC conditions [7].

As illustrated in Fig. 10, the current ripple can be attenuated by reducing the speed of the current compensator, which is pos- sible by reducing the gain K II , as in the tuning 2 case. However,

it is to highlight that the speed of the current compensator must

remain high enough to warrant the safe operation of the system. Table IV shows a comparison of the results obtained by using the proposed control structure with the ones obtained in [8] and [9]. It is appropriate to remark that in this study the sizes of the LVC and the HVC have been reduced to 18% and 48%, respectively, compared to the ones used in [8], [9]. In order to provide a better indication of the different avail- able solutions of ripple mitigation, a summary of some recently

published methods with a brief description of achievements and the characteristics of each one is given in Table V.

V. EXPERIMENTAL RESULTS

The proposed control for an FC system has been evaluated experimentally using a water-cooled PEM-FC system connected to the developed PCS (switched capacitor boost converter and IGBT inverter prototypes) and a measurement system based on Xilinx Virtex-5 development board [33]. The system supplies

a variable power load represented by a set of commercial light bulbs. Fig. 11 presents a real view of the implemented SCBC, and Fig. 12 shows the whole test bench.

A. Static Gain of DC–DC Converter

The developed prototype of dc–dc converter has been prelim- inary tested using a dc load in order to verify the steady-state

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TABLE V

SUMMARY OF RECENTLY PROPOSED CURRENT RIPPLE MITIGATION TECHNIQUES

Year

Technique

Characteristics

2010

Dual-loop dc–dc converter control with BPF [11]

Experiments show that the technique permits to reduce the current ripple to 4%. The dc–dc converter used in this study consists of a current fed push–pull converter with auxiliary circuit (flyback converter).

2010

DC-active filter with a center tap

With this technique, the ripple current can be decreased to 20% compared to the conventional circuit (without compensation). Experiments show an input current total harmonic distortion (THD) over 10%, depending on the output power.

[12].

2013

Waveform control [13].

Experiments show a 100 Hz current ripple of 11.9% for a dc current of 1.84 A. A 200 Hz current ripple of 8.9% appears. THD of ac voltage is slightly increased. Ripple of dc-link voltage (or FC voltage) is not presented.

2014

Feed-forward control scheme

The 120 Hz component of input current is reduced to 0.3%. Peak-to-peak ripple current is 1.32 A (3.2% of 14.4 A). DC-link voltage ripple is 27 V (7.63% of 250 V).

[14].

DC-link voltage ripple is 27 V (7.63% of 250 V). [14]. Fig. 11. Real view of

Fig. 11.

Real view of the implemented SCBC.

voltage gain (G) for different duty cycle (D). The experimen- tal results of the static gain of the dc–dc converter are plotted in Fig. 13 for the open-loop operation, and in Fig. 14, for the closed loop. The obtained experimental values are close to those of the theory obtained by using (3). The experimental gain is lower than the theoretical value, which can be explained by the converter losses.

B. Inverter Load Operation

The operation of the FC system has been validated with dif- ferent ac load conditions. The first test has been carried out by using optimal tuning of classic PI controllers for the current and voltage loops obtained by the classic Ziegler–Nichols rule with

IEEE TRANSACTIONS ON ENERGY CONVERSION, VOL. 30, NO. 1, MARCH 2015

ON ENERGY CONVERSION, VOL. 30, NO. 1, MARCH 2015 Fig. 12. Real view of the implemented

Fig. 12.

Real view of the implemented test bench of FC power system.

Real view of the implemented test bench of FC power system. Fig. 13. Experimental dc–dc static

Fig. 13.

Experimental dc–dc static gain of converter prototype operating in

open loop.

gain of converter prototype operating in open loop. Fig. 14. closed loop at two different operation

Fig. 14.

closed loop at two different operation points, V dc = 180 V and V dc = 200 V.

Experimental results of static gain of the dc–dc converter working in

MATLAB-SISOTool. Fig. 15 presents the results of FC and ac load currents; it is observed that the current ripple is over 4% even if, in that case, the power is low (I acrms = 4.2 A). The proposed controller, illustrated in Fig. 7, has been also evaluated for different operating powers; the current ripple has been computed for each case by postprocessing using MATLAB software from data collected by means of the user interface (Windows-MATLAB-Xilinx). Fig. 16 presents a summary of the experimental results of FC current ripple for different ac load power corresponding to different mean FC current (limited to 40 A). It is to remark that the ripple factor remains well under 4% and near to 2% confirming the results obtained by co-simulation.

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WITH FPGA-BASED ADAPTIVE CONTROL FOR PEM-FC SYSTEM 303 Fig. 15. Experimental results of inverter load operation

Fig. 15. Experimental results of inverter load operation at low load power (I acrms = 4.2 A) (classic control with optimal controller tuning using Ziegler- Nichols rule with MATLAB SISOTool).

tuning using Ziegler- Nichols rule with MATLAB SISOTool). Fig. 16. Experimental results of current ripple for

Fig. 16. Experimental results of current ripple for different ac load power (the proposed control scheme using tuning 2).

ac load power (the proposed control scheme using tuning 2). Fig. 17. Experimental results of inverter

Fig. 17. Experimental results of inverter load operation at low load power (I acrms = 7 A, I FCmean = 25.6 A). (a) Voltage waveforms and (b) current waveforms with the proposed control scheme using tuning 2.

Fig. 17 provides the plots of the measured voltages (dc link, FC, and ac load) and currents (dc–dc converter, FC, and ac

load), when the mean FC current is 25.6 A (corresponding to a sinusoidal load current of 7 A rms); in this case, the computed FC current ripple is 1.85%. The plots of the measured voltages and currents when the mean FC current is 39.9 A (corresponding

to

a sinusoidal load current of 11 A rms) are shown in Fig. 18;

in

this case, the computed FC current ripple is 1.99%.

C.

Evaluation of the Conversion Efficiency

The efficiency of the power electronics converter has been experimentally evaluated for different operating powers; the re- sults, plotted in Fig. 19, show a mean efficiency of over 94%.

D. Evaluation of Dynamic Performance

The dynamic performance of the proposed strategy has been

experimentally verified confirming that the transient response

of the voltage controller is kept fast enough to maintain the dc-

link voltage and to warrant a correct ac load supply. Figs. 20 and 21 show the experimental results applying a transient load power by switching ON (see Fig. 20) and OFF (see Fig. 21) a

commercial light bulb. The reference of dc-link voltage was in- tentionally set to 196 V (<< 220 V) considering the low-power transient used in the test, and as expected, according to Fig. 3, the dc-link voltage was maintained over 180 V when the transient load power was introduced. This behavior can be only achieved

if the time response of the voltage controller is fast enough to

start a corrective action within one electric cycle (<17 ms).

A better response of voltage regulation will be obtained if the

reference of the dc-link voltage is set to 220 V as suggested in Fig. 4. As observed in Fig. 20(a), the dc-link voltage regulation is rapidly achieved (within 20 ms) without any overshoot or os- cillation. The voltage is once again set at the working value with a settling time of 35 ms (considering a 2% of error). As the commercial light bulbs used in this test present very low impedance when switched ON, their start-up power demand is three times higher than their nominal power; this fact permits to introduce a power transient near to 500 W using a single 150-W lamp. The results presented in Fig. 21 confirm the transient response of the proposed voltage controller when the load power falls down. For the power decreasing case, the dc-link voltage is well regulated, preventing from undesired overshoots or oscillations; and similarly to the previous case, the FC current is adjusted within a short time (<20 ms) following the ac load variations. In order to evaluate the dynamic response of the proposed controller face to the variations of the reference voltage, a square signal of 10 V at 1 Hz has been momentarily applied in a short period of time to the actual reference voltage. The results of the dc-link voltage tracking response are presented in Fig. 22(a); here the reference of dc-link voltage and the “mean” dc-link voltage obtained through the ADALINE low-pass filter bank (ADALINE-LPF) and used as the feedback signal are plotted. Fig. 22(b) shows the current and the voltage of the FC during the same time interval. The results of the step response of the entire conversion sys- tem have been used to compute the settling time. This computa- tion has been carried out by means of the MATLAB “lsiminfo”

304

304 Fig. 18. Experimental results of inverter load operation at low load power ( I F

Fig. 18. Experimental results of inverter load operation at low load power (I FCmean = 39.9 A). (a) Voltage waveforms and (b) current waveforms with the proposed control scheme using tuning 2.

waveforms with the proposed control scheme using tuning 2. Fig. 19. scheme using tuning 2). Experimental

Fig. 19.

scheme using tuning 2).

Experimental results of converter’s efficiency (the proposed control

function; the obtained result is 96 ms, which corresponds to a time constant of 24.6 ms (considering a first-order approxima- tion and a tacking error of 2%). In the results, it is important to remark that the system presents a time constant lower than two electric cycles. Also, it must be highlighted that in this study the bandwidth of the voltage control loop was set to 5 Hz, which permits a good tracking of the reference voltage; most of literature works use bandwidths lower than 10 Hz (much lower than 120 Hz) for the voltage control loop, e.g., the strategy of ripple reduction proposed in [8] and [9] has been evaluated with a bandwidth of voltage control loop of 1.2, 2, and 4 Hz, and the best results were obtained when 1.2 Hz was employed. In this study, a higher bandwidth is possible due to the use of the ADALINE low- pass filter bank, which permits to reduce the 120 Hz ripple of the voltage feedback signal without important delay improving

IEEE TRANSACTIONS ON ENERGY CONVERSION, VOL. 30, NO. 1, MARCH 2015

ON ENERGY CONVERSION, VOL. 30, NO. 1, MARCH 2015 Fig. 20. tion, and (b) FC current

Fig. 20.

tion, and (b) FC current and voltage. Power transient of 150 W by switching OFF a commercial light bulb.

Experimental results of transient response (a) dc-link voltage regula-

results of transient response (a) dc-link voltage regula- Fig. 21. tion, and (b) FC current and

Fig. 21.

tion, and (b) FC current and voltage. Power transient of +150 W by switching ON a commercial light bulb.

Experimental results of transient response (a) dc-link voltage regula-

CARDENAS et al.: DEVELOPMENT OF POWER INTERFACE WITH FPGA-BASED ADAPTIVE CONTROL FOR PEM-FC SYSTEM

305

WITH FPGA-BASED ADAPTIVE CONTROL FOR PEM-FC SYSTEM 305 Fig. 22. Experimental results of voltage controller response

Fig. 22. Experimental results of voltage controller response face to steps on the reference voltage: (a) dc-link voltage response; and (b) FC current and voltage.

the transient response and mitigating the steady-state ripple of the FC current.

VI. CONCLUSION

The development of a power interface for an FC system sup- plying an ac load has been presented. The proposed system includes a prototype of dc–dc and dc–ac converters, and all the control is implemented in FPGA. The proposed control includes the ADALINE&FLL structure implemented in hardware, which is used to control in parallel both the inverter and the SCBC. Additionally, a dc voltage droop scheme is adopted to improve the response of the dc–dc converter even with the low size of the HVC. The proposed system has been experimentally validated showing many advantages compared with classic solutions some of them are the low current ripple, the fast transient response, and a reduced dc-link capacitor compared to the classic and recently proposed alternative solutions. All control blocks have been embedded in a single FPGA device, working in parallel and sharing in real time the main variables information. This fact demonstrates the validity and potential of the proposed system by using modern digital control systems.

ACKNOWLEDGMENT

The authors would like to thank the Xilinx University Pro- gram for the hardware, software, and technical support.

REFERENCES

[1] K. Agbossou, M. Kolhe, J. Hamelin, and T. K. Bose, “Performance of a stand-alone renewable energy system based on energy storage as hy- drogen,” IEEE Trans. Energy Convers., vol. 19, no. 3, pp. 633–640, Sep. 2004. [2] A. Cardenas and K. Agbossou, “Experimental evaluation of voltage pos- itive feedback based anti-islanding algorithm: Multi-inverter case,” IEEE

[3]

[4]

Trans. Energy Convers., vol. 27, no. 2, pp. 498–506, Jun. 2012. W. Choi, P. N. Enjeti, J. W. Howze, and G. Joung, “An experimental eval- uation of the effects of ripple current generated by the power conditioning stage on a proton exchange membrane fuel cell stack,” J. Mater. Eng. Performance, vol. 13, no. 3, pp. 257–264, 2004. M. E. Schenck, J.-S. Lai, and K. Stanton, “Fuel cell and power conditioning system interactions,” in Proc. 20th Annu. IEEE Appl. Power Electron. Conf. Expo., 2005, pp. 114–120.

conditioning system interactions,” in Proc. 20th Annu. IEEE Appl. Power Electron. Conf. Expo. , 2005, pp.

[5] P. Thounthong, B. Davat, S. Ra el,¨ and P. Sethakul, “Fuel cell high- power applications,” IEEE Ind. Electron. Mag., vol. 3, no. 1, pp. 32–46, Mar. 2009.

[6] R. S. Gemmen, “Analysis for the effect of inverter ripple current on fuel cell operation condition,” J. Fluids Eng., vol. 125, no. 3, pp. 576–585,

2003.

[7] S. K. Mazumder, R. K. Burra, and K. Acharya, “A ripple-mitigating and energy-efficient fuel cell power-conditioning system,” IEEE Trans. Power Electron., vol. 22, no. 4, pp. 1437–1452, Jul. 2007. [8] C. Liu and J.-S. Lai, “Low frequency current ripple reduction technique with active control in a fuel cell power system with inverter load,” IEEE

Trans. Power Electron., vol. 22, no. 4, pp. 1429–1436, Jul. 2007. [9] C. Liu and J.-S. Lai, “Low frequency current ripple reduction technique with active control in a fuel cell power system with inverter load,” in Proc. IEEE 36th Power Electron. Spec. Conf., 2005, pp. 2905–2911. [10] L. Xiaohu, W. Zhan, and L. Hui, “A new fuel cell power conditioning system with extended life time and minimized DC-bus capacitor,” in Proc. 28th Annu. IEEE Appl. Power Electron. Conf. Expo., 2013, pp. 1926–1930. [11] R. Bojoi, C. Pica, D. Roiu, and A. Tenconi, “New DC–DC converter with reduced low-frequency current ripple for fuel cell in single-phase distributed generation,” in Proc. IEEE Int. Conf. Ind. Technol., 2010,

pp. 1213–1218.

[12] J.-I. Itoh and F. Hayashi, “Ripple current reduction of a fuel cell for a single-phase isolated converter using a dc active filter with a center tap,” IEEE Trans. Power Electron., vol. 25, no. 3, pp. 550–556, Mar. 2010.

G.-R. Zhu, S.-C. Tan, Y. Chen, and C. K. Tse, “Mitigation of low-frequency current ripple in fuel-cell inverter systems through waveform control,” IEEE Trans. Power Electron., vol. 28, no. 2, pp. 779–792, Feb. 2013.

[14] J.-H. Kim, K.-Y. Choi, and R.-Y. Kim, “A low frequency input current reduction scheme of a two-stage single-phase inverter with DC–DC boost converter,” in Proc. 29th Annu. IEEE Appl. Power Electron. Conf. Expo., 2014, pp. 2351–2358. [15] E. Monmasson, L. Idkhajine, M. N. Cirstea, I. Bahri, A. Tisan, and

[13]

 

M.

W. Naouar, “FPGAs in industrial control applications,” IEEE Trans

[16]

Ind. Informat., vol. 7, no. 2, pp. 224–243, May 2011. P. Patel and M. Moallem, “Reconfigurable system for real-time embedded control applications,” IET Control Theory Appl., vol. 4, no. 11, pp. 2506–

[17]

2515, Nov. 2010. C. Sepulveda, J. Munoz, J. R. Espinoza, M. Figueroa, and C. Baier, “FPGA v/s DSP performance comparison for a VSC-based STATCOM control application,” IEEE Trans Ind. Informat., vol. 9, no. 3, pp. 1351–1360, Aug. 2013.

[18] A. Cardenas, C. Guzman, and K. Agbossou, “Development of a FPGA based real-time power analysis and control for distributed generation interface,” IEEE Trans. Power Syst., vol. 27 no. 3, pp. 1343–1353,

Aug. 2012. [19] HyPM-XR-8 Installation, Operation and Maintenance Manual, Rev. 2, Hydrogenics Corp., Mississauga, ON, Canada, 2010. [20] B. Axelrod, Y. Berkovich, and A. Ioinovici, “Switched-capacitor/ switched-inductor structures for getting transformerless hybrid DC–DC PWM converters,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 55,

no. 2, pp. 687–696, Mar. 2008.

[21]

B. Axelrod, Y. Berkovich, A. Shenkman, and G. Golan, “Diode-capacitor

[22]

voltage multipliers combined with boost-converters: Topologies and char- acteristics,” IET Power Electron., vol. 5, no. 6, pp. 873–884, Jul. 2012. L. Wuhua, L. Xiaodong, D. Yan, L. Jun, and H. Xiangning, “A review of non-isolated high step-up DC/DC converters in renewable energy appli- cations,” in Proc. 24th Annu. IEEE Appl. Power Electron. Conf. Expo., 2009, pp. 364–369.

306

[23] R. Gules, L. L. Pfitscher, and L. C. Franco, “An interleaved boost DC– DC converter with large conversion ratio,” in Proc. IEEE Int. Symp. Ind. Electron, 2003, pp. 411–416. [24] X. Hu and C. Gong, “A high voltage gain DC–DC converter integrating coupled-inductor and diode–capacitor techniques,” IEEE Trans. Power Electron., vol. 29, no. 2, pp. 789–800, Feb. 2014.

[25] K.-I. Hwu and T.-J. Peng, “High-voltage-boosting converter with charge pump capacitor and coupling inductor combined with buck–boost con- verter,” IET Power Electron., vol. 7, no. 1, pp. 177–188, 2014.

Y. Tang, T. Wang, and Y. He, “A switched-capacitor-based active-network

converter with high voltage gain,” IEEE Trans. Power Electron., vol. 29, no. 6, pp. 2959–2968, Jun. 2014. [27] Y.-P. Hsieh, J.-F. Chen, L.-S. Yang, C.-Y. Wu, and W.-S. Liu, “High- conversion-ratio bidirectional dc–dc converter with coupled inductor,” IEEE Trans. Ind. Electron., vol. 61, no. 1, pp. 210–222, Jan. 2014. [28] W. Li, W. Li, X. Xiang, Y. Hu, and X. He, “High step-up interleaved converter with built-in transformer voltage multiplier cells for sustain- able energy applications,” IEEE Trans. Power Electron., vol. 29, no. 6, pp. 2829–2836, Jun. 2014. [29] M. Ohshima and E. Masada, “The P, Q controllable domain of a single phase PWM converter to preserve sinusoidal AC current waveform,” in Proc. 29th Annu. IEEE Power Electron. Spec. Conf., 1998, pp. 1612–1618. [30] IEEE Standard for Interconnecting Distributed Resources with Electric Power Systems, IEEE Standard 1547-2003, Jul. 2003. [31] C. Guzman, A. Cardenas, and K. Agbossou, “Control of voltage source

[26]

inverter using FPGA implementation of ADALINE-FLL,” in Proc. 38th Annu. Conf. IEEE Ind. Electron. Soc., 2012, pp. 3037–3042. [32] K. H. Ang, G. Chong, and Y. Li, “PID control system analysis, de- sign, and technology,” IEEE Trans. Control Syst. Technol., vol. 13, no. 4, pp. 559–576, Jul. 2005. [33] Xilinx Inc. (2013, May). Xilinx University Program XUPV5- LX110T Development System [Online]. Available: http://www.xilinx.com/

univ/xupv5-lx110t.htm

Alben Cardenas (S’09–M’12) received the B.S. degree in electronic engineering from the Antonio Narino˜ University, Villavicencio, Colombia, in 2003, and the M.S. and PhD. degrees in electrical engineer- ing from the Universite´ du Quebec´ a` Trois-Rivieres` (UQTR), Trois-Rivieres,` QC, Canada, in 2008 and 2012, respectively. He is currently a Researcher at the Hydrogen Re- search Institute (HRI), and a Lecturer in the Electri- cal and Computer Engineering Department, UQTR. His current research interests include renewable en- ergy, distributed generation, power electronics, and very large scale integration (VLSI) technologies for energy conversion and power quality applications. Dr. Cardenas is a Member of the Ordre des Ingenieurs´ du Quebec,´ and a Member of the IEEE Power and Energy Society and the IEEE Industrial Elec- tronics Society.

Society and the IEEE Industrial Elec- tronics Society. IEEE TRANSACTIONS ON ENERGY CONVERSION, VOL. 30, NO.

IEEE TRANSACTIONS ON ENERGY CONVERSION, VOL. 30, NO. 1, MARCH 2015

Kodjo Agbossou (M’98–SM’01) received the B.S., M.S., and Ph.D. degrees in electronic measurements from the Universite´ de Nancy I, Nancy, France, in 1987, 1989, and 1992, respectively. He is currently the Head of the Engineer- ing School, Universite´ du Quebec´ a` Trois-Rivieres` (UQTR), Trois-Rivieres,` QC, Canada. He was a Post- doctoral Research Fellow in the Electrical Engineer- ing Department, UQTR (1993–1994), where he was a Lecturer (1997–1998). Since 1998, he has been an Associate Professor, and since 2004, he has been a Full Professor in the Electrical and Computer Engineering Department, UQTR. He was the Head of the Electrical and Computer Engineering Department. He was also the Director of Graduate Studies in Electrical Engineering. He is the author or coauthor of more than 180 publications and has 4 patents. His current research include in the areas of renewable energy, smart grid, integration of hydrogen production, storage and electrical energy generation system, hybrid electrical vehicle, control, and measurements. He is a member of the Hydrogen Research Institute and Research group “Group de reserche en electronique´ in- dustrielle (GREI)”, UQTR. Dr. Agbossou is a Member of the IEEE Power and Energy Society, the In- dustry Applications Societies, the Communications Society, and the Industrial Electronics Society Technical Committee on Renewable Energy Systems. He was the Chair of the IEEE Section Saint Maurice, QC, Canada. He is a Profes- sional Engineer and joined the Ordre des Ingenieurs´ du Quebec´ in 1998.

joined the Ordre des Ingenieurs´ du Qu ebec ´ in 1998. Nilson Henao (S’14) received the

Nilson Henao (S’14) received the B.S. degree in electronics engineering from the Universidad de los Llanos, Villavicencio, Colombia, in 2010, and the M.Sc. degree in electrical engineering from the Uni- versity of Quebec at Trois-Rivieres (UQTR), Trois- Rivieres, QC, Canada in 2013, where he is currently working toward the Ph.D. degree with the Depart- ment of Electrical and Computer Engineering. His current research interests include fuel cell con- trol and optimization, and energy management for hy- brid electric vehicles. He is currently involved in ma- chine learning techniques for nonintrusive appliance load monitoring (NIALM) to disaggregate and track device electrical signatures.

techniques for nonintrusive appliance load monitoring (NIALM) to disaggregate and track device electrical signatures.