Counter&Reg

16-Jun-15
Digital Electronics
(EEE 365)
Muhammad Asad Rahman
Asst. Prof., Dept. of EEE
CUET
http:/asad31.webs.com
1
Sequential Logic
Counters and Registers
Counters
Registers
2
16-Jun-15
Introduction: Counters
Counters are circuits that cycle through a specified
number of states.
Two types of counters:

synchronous (parallel) counters
asynchronous (ripple) counters
Ripple counters allow some flip-flop outputs to be used

as a source of clock for other flip-flops.
Synchronous counters apply the same clock to all flipflops.
16-Jun-15
Digital Systems Principles & Applications

by R. J. Tocci
Asynchronous (Ripple) Counters

Asynchronous counters: the flip-flops do not change
states at exactly the same time as they do not have a
common clock pulse.
Also known as ripple counters, as the input clock pulse

ripples through the counter cumulative delay is a
drawback.
n flip-flops a MOD (modulus) 2n counter. (Note: A

MOD-x counter cycles through x states.)
Output of the last flip-flop (MSB) divides the input clock

frequency by the MOD number of the counter, hence a
counter is also a frequency divider.
16-Jun-15

by R. J. Tocci
16-Jun-15

Example: 2-bit ripple binary counter.
Output of one flip-flop is connected to the clock input of
the next more-significant flip-flop.
HIGH
Q0
J
C
K
CLK
C
K
Q0
FF0
CLK
Q1
FF1
Q0
Timing diagram
Q0
Q1
00 01 10 11 00 ...

by R. J. Tocci
16-Jun-15

Example: 3-bit ripple binary counter.
HIGH
Q0
J
C
K
CLK
C
K
Q0
FF0
CLK
Q1
C
K
Q1
FF2
FF1
Q2
Q0
Q1
Q2
0
Recycles back to 0
16-Jun-15

by R. J. Tocci
16-Jun-15

Example: 4-bit ripple binary counter (negative-edge
triggered).
HIGH
Q0
J
C
K
CLK
Q1
C
K
FF0
Q2
C
K
FF1
Q3
C
K
FF2
FF3
CLK
1
10 11 12 13 14 15 16
Q0
Q1
Q2
Q3
by R. J. Tocci
16-Jun-15
Propagation delay in Ripple Counters
Propagation delays in an asynchronous (ripple-clocked)

binary counter.
If the accumulated delay is greater than the clock pulse,

some counter states may be misrepresented!
CLK
Q0
Q1
Q2
tPLH
(CLK to Q0)
16-Jun-15
tPHL (CLK to Q0)

tPLH (Q0 to Q1)

by R. J. Tocci
tPHL (CLK to Q0)

tPHL (Q0 to Q1)
tPLH (Q1 to Q2)
16-Jun-15
Propagation delay in Ripple Counters

For proper counter operation
Tclock Ntpd
Where N = number of FFs.
100 ns
CLK
Q0
Q1
Q2
50 ns
50 ns
50 ns
The 100 condition
does not occur.

by R. J. Tocci
16-Jun-15
Asyn. Counters with MOD no. < 2
States may be skipped resulting in a truncated

sequence.
Technique: force counter to recycle before going

through all of the states in the binary sequence.
Example: Given the following circuit, determine the

counting sequence (and hence the modulus no.)
C
All J, K
inputs
are 1
(HIGH).
16-Jun-15
CLK
K
Q
CLR
CLK
K
Q
CLR
CLK
K
Q
CLR
B
C

by R. J. Tocci
10
16-Jun-15
Example (contd):
C
CLK
K
Q
CLR
All J, K
inputs
are 1
(HIGH).
Clock
CLK
K
Q
CLR
CLK
K
Q
CLR
B
C
1
10 11 12
MOD-6 counter
produced by
clearing (a MOD-8
binary counter)
when count of six
(110) occurs.
A
B
C
NAND 1
Output 0
by R. J. Tocci
16-Jun-15
11
Example (contd): Counting sequence of circuit (in CBA

order).
1
Clock
A 0
0 1
0 1
B 0
0 0
0 0
C 0
NAND 1
Output 0
1 1
0 0
Temporary
state
111
10 11 12
000
001
110
010
101
Counter is a MOD-6
counter.
011
100
16-Jun-15

by R. J. Tocci
12
16-Jun-15
Exercise: How to construct an asynchronous MOD-5

counter? MOD-7 counter? MOD-12 counter?
Question: The following is a MOD- ? counter?

F
K
CLR
K
CLR
K
CLR
K
CLR
C
D
E
F
K
CLR
K
CLR
All J = K = 1.

by R. J. Tocci
16-Jun-15
13
Decade counters (or BCD counters) are counters with 10

states (modulus-10) in their sequence.
They are
commonly used in daily life (e.g.: utility meters, digital
clock, etc.).
Design an asynchronous decade counter.

(A.C)'
HIGH
J
CLK
16-Jun-15
K
CLR
K
CLR
K
CLR
K
CLR

by R. J. Tocci
14
16-Jun-15
Asynchronous decade/BCD counter (contd).

HIGH
C
K
CLK
C
K
CLR
Clock
C
K
CLR
(A.C)'
C
K
CLR
CLR
10
D 0
C 0
B 0
A 0
11
NAND
output
by R. J. Tocci
16-Jun-15
15
Asynchronous Down Counters

So far we are dealing with up counters. Down counters,
on the other hand, count downward from a maximum
value to zero, and repeat.
Example: A 3-bit binary (MOD-23) down counter.

1
J
CLK
Q0
Q1
C
K Q'
C
Q'
K
Q2
C
K Q'
3-bit binary
up counter
1
J
CLK
16-Jun-15
C
Q'
K
Q0
C
K Q'
Q1
Q2
C
K Q'

by R. J. Tocci
3-bit binary
down counter
16
16-Jun-15
Asynchronous Down Counters

Example: A 3-bit binary (MOD-8) down counter.
000
1
J
CLK
Q0
Q1
C
K Q'
C
Q'
K
111
001
Q2
C
K Q'
010
110
011
101
100
CLK
Q0
Q1
Q2

by R. J. Tocci
16-Jun-15
17
Cascading Asynchronous Counters

Larger
asynchronous (ripple) counter can

constructed by cascading smaller ripple counters.
be
Connect last-stage output of one counter to the clock

input of next counter so as to achieve higher-modulus
operation.
Example: A modulus-32 ripple counter constructed from

a modulus-4 counter and a modulus-8 counter.
Q0
J
CLK
Q
C
Q'
K
Q1
J
Q
C
K Q'
Modulus-4 counter
16-Jun-15
Q2
J
Q
C
Q'
K
Q3
J
Q
C
K Q'
Q4
J
Q
C
K Q'
Modulus-8 counter

by R. J. Tocci
18
16-Jun-15

Example: A 6-bit binary counter (counts from 0 to 63)
constructed from two 3-bit counters.
A0
Count
pulse
A1
A2
A3
3-bit
binary counter
A4
A5
3-bit
binary counter
A5
A4
A3
A2
A1
A0
0
0
0
0
0
0
:
0
0
0
0
0
0
:
0
0
0
0
1
1
:
0
0
:
1
0
0
:
0
0
:
1
0
0
:
0
1
:
1
0
1
:

by R. J. Tocci
16-Jun-15
19

To count large decimal values, we can cascade BCD
counter stages as shown in Figure.
Example: Cascading BCD counters to count and display

numbers from 000 to 999
Display
A3
16-Jun-15
0-9
A2 A1 A0
Display
A3
0-9
Display
A2 A1 A0
A3
0-9
A2 A1 A0
BCD
counter
BCD
counter
BCD
counter
Hundreds
Tens
Units

by R. J. Tocci
Count
pulse
20
10
16-Jun-15
Synchronous (Parallel) Counters

Synchronous (parallel) counters: the flip-flops are
clocked at the same time by a common clock pulse.
We can design these counters using the sequential logic

design process (covered in previous lecture).
Example: 2-bit synchronous binary counter (using T flipflops, or JK flip-flops with identical J,K inputs).
00
01
11
10
Present
state
Next
state
Flip-flop
inputs
A1 A0
0
0
0
1
1
0
1
1
A1+ A0+
0
1
1
0
1
1
0
0
TA1 TA0
0
1
1
1
0
1
1
1

by R. J. Tocci
16-Jun-15
21

Example: 2-bit synchronous binary counter (using T flipflops, or JK flip-flops with identical J,K inputs).
Present
state
Next
state
Flip-flop
inputs
A1 A0
0
0
0
1
1
0
1
1
A1+ A0+
0
1
1
0
1
1
0
0
TA1 TA0
0
1
1
1
0
1
1
1
TA1 = A0
TA0 = 1
1
J
C
Q'
K
A0
A1
C
K Q'
CLK
16-Jun-15

by R. J. Tocci
22
11
16-Jun-15

Example: 3-bit synchronous binary counter (using T flipflops, or JK flip-flops with identical J, K inputs).
Present
state
A2 A1 A0
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
A2+
0
0
0
1
1
1
1
0
Next
state
A1+
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
A1
A1
1
A2
Flip-flop
inputs
TA2 TA1 TA0
0
0
1
0
1
1
0
0
1
1
1
1
0
0
1
0
1
1
0
0
1
1
1
1
A0+
A2
1
A0
A1
A2
A0
TA2 = A1.A0
A0
TA1 = A0
TA0 = 1

by R. J. Tocci
16-Jun-15
23

Example: 3-bit synchronous binary counter (contd).
TA2 = A1.A0
TA1 = A0
TA0 = 1
A2
A1
Q
J
A0
Q
J
Q
J
CP
1
16-Jun-15

by R. J. Tocci
24
12
16-Jun-15

Note that in a binary counter, the nth bit (shown
underlined) is always complemented whenever
01111 10000
11111 00000
or
Hence, Xn is complemented whenever

Xn-1Xn-2 ... X1X0 = 1111.
As a result, if T flip-flops are used, then

TXn = Xn-1 . Xn-2 . ... . X1 . X0

by R. J. Tocci
16-Jun-15
25

Example: 4-bit synchronous binary counter.
TA3 = A2 . A1 . A0
TA2 = A1 . A0
TA1 = A0
TA0 = 1
A1.A0
1
J
C
Q'
K
A0
C
K Q'
A1
A2.A1.A0
Q
A2
C
K Q'
A3
C
K Q'
CLK
16-Jun-15

by R. J. Tocci
26
13
16-Jun-15

Example: Synchronous decade/BCD counter.
Clock pulse
Q3
Q2
Q1
Q0
Initially
1
2
3
4
5
6
7
8
9
10 (recycle)
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
0
0
0
0
1
0
1
0
1
0
1
0
1
0
T0 = 1
T1 = Q3'.Q0
T2 = Q1.Q0
T3 = Q2.Q1.Q0 + Q3.Q0

by R. J. Tocci
16-Jun-15
27

Example: Synchronous decade/BCD counter (contd).
T0 = 1
T1 = Q3'.Q0
T2 = Q1.Q0
T3 = Q2.Q1.Q0 + Q3.Q0
Q0
1
T
C
Q
Q'
T
C
Q
Q'
Q1
T
C
Q2
Q'
T
C
Q3
Q'
CLK
16-Jun-15

by R. J. Tocci
28
14
16-Jun-15
Propagation Delay in Sync. Counters

For a synchronous counter,
total delay = FF tpd + AND gate tpd
Q0
1
T
C
Q
Q'
T
C
Q1
Q'
T
C
Q2
Q'
T
C
Q3
Q'
CLK
16-Jun-15

by R. J. Tocci
29
Up/Down Synchronous Counters

Up/down synchronous counter: a bidirectional counter
that is capable of counting either up or down.
An input (control) line Up/Down (or simply Up) specifies

the direction of counting.
Up/Down = 1 Count upward
Up/Down = 0 Count downward
16-Jun-15

by R. J. Tocci
30
15
16-Jun-15

Example: A 3-bit up/down synchronous binary counter.
Clock pulse
Up
Q2
Q1
Q0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
2
3
4
5
6
7
Down
Up counter
TQ0 = 1
TQ1 = Q0
TQ2 = Q0.Q1
TQ0 = 1
TQ1 = (Q0.Up) + (Q0'.Up' )
TQ2 = ( Q0.Q1.Up ) + (Q0'. Q1'. Up' )
Down counter
TQ0 = 1
TQ1 = Q0
TQ2 = Q0.Q1

by R. J. Tocci
16-Jun-15
31

Example: A 3-bit up/down synchronous binary counter
(contd).
TQ0 = 1
TQ1 = (Q0.Up) + (Q0'.Up' )
TQ2 = ( Q0.Q1.Up ) + (Q0'. Q1'. Up' )
Q0
Up/down
T
C
Q
Q'
Q1
T
C
Q
Q'
T
C
Q2
Q'
CLK
16-Jun-15

by R. J. Tocci
32
16
16-Jun-15
Designing Synchronous Counters

Covered in previous lecture.
Example: A 3-bit Gray code
000
001
100
101
counter (using JK flip-flops).
011
111
010
110
Present
state
Q2 Q1 Q0
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Q2 +
0
0
1
0
0
1
1
1
Next
state
Q1 +
0
1
1
1
0
0
1
0
Q0 +
1
1
0
0
0
0
1
1
JQ2 KQ2
0
X
0
X
1
X
0
X
X
1
X
0
X
0
X
0
Flip-flop
inputs
JQ1 KQ1 JQ0 KQ0
0
X
1
X
1
X
X
0
X
0
0
X
X
0
X
1
0
X
0
X
0
X
X
1
X
0
1
X
X
1
X
0

by R. J. Tocci
16-Jun-15
33

3-bit Gray code counter: flip-flop inputs.
Q2
Q 1Q 0
00
01 11
0
1
10
1
Q2
00
0 X
01 11
X X
10
X
1 1
KQ2 = Q1'.Q0'
16-Jun-15
01 11
1
X
10
X
Q 1Q 0
00
0
JQ1 = Q2'.Q0
JQ2 = Q1.Q0'
Q2
Q 1Q 0
Q2
Q 1Q 0
00
0 X
01 11
X
1 X
10
Q2
00
0 1
01 11
X X
10
JQ0 = Q2.Q1 + Q2'.Q1'

= (Q2 Q1)'
Q2
KQ1 = Q2.Q0
Q 1Q 0
Q 1Q 0
00
0 X
01 11
1
10
X
1 X
KQ0 = Q2.Q1' + Q2'.Q1

= Q2 Q1

by R. J. Tocci
34
17
16-Jun-15

3-bit Gray code counter: logic diagram.
JQ2 = Q1.Q0'
KQ2 = Q1'.Q0'
Q0
C
K Q'
CLK
16-Jun-15
JQ0 = (Q2 Q1)'

KQ0 = Q2 Q1
JQ1 = Q2'.Q0
KQ1 = Q2.Q0
Q0
'
Q1
C
Q1
K Q' '

by R. J. Tocci
C
K Q'
Q2
Q2
'
35
Decoding A Counter
Decoding a counter involves determining which state in
the sequence the counter is in.
Differentiate between active-HIGH and active-LOW

decoding.
Active-HIGH decoding: output HIGH if the counter is in

the state concerned.
Active-LOW decoding: output LOW if the counter is in

the state concerned.
16-Jun-15

by R. J. Tocci
36
18
16-Jun-15
Decoding A Counter
Example: MOD-8 ripple counter (active-HIGH decoding).
Clock
10
A'
B'
C'
HIGH only on
count of ABC = 000
A'
B'
C
HIGH only on
count of ABC = 001
A'
B
C'
HIGH only on
count of ABC = 010
.
.
.
A
B
C
HIGH only on
count of ABC = 111

by R. J. Tocci
16-Jun-15
37
Decoding A Counter
Example: To detect that a MOD-8 counter is in state 0
(000) or state 1 (001).
A'
B'
C'
A'
B'
C
Clock
10
HIGH only on
count of ABC = 000
or ABC = 001
A'
B'
Example: To detect that a MOD-8 counter is in the odd

states (states 1, 3, 5 or 7), simply use C.
Clock
C
16-Jun-15
10
HIGH only on count

of odd states
by R. J. Tocci
38
19
16-Jun-15
Counters with Parallel Load

Counters could be augmented with parallel load
capability for the following purposes:
To start at a different state
To count a different sequence
As more sophisticated register with increment/decrement
functionality.
16-Jun-15
Digital Logic & Computer Design

by M. Morris Mano
39

4-bit counter with
parallel load.
Clear CP Load Count
Function
0
X
X
X
Clear to 0
1
X
0
0
No change
1
1
X
Load inputs
1
0
1
Next state
16-Jun-15

by M. Morris Mano
40
20
16-Jun-15

Different ways of getting a MOD-6 counter:
A4 A3 A2 A1
Load
I4 I3 I2 I1
A4 A3 A2 A1
Count = 1
Clear = 1
CP
I4 I3 I2 I1
Inputs = 0
Inputs have no effect
(a) Binary states 0,1,2,3,4,5.
(b) Binary states 0,1,2,3,4,5.
A4 A3 A2 A1
A4 A3 A2 A1
Carry-out
Load
I4 I3 I2 I1
Count = 1
Clear = 1
CP
Load
I4 I3 I2 I1
1 0 1 0
Count = 1
Clear = 1
CP
0 0 1 1
(c) Binary states 10,11,12,13,14,15.

16-Jun-15
Count = 1
Load = 0
CP
Clear
(d) Binary states 3,4,5,6,7,8.

by M. Morris Mano
41
Introduction: Registers
An n-bit register has a group of n flip-flops and some
logic gates and is capable of storing n bits of information.
The flip-flops store the information while the gates

control when and how new information is transferred into
the register.
Some functions of register:

retrieve data from register
store/load new data into register (serial or parallel)
shift the data within register (left or right)
16-Jun-15

by M. Morris Mano
42
21
16-Jun-15
Simple Registers
No external gates.
Example: A 4-bit register. A new 4-bit data is loaded
every clock cycle.
A3
A2
A1
A0
I3
I2
I1
I0
CP
16-Jun-15

by M. Morris Mano
43
Registers With Parallel Load

Instead of loading the register at every clock pulse, we
may want to control when to load.
Loading a register: transfer new information into the

register. Requires a load control input.
Parallel loading: all bits are loaded simultaneously.
16-Jun-15

by M. Morris Mano
44
22
16-Jun-15
Registers With Parallel Load

Load'.A0 + Load. I0
Load
D Q
A0
D Q
A1
D Q
A2
D Q
A3
I0
I1
I2
I3
CLK
CLEAR
by M. Morris Mano
16-Jun-15
45
Using Registers to implement Sequential Circuits

A sequential circuit may consist of a register (memory)
and a combinational circuit.
Next-state value
Register
Clock
Combinational
circuit
Inputs
Outputs
The external inputs and present states of the register

determine the next states of the register and the external
outputs, through the combinational circuit.
The combinational circuit may be implemented by any of

the methods covered in MSI
Programmable Logic Devices.
16-Jun-15

by M. Morris Mano
components
and
46
23
16-Jun-15
Example 1:
A1+ = m(4,6) = A1.x'
A2+ = m(1,2,5,6) = A2.x' + A2'.x = A2 x
y = m(3,7) = A2.x
Present
state
A1 A2
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
Input
x
0
1
0
1
0
1
0
1
Next
State
A1+ A2+
0
0
0
1
0
1
0
0
1
0
0
1
1
1
0
0
Output
y
0
0
0
1
0
0
0
1
A1.x' A
1
A2x
A2
y

by M. Morris Mano
16-Jun-15
47

Example 2: Repeat example 1, but use a ROM.
Address
1
2
3
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
1
0
0
0
0
1
0
1
0
Outputs
2
3
0
0
1
0
1
0
0
1
0
0
1
0
1
0
0
1
A1
A2
x
1
2
3
8x3
ROM
2
3
ROM truth table
16-Jun-15

by M. Morris Mano
48
24
16-Jun-15
Shift Registers
Another function of a register, besides storage, is to
provide for data movements.
Each stage (flip-flop) in a shift register represents one

bit of storage, and the shifting capability of a register
permits the movement of data from stage to stage within
the register, or into or out of the register upon
application of clock pulses.

by M. Morris Mano
16-Jun-15
49
Shift Registers
Basic data movement in shift registers (four bits are
used for illustration).
Data in
Data out
(a) Serial in/shift right/serial out

Data in
Data out
(b) Serial in/shift left/serial out

Data in
Data in
Data out
(c) Parallel in/serial out
Data in
Data out
(d) Serial in/parallel out

Data out
(e) Parallel in /
parallel out
(f) Rotate right
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(g) Rotate left

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Serial In/Serial Out Shift Registers

Accepts data serially one bit at a time and also
produces output serially.
Serial data
input
D Q
Q0
D Q
Q1
D Q
Q2
D Q
Q3
Serial data
output
CLK

by M. Morris Mano
16-Jun-15
51

Application: Serial transfer of data from one register to
another.
SI
Clock
Shift control
Shift register A
SO
SI
Shift register B
SO
CP
Clock
Shift
control
CP
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Wordtime
T1
T2
T3
T4

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Serial-transfer example.
SI
Initial value
After T1
After T2
After T3
After T4
SI
Shift register B
SO
CP
Clock
Shift control
Timing Pulse
SO
Shift register A
Shift register A
1
1
1
0
1
0
1
1
1
0
1
0
1
1
1
Shift register B
1
1
0
1
1
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
Serial output of B
0
1
0
0
1
0
1
0
0
1

by M. Morris Mano
16-Jun-15
53
Serial In/Parallel Out Shift Registers

Accepts data serially.
Outputs of all stages are available simultaneously.
Data input
D Q
D Q
D Q
D Q
CLK
Q0
Q1
Data input
CLK
Q2
Q3
SRG 4
Logic symbol
C
Q0 Q1 Q2 Q3
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16-Jun-15
Parallel In/Serial Out Shift Registers

Bits are entered simultaneously, but output is serial.
Data input
D0
D1
D2
D3
SHIFT/LOAD
D Q
C
D Q
Q0
Q1
D Q
C
Q2
D Q
C
Serial
data
Q3 out
CLK
SHIFT.Q0 + SHIFT'.D1

by M. Morris Mano
16-Jun-15
55
Parallel In/Serial Out Shift Registers

Bits are entered simultaneously, but output is serial.
Data in
D0 D1 D2 D3
SHIFT/LOAD
CLK
SRG 4
C
Serial data out
Logic symbol
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by M. Morris Mano
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16-Jun-15
Parallel In/Parallel Out Shift Registers

Simultaneous input and output of all data bits.
Parallel data inputs
D0
D1
D2
D3
D Q
D Q
D Q
D Q
CLK
Q0
Q1
Q2
Q3
Parallel data outputs

by M. Morris Mano
16-Jun-15
57
Bidirectional Shift Registers

Data can be shifted either left or right, using a control
line RIGHT/LEFT (or simply RIGHT) to indicate the
direction.
RIGHT/LEFT
Serial
data in
RIGHT.Q0 +
RIGHT'.Q2
D Q
D Q
Q1
D Q
C
Q2
D Q
Q3
Q0
CLK
16-Jun-15

by M. Morris Mano
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16-Jun-15

4-bit bidirectional shift register with parallel load.
Parallel outputs
Clear
A4
A3
A2
A1
CLK
s1
s0
Serial
input for
shift-right
4x1
MUX
3 2 1 0
4x1
MUX
3 2 1 0
4x1
MUX
3 2 1 0
4x1
MUX
3 2 1 0
I4
I3
I2
I1
Serial
input for
shift-left
Parallel inputs
by M. Morris Mano
16-Jun-15
59

4-bit bidirectional shift register with parallel load.
Mode Control
s1
s0
0
0
1
1
16-Jun-15
0
1
0
1
Register Operation
No change
Shift right
Shift left
Parallel load

by M. Morris Mano
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30
16-Jun-15
An Application Serial Addition

Most operations in digital computers are done in
parallel. Serial operations are slower but require less
equipment.
A serial adder is shown below. A A + B.

SI
Shift-right
CP
External input
Shift-register A
SI
Shift-register B
SO
x
S
y FA
C
z
SO
Q D
Clear
by M. Morris Mano
16-Jun-15
61
An Application Serial Addition

A = 0100; B = 0111. A + B = 1011 is stored in A after 4
clock pulses.
16-Jun-15
Initial:
A: 0 1 0 0
B: 0 1 1 1
Q: 0
Step 1: 0 + 1 + 0
S = 1, C = 0
A: 1 0 1 0
B: x 0 1 1
Q: 0
Step 2: 0 + 1 + 0
S = 1, C = 0
A: 1 1 0 1
B: x x 0 1
Q: 0
Step 3: 1 + 1 + 0
S = 0, C = 1
A: 0 1 1 0
B: x x x 0
Q: 1
Step 4: 0 + 0 + 1
S = 1, C = 0
A: 1 0 1 1
B: x x x x
Q: 0

by M. Morris Mano
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16-Jun-15
Shift Register Counters

Shift register counter: a shift register with the serial
output connected back to the serial input.
They are classified as counters because they give a

specified sequence of states.
Two common types: the Johnson counter and the Ring

counter.
16-Jun-15

by M. Morris Mano
63
Ring Counters
One flip-flop (stage) for each state in the sequence.
The output of the last stage is connected to the D input
of the first stage.
An n-bit ring counter cycles through n states.

No decoding gates are required, as there is an output
that corresponds to every state the counter is in.
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by M. Morris Mano
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16-Jun-15
Ring Counters
Example: A 6-bit (MOD-6) ring counter.
PRE
D Q
Q0
D Q
Q1
D Q
Q2
D Q
Q3
D Q
Q4
D Q
Q5
CLR
CLK
Clock
0
1
2
3
4
5
16-Jun-15
Q0
1
0
0
0
0
0
Q1
0
1
0
0
0
0
Q2
0
0
1
0
0
0
Q3
0
0
0
1
0
0
Q4
0
0
0
0
1
0
Q5
0
0
0
0
0
1
100000
000001
010000
000010
001000
000100

by M. Morris Mano
65
Johnson Counters
The complement of the output of the last stage is
connected back to the D input of the first stage.
Also called the twisted-ring counter.

Require fewer flip-flops than ring counters but more flipflops than binary counters.
An n-bit Johnson counter cycles through 2n states.

Require more decoding circuitry than ring counter but
less than binary counters.
16-Jun-15

by M. Morris Mano
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16-Jun-15
Johnson Counters
Example: A 4-bit (MOD-8) Johnson counter.
D Q
Q0
D Q
Q1
Q2
D Q
D Q
Q'
Q3'
CLR
CLK
Q0
0
1
1
1
1
0
0
0
Clock
0
1
2
3
4
5
6
7
Q1
0
0
1
1
1
1
0
0
Q2
0
0
0
1
1
1
1
0
Q3
0
0
0
0
1
1
1
1
0000
0001
1000
0011
1100
0111
1110
1111

by M. Morris Mano
16-Jun-15
67
Johnson Counters
Decoding logic for a 4-bit Johnson counter.
Clock
0
1
2
3
4
5
6
7
16-Jun-15
A
0
1
1
1
1
0
0
0
B
0
0
1
1
1
1
0
0
C
0
0
0
1
1
1
1
0
D
0
0
0
0
1
1
1
1
Decoding
A'.D'
A.B'
B.C'
C.D'
A.D
A'.B
B'.C
C'.D
A'
D'
State 0
A
B'
State 1
B
C'
State 2
C
D'
State 3
B'
C
State 6
A
D
State 4
C'
D
State 7
A'
B
State 5

by M. Morris Mano
68
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16-Jun-15
The End
35

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16-Jun-15

Two types of counters:

Ripple counters allow some flip-flop outputs to be used

Synchronous counters apply the same clock to all flipflops.

Digital Systems Principles & Applications

Asynchronous (Ripple) Counters

Also known as ripple counters, as the input clock pulse

n flip-flops a MOD (modulus) 2n counter. (Note: A

Output of the last flip-flop (MSB) divides the input clock

Digital Systems Principles & Applications

Asynchronous (Ripple) Counters

Digital Systems Principles & Applications

Asynchronous (Ripple) Counters

Digital Systems Principles & Applications

Asynchronous (Ripple) Counters

Propagation delay in Ripple Counters

Propagation delays in an asynchronous (ripple-clocked)

If the accumulated delay is greater than the clock pulse,

tPHL (CLK to Q0)

Digital Systems Principles & Applications

tPHL (CLK to Q0)

Propagation delay in Ripple Counters

Digital Systems Principles & Applications

Asyn. Counters with MOD no. < 2

States may be skipped resulting in a truncated

Technique: force counter to recycle before going

Example: Given the following circuit, determine the

Digital Systems Principles & Applications

Asyn. Counters with MOD no. < 2

Asyn. Counters with MOD no. < 2

Example (contd): Counting sequence of circuit (in CBA

Digital Systems Principles & Applications

Asyn. Counters with MOD no. < 2

Exercise: How to construct an asynchronous MOD-5

Question: The following is a MOD- ? counter?

Digital Systems Principles & Applications

Asyn. Counters with MOD no. < 2

Decade counters (or BCD counters) are counters with 10

Design an asynchronous decade counter.

Digital Systems Principles & Applications

Asyn. Counters with MOD no. < 2

Asynchronous decade/BCD counter (contd).

Asynchronous Down Counters

Example: A 3-bit binary (MOD-23) down counter.

Digital Systems Principles & Applications

Asynchronous Down Counters

Digital Systems Principles & Applications

Cascading Asynchronous Counters

asynchronous (ripple) counter can

Connect last-stage output of one counter to the clock

Example: A modulus-32 ripple counter constructed from

Digital Systems Principles & Applications

Cascading Asynchronous Counters

Digital Systems Principles & Applications

Cascading Asynchronous Counters

Example: Cascading BCD counters to count and display

Digital Systems Principles & Applications

Synchronous (Parallel) Counters

We can design these counters using the sequential logic

Digital Systems Principles & Applications

Synchronous (Parallel) Counters

Digital Systems Principles & Applications

Synchronous (Parallel) Counters

Digital Systems Principles & Applications

Counter&Reg

Counter&Reg