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Experiment Number - 3
Objective Write a VHDL programme to implement a 4*1 Multiplexer (MUX) using if else logic.

Practical Significance HDL (Hardware Description Language) based design has established itself as the
modern approach to design of digital systems, with VHDL (VHSIC Hardware Description
Language) and Verilog HDL being the two dominant HDLs.

Resources Required Computer System, Software : Xilinx ise 9.2i, Book:Digital Logic and Computer
Design by M. Morris Mano.

Principle Of Experiment A multiplexer is a combinational circuit that selects binary information from one of
many input lines and directs it to a single output line. The selection of a particular input line is
controlled by a set of selection lines. Normally, there are 2^n input lines and n selection lines whose
bit combinations determine which input is selected.
A four-to-one-line multiplexer is shown in Fig. (a). Each of the four inputs, I0 through
I3, is applied to one input of an AND gate. Selection lines S1 and S0 are decoded to select a
particular AND gate. The outputs of the AND gates are applied to a single OR gate that provides the
one-line output. The function table lists the input that is passed to the output for each combination of
the binary selection values. To demonstrate the operation of the circuit, consider the case when S1S0
= 10. The AND gate associated with input I2 has two of its inputs equal to 1 and the third input
connected to I2. The other three AND gates have at least one input equal to 0, which makes their
outputs equal to 0. The output of the OR gate is now equal to the value of I2, providing a path from
the selected input to the output. A multiplexer is also called a data selector , since it selects one of
many inputs and steers the binary information to the output line.
The AND gates and inverters in the multiplexer resemble a decoder circuit, and
indeed, they decode the selection input lines. In general, a 2 n -to-1-line multiplexer is constructed
from an n -to-2 n decoder by adding 2n input lines to it, one to each AND gate. The outputs of the
AND gates are applied to a single OR gate. The size of a multiplexer is specified by the number 2n
of its data input lines and the single output line. The n selection lines are implied from the 2n data
lines. As in decoders, multiplexers may have an enable input to control the operation of the unit.
When the enable input is in the inactive state, the outputs are disabled, and when it is in the active
state, the circuit functions as a normal multiplexer.

 Circuit Diagram (a) Block Diagram

(B) Internal Circuit of multiplexer

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 VHDL Code For 4*1 Mux

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity a4x1muxifelse is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : in STD_LOGIC;
d : in STD_LOGIC;
z : out STD_LOGIC;
ctrl : STD_LOGIC_VECTOR(1 downto 0)
);
end a4x1muxifelse;

architecture Behavioral of a4x1muxifelse is

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begin
label1 : process (a,b,c,d,ctrl)
begin
if (ctrl = "00") then
z<=a;
elsif (ctrl="01") then
z<=b;
elsif(ctrl="10") then
z<=c;
elsif(ctrl="11") then
z<=d;
else null;
end if;
end process;
end Behavioral;

Result - Output Waveform

Conclusion The multiplexer gives the output according to the selected lines .In 4*1 MUX the 2-bit
selection lines is available for selection of particular output according to 4 input present on MUX.
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