Sodavaram Nireekshan Kumar

ICGraph Features

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Knowing the Tool

Status Line

Pulldown
Menus

Popup Menu
(RMB)

Message Bar

Palette Menus

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Knowing the Tool

Context

Toolbar

Prompt Bar

Process

Cursor
Location
IC Layout
window

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Setting the Grid values

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Opening the Layer Palette

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Lab on Full Custom Layout of Inverter

To start with the inverter with basic editing features you must be clear with the target
technologys process file and the rule file.
The inverter you will be creating now is targeting the ADK 3.0 ami05 process. The
Lambda value for this process is 1 micron.
Before starting make sure that you are in the $WORK/Basic_inv folder.
Invoke the IC station tool by typing the following command
ic &
You will be seeing the below window.

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Now choose the create option from the palette

You should see the following window

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In the Cell Name tab type inv

In the Process tab browse to $ADK/technology/ic/process/ami05
In the Rules file tab browse to $ADK/technology/ic/process/ami05.rules
Leave the remaining tabs to default settings.
Select OK.

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You should be seeing the following window.

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Set the grid to 0.1X0.1 micron. To do this:

Select Menu > Other > Window > Set Grid
as shown in the figure below.

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Set the Snap X to 0.1 and Snap Y to 0.1 and others to default.

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Now select the layers in which you want to work.

For this select Menu > Other > Layers > Show Layer Palette as shown below.

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Here, scroll down a bit and select the layers that you want to display by pressing the
ctrl button as shown below. For drawing this inverter select
PWELL, NWELL, ACTIVE, P_PLUS_SELECT, N_PLUS_SELECT, POLY,
CONTACT_TO_POLY, CONTACT_TO_ACTIVE, METAL1, VIA, METAL2.

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Select OK here the layout window should get updated as shown below.

Now add the ruler from the origin to draw the inverter.

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Select Edit in the palette. Now click on the RU* tab. You will get the prompt as
shown below.

Click OK to start drawing the ruler.

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Draw the ruler for a height of 120 microns as shown in the figure.

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Now we start drawing the inverter.

Start with drawing the VSS Metal. This is drawn in the Metal1 layer. Choose the
METAL1 Layer from the Palette as shown below.

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Now draw a path to layout the Metal1 VSS rail.

For this, choose the PAT* from the palette so that you would get the PATH prompt as
shown below.

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Select the options tab and enter the width as 10 microns as shown below.

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Choose OK and draw the Metal1 near the origin for the VSS rail as shown below. Draw it
for a length of 25 microns.

Now you have to place the NPLUS_Select to create the N Active region for the
transistor.

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The Nplus region is drawn at a distance of 14 microns from the top edge of the VSS
metal and 4 microns from away from the reference ruler. This is shown in the figure
below

Choose the Nplus layer from the Layer palette.

Select the PAT* from the palette to add the path. Choose the Options tab and enter the
width as 9 as shown below.

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Draw the Nplus region for 17 microns.

Now to flatten the Nplus path to shape, select the Nplus path.
Choose the Edit > Flatten option.
This is shown in the fig below.

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Next you will be drawing the N-Active to get the N diffusion.

Here the N-Active region is drawn inside the N-Plus region with a clearance of 2microns.
This is shown in the figure below.

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Choose the Active layer from the Layer palette as shown in the figure below.
Choose the PAT* from the palette and select the Options tab and enter the width as 5
as shown in the figure below.

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Draw the path for 13microns. The Nactive and the Nplus looks as shown below.

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Now you will be placing the contact on the N-Active region with 1.5 microns distance
from the left inner edge of the Active region as shown below.

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Select the Contact_to_Active layer from the layer palette and choose the width of the
contact as 2microns by selecting the PAT* option from the palette and draw the
contact to distance of 2microns as shown in the figure below.

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Now draw the contact on the right side of the Active region with the same distance and
dimension from the inner edge of the Active as the previous contact as shown below.

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Draw the Metal overlap on these contacts at a distance of 0.5microns from the inner edge
of N-Active region as shown below.

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Now select Metal1 from the Layer Palette and choose PAT* from the palette, enter the
width as 4microns. Draw the Metal overlapping the contact for a distance of 4microns.
Draw another metal overlap on the other side contact with the same distance and
dimension as the one you just drawn. After adding both the Metals, the complete N
region should look as shown below.

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Now connect the VSS rail to one of the contact in the N-Region with a metal of width 3
microns.

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Draw the Pwell region surrounding the N Region. For this, mark the dimension of 27
microns from the top edge of the VSS rail as shown in the figure below.

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Select the Pwell layer from the layer palette. Choose the PAT* from the palette, choose
the width of 27 microns and draw it to a distance of 25 microns as shown below.

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Place the P-WELL contact to connect the bulk of the N transistor to Ground. For this,
Right Click on layout window. Select the ADD > Cell option.
Browse to the folder:
$ADK/technology/ic/process/ami05_via.
Choose the P_WELL_CONTACT cells and place it on the VSS rail such that it also
overlaps on the P_WELL region that you have already drawn as shown below.

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After this, draw the VDD rail with a width of 10microns for a distance of 25microns as
shown below.

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Draw the P-Plus region at a distance of 19 microns from the bottom edge of the VDD rail
and 4microns from the reference marker as shown below.

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Choose the P_PLUS layer from the layer palette. Select the PAT* from the palette.
Enter the width as 14 microns. Draw the P_PLUS region for a distance of 17 microns as
shown below.

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Place the Active region at a distance of 2microns from the inner edge of the PPLUS layer
as shown below. Choose the Active Layer from the Layer palette. Select the PAT*
from the palette and enter the width as 10 microns. Draw it for a distance of 13microns as
shown below.

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Place the contacts in the Pdiff laver. Place the contact at a distance of 1.5microns from
the inner walls of the active region. Place 2 contacts on each side for better connectivity.
The distance between the contacts that are placed one below the other should be
3microns. Please refer the figure below. The contact dimensions should be exactly 2X2
microns.

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Place the Metal1 overlapping the contact with a width of 4microns. Draw the metal at a
distance of 0.5 microns from the inner edge of the Active as shown below.

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Connect the output metal from the P-Region to the N-Region. The Metal width is
3microns.
Please refer the below figure.

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Place the Nwell surrounding the Pregion with a width of 37 microns starting from the
point of reference marker and the bottom part of VDD rail. Draw the Nwell for a distance
of 25microns. Please refer figure below.

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Connect the VDD to the metal in the P-Diffusion with a width of 3micron as shown
below.

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Place the gate poly with a width of 2microns. The poly has an end cap of 2microns on
either side. This is placed at a distance of 1micron from the metal1 edges. This is as
shown in the figure below.

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Place the nwell contact on the VDD rail to make the Bulk connection of the PMOS as
shown below.

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Next is to make the Input connection to the poly. For this extend the poly in between the
PMOS and NMOS for about 5X5micron as shown below.

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Place the Metal1 overlap with a dimension of 4X4 microns and with a distance of
0.5microns from the poly inner edge.

Place the Poly contact by choosing the CONTACT_TO_POLY layer in the layer palette.
The contact dimension is 2X2 microns. Place it at a distance of 1micron from the inner
edge of the metal1. This is as shown below.

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Extend the Metal1 with a width of 3micron away from the poly layer so that you
construct a port by bringing the connection to Metal2. Now at the edge of Metal1 Place a
4X4micron Metal1 layer and place 4X4micron Metal2 over the Metal1 square as shown
in the figure.

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Place the via of size 2X2 micron at a distance of 1micron from the inner edge of Metal2
as shown in the figure below.

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Similarly create an output port for the output Metal1 layer. Both the ports should look
something like shown below.

The complete inverter looks as shown below.

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Now check the DRC by choosing the Checking > DRC (ICRules). You should see the
count Total results:0 in the transcript window at the bottom of the tool.
Creating Ports:
1. Select the VDD Metal. Choose the Objects > Make > Port menu.
Choose the port type as Power. Direction as Bidirectional. Enter the Port name as VDD.
2. Select the VSS Metal. Choose the Objects > Make > Port menu.
Choose the port type as Power. Direction as Bidirectional. Enter the Port name as VSS.
3. Select the IN Metal. Choose the Objects > Make > Port menu.
Choose the port type as Signal. Direction as In. Enter the Port name as IN.
4. Select the OUT Metal. Choose the Objects > Make > Port menu.
Choose the port type as Signal. Direction as Out. Enter the Port name as Out.
This completes the basic inverter.

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